./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.07.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c7c6ca5d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.07.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 --- Real Ultimate output --- This is Ultimate 0.2.5-?-c7c6ca5-m [2024-11-09 16:07:44,571 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-09 16:07:44,646 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-09 16:07:44,651 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-09 16:07:44,652 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-09 16:07:44,678 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-09 16:07:44,679 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-09 16:07:44,679 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-09 16:07:44,679 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-09 16:07:44,680 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-09 16:07:44,680 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-09 16:07:44,680 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-09 16:07:44,680 INFO L153 SettingsManager]: * Use SBE=true [2024-11-09 16:07:44,684 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-09 16:07:44,684 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-09 16:07:44,685 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-09 16:07:44,685 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-09 16:07:44,685 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-09 16:07:44,685 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-09 16:07:44,685 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-09 16:07:44,685 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-09 16:07:44,686 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-09 16:07:44,686 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-09 16:07:44,686 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-09 16:07:44,687 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-09 16:07:44,687 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-09 16:07:44,687 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-09 16:07:44,687 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-09 16:07:44,687 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-09 16:07:44,687 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-09 16:07:44,687 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-09 16:07:44,688 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-09 16:07:44,688 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-09 16:07:44,688 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-09 16:07:44,688 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-09 16:07:44,688 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-09 16:07:44,689 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-09 16:07:44,689 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-09 16:07:44,691 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-09 16:07:44,691 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 [2024-11-09 16:07:44,917 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-09 16:07:44,939 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-09 16:07:44,941 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-09 16:07:44,942 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-09 16:07:44,943 INFO L274 PluginConnector]: CDTParser initialized [2024-11-09 16:07:44,944 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2024-11-09 16:07:46,283 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-09 16:07:46,471 INFO L384 CDTParser]: Found 1 translation units. [2024-11-09 16:07:46,472 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2024-11-09 16:07:46,489 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d9dc380f8/0def8c7a2d76450d875dea14b65ec6c0/FLAGa24128f47 [2024-11-09 16:07:46,848 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d9dc380f8/0def8c7a2d76450d875dea14b65ec6c0 [2024-11-09 16:07:46,850 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-09 16:07:46,851 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-09 16:07:46,852 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-09 16:07:46,852 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-09 16:07:46,856 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-09 16:07:46,857 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:07:46" (1/1) ... [2024-11-09 16:07:46,858 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4ab57825 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:46, skipping insertion in model container [2024-11-09 16:07:46,858 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:07:46" (1/1) ... [2024-11-09 16:07:46,899 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-09 16:07:47,133 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:07:47,143 INFO L200 MainTranslator]: Completed pre-run [2024-11-09 16:07:47,183 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:07:47,200 INFO L204 MainTranslator]: Completed translation [2024-11-09 16:07:47,200 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47 WrapperNode [2024-11-09 16:07:47,200 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-09 16:07:47,201 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-09 16:07:47,201 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-09 16:07:47,202 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-09 16:07:47,207 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,215 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,261 INFO L138 Inliner]: procedures = 42, calls = 53, calls flagged for inlining = 48, calls inlined = 135, statements flattened = 2006 [2024-11-09 16:07:47,262 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-09 16:07:47,263 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-09 16:07:47,263 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-09 16:07:47,263 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-09 16:07:47,276 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,277 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,281 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,300 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-09 16:07:47,301 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,301 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,317 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,334 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,337 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,342 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,348 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-09 16:07:47,351 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-09 16:07:47,351 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-09 16:07:47,351 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-09 16:07:47,352 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (1/1) ... [2024-11-09 16:07:47,359 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:07:47,372 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:07:47,391 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:07:47,405 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-09 16:07:47,440 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-09 16:07:47,440 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-09 16:07:47,440 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-09 16:07:47,440 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-09 16:07:47,520 INFO L238 CfgBuilder]: Building ICFG [2024-11-09 16:07:47,522 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-09 16:07:48,489 INFO L? ?]: Removed 392 outVars from TransFormulas that were not future-live. [2024-11-09 16:07:48,490 INFO L287 CfgBuilder]: Performing block encoding [2024-11-09 16:07:48,510 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-09 16:07:48,510 INFO L316 CfgBuilder]: Removed 10 assume(true) statements. [2024-11-09 16:07:48,511 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:07:48 BoogieIcfgContainer [2024-11-09 16:07:48,511 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-09 16:07:48,512 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-09 16:07:48,512 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-09 16:07:48,515 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-09 16:07:48,515 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:07:48,515 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 04:07:46" (1/3) ... [2024-11-09 16:07:48,516 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e21a6d4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:07:48, skipping insertion in model container [2024-11-09 16:07:48,516 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:07:48,516 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:47" (2/3) ... [2024-11-09 16:07:48,517 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e21a6d4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:07:48, skipping insertion in model container [2024-11-09 16:07:48,517 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:07:48,517 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:07:48" (3/3) ... [2024-11-09 16:07:48,518 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-1.c [2024-11-09 16:07:48,615 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-09 16:07:48,615 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-09 16:07:48,615 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-09 16:07:48,615 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-09 16:07:48,615 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-09 16:07:48,615 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-09 16:07:48,615 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-09 16:07:48,616 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-09 16:07:48,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 845 states, 844 states have (on average 1.5130331753554502) internal successors, (1277), 844 states have internal predecessors, (1277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:48,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 738 [2024-11-09 16:07:48,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:48,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:48,671 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:48,671 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:48,671 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-09 16:07:48,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 845 states, 844 states have (on average 1.5130331753554502) internal successors, (1277), 844 states have internal predecessors, (1277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:48,686 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 738 [2024-11-09 16:07:48,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:48,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:48,689 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:48,689 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:48,696 INFO L745 eck$LassoCheckResult]: Stem: 111#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 764#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 625#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 760#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 581#L536true assume !(1 == ~m_i~0);~m_st~0 := 2; 793#L536-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 264#L541-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 151#L546-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 650#L551-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 139#L556-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 599#L561-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 578#L566-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 376#L571-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 670#L769true assume !(0 == ~M_E~0); 393#L769-2true assume !(0 == ~T1_E~0); 417#L774-1true assume !(0 == ~T2_E~0); 688#L779-1true assume !(0 == ~T3_E~0); 559#L784-1true assume !(0 == ~T4_E~0); 374#L789-1true assume !(0 == ~T5_E~0); 473#L794-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 826#L799-1true assume !(0 == ~T7_E~0); 378#L804-1true assume !(0 == ~E_M~0); 410#L809-1true assume !(0 == ~E_1~0); 592#L814-1true assume !(0 == ~E_2~0); 9#L819-1true assume !(0 == ~E_3~0); 189#L824-1true assume !(0 == ~E_4~0); 816#L829-1true assume !(0 == ~E_5~0); 683#L834-1true assume 0 == ~E_6~0;~E_6~0 := 1; 72#L839-1true assume !(0 == ~E_7~0); 479#L844-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 330#L376true assume !(1 == ~m_pc~0); 328#L376-2true is_master_triggered_~__retres1~0#1 := 0; 775#L387true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43#L955true assume !(0 != activate_threads_~tmp~1#1); 256#L955-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 394#L395true assume 1 == ~t1_pc~0; 61#L396true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 560#L406true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 606#L963true assume !(0 != activate_threads_~tmp___0~0#1); 336#L963-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 836#L414true assume !(1 == ~t2_pc~0); 590#L414-2true is_transmit2_triggered_~__retres1~2#1 := 0; 824#L425true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 196#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 588#L971true assume !(0 != activate_threads_~tmp___1~0#1); 699#L971-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 261#L433true assume 1 == ~t3_pc~0; 220#L434true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 709#L444true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 522#L979true assume !(0 != activate_threads_~tmp___2~0#1); 55#L979-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 794#L452true assume !(1 == ~t4_pc~0); 137#L452-2true is_transmit4_triggered_~__retres1~4#1 := 0; 363#L463true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 706#L987true assume !(0 != activate_threads_~tmp___3~0#1); 156#L987-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 458#L471true assume 1 == ~t5_pc~0; 755#L472true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 145#L482true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 542#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 822#L995true assume !(0 != activate_threads_~tmp___4~0#1); 673#L995-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 741#L490true assume 1 == ~t6_pc~0; 632#L491true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 368#L501true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 186#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 371#L1003true assume !(0 != activate_threads_~tmp___5~0#1); 270#L1003-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 244#L509true assume !(1 == ~t7_pc~0); 593#L509-2true is_transmit7_triggered_~__retres1~7#1 := 0; 123#L520true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 778#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 159#L1011true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 708#L1011-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 603#L857true assume !(1 == ~M_E~0); 46#L857-2true assume !(1 == ~T1_E~0); 198#L862-1true assume !(1 == ~T2_E~0); 203#L867-1true assume !(1 == ~T3_E~0); 262#L872-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 436#L877-1true assume !(1 == ~T5_E~0); 631#L882-1true assume !(1 == ~T6_E~0); 748#L887-1true assume !(1 == ~T7_E~0); 497#L892-1true assume !(1 == ~E_M~0); 714#L897-1true assume !(1 == ~E_1~0); 213#L902-1true assume !(1 == ~E_2~0); 514#L907-1true assume !(1 == ~E_3~0); 448#L912-1true assume 1 == ~E_4~0;~E_4~0 := 2; 442#L917-1true assume !(1 == ~E_5~0); 692#L922-1true assume !(1 == ~E_6~0); 801#L927-1true assume !(1 == ~E_7~0); 433#L932-1true assume { :end_inline_reset_delta_events } true; 727#L1178-2true [2024-11-09 16:07:48,701 INFO L747 eck$LassoCheckResult]: Loop: 727#L1178-2true assume !false; 420#L1179true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 536#L744-1true assume false; 500#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 306#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 668#L769-3true assume 0 == ~M_E~0;~M_E~0 := 1; 259#L769-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 399#L774-3true assume !(0 == ~T2_E~0); 99#L779-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 14#L784-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 837#L789-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 10#L794-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 32#L799-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 162#L804-3true assume 0 == ~E_M~0;~E_M~0 := 1; 332#L809-3true assume 0 == ~E_1~0;~E_1~0 := 1; 30#L814-3true assume !(0 == ~E_2~0); 570#L819-3true assume 0 == ~E_3~0;~E_3~0 := 1; 525#L824-3true assume 0 == ~E_4~0;~E_4~0 := 1; 518#L829-3true assume 0 == ~E_5~0;~E_5~0 := 1; 199#L834-3true assume 0 == ~E_6~0;~E_6~0 := 1; 472#L839-3true assume 0 == ~E_7~0;~E_7~0 := 1; 600#L844-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 740#L376-27true assume !(1 == ~m_pc~0); 827#L376-29true is_master_triggered_~__retres1~0#1 := 0; 397#L387-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 464#is_master_triggered_returnLabel#10true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 701#L955-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 832#L955-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 817#L395-27true assume !(1 == ~t1_pc~0); 275#L395-29true is_transmit1_triggered_~__retres1~1#1 := 0; 200#L406-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 366#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 392#L963-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 266#L963-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 664#L414-27true assume !(1 == ~t2_pc~0); 757#L414-29true is_transmit2_triggered_~__retres1~2#1 := 0; 441#L425-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 439#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 319#L971-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36#L971-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85#L433-27true assume !(1 == ~t3_pc~0); 323#L433-29true is_transmit3_triggered_~__retres1~3#1 := 0; 272#L444-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 302#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 125#L979-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 765#L979-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 751#L452-27true assume !(1 == ~t4_pc~0); 408#L452-29true is_transmit4_triggered_~__retres1~4#1 := 0; 563#L463-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 243#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 659#L987-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 671#L987-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33#L471-27true assume 1 == ~t5_pc~0; 501#L472-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 833#L482-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 555#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 461#L995-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 395#L995-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 329#L490-27true assume !(1 == ~t6_pc~0); 622#L490-29true is_transmit6_triggered_~__retres1~6#1 := 0; 131#L501-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 684#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 447#L1003-27true assume !(0 != activate_threads_~tmp___5~0#1); 722#L1003-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18#L509-27true assume !(1 == ~t7_pc~0); 242#L509-29true is_transmit7_triggered_~__retres1~7#1 := 0; 552#L520-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 166#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 349#L1011-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 811#L1011-29true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 359#L857-3true assume 1 == ~M_E~0;~M_E~0 := 2; 389#L857-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 798#L862-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 742#L867-3true assume !(1 == ~T3_E~0); 273#L872-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 354#L877-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 776#L882-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 386#L887-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 109#L892-3true assume 1 == ~E_M~0;~E_M~0 := 2; 548#L897-3true assume 1 == ~E_1~0;~E_1~0 := 2; 835#L902-3true assume 1 == ~E_2~0;~E_2~0 := 2; 212#L907-3true assume !(1 == ~E_3~0); 310#L912-3true assume 1 == ~E_4~0;~E_4~0 := 2; 585#L917-3true assume 1 == ~E_5~0;~E_5~0 := 2; 276#L922-3true assume 1 == ~E_6~0;~E_6~0 := 2; 138#L927-3true assume 1 == ~E_7~0;~E_7~0 := 2; 221#L932-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 60#L584-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 476#L626-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 170#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 251#L1197true assume !(0 == start_simulation_~tmp~3#1); 529#L1197-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 88#L584-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 258#L626-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 753#L1152true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 545#L1159true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 321#stop_simulation_returnLabel#1true start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 24#L1210true assume !(0 != start_simulation_~tmp___0~1#1); 727#L1178-2true [2024-11-09 16:07:48,707 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:48,707 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2024-11-09 16:07:48,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:48,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393326098] [2024-11-09 16:07:48,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:48,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:48,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:48,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:48,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:48,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393326098] [2024-11-09 16:07:48,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [393326098] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:48,925 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:48,925 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:48,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805241392] [2024-11-09 16:07:48,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:48,930 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:48,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:48,930 INFO L85 PathProgramCache]: Analyzing trace with hash 698466512, now seen corresponding path program 1 times [2024-11-09 16:07:48,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:48,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578576580] [2024-11-09 16:07:48,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:48,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:48,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:48,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:48,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:48,975 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578576580] [2024-11-09 16:07:48,976 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [578576580] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:48,976 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:48,976 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:48,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [148295664] [2024-11-09 16:07:48,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:48,977 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:48,978 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:49,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:49,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:49,016 INFO L87 Difference]: Start difference. First operand has 845 states, 844 states have (on average 1.5130331753554502) internal successors, (1277), 844 states have internal predecessors, (1277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:49,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:49,066 INFO L93 Difference]: Finished difference Result 843 states and 1253 transitions. [2024-11-09 16:07:49,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1253 transitions. [2024-11-09 16:07:49,073 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:49,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 838 states and 1248 transitions. [2024-11-09 16:07:49,085 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-11-09 16:07:49,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-11-09 16:07:49,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1248 transitions. [2024-11-09 16:07:49,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:49,093 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1248 transitions. [2024-11-09 16:07:49,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1248 transitions. [2024-11-09 16:07:49,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-11-09 16:07:49,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4892601431980907) internal successors, (1248), 837 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:49,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1248 transitions. [2024-11-09 16:07:49,138 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1248 transitions. [2024-11-09 16:07:49,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:49,141 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1248 transitions. [2024-11-09 16:07:49,142 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-09 16:07:49,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1248 transitions. [2024-11-09 16:07:49,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:49,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:49,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:49,150 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:49,150 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:49,151 INFO L745 eck$LassoCheckResult]: Stem: 1924#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1925#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2481#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2482#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2461#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2462#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2169#L541-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1993#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1994#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1975#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1976#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2460#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2285#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2286#L769 assume !(0 == ~M_E~0); 2305#L769-2 assume !(0 == ~T1_E~0); 2306#L774-1 assume !(0 == ~T2_E~0); 2333#L779-1 assume !(0 == ~T3_E~0); 2450#L784-1 assume !(0 == ~T4_E~0); 2283#L789-1 assume !(0 == ~T5_E~0); 2284#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2389#L799-1 assume !(0 == ~T7_E~0); 2288#L804-1 assume !(0 == ~E_M~0); 2289#L809-1 assume !(0 == ~E_1~0); 2328#L814-1 assume !(0 == ~E_2~0); 1712#L819-1 assume !(0 == ~E_3~0); 1713#L824-1 assume !(0 == ~E_4~0); 2066#L829-1 assume !(0 == ~E_5~0); 2509#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1849#L839-1 assume !(0 == ~E_7~0); 1850#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2241#L376 assume !(1 == ~m_pc~0); 2230#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2229#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2435#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1790#L955 assume !(0 != activate_threads_~tmp~1#1); 1791#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2162#L395 assume 1 == ~t1_pc~0; 1826#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1827#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1742#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1743#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2245#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2246#L414 assume !(1 == ~t2_pc~0); 1852#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1853#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2072#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2073#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2465#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2166#L433 assume 1 == ~t3_pc~0; 2108#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1964#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1710#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1711#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1815#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1816#L452 assume !(1 == ~t4_pc~0); 1971#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1972#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1809#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1810#L987 assume !(0 != activate_threads_~tmp___3~0#1); 2004#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2005#L471 assume 1 == ~t5_pc~0; 2376#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1986#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1987#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2438#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2500#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2501#L490 assume 1 == ~t6_pc~0; 2486#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2244#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2059#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2060#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2176#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2144#L509 assume !(1 == ~t7_pc~0); 2145#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1946#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1947#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2011#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2012#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2471#L857 assume !(1 == ~M_E~0); 1797#L857-2 assume !(1 == ~T1_E~0); 1798#L862-1 assume !(1 == ~T2_E~0); 2076#L867-1 assume !(1 == ~T3_E~0); 2081#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2167#L877-1 assume !(1 == ~T5_E~0); 2352#L882-1 assume !(1 == ~T6_E~0); 2485#L887-1 assume !(1 == ~T7_E~0); 2405#L892-1 assume !(1 == ~E_M~0); 2406#L897-1 assume !(1 == ~E_1~0); 2096#L902-1 assume !(1 == ~E_2~0); 2097#L907-1 assume !(1 == ~E_3~0); 2366#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2358#L917-1 assume !(1 == ~E_5~0); 2359#L922-1 assume !(1 == ~E_6~0); 2511#L927-1 assume !(1 == ~E_7~0); 2347#L932-1 assume { :end_inline_reset_delta_events } true; 1747#L1178-2 [2024-11-09 16:07:49,151 INFO L747 eck$LassoCheckResult]: Loop: 1747#L1178-2 assume !false; 2334#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2335#L744-1 assume !false; 2208#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2209#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1782#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1991#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2093#L641 assume !(0 != eval_~tmp~0#1); 2407#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2216#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2217#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2164#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2165#L774-3 assume !(0 == ~T2_E~0); 1903#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1723#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1724#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1714#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1715#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1764#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2018#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1760#L814-3 assume !(0 == ~E_2~0); 1761#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2426#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2421#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2077#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2078#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2388#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2469#L376-27 assume 1 == ~m_pc~0; 2362#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2311#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2312#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2383#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2513#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2534#L395-27 assume 1 == ~t1_pc~0; 2530#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2079#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2080#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2276#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2171#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2172#L414-27 assume 1 == ~t2_pc~0; 2497#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2357#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2356#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2232#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1772#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1773#L433-27 assume !(1 == ~t3_pc~0); 1875#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2178#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2179#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1949#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1950#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2525#L452-27 assume !(1 == ~t4_pc~0); 2325#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2326#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2142#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2143#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2494#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1765#L471-27 assume 1 == ~t5_pc~0; 1766#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2090#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2447#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2380#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2307#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2240#L490-27 assume 1 == ~t6_pc~0; 2139#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1960#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1961#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2364#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 2365#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1732#L509-27 assume 1 == ~t7_pc~0; 1733#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2141#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2022#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2023#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2260#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2272#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2273#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2303#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2524#L867-3 assume !(1 == ~T3_E~0); 2180#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2181#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2267#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2297#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1920#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1921#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2444#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2094#L907-3 assume !(1 == ~E_3~0); 2095#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2220#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2185#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1973#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1974#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1824#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1721#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2031#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2032#L1197 assume !(0 == start_simulation_~tmp~3#1); 2153#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1883#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1847#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1740#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1741#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2441#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2234#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1746#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1747#L1178-2 [2024-11-09 16:07:49,152 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:49,152 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2024-11-09 16:07:49,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:49,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604024937] [2024-11-09 16:07:49,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:49,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:49,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:49,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:49,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:49,218 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604024937] [2024-11-09 16:07:49,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604024937] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:49,219 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:49,219 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:49,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884077789] [2024-11-09 16:07:49,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:49,219 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:49,220 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:49,220 INFO L85 PathProgramCache]: Analyzing trace with hash -542624296, now seen corresponding path program 1 times [2024-11-09 16:07:49,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:49,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40454784] [2024-11-09 16:07:49,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:49,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:49,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:49,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:49,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:49,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40454784] [2024-11-09 16:07:49,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [40454784] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:49,312 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:49,312 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:49,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [170269152] [2024-11-09 16:07:49,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:49,313 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:49,313 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:49,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:49,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:49,313 INFO L87 Difference]: Start difference. First operand 838 states and 1248 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:49,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:49,333 INFO L93 Difference]: Finished difference Result 838 states and 1247 transitions. [2024-11-09 16:07:49,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1247 transitions. [2024-11-09 16:07:49,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:49,341 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1247 transitions. [2024-11-09 16:07:49,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-11-09 16:07:49,341 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-11-09 16:07:49,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1247 transitions. [2024-11-09 16:07:49,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:49,344 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1247 transitions. [2024-11-09 16:07:49,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1247 transitions. [2024-11-09 16:07:49,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-11-09 16:07:49,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4880668257756564) internal successors, (1247), 837 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:49,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1247 transitions. [2024-11-09 16:07:49,391 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1247 transitions. [2024-11-09 16:07:49,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:49,392 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1247 transitions. [2024-11-09 16:07:49,392 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-09 16:07:49,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1247 transitions. [2024-11-09 16:07:49,400 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:49,400 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:49,400 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:49,402 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:49,402 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:49,402 INFO L745 eck$LassoCheckResult]: Stem: 3607#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3608#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4164#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4165#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4144#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 4145#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3852#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3676#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3677#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3658#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3659#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4143#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3968#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3969#L769 assume !(0 == ~M_E~0); 3988#L769-2 assume !(0 == ~T1_E~0); 3989#L774-1 assume !(0 == ~T2_E~0); 4016#L779-1 assume !(0 == ~T3_E~0); 4133#L784-1 assume !(0 == ~T4_E~0); 3966#L789-1 assume !(0 == ~T5_E~0); 3967#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4072#L799-1 assume !(0 == ~T7_E~0); 3971#L804-1 assume !(0 == ~E_M~0); 3972#L809-1 assume !(0 == ~E_1~0); 4011#L814-1 assume !(0 == ~E_2~0); 3395#L819-1 assume !(0 == ~E_3~0); 3396#L824-1 assume !(0 == ~E_4~0); 3749#L829-1 assume !(0 == ~E_5~0); 4192#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3532#L839-1 assume !(0 == ~E_7~0); 3533#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3924#L376 assume !(1 == ~m_pc~0); 3913#L376-2 is_master_triggered_~__retres1~0#1 := 0; 3912#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4118#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3473#L955 assume !(0 != activate_threads_~tmp~1#1); 3474#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3845#L395 assume 1 == ~t1_pc~0; 3509#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3510#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3425#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3426#L963 assume !(0 != activate_threads_~tmp___0~0#1); 3928#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3929#L414 assume !(1 == ~t2_pc~0); 3535#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3536#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3755#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3756#L971 assume !(0 != activate_threads_~tmp___1~0#1); 4148#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3849#L433 assume 1 == ~t3_pc~0; 3791#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3647#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3393#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3394#L979 assume !(0 != activate_threads_~tmp___2~0#1); 3498#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3499#L452 assume !(1 == ~t4_pc~0); 3654#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3655#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3492#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3493#L987 assume !(0 != activate_threads_~tmp___3~0#1); 3687#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3688#L471 assume 1 == ~t5_pc~0; 4059#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3669#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3670#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4121#L995 assume !(0 != activate_threads_~tmp___4~0#1); 4183#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4184#L490 assume 1 == ~t6_pc~0; 4169#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3927#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3742#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3743#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 3859#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3827#L509 assume !(1 == ~t7_pc~0); 3828#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3629#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3630#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3694#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3695#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4154#L857 assume !(1 == ~M_E~0); 3480#L857-2 assume !(1 == ~T1_E~0); 3481#L862-1 assume !(1 == ~T2_E~0); 3759#L867-1 assume !(1 == ~T3_E~0); 3764#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3850#L877-1 assume !(1 == ~T5_E~0); 4035#L882-1 assume !(1 == ~T6_E~0); 4168#L887-1 assume !(1 == ~T7_E~0); 4088#L892-1 assume !(1 == ~E_M~0); 4089#L897-1 assume !(1 == ~E_1~0); 3779#L902-1 assume !(1 == ~E_2~0); 3780#L907-1 assume !(1 == ~E_3~0); 4049#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4041#L917-1 assume !(1 == ~E_5~0); 4042#L922-1 assume !(1 == ~E_6~0); 4194#L927-1 assume !(1 == ~E_7~0); 4030#L932-1 assume { :end_inline_reset_delta_events } true; 3430#L1178-2 [2024-11-09 16:07:49,405 INFO L747 eck$LassoCheckResult]: Loop: 3430#L1178-2 assume !false; 4017#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4018#L744-1 assume !false; 3891#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3892#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3465#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3674#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3776#L641 assume !(0 != eval_~tmp~0#1); 4090#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3899#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3900#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3847#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3848#L774-3 assume !(0 == ~T2_E~0); 3586#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3406#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3407#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3397#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3398#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3447#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3701#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3443#L814-3 assume !(0 == ~E_2~0); 3444#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4109#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4104#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3760#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3761#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4071#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4152#L376-27 assume 1 == ~m_pc~0; 4045#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3994#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3995#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4066#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4196#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4217#L395-27 assume 1 == ~t1_pc~0; 4213#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3762#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3763#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3959#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3854#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3855#L414-27 assume 1 == ~t2_pc~0; 4180#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4040#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4039#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3915#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3455#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3456#L433-27 assume !(1 == ~t3_pc~0); 3558#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 3861#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3862#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3632#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3633#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4208#L452-27 assume 1 == ~t4_pc~0; 4209#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4009#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3825#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3826#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4177#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3448#L471-27 assume 1 == ~t5_pc~0; 3449#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3773#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4130#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4063#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3990#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3923#L490-27 assume 1 == ~t6_pc~0; 3822#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3643#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3644#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4047#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 4048#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3415#L509-27 assume 1 == ~t7_pc~0; 3416#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3824#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3705#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3706#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3943#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3955#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3956#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3986#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4207#L867-3 assume !(1 == ~T3_E~0); 3863#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3864#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3950#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3980#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3603#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3604#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4127#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3777#L907-3 assume !(1 == ~E_3~0); 3778#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3903#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3868#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3656#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3657#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3507#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3404#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3714#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3715#L1197 assume !(0 == start_simulation_~tmp~3#1); 3836#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3566#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3530#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3423#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 3424#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4124#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3917#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3429#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 3430#L1178-2 [2024-11-09 16:07:49,406 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:49,407 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2024-11-09 16:07:49,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:49,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1894287558] [2024-11-09 16:07:49,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:49,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:49,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:49,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:49,494 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:49,495 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1894287558] [2024-11-09 16:07:49,495 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1894287558] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:49,495 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:49,495 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:49,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953452428] [2024-11-09 16:07:49,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:49,496 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:49,497 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:49,497 INFO L85 PathProgramCache]: Analyzing trace with hash -268845801, now seen corresponding path program 1 times [2024-11-09 16:07:49,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:49,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452370423] [2024-11-09 16:07:49,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:49,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:49,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:49,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:49,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:49,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1452370423] [2024-11-09 16:07:49,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1452370423] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:49,610 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:49,611 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:49,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [362970455] [2024-11-09 16:07:49,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:49,611 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:49,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:49,614 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:49,614 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:49,614 INFO L87 Difference]: Start difference. First operand 838 states and 1247 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:49,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:49,629 INFO L93 Difference]: Finished difference Result 838 states and 1246 transitions. [2024-11-09 16:07:49,630 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1246 transitions. [2024-11-09 16:07:49,634 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:49,638 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1246 transitions. [2024-11-09 16:07:49,638 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-11-09 16:07:49,638 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-11-09 16:07:49,638 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1246 transitions. [2024-11-09 16:07:49,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:49,640 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1246 transitions. [2024-11-09 16:07:49,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1246 transitions. [2024-11-09 16:07:49,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-11-09 16:07:49,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4868735083532219) internal successors, (1246), 837 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:49,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1246 transitions. [2024-11-09 16:07:49,651 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1246 transitions. [2024-11-09 16:07:49,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:49,653 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1246 transitions. [2024-11-09 16:07:49,653 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-09 16:07:49,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1246 transitions. [2024-11-09 16:07:49,657 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:49,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:49,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:49,659 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:49,661 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:49,661 INFO L745 eck$LassoCheckResult]: Stem: 5290#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5847#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5848#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5827#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 5828#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5535#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5359#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5360#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5341#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5342#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5826#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5651#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5652#L769 assume !(0 == ~M_E~0); 5671#L769-2 assume !(0 == ~T1_E~0); 5672#L774-1 assume !(0 == ~T2_E~0); 5699#L779-1 assume !(0 == ~T3_E~0); 5816#L784-1 assume !(0 == ~T4_E~0); 5649#L789-1 assume !(0 == ~T5_E~0); 5650#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5755#L799-1 assume !(0 == ~T7_E~0); 5654#L804-1 assume !(0 == ~E_M~0); 5655#L809-1 assume !(0 == ~E_1~0); 5694#L814-1 assume !(0 == ~E_2~0); 5078#L819-1 assume !(0 == ~E_3~0); 5079#L824-1 assume !(0 == ~E_4~0); 5432#L829-1 assume !(0 == ~E_5~0); 5875#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5215#L839-1 assume !(0 == ~E_7~0); 5216#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5607#L376 assume !(1 == ~m_pc~0); 5596#L376-2 is_master_triggered_~__retres1~0#1 := 0; 5595#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5801#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5156#L955 assume !(0 != activate_threads_~tmp~1#1); 5157#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5528#L395 assume 1 == ~t1_pc~0; 5192#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5193#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5108#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5109#L963 assume !(0 != activate_threads_~tmp___0~0#1); 5611#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5612#L414 assume !(1 == ~t2_pc~0); 5218#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5219#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5438#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5439#L971 assume !(0 != activate_threads_~tmp___1~0#1); 5831#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5532#L433 assume 1 == ~t3_pc~0; 5474#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5330#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5076#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5077#L979 assume !(0 != activate_threads_~tmp___2~0#1); 5181#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5182#L452 assume !(1 == ~t4_pc~0); 5337#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5338#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5175#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5176#L987 assume !(0 != activate_threads_~tmp___3~0#1); 5370#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5371#L471 assume 1 == ~t5_pc~0; 5742#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5352#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5353#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5804#L995 assume !(0 != activate_threads_~tmp___4~0#1); 5866#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5867#L490 assume 1 == ~t6_pc~0; 5852#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5610#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5425#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5426#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 5542#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5510#L509 assume !(1 == ~t7_pc~0); 5511#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5312#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5313#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5377#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5378#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5837#L857 assume !(1 == ~M_E~0); 5163#L857-2 assume !(1 == ~T1_E~0); 5164#L862-1 assume !(1 == ~T2_E~0); 5442#L867-1 assume !(1 == ~T3_E~0); 5447#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5533#L877-1 assume !(1 == ~T5_E~0); 5718#L882-1 assume !(1 == ~T6_E~0); 5851#L887-1 assume !(1 == ~T7_E~0); 5771#L892-1 assume !(1 == ~E_M~0); 5772#L897-1 assume !(1 == ~E_1~0); 5462#L902-1 assume !(1 == ~E_2~0); 5463#L907-1 assume !(1 == ~E_3~0); 5732#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5724#L917-1 assume !(1 == ~E_5~0); 5725#L922-1 assume !(1 == ~E_6~0); 5877#L927-1 assume !(1 == ~E_7~0); 5713#L932-1 assume { :end_inline_reset_delta_events } true; 5113#L1178-2 [2024-11-09 16:07:49,662 INFO L747 eck$LassoCheckResult]: Loop: 5113#L1178-2 assume !false; 5700#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5701#L744-1 assume !false; 5574#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5575#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5148#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5357#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5459#L641 assume !(0 != eval_~tmp~0#1); 5773#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5582#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5583#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5530#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5531#L774-3 assume !(0 == ~T2_E~0); 5269#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5089#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5090#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5080#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5081#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5130#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5384#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5126#L814-3 assume !(0 == ~E_2~0); 5127#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5792#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5787#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5443#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5444#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5754#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5835#L376-27 assume 1 == ~m_pc~0; 5728#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5677#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5678#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5749#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5879#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5900#L395-27 assume 1 == ~t1_pc~0; 5896#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5445#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5446#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5642#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5537#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5538#L414-27 assume 1 == ~t2_pc~0; 5863#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5723#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5722#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5598#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5138#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5139#L433-27 assume !(1 == ~t3_pc~0); 5241#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 5544#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5545#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5315#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5316#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5891#L452-27 assume 1 == ~t4_pc~0; 5892#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5692#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5508#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5509#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5860#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5131#L471-27 assume 1 == ~t5_pc~0; 5132#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5456#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5813#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5746#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5673#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5606#L490-27 assume 1 == ~t6_pc~0; 5505#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5326#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5327#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5730#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 5731#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5098#L509-27 assume 1 == ~t7_pc~0; 5099#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5507#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5388#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5389#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5626#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5638#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5639#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5669#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5890#L867-3 assume !(1 == ~T3_E~0); 5546#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5547#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5633#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5663#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5286#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5287#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5810#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5460#L907-3 assume !(1 == ~E_3~0); 5461#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5586#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5551#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5339#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5340#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5190#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5087#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5398#L1197 assume !(0 == start_simulation_~tmp~3#1); 5519#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5249#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5213#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5106#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 5107#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5807#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5600#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5112#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 5113#L1178-2 [2024-11-09 16:07:49,662 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:49,662 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2024-11-09 16:07:49,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:49,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637467778] [2024-11-09 16:07:49,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:49,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:49,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:49,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:49,707 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:49,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [637467778] [2024-11-09 16:07:49,707 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [637467778] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:49,711 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:49,711 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:49,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089400413] [2024-11-09 16:07:49,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:49,712 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:49,712 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:49,712 INFO L85 PathProgramCache]: Analyzing trace with hash -268845801, now seen corresponding path program 2 times [2024-11-09 16:07:49,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:49,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1302462264] [2024-11-09 16:07:49,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:49,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:49,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:49,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:49,767 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:49,767 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1302462264] [2024-11-09 16:07:49,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1302462264] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:49,767 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:49,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:49,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29777180] [2024-11-09 16:07:49,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:49,768 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:49,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:49,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:49,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:49,769 INFO L87 Difference]: Start difference. First operand 838 states and 1246 transitions. cyclomatic complexity: 409 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:49,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:49,783 INFO L93 Difference]: Finished difference Result 838 states and 1245 transitions. [2024-11-09 16:07:49,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1245 transitions. [2024-11-09 16:07:49,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:49,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1245 transitions. [2024-11-09 16:07:49,790 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-11-09 16:07:49,791 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-11-09 16:07:49,791 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1245 transitions. [2024-11-09 16:07:49,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:49,792 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1245 transitions. [2024-11-09 16:07:49,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1245 transitions. [2024-11-09 16:07:49,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-11-09 16:07:49,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4856801909307875) internal successors, (1245), 837 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:49,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1245 transitions. [2024-11-09 16:07:49,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1245 transitions. [2024-11-09 16:07:49,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:49,807 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1245 transitions. [2024-11-09 16:07:49,807 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-09 16:07:49,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1245 transitions. [2024-11-09 16:07:49,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:49,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:49,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:49,814 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:49,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:49,815 INFO L745 eck$LassoCheckResult]: Stem: 6975#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 6976#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7530#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7531#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7510#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 7511#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7218#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7042#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7043#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7024#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7025#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7509#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7334#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7335#L769 assume !(0 == ~M_E~0); 7354#L769-2 assume !(0 == ~T1_E~0); 7355#L774-1 assume !(0 == ~T2_E~0); 7382#L779-1 assume !(0 == ~T3_E~0); 7499#L784-1 assume !(0 == ~T4_E~0); 7332#L789-1 assume !(0 == ~T5_E~0); 7333#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7438#L799-1 assume !(0 == ~T7_E~0); 7337#L804-1 assume !(0 == ~E_M~0); 7338#L809-1 assume !(0 == ~E_1~0); 7377#L814-1 assume !(0 == ~E_2~0); 6763#L819-1 assume !(0 == ~E_3~0); 6764#L824-1 assume !(0 == ~E_4~0); 7115#L829-1 assume !(0 == ~E_5~0); 7558#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6898#L839-1 assume !(0 == ~E_7~0); 6899#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7290#L376 assume !(1 == ~m_pc~0); 7283#L376-2 is_master_triggered_~__retres1~0#1 := 0; 7282#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7484#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6841#L955 assume !(0 != activate_threads_~tmp~1#1); 6842#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7211#L395 assume 1 == ~t1_pc~0; 6875#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6876#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6791#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6792#L963 assume !(0 != activate_threads_~tmp___0~0#1); 7295#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7296#L414 assume !(1 == ~t2_pc~0); 6901#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6902#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7121#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7122#L971 assume !(0 != activate_threads_~tmp___1~0#1); 7514#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7215#L433 assume 1 == ~t3_pc~0; 7157#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7015#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6759#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6760#L979 assume !(0 != activate_threads_~tmp___2~0#1); 6864#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6865#L452 assume !(1 == ~t4_pc~0); 7020#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7021#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6858#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6859#L987 assume !(0 != activate_threads_~tmp___3~0#1); 7053#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7054#L471 assume 1 == ~t5_pc~0; 7425#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7035#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7036#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7487#L995 assume !(0 != activate_threads_~tmp___4~0#1); 7549#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7550#L490 assume 1 == ~t6_pc~0; 7536#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7293#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7108#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7109#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 7227#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7193#L509 assume !(1 == ~t7_pc~0); 7194#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7000#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7001#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7060#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7061#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7520#L857 assume !(1 == ~M_E~0); 6846#L857-2 assume !(1 == ~T1_E~0); 6847#L862-1 assume !(1 == ~T2_E~0); 7125#L867-1 assume !(1 == ~T3_E~0); 7130#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7216#L877-1 assume !(1 == ~T5_E~0); 7401#L882-1 assume !(1 == ~T6_E~0); 7534#L887-1 assume !(1 == ~T7_E~0); 7454#L892-1 assume !(1 == ~E_M~0); 7455#L897-1 assume !(1 == ~E_1~0); 7147#L902-1 assume !(1 == ~E_2~0); 7148#L907-1 assume !(1 == ~E_3~0); 7417#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7407#L917-1 assume !(1 == ~E_5~0); 7408#L922-1 assume !(1 == ~E_6~0); 7560#L927-1 assume !(1 == ~E_7~0); 7396#L932-1 assume { :end_inline_reset_delta_events } true; 6796#L1178-2 [2024-11-09 16:07:49,816 INFO L747 eck$LassoCheckResult]: Loop: 6796#L1178-2 assume !false; 7383#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7384#L744-1 assume !false; 7257#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7258#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6831#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7040#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7144#L641 assume !(0 != eval_~tmp~0#1); 7456#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7265#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7266#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7213#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7214#L774-3 assume !(0 == ~T2_E~0); 6954#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6772#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6773#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6765#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6766#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6813#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7068#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6809#L814-3 assume !(0 == ~E_2~0); 6810#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7475#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7470#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7126#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7127#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7437#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7518#L376-27 assume 1 == ~m_pc~0; 7411#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7360#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7361#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7432#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7562#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7583#L395-27 assume !(1 == ~t1_pc~0); 7233#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7128#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7129#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7325#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7220#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7221#L414-27 assume 1 == ~t2_pc~0; 7546#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7406#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7405#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7278#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6821#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6822#L433-27 assume !(1 == ~t3_pc~0); 6924#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 7225#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7226#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6996#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6997#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7574#L452-27 assume 1 == ~t4_pc~0; 7575#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7375#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7191#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7192#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7543#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6814#L471-27 assume !(1 == ~t5_pc~0); 6816#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 7136#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7496#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7429#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7356#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7289#L490-27 assume 1 == ~t6_pc~0; 7188#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7009#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7010#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7413#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 7414#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6781#L509-27 assume 1 == ~t7_pc~0; 6782#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7190#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7071#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7072#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7309#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7321#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7322#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7352#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7573#L867-3 assume !(1 == ~T3_E~0); 7229#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7230#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7316#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7346#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6967#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6968#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7493#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7142#L907-3 assume !(1 == ~E_3~0); 7143#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7269#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7234#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7022#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7023#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6873#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6770#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7080#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7081#L1197 assume !(0 == start_simulation_~tmp~3#1); 7201#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6932#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6896#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6789#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 6790#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7490#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7280#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 6795#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 6796#L1178-2 [2024-11-09 16:07:49,816 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:49,817 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2024-11-09 16:07:49,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:49,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384053644] [2024-11-09 16:07:49,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:49,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:49,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:49,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:49,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:49,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [384053644] [2024-11-09 16:07:49,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [384053644] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:49,856 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:49,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:49,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624260680] [2024-11-09 16:07:49,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:49,857 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:49,857 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:49,858 INFO L85 PathProgramCache]: Analyzing trace with hash 177358105, now seen corresponding path program 1 times [2024-11-09 16:07:49,858 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:49,858 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [505367912] [2024-11-09 16:07:49,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:49,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:49,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:49,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:49,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:49,893 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [505367912] [2024-11-09 16:07:49,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [505367912] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:49,894 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:49,894 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:49,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174334268] [2024-11-09 16:07:49,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:49,895 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:49,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:49,895 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:49,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:49,896 INFO L87 Difference]: Start difference. First operand 838 states and 1245 transitions. cyclomatic complexity: 408 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:49,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:49,907 INFO L93 Difference]: Finished difference Result 838 states and 1244 transitions. [2024-11-09 16:07:49,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1244 transitions. [2024-11-09 16:07:49,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:49,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1244 transitions. [2024-11-09 16:07:49,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-11-09 16:07:49,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-11-09 16:07:49,913 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1244 transitions. [2024-11-09 16:07:49,914 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:49,914 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1244 transitions. [2024-11-09 16:07:49,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1244 transitions. [2024-11-09 16:07:49,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-11-09 16:07:49,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4844868735083532) internal successors, (1244), 837 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:49,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1244 transitions. [2024-11-09 16:07:49,923 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1244 transitions. [2024-11-09 16:07:49,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:49,925 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1244 transitions. [2024-11-09 16:07:49,925 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-09 16:07:49,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1244 transitions. [2024-11-09 16:07:49,928 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:49,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:49,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:49,931 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:49,931 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:49,931 INFO L745 eck$LassoCheckResult]: Stem: 8656#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9213#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9214#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9193#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 9194#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8901#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8725#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8726#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8707#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8708#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9192#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9017#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9018#L769 assume !(0 == ~M_E~0); 9037#L769-2 assume !(0 == ~T1_E~0); 9038#L774-1 assume !(0 == ~T2_E~0); 9065#L779-1 assume !(0 == ~T3_E~0); 9182#L784-1 assume !(0 == ~T4_E~0); 9015#L789-1 assume !(0 == ~T5_E~0); 9016#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9121#L799-1 assume !(0 == ~T7_E~0); 9020#L804-1 assume !(0 == ~E_M~0); 9021#L809-1 assume !(0 == ~E_1~0); 9060#L814-1 assume !(0 == ~E_2~0); 8446#L819-1 assume !(0 == ~E_3~0); 8447#L824-1 assume !(0 == ~E_4~0); 8798#L829-1 assume !(0 == ~E_5~0); 9241#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8581#L839-1 assume !(0 == ~E_7~0); 8582#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8973#L376 assume !(1 == ~m_pc~0); 8963#L376-2 is_master_triggered_~__retres1~0#1 := 0; 8962#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9167#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8524#L955 assume !(0 != activate_threads_~tmp~1#1); 8525#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8894#L395 assume 1 == ~t1_pc~0; 8558#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8559#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8474#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8475#L963 assume !(0 != activate_threads_~tmp___0~0#1); 8978#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8979#L414 assume !(1 == ~t2_pc~0); 8584#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8585#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8804#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8805#L971 assume !(0 != activate_threads_~tmp___1~0#1); 9197#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8898#L433 assume 1 == ~t3_pc~0; 8840#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8698#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8442#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8443#L979 assume !(0 != activate_threads_~tmp___2~0#1); 8547#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8548#L452 assume !(1 == ~t4_pc~0); 8703#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8704#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8541#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8542#L987 assume !(0 != activate_threads_~tmp___3~0#1); 8736#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8737#L471 assume 1 == ~t5_pc~0; 9108#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8718#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8719#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9170#L995 assume !(0 != activate_threads_~tmp___4~0#1); 9232#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9233#L490 assume 1 == ~t6_pc~0; 9219#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8976#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8791#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8792#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 8908#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8876#L509 assume !(1 == ~t7_pc~0); 8877#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8680#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8681#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8743#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8744#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9203#L857 assume !(1 == ~M_E~0); 8529#L857-2 assume !(1 == ~T1_E~0); 8530#L862-1 assume !(1 == ~T2_E~0); 8808#L867-1 assume !(1 == ~T3_E~0); 8813#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8899#L877-1 assume !(1 == ~T5_E~0); 9084#L882-1 assume !(1 == ~T6_E~0); 9217#L887-1 assume !(1 == ~T7_E~0); 9137#L892-1 assume !(1 == ~E_M~0); 9138#L897-1 assume !(1 == ~E_1~0); 8830#L902-1 assume !(1 == ~E_2~0); 8831#L907-1 assume !(1 == ~E_3~0); 9100#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9090#L917-1 assume !(1 == ~E_5~0); 9091#L922-1 assume !(1 == ~E_6~0); 9243#L927-1 assume !(1 == ~E_7~0); 9079#L932-1 assume { :end_inline_reset_delta_events } true; 8479#L1178-2 [2024-11-09 16:07:49,931 INFO L747 eck$LassoCheckResult]: Loop: 8479#L1178-2 assume !false; 9066#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9067#L744-1 assume !false; 8940#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8941#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8514#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8723#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8827#L641 assume !(0 != eval_~tmp~0#1); 9139#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8948#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8949#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8896#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8897#L774-3 assume !(0 == ~T2_E~0); 8635#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8455#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8456#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8448#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8449#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8496#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8751#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8494#L814-3 assume !(0 == ~E_2~0); 8495#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9158#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9153#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8809#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8810#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9120#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9201#L376-27 assume 1 == ~m_pc~0; 9094#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9043#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9044#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9115#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9245#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9266#L395-27 assume !(1 == ~t1_pc~0); 8917#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 8811#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8812#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9008#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8903#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8904#L414-27 assume 1 == ~t2_pc~0; 9229#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9089#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9088#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8965#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8504#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8505#L433-27 assume 1 == ~t3_pc~0; 8608#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8910#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8911#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8683#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8684#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9257#L452-27 assume !(1 == ~t4_pc~0); 9057#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 9058#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8874#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8875#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9226#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8497#L471-27 assume 1 == ~t5_pc~0; 8498#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8817#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9179#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9112#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9039#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8972#L490-27 assume 1 == ~t6_pc~0; 8871#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8692#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8693#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9096#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 9097#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8464#L509-27 assume 1 == ~t7_pc~0; 8465#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8873#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8754#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8755#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8991#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9004#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9005#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9033#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9256#L867-3 assume !(1 == ~T3_E~0); 8912#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8913#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8999#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9029#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8650#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8651#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9176#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8825#L907-3 assume !(1 == ~E_3~0); 8826#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8952#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8916#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8705#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8706#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8556#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8451#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8763#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8764#L1197 assume !(0 == start_simulation_~tmp~3#1); 8883#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8612#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8579#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8472#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 8473#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9173#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8960#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8478#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 8479#L1178-2 [2024-11-09 16:07:49,932 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:49,932 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2024-11-09 16:07:49,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:49,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [496930219] [2024-11-09 16:07:49,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:49,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:49,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:49,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:49,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:49,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [496930219] [2024-11-09 16:07:49,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [496930219] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:49,959 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:49,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:49,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1519758689] [2024-11-09 16:07:49,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:49,959 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:49,960 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:49,960 INFO L85 PathProgramCache]: Analyzing trace with hash -1466614696, now seen corresponding path program 1 times [2024-11-09 16:07:49,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:49,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151360533] [2024-11-09 16:07:49,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:49,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:49,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:50,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:50,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:50,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151360533] [2024-11-09 16:07:50,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1151360533] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:50,019 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:50,019 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:50,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [341310690] [2024-11-09 16:07:50,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:50,019 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:50,019 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:50,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:50,020 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:50,020 INFO L87 Difference]: Start difference. First operand 838 states and 1244 transitions. cyclomatic complexity: 407 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:50,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:50,031 INFO L93 Difference]: Finished difference Result 838 states and 1243 transitions. [2024-11-09 16:07:50,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1243 transitions. [2024-11-09 16:07:50,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:50,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1243 transitions. [2024-11-09 16:07:50,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-11-09 16:07:50,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-11-09 16:07:50,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1243 transitions. [2024-11-09 16:07:50,038 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:50,038 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1243 transitions. [2024-11-09 16:07:50,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1243 transitions. [2024-11-09 16:07:50,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-11-09 16:07:50,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4832935560859188) internal successors, (1243), 837 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:50,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1243 transitions. [2024-11-09 16:07:50,046 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1243 transitions. [2024-11-09 16:07:50,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:50,047 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1243 transitions. [2024-11-09 16:07:50,047 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-09 16:07:50,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1243 transitions. [2024-11-09 16:07:50,049 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:50,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:50,049 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:50,050 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,050 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,050 INFO L745 eck$LassoCheckResult]: Stem: 10339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10896#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10897#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10876#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 10877#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10584#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10408#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10409#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10390#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10391#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10875#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10700#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10701#L769 assume !(0 == ~M_E~0); 10720#L769-2 assume !(0 == ~T1_E~0); 10721#L774-1 assume !(0 == ~T2_E~0); 10748#L779-1 assume !(0 == ~T3_E~0); 10865#L784-1 assume !(0 == ~T4_E~0); 10698#L789-1 assume !(0 == ~T5_E~0); 10699#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10804#L799-1 assume !(0 == ~T7_E~0); 10703#L804-1 assume !(0 == ~E_M~0); 10704#L809-1 assume !(0 == ~E_1~0); 10743#L814-1 assume !(0 == ~E_2~0); 10127#L819-1 assume !(0 == ~E_3~0); 10128#L824-1 assume !(0 == ~E_4~0); 10481#L829-1 assume !(0 == ~E_5~0); 10924#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10264#L839-1 assume !(0 == ~E_7~0); 10265#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10656#L376 assume !(1 == ~m_pc~0); 10645#L376-2 is_master_triggered_~__retres1~0#1 := 0; 10644#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10850#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10205#L955 assume !(0 != activate_threads_~tmp~1#1); 10206#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10577#L395 assume 1 == ~t1_pc~0; 10241#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10242#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10158#L963 assume !(0 != activate_threads_~tmp___0~0#1); 10660#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10661#L414 assume !(1 == ~t2_pc~0); 10267#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10268#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10487#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10488#L971 assume !(0 != activate_threads_~tmp___1~0#1); 10880#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10581#L433 assume 1 == ~t3_pc~0; 10523#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10379#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10126#L979 assume !(0 != activate_threads_~tmp___2~0#1); 10230#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10231#L452 assume !(1 == ~t4_pc~0); 10386#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10387#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10224#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10225#L987 assume !(0 != activate_threads_~tmp___3~0#1); 10419#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10420#L471 assume 1 == ~t5_pc~0; 10791#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10401#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10402#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10853#L995 assume !(0 != activate_threads_~tmp___4~0#1); 10915#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10916#L490 assume 1 == ~t6_pc~0; 10901#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10659#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10474#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10475#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 10591#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10559#L509 assume !(1 == ~t7_pc~0); 10560#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10361#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10362#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10426#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10427#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10886#L857 assume !(1 == ~M_E~0); 10212#L857-2 assume !(1 == ~T1_E~0); 10213#L862-1 assume !(1 == ~T2_E~0); 10491#L867-1 assume !(1 == ~T3_E~0); 10496#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10582#L877-1 assume !(1 == ~T5_E~0); 10767#L882-1 assume !(1 == ~T6_E~0); 10900#L887-1 assume !(1 == ~T7_E~0); 10820#L892-1 assume !(1 == ~E_M~0); 10821#L897-1 assume !(1 == ~E_1~0); 10511#L902-1 assume !(1 == ~E_2~0); 10512#L907-1 assume !(1 == ~E_3~0); 10781#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10773#L917-1 assume !(1 == ~E_5~0); 10774#L922-1 assume !(1 == ~E_6~0); 10926#L927-1 assume !(1 == ~E_7~0); 10762#L932-1 assume { :end_inline_reset_delta_events } true; 10162#L1178-2 [2024-11-09 16:07:50,051 INFO L747 eck$LassoCheckResult]: Loop: 10162#L1178-2 assume !false; 10749#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10750#L744-1 assume !false; 10623#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10624#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10197#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10406#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10508#L641 assume !(0 != eval_~tmp~0#1); 10822#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10631#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10632#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10579#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10580#L774-3 assume !(0 == ~T2_E~0); 10318#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10138#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10139#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10129#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10130#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10179#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10433#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10175#L814-3 assume !(0 == ~E_2~0); 10176#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10841#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10836#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10492#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10493#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10803#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10884#L376-27 assume 1 == ~m_pc~0; 10777#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10726#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10727#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10798#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10928#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10949#L395-27 assume 1 == ~t1_pc~0; 10945#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10494#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10495#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10691#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10586#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10587#L414-27 assume 1 == ~t2_pc~0; 10912#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10772#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10771#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10647#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10187#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10188#L433-27 assume !(1 == ~t3_pc~0); 10290#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 10593#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10594#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10364#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10365#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10940#L452-27 assume !(1 == ~t4_pc~0); 10740#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 10741#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10557#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10558#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10909#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10180#L471-27 assume 1 == ~t5_pc~0; 10181#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10505#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10862#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10795#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10722#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10655#L490-27 assume 1 == ~t6_pc~0; 10554#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10375#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10376#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10779#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 10780#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10147#L509-27 assume 1 == ~t7_pc~0; 10148#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10556#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10437#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10438#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10675#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10687#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10688#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10718#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10939#L867-3 assume !(1 == ~T3_E~0); 10595#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10596#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10682#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10712#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10335#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10336#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10859#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10509#L907-3 assume !(1 == ~E_3~0); 10510#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10635#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10600#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10388#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10389#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10239#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10136#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10446#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10447#L1197 assume !(0 == start_simulation_~tmp~3#1); 10568#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10298#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10262#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10155#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 10156#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10856#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10649#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10161#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 10162#L1178-2 [2024-11-09 16:07:50,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,052 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2024-11-09 16:07:50,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1133571217] [2024-11-09 16:07:50,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:50,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:50,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:50,075 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1133571217] [2024-11-09 16:07:50,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1133571217] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:50,075 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:50,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:50,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507005431] [2024-11-09 16:07:50,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:50,075 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:50,075 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,076 INFO L85 PathProgramCache]: Analyzing trace with hash -542624296, now seen corresponding path program 2 times [2024-11-09 16:07:50,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819328890] [2024-11-09 16:07:50,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:50,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:50,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:50,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1819328890] [2024-11-09 16:07:50,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1819328890] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:50,104 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:50,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:50,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [172516170] [2024-11-09 16:07:50,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:50,105 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:50,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:50,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:50,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:50,105 INFO L87 Difference]: Start difference. First operand 838 states and 1243 transitions. cyclomatic complexity: 406 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:50,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:50,116 INFO L93 Difference]: Finished difference Result 838 states and 1242 transitions. [2024-11-09 16:07:50,116 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1242 transitions. [2024-11-09 16:07:50,119 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:50,122 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1242 transitions. [2024-11-09 16:07:50,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-11-09 16:07:50,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-11-09 16:07:50,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1242 transitions. [2024-11-09 16:07:50,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:50,123 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1242 transitions. [2024-11-09 16:07:50,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1242 transitions. [2024-11-09 16:07:50,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-11-09 16:07:50,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4821002386634845) internal successors, (1242), 837 states have internal predecessors, (1242), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:50,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1242 transitions. [2024-11-09 16:07:50,132 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1242 transitions. [2024-11-09 16:07:50,132 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:50,132 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1242 transitions. [2024-11-09 16:07:50,132 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-09 16:07:50,132 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1242 transitions. [2024-11-09 16:07:50,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-11-09 16:07:50,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:50,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:50,135 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,135 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,136 INFO L745 eck$LassoCheckResult]: Stem: 12022#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12579#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12580#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12559#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 12560#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12267#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12091#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12092#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12073#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12074#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12558#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12383#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12384#L769 assume !(0 == ~M_E~0); 12403#L769-2 assume !(0 == ~T1_E~0); 12404#L774-1 assume !(0 == ~T2_E~0); 12431#L779-1 assume !(0 == ~T3_E~0); 12548#L784-1 assume !(0 == ~T4_E~0); 12381#L789-1 assume !(0 == ~T5_E~0); 12382#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12487#L799-1 assume !(0 == ~T7_E~0); 12386#L804-1 assume !(0 == ~E_M~0); 12387#L809-1 assume !(0 == ~E_1~0); 12426#L814-1 assume !(0 == ~E_2~0); 11810#L819-1 assume !(0 == ~E_3~0); 11811#L824-1 assume !(0 == ~E_4~0); 12164#L829-1 assume !(0 == ~E_5~0); 12607#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11947#L839-1 assume !(0 == ~E_7~0); 11948#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12339#L376 assume !(1 == ~m_pc~0); 12328#L376-2 is_master_triggered_~__retres1~0#1 := 0; 12327#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12533#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11888#L955 assume !(0 != activate_threads_~tmp~1#1); 11889#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12260#L395 assume 1 == ~t1_pc~0; 11924#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11925#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11840#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11841#L963 assume !(0 != activate_threads_~tmp___0~0#1); 12343#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12344#L414 assume !(1 == ~t2_pc~0); 11950#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11951#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12170#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12171#L971 assume !(0 != activate_threads_~tmp___1~0#1); 12563#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12264#L433 assume 1 == ~t3_pc~0; 12206#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12062#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11808#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11809#L979 assume !(0 != activate_threads_~tmp___2~0#1); 11913#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11914#L452 assume !(1 == ~t4_pc~0); 12069#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12070#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11907#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11908#L987 assume !(0 != activate_threads_~tmp___3~0#1); 12102#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12103#L471 assume 1 == ~t5_pc~0; 12474#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12084#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12085#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12536#L995 assume !(0 != activate_threads_~tmp___4~0#1); 12598#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12599#L490 assume 1 == ~t6_pc~0; 12584#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12342#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12157#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12158#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 12274#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12242#L509 assume !(1 == ~t7_pc~0); 12243#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12044#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12045#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12109#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12110#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12569#L857 assume !(1 == ~M_E~0); 11895#L857-2 assume !(1 == ~T1_E~0); 11896#L862-1 assume !(1 == ~T2_E~0); 12174#L867-1 assume !(1 == ~T3_E~0); 12179#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12265#L877-1 assume !(1 == ~T5_E~0); 12450#L882-1 assume !(1 == ~T6_E~0); 12583#L887-1 assume !(1 == ~T7_E~0); 12503#L892-1 assume !(1 == ~E_M~0); 12504#L897-1 assume !(1 == ~E_1~0); 12194#L902-1 assume !(1 == ~E_2~0); 12195#L907-1 assume !(1 == ~E_3~0); 12464#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12456#L917-1 assume !(1 == ~E_5~0); 12457#L922-1 assume !(1 == ~E_6~0); 12609#L927-1 assume !(1 == ~E_7~0); 12445#L932-1 assume { :end_inline_reset_delta_events } true; 11845#L1178-2 [2024-11-09 16:07:50,136 INFO L747 eck$LassoCheckResult]: Loop: 11845#L1178-2 assume !false; 12432#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12433#L744-1 assume !false; 12306#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12307#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11880#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12089#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12191#L641 assume !(0 != eval_~tmp~0#1); 12505#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12314#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12315#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12262#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12263#L774-3 assume !(0 == ~T2_E~0); 12001#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11821#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11822#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11812#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11813#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11862#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12116#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11858#L814-3 assume !(0 == ~E_2~0); 11859#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12524#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12519#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12175#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12176#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12486#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12567#L376-27 assume 1 == ~m_pc~0; 12460#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12409#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12410#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12481#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12611#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12632#L395-27 assume 1 == ~t1_pc~0; 12628#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12177#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12178#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12374#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12269#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12270#L414-27 assume 1 == ~t2_pc~0; 12595#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12455#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12454#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12330#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11870#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11871#L433-27 assume !(1 == ~t3_pc~0); 11973#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 12276#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12277#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12047#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12048#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12623#L452-27 assume 1 == ~t4_pc~0; 12624#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12424#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12240#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12241#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12592#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11863#L471-27 assume 1 == ~t5_pc~0; 11864#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12188#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12545#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12478#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12405#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12338#L490-27 assume 1 == ~t6_pc~0; 12237#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12058#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12059#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12462#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 12463#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11830#L509-27 assume 1 == ~t7_pc~0; 11831#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12239#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12120#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12121#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12358#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12370#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12371#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12401#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12622#L867-3 assume !(1 == ~T3_E~0); 12278#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12279#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12365#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12395#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12018#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12019#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12542#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12192#L907-3 assume !(1 == ~E_3~0); 12193#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12318#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12283#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12071#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12072#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11922#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11819#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12129#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 12130#L1197 assume !(0 == start_simulation_~tmp~3#1); 12251#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11981#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11945#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11838#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 11839#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12539#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12332#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11844#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 11845#L1178-2 [2024-11-09 16:07:50,136 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,136 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2024-11-09 16:07:50,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1811266257] [2024-11-09 16:07:50,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:50,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:50,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:50,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1811266257] [2024-11-09 16:07:50,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1811266257] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:50,193 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:50,193 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:50,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704735723] [2024-11-09 16:07:50,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:50,193 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:50,193 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,193 INFO L85 PathProgramCache]: Analyzing trace with hash -268845801, now seen corresponding path program 3 times [2024-11-09 16:07:50,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,194 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186750405] [2024-11-09 16:07:50,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:50,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:50,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:50,230 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186750405] [2024-11-09 16:07:50,230 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186750405] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:50,230 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:50,230 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:50,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061517409] [2024-11-09 16:07:50,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:50,230 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:50,230 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:50,230 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:07:50,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:07:50,231 INFO L87 Difference]: Start difference. First operand 838 states and 1242 transitions. cyclomatic complexity: 405 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:50,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:50,327 INFO L93 Difference]: Finished difference Result 1515 states and 2236 transitions. [2024-11-09 16:07:50,327 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1515 states and 2236 transitions. [2024-11-09 16:07:50,333 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1396 [2024-11-09 16:07:50,337 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1515 states to 1515 states and 2236 transitions. [2024-11-09 16:07:50,337 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1515 [2024-11-09 16:07:50,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1515 [2024-11-09 16:07:50,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1515 states and 2236 transitions. [2024-11-09 16:07:50,339 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:50,339 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1515 states and 2236 transitions. [2024-11-09 16:07:50,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1515 states and 2236 transitions. [2024-11-09 16:07:50,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1515 to 1515. [2024-11-09 16:07:50,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1515 states, 1515 states have (on average 1.475907590759076) internal successors, (2236), 1514 states have internal predecessors, (2236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:50,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1515 states to 1515 states and 2236 transitions. [2024-11-09 16:07:50,359 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1515 states and 2236 transitions. [2024-11-09 16:07:50,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:07:50,360 INFO L425 stractBuchiCegarLoop]: Abstraction has 1515 states and 2236 transitions. [2024-11-09 16:07:50,360 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-09 16:07:50,360 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1515 states and 2236 transitions. [2024-11-09 16:07:50,365 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1396 [2024-11-09 16:07:50,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:50,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:50,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,366 INFO L745 eck$LassoCheckResult]: Stem: 14385#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14386#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14948#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 14949#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14635#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14455#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14456#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14436#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14437#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14947#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14758#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14759#L769 assume !(0 == ~M_E~0); 14779#L769-2 assume !(0 == ~T1_E~0); 14780#L774-1 assume !(0 == ~T2_E~0); 14809#L779-1 assume !(0 == ~T3_E~0); 14936#L784-1 assume !(0 == ~T4_E~0); 14756#L789-1 assume !(0 == ~T5_E~0); 14757#L794-1 assume !(0 == ~T6_E~0); 14869#L799-1 assume !(0 == ~T7_E~0); 14761#L804-1 assume !(0 == ~E_M~0); 14762#L809-1 assume !(0 == ~E_1~0); 14803#L814-1 assume !(0 == ~E_2~0); 14173#L819-1 assume !(0 == ~E_3~0); 14174#L824-1 assume !(0 == ~E_4~0); 14530#L829-1 assume !(0 == ~E_5~0); 15008#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14310#L839-1 assume !(0 == ~E_7~0); 14311#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14709#L376 assume !(1 == ~m_pc~0); 14696#L376-2 is_master_triggered_~__retres1~0#1 := 0; 14695#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14916#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14251#L955 assume !(0 != activate_threads_~tmp~1#1); 14252#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14628#L395 assume 1 == ~t1_pc~0; 14287#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14288#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14204#L963 assume !(0 != activate_threads_~tmp___0~0#1); 14713#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14714#L414 assume !(1 == ~t2_pc~0); 14313#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14314#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14536#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14537#L971 assume !(0 != activate_threads_~tmp___1~0#1); 14953#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14632#L433 assume 1 == ~t3_pc~0; 14573#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14425#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14171#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14172#L979 assume !(0 != activate_threads_~tmp___2~0#1); 14276#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14277#L452 assume !(1 == ~t4_pc~0); 14432#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14433#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14270#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14271#L987 assume !(0 != activate_threads_~tmp___3~0#1); 14466#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14467#L471 assume 1 == ~t5_pc~0; 14856#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14447#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14448#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14920#L995 assume !(0 != activate_threads_~tmp___4~0#1); 14999#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15000#L490 assume 1 == ~t6_pc~0; 14979#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14712#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14523#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14524#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 14642#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14610#L509 assume !(1 == ~t7_pc~0); 14611#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14407#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14408#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14473#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14474#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14959#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 14258#L857-2 assume !(1 == ~T1_E~0); 14259#L862-1 assume !(1 == ~T2_E~0); 14540#L867-1 assume !(1 == ~T3_E~0); 14545#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14633#L877-1 assume !(1 == ~T5_E~0); 14831#L882-1 assume !(1 == ~T6_E~0); 14978#L887-1 assume !(1 == ~T7_E~0); 15159#L892-1 assume !(1 == ~E_M~0); 15157#L897-1 assume !(1 == ~E_1~0); 15155#L902-1 assume !(1 == ~E_2~0); 15153#L907-1 assume !(1 == ~E_3~0); 14845#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14846#L917-1 assume !(1 == ~E_5~0); 15076#L922-1 assume !(1 == ~E_6~0); 15072#L927-1 assume !(1 == ~E_7~0); 14826#L932-1 assume { :end_inline_reset_delta_events } true; 14208#L1178-2 [2024-11-09 16:07:50,366 INFO L747 eck$LassoCheckResult]: Loop: 14208#L1178-2 assume !false; 14810#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14811#L744-1 assume !false; 14674#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14675#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14243#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14453#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14558#L641 assume !(0 != eval_~tmp~0#1); 14887#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14682#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14683#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14630#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14631#L774-3 assume !(0 == ~T2_E~0); 14364#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14184#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14185#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14175#L794-3 assume !(0 == ~T6_E~0); 14176#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14225#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14480#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14221#L814-3 assume !(0 == ~E_2~0); 14222#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14907#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14902#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14541#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14542#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14868#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14957#L376-27 assume 1 == ~m_pc~0; 14841#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14785#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14786#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14863#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15012#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15040#L395-27 assume 1 == ~t1_pc~0; 15032#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14543#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14544#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14749#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14637#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14638#L414-27 assume 1 == ~t2_pc~0; 14992#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14836#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14835#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14698#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14233#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14234#L433-27 assume !(1 == ~t3_pc~0); 14336#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 14644#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14645#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14410#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14411#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15026#L452-27 assume !(1 == ~t4_pc~0); 14800#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 14801#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14608#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14609#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14989#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14997#L471-27 assume !(1 == ~t5_pc~0); 15146#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15145#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15144#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15143#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15142#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15141#L490-27 assume 1 == ~t6_pc~0; 15139#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15138#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15134#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15132#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 15130#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15129#L509-27 assume 1 == ~t7_pc~0; 14739#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14607#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14484#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14485#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14729#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15037#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14745#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14777#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15024#L867-3 assume !(1 == ~T3_E~0); 14646#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14647#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14738#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14771#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14381#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14382#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14927#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14559#L907-3 assume !(1 == ~E_3~0); 14560#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14686#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14951#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15099#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15098#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15097#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15088#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15086#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 15085#L1197 assume !(0 == start_simulation_~tmp~3#1); 15031#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15084#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15068#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15067#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 15066#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15065#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14700#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 14207#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 14208#L1178-2 [2024-11-09 16:07:50,366 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,366 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2024-11-09 16:07:50,366 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,366 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137854843] [2024-11-09 16:07:50,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:50,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:50,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:50,412 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137854843] [2024-11-09 16:07:50,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1137854843] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:50,412 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:50,412 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:50,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115337623] [2024-11-09 16:07:50,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:50,413 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:50,413 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,413 INFO L85 PathProgramCache]: Analyzing trace with hash 864207127, now seen corresponding path program 1 times [2024-11-09 16:07:50,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1645550140] [2024-11-09 16:07:50,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:50,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:50,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:50,444 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1645550140] [2024-11-09 16:07:50,444 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1645550140] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:50,444 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:50,444 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:50,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677328294] [2024-11-09 16:07:50,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:50,445 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:50,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:50,445 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:07:50,445 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:07:50,445 INFO L87 Difference]: Start difference. First operand 1515 states and 2236 transitions. cyclomatic complexity: 723 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:50,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:50,599 INFO L93 Difference]: Finished difference Result 2735 states and 4023 transitions. [2024-11-09 16:07:50,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2735 states and 4023 transitions. [2024-11-09 16:07:50,609 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2602 [2024-11-09 16:07:50,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2735 states to 2735 states and 4023 transitions. [2024-11-09 16:07:50,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2735 [2024-11-09 16:07:50,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2735 [2024-11-09 16:07:50,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2735 states and 4023 transitions. [2024-11-09 16:07:50,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:50,622 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2735 states and 4023 transitions. [2024-11-09 16:07:50,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2735 states and 4023 transitions. [2024-11-09 16:07:50,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2735 to 2733. [2024-11-09 16:07:50,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2733 states, 2733 states have (on average 1.4712769849981706) internal successors, (4021), 2732 states have internal predecessors, (4021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:50,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2733 states to 2733 states and 4021 transitions. [2024-11-09 16:07:50,654 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2733 states and 4021 transitions. [2024-11-09 16:07:50,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:07:50,654 INFO L425 stractBuchiCegarLoop]: Abstraction has 2733 states and 4021 transitions. [2024-11-09 16:07:50,655 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-09 16:07:50,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2733 states and 4021 transitions. [2024-11-09 16:07:50,660 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2602 [2024-11-09 16:07:50,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:50,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:50,661 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,661 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,661 INFO L745 eck$LassoCheckResult]: Stem: 18647#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19216#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19217#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19194#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 19195#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18893#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18714#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18715#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18696#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18697#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19193#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19012#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19013#L769 assume !(0 == ~M_E~0); 19032#L769-2 assume !(0 == ~T1_E~0); 19033#L774-1 assume !(0 == ~T2_E~0); 19060#L779-1 assume !(0 == ~T3_E~0); 19181#L784-1 assume !(0 == ~T4_E~0); 19010#L789-1 assume !(0 == ~T5_E~0); 19011#L794-1 assume !(0 == ~T6_E~0); 19117#L799-1 assume !(0 == ~T7_E~0); 19015#L804-1 assume !(0 == ~E_M~0); 19016#L809-1 assume !(0 == ~E_1~0); 19055#L814-1 assume !(0 == ~E_2~0); 18435#L819-1 assume !(0 == ~E_3~0); 18436#L824-1 assume !(0 == ~E_4~0); 18789#L829-1 assume !(0 == ~E_5~0); 19245#L834-1 assume !(0 == ~E_6~0); 18570#L839-1 assume !(0 == ~E_7~0); 18571#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18966#L376 assume !(1 == ~m_pc~0); 18959#L376-2 is_master_triggered_~__retres1~0#1 := 0; 18958#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19165#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18513#L955 assume !(0 != activate_threads_~tmp~1#1); 18514#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18886#L395 assume 1 == ~t1_pc~0; 18547#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18548#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18463#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18464#L963 assume !(0 != activate_threads_~tmp___0~0#1); 18971#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18972#L414 assume !(1 == ~t2_pc~0); 18573#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18574#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18795#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18796#L971 assume !(0 != activate_threads_~tmp___1~0#1); 19198#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18890#L433 assume 1 == ~t3_pc~0; 18832#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18687#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18431#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18432#L979 assume !(0 != activate_threads_~tmp___2~0#1); 18536#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18537#L452 assume !(1 == ~t4_pc~0); 18692#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18693#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18530#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18531#L987 assume !(0 != activate_threads_~tmp___3~0#1); 18725#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18726#L471 assume 1 == ~t5_pc~0; 19103#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18707#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18708#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19168#L995 assume !(0 != activate_threads_~tmp___4~0#1); 19236#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19237#L490 assume 1 == ~t6_pc~0; 19222#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18969#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18782#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18783#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 18902#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18868#L509 assume !(1 == ~t7_pc~0); 18869#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18672#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18673#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18732#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18733#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19204#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 19205#L857-2 assume !(1 == ~T1_E~0); 19402#L862-1 assume !(1 == ~T2_E~0); 18804#L867-1 assume !(1 == ~T3_E~0); 18805#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18891#L877-1 assume !(1 == ~T5_E~0); 19079#L882-1 assume !(1 == ~T6_E~0); 19220#L887-1 assume !(1 == ~T7_E~0); 19133#L892-1 assume !(1 == ~E_M~0); 19134#L897-1 assume !(1 == ~E_1~0); 19352#L902-1 assume !(1 == ~E_2~0); 19350#L907-1 assume !(1 == ~E_3~0); 19095#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19085#L917-1 assume !(1 == ~E_5~0); 19086#L922-1 assume !(1 == ~E_6~0); 19322#L927-1 assume !(1 == ~E_7~0); 19314#L932-1 assume { :end_inline_reset_delta_events } true; 19308#L1178-2 [2024-11-09 16:07:50,662 INFO L747 eck$LassoCheckResult]: Loop: 19308#L1178-2 assume !false; 19304#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19303#L744-1 assume !false; 19302#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19301#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19293#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19292#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19290#L641 assume !(0 != eval_~tmp~0#1); 19289#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19288#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19286#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19287#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20481#L774-3 assume !(0 == ~T2_E~0); 20156#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20147#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20145#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20143#L794-3 assume !(0 == ~T6_E~0); 20141#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20139#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20137#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20135#L814-3 assume !(0 == ~E_2~0); 20116#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20113#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20110#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20106#L834-3 assume !(0 == ~E_6~0); 20103#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20100#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20097#L376-27 assume 1 == ~m_pc~0; 20073#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20069#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20065#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20049#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20044#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20038#L395-27 assume !(1 == ~t1_pc~0); 20030#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 20025#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20021#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20016#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20012#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20006#L414-27 assume 1 == ~t2_pc~0; 19998#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19993#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19988#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19981#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19976#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19971#L433-27 assume !(1 == ~t3_pc~0); 19963#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 19958#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19953#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19946#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19941#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19937#L452-27 assume 1 == ~t4_pc~0; 19930#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19851#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19849#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19847#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19844#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19842#L471-27 assume 1 == ~t5_pc~0; 19840#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19837#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19767#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19765#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19763#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19761#L490-27 assume 1 == ~t6_pc~0; 19758#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19756#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19753#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19752#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 19722#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19721#L509-27 assume 1 == ~t7_pc~0; 19719#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19716#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19714#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19712#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19710#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19708#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18998#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19705#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19703#L867-3 assume !(1 == ~T3_E~0); 19701#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19685#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19641#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19638#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19636#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19635#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19634#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19633#L907-3 assume !(1 == ~E_3~0); 19631#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19628#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19604#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19599#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19594#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19586#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19575#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19572#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 19571#L1197 assume !(0 == start_simulation_~tmp~3#1); 19278#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19370#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19360#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19358#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 19336#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19332#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19323#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19315#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 19308#L1178-2 [2024-11-09 16:07:50,662 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,662 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2024-11-09 16:07:50,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294681540] [2024-11-09 16:07:50,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:50,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:50,698 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:50,698 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294681540] [2024-11-09 16:07:50,698 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1294681540] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:50,699 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:50,699 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:50,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784967173] [2024-11-09 16:07:50,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:50,699 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:50,699 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,700 INFO L85 PathProgramCache]: Analyzing trace with hash -66395884, now seen corresponding path program 1 times [2024-11-09 16:07:50,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [700330558] [2024-11-09 16:07:50,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:50,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:50,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:50,733 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [700330558] [2024-11-09 16:07:50,733 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [700330558] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:50,733 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:50,733 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:50,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [323462350] [2024-11-09 16:07:50,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:50,734 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:50,734 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:50,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:50,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:50,734 INFO L87 Difference]: Start difference. First operand 2733 states and 4021 transitions. cyclomatic complexity: 1292 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:50,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:50,798 INFO L93 Difference]: Finished difference Result 5067 states and 7400 transitions. [2024-11-09 16:07:50,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5067 states and 7400 transitions. [2024-11-09 16:07:50,813 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4929 [2024-11-09 16:07:50,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5067 states to 5067 states and 7400 transitions. [2024-11-09 16:07:50,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5067 [2024-11-09 16:07:50,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5067 [2024-11-09 16:07:50,831 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5067 states and 7400 transitions. [2024-11-09 16:07:50,835 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:50,835 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5067 states and 7400 transitions. [2024-11-09 16:07:50,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5067 states and 7400 transitions. [2024-11-09 16:07:50,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5067 to 5059. [2024-11-09 16:07:50,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5059 states, 5059 states have (on average 1.4611583316861039) internal successors, (7392), 5058 states have internal predecessors, (7392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:50,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5059 states to 5059 states and 7392 transitions. [2024-11-09 16:07:50,898 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5059 states and 7392 transitions. [2024-11-09 16:07:50,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:50,899 INFO L425 stractBuchiCegarLoop]: Abstraction has 5059 states and 7392 transitions. [2024-11-09 16:07:50,899 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-09 16:07:50,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5059 states and 7392 transitions. [2024-11-09 16:07:50,910 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4921 [2024-11-09 16:07:50,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:50,910 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:50,911 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,911 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,912 INFO L745 eck$LassoCheckResult]: Stem: 26452#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 26453#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 27094#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27095#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27063#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 27064#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26708#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26527#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26528#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26507#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26508#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27060#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26841#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26842#L769 assume !(0 == ~M_E~0); 26862#L769-2 assume !(0 == ~T1_E~0); 26863#L774-1 assume !(0 == ~T2_E~0); 26898#L779-1 assume !(0 == ~T3_E~0); 27047#L784-1 assume !(0 == ~T4_E~0); 26839#L789-1 assume !(0 == ~T5_E~0); 26840#L794-1 assume !(0 == ~T6_E~0); 26965#L799-1 assume !(0 == ~T7_E~0); 26844#L804-1 assume !(0 == ~E_M~0); 26845#L809-1 assume !(0 == ~E_1~0); 26890#L814-1 assume !(0 == ~E_2~0); 26242#L819-1 assume !(0 == ~E_3~0); 26243#L824-1 assume !(0 == ~E_4~0); 26600#L829-1 assume !(0 == ~E_5~0); 27144#L834-1 assume !(0 == ~E_6~0); 26376#L839-1 assume !(0 == ~E_7~0); 26377#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26791#L376 assume !(1 == ~m_pc~0); 26779#L376-2 is_master_triggered_~__retres1~0#1 := 0; 26778#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27024#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26319#L955 assume !(0 != activate_threads_~tmp~1#1); 26320#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26701#L395 assume !(1 == ~t1_pc~0); 26864#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27026#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26270#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26271#L963 assume !(0 != activate_threads_~tmp___0~0#1); 26796#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26797#L414 assume !(1 == ~t2_pc~0); 26379#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26380#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26608#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26609#L971 assume !(0 != activate_threads_~tmp___1~0#1); 27070#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26705#L433 assume 1 == ~t3_pc~0; 26645#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26498#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26238#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26239#L979 assume !(0 != activate_threads_~tmp___2~0#1); 26343#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26344#L452 assume !(1 == ~t4_pc~0); 26503#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26504#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26337#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26338#L987 assume !(0 != activate_threads_~tmp___3~0#1); 26538#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26539#L471 assume 1 == ~t5_pc~0; 26947#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26519#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26520#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27029#L995 assume !(0 != activate_threads_~tmp___4~0#1); 27133#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27134#L490 assume 1 == ~t6_pc~0; 27103#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26794#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26594#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26595#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 26717#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26683#L509 assume !(1 == ~t7_pc~0); 26684#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26478#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26479#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26545#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26546#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27079#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 27080#L857-2 assume !(1 == ~T1_E~0); 29842#L862-1 assume !(1 == ~T2_E~0); 26617#L867-1 assume !(1 == ~T3_E~0); 26618#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26706#L877-1 assume !(1 == ~T5_E~0); 27100#L882-1 assume !(1 == ~T6_E~0); 27101#L887-1 assume !(1 == ~T7_E~0); 26985#L892-1 assume !(1 == ~E_M~0); 26986#L897-1 assume !(1 == ~E_1~0); 26635#L902-1 assume !(1 == ~E_2~0); 26636#L907-1 assume !(1 == ~E_3~0); 26939#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 26926#L917-1 assume !(1 == ~E_5~0); 26927#L922-1 assume !(1 == ~E_6~0); 27146#L927-1 assume !(1 == ~E_7~0); 26912#L932-1 assume { :end_inline_reset_delta_events } true; 26913#L1178-2 [2024-11-09 16:07:50,912 INFO L747 eck$LassoCheckResult]: Loop: 26913#L1178-2 assume !false; 27447#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27087#L744-1 assume !false; 27440#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27431#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 26524#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 26525#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26632#L641 assume !(0 != eval_~tmp~0#1); 26988#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26760#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26761#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26703#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26704#L774-3 assume !(0 == ~T2_E~0); 26430#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26251#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26252#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26244#L794-3 assume !(0 == ~T6_E~0); 26245#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26291#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26553#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26289#L814-3 assume !(0 == ~E_2~0); 26290#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27013#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27006#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26613#L834-3 assume !(0 == ~E_6~0); 26614#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26964#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31175#L376-27 assume 1 == ~m_pc~0; 31173#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 31172#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31171#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31170#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31169#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31168#L395-27 assume !(1 == ~t1_pc~0); 31167#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 31166#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31165#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31164#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31163#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31162#L414-27 assume 1 == ~t2_pc~0; 31159#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31156#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31155#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31154#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31153#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31152#L433-27 assume !(1 == ~t3_pc~0); 31150#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 31149#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31148#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31147#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31146#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31145#L452-27 assume 1 == ~t4_pc~0; 31143#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31142#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31141#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31140#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31139#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31138#L471-27 assume !(1 == ~t5_pc~0); 31136#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 31135#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31134#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31132#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31119#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31117#L490-27 assume 1 == ~t6_pc~0; 31114#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31111#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31108#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31105#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 31102#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31097#L509-27 assume 1 == ~t7_pc~0; 31091#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31087#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31084#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31081#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31078#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31075#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26825#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31070#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27173#L867-3 assume !(1 == ~T3_E~0); 26719#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26720#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26819#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26854#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26446#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26447#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27037#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26630#L907-3 assume !(1 == ~E_3~0); 26631#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26765#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26723#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26505#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26506#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 26353#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 26247#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 26565#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 26566#L1197 assume !(0 == start_simulation_~tmp~3#1); 26690#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27545#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27536#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27535#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 27531#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27525#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27461#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 27455#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 26913#L1178-2 [2024-11-09 16:07:50,913 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,913 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2024-11-09 16:07:50,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,913 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308590919] [2024-11-09 16:07:50,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:50,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:50,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:50,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308590919] [2024-11-09 16:07:50,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308590919] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:50,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:50,948 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:50,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984295837] [2024-11-09 16:07:50,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:50,948 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:50,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,949 INFO L85 PathProgramCache]: Analyzing trace with hash -1959838059, now seen corresponding path program 1 times [2024-11-09 16:07:50,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1385033796] [2024-11-09 16:07:50,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:51,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:51,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:51,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:51,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1385033796] [2024-11-09 16:07:51,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1385033796] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:51,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:51,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:51,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [851562204] [2024-11-09 16:07:51,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:51,023 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:51,023 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:51,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:51,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:51,024 INFO L87 Difference]: Start difference. First operand 5059 states and 7392 transitions. cyclomatic complexity: 2341 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:51,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:51,095 INFO L93 Difference]: Finished difference Result 9453 states and 13724 transitions. [2024-11-09 16:07:51,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9453 states and 13724 transitions. [2024-11-09 16:07:51,123 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9300 [2024-11-09 16:07:51,151 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9453 states to 9453 states and 13724 transitions. [2024-11-09 16:07:51,151 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9453 [2024-11-09 16:07:51,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9453 [2024-11-09 16:07:51,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9453 states and 13724 transitions. [2024-11-09 16:07:51,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:51,165 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9453 states and 13724 transitions. [2024-11-09 16:07:51,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9453 states and 13724 transitions. [2024-11-09 16:07:51,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9453 to 9437. [2024-11-09 16:07:51,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9437 states, 9437 states have (on average 1.4525802691533327) internal successors, (13708), 9436 states have internal predecessors, (13708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:51,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9437 states to 9437 states and 13708 transitions. [2024-11-09 16:07:51,278 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9437 states and 13708 transitions. [2024-11-09 16:07:51,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:51,279 INFO L425 stractBuchiCegarLoop]: Abstraction has 9437 states and 13708 transitions. [2024-11-09 16:07:51,279 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-09 16:07:51,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9437 states and 13708 transitions. [2024-11-09 16:07:51,300 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9284 [2024-11-09 16:07:51,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:51,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:51,301 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:51,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:51,301 INFO L745 eck$LassoCheckResult]: Stem: 40971#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 40972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 41577#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41578#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41551#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 41552#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41216#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41041#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41042#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41023#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41024#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41550#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41345#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41346#L769 assume !(0 == ~M_E~0); 41367#L769-2 assume !(0 == ~T1_E~0); 41368#L774-1 assume !(0 == ~T2_E~0); 41400#L779-1 assume !(0 == ~T3_E~0); 41535#L784-1 assume !(0 == ~T4_E~0); 41342#L789-1 assume !(0 == ~T5_E~0); 41343#L794-1 assume !(0 == ~T6_E~0); 41462#L799-1 assume !(0 == ~T7_E~0); 41348#L804-1 assume !(0 == ~E_M~0); 41349#L809-1 assume !(0 == ~E_1~0); 41392#L814-1 assume !(0 == ~E_2~0); 40763#L819-1 assume !(0 == ~E_3~0); 40764#L824-1 assume !(0 == ~E_4~0); 41115#L829-1 assume !(0 == ~E_5~0); 41621#L834-1 assume !(0 == ~E_6~0); 40894#L839-1 assume !(0 == ~E_7~0); 40895#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41293#L376 assume !(1 == ~m_pc~0); 41285#L376-2 is_master_triggered_~__retres1~0#1 := 0; 41284#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41514#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40838#L955 assume !(0 != activate_threads_~tmp~1#1); 40839#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41209#L395 assume !(1 == ~t1_pc~0); 41369#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41517#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40789#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40790#L963 assume !(0 != activate_threads_~tmp___0~0#1); 41298#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41299#L414 assume !(1 == ~t2_pc~0); 40897#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40898#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41121#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41122#L971 assume !(0 != activate_threads_~tmp___1~0#1); 41555#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41213#L433 assume !(1 == ~t3_pc~0); 41013#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41014#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40757#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40758#L979 assume !(0 != activate_threads_~tmp___2~0#1); 40862#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40863#L452 assume !(1 == ~t4_pc~0); 41019#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41020#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40856#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40857#L987 assume !(0 != activate_threads_~tmp___3~0#1); 41053#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41054#L471 assume 1 == ~t5_pc~0; 41448#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41036#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41037#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41518#L995 assume !(0 != activate_threads_~tmp___4~0#1); 41612#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41613#L490 assume 1 == ~t6_pc~0; 41585#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41296#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41109#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41110#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 41227#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41191#L509 assume !(1 == ~t7_pc~0); 41192#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 40999#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41000#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41060#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41061#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41563#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 40843#L857-2 assume !(1 == ~T1_E~0); 40844#L862-1 assume !(1 == ~T2_E~0); 41125#L867-1 assume !(1 == ~T3_E~0); 41130#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41214#L877-1 assume !(1 == ~T5_E~0); 41423#L882-1 assume !(1 == ~T6_E~0); 41583#L887-1 assume !(1 == ~T7_E~0); 42509#L892-1 assume !(1 == ~E_M~0); 42506#L897-1 assume !(1 == ~E_1~0); 42504#L902-1 assume !(1 == ~E_2~0); 42502#L907-1 assume !(1 == ~E_3~0); 42500#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 42498#L917-1 assume !(1 == ~E_5~0); 42496#L922-1 assume !(1 == ~E_6~0); 42492#L927-1 assume !(1 == ~E_7~0); 42460#L932-1 assume { :end_inline_reset_delta_events } true; 42458#L1178-2 [2024-11-09 16:07:51,301 INFO L747 eck$LassoCheckResult]: Loop: 42458#L1178-2 assume !false; 42341#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42339#L744-1 assume !false; 42337#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 42335#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 42326#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 42323#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42320#L641 assume !(0 != eval_~tmp~0#1); 42321#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49902#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49901#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49900#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49899#L774-3 assume !(0 == ~T2_E~0); 49898#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49897#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49896#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49895#L794-3 assume !(0 == ~T6_E~0); 49894#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49892#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49890#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49888#L814-3 assume !(0 == ~E_2~0); 49886#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49884#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49882#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49880#L834-3 assume !(0 == ~E_6~0); 49878#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49876#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49874#L376-27 assume !(1 == ~m_pc~0); 49872#L376-29 is_master_triggered_~__retres1~0#1 := 0; 49869#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49867#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49865#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49863#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49861#L395-27 assume !(1 == ~t1_pc~0); 49859#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 49857#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49855#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49852#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49850#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49848#L414-27 assume 1 == ~t2_pc~0; 41688#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41658#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49819#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49818#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49688#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49687#L433-27 assume !(1 == ~t3_pc~0); 49529#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 45574#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45571#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45569#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45567#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45565#L452-27 assume 1 == ~t4_pc~0; 45562#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45560#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45557#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45555#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45553#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45551#L471-27 assume !(1 == ~t5_pc~0); 45547#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 45544#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45542#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45540#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45538#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45536#L490-27 assume 1 == ~t6_pc~0; 45533#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45530#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45528#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45526#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 45524#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45522#L509-27 assume 1 == ~t7_pc~0; 45520#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45518#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45516#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45514#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45512#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45510#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44834#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45505#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45503#L867-3 assume !(1 == ~T3_E~0); 45501#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45497#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44820#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44817#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44815#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44813#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44811#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44809#L907-3 assume !(1 == ~E_3~0); 44807#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44034#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44031#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44028#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44026#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43247#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43238#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43236#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 43234#L1197 assume !(0 == start_simulation_~tmp~3#1); 43231#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 42480#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 42471#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 42469#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 42467#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42465#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42463#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 42461#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 42458#L1178-2 [2024-11-09 16:07:51,301 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:51,301 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2024-11-09 16:07:51,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:51,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788543884] [2024-11-09 16:07:51,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:51,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:51,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:51,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:51,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:51,343 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788543884] [2024-11-09 16:07:51,344 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788543884] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:51,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:51,345 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:51,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2129700806] [2024-11-09 16:07:51,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:51,345 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:51,345 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:51,345 INFO L85 PathProgramCache]: Analyzing trace with hash 492815446, now seen corresponding path program 1 times [2024-11-09 16:07:51,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:51,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175865411] [2024-11-09 16:07:51,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:51,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:51,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:51,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:51,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:51,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175865411] [2024-11-09 16:07:51,441 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [175865411] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:51,441 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:51,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:51,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1087835725] [2024-11-09 16:07:51,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:51,442 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:51,442 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:51,442 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:51,442 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:51,443 INFO L87 Difference]: Start difference. First operand 9437 states and 13708 transitions. cyclomatic complexity: 4287 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:51,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:51,543 INFO L93 Difference]: Finished difference Result 18156 states and 26197 transitions. [2024-11-09 16:07:51,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18156 states and 26197 transitions. [2024-11-09 16:07:51,620 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17948 [2024-11-09 16:07:51,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18156 states to 18156 states and 26197 transitions. [2024-11-09 16:07:51,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18156 [2024-11-09 16:07:51,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18156 [2024-11-09 16:07:51,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18156 states and 26197 transitions. [2024-11-09 16:07:51,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:51,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18156 states and 26197 transitions. [2024-11-09 16:07:51,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18156 states and 26197 transitions. [2024-11-09 16:07:51,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18156 to 18124. [2024-11-09 16:07:51,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18124 states, 18124 states have (on average 1.4436658574266166) internal successors, (26165), 18123 states have internal predecessors, (26165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:51,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18124 states to 18124 states and 26165 transitions. [2024-11-09 16:07:51,981 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18124 states and 26165 transitions. [2024-11-09 16:07:51,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:51,981 INFO L425 stractBuchiCegarLoop]: Abstraction has 18124 states and 26165 transitions. [2024-11-09 16:07:51,981 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-09 16:07:51,982 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18124 states and 26165 transitions. [2024-11-09 16:07:52,023 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17916 [2024-11-09 16:07:52,023 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:52,023 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:52,024 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:52,024 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:52,024 INFO L745 eck$LassoCheckResult]: Stem: 68570#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 68571#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 69238#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69239#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69198#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 69199#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68827#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68646#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68647#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68626#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68627#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69197#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68963#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68964#L769 assume !(0 == ~M_E~0); 68988#L769-2 assume !(0 == ~T1_E~0); 68989#L774-1 assume !(0 == ~T2_E~0); 69023#L779-1 assume !(0 == ~T3_E~0); 69179#L784-1 assume !(0 == ~T4_E~0); 68961#L789-1 assume !(0 == ~T5_E~0); 68962#L794-1 assume !(0 == ~T6_E~0); 69090#L799-1 assume !(0 == ~T7_E~0); 68966#L804-1 assume !(0 == ~E_M~0); 68967#L809-1 assume !(0 == ~E_1~0); 69015#L814-1 assume !(0 == ~E_2~0); 68359#L819-1 assume !(0 == ~E_3~0); 68360#L824-1 assume !(0 == ~E_4~0); 68719#L829-1 assume !(0 == ~E_5~0); 69290#L834-1 assume !(0 == ~E_6~0); 68494#L839-1 assume !(0 == ~E_7~0); 68495#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68912#L376 assume !(1 == ~m_pc~0); 68899#L376-2 is_master_triggered_~__retres1~0#1 := 0; 68898#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69154#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68438#L955 assume !(0 != activate_threads_~tmp~1#1); 68439#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68818#L395 assume !(1 == ~t1_pc~0); 68990#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69156#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68389#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68390#L963 assume !(0 != activate_threads_~tmp___0~0#1); 68917#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68918#L414 assume !(1 == ~t2_pc~0); 68497#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68498#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68726#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68727#L971 assume !(0 != activate_threads_~tmp___1~0#1); 69207#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68823#L433 assume !(1 == ~t3_pc~0); 68616#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68617#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68357#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68358#L979 assume !(0 != activate_threads_~tmp___2~0#1); 68461#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68462#L452 assume !(1 == ~t4_pc~0); 68622#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68623#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68455#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68456#L987 assume !(0 != activate_threads_~tmp___3~0#1); 68657#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68658#L471 assume !(1 == ~t5_pc~0); 69074#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68639#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69159#L995 assume !(0 != activate_threads_~tmp___4~0#1); 69279#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69280#L490 assume 1 == ~t6_pc~0; 69249#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68915#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68713#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68714#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 68834#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68798#L509 assume !(1 == ~t7_pc~0); 68799#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68595#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68596#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68664#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 68665#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69220#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 68443#L857-2 assume !(1 == ~T1_E~0); 68444#L862-1 assume !(1 == ~T2_E~0); 68730#L867-1 assume !(1 == ~T3_E~0); 68735#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68824#L877-1 assume !(1 == ~T5_E~0); 69044#L882-1 assume !(1 == ~T6_E~0); 71093#L887-1 assume !(1 == ~T7_E~0); 71090#L892-1 assume !(1 == ~E_M~0); 71088#L897-1 assume !(1 == ~E_1~0); 71086#L902-1 assume !(1 == ~E_2~0); 71084#L907-1 assume !(1 == ~E_3~0); 69064#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69051#L917-1 assume !(1 == ~E_5~0); 69052#L922-1 assume !(1 == ~E_6~0); 70997#L927-1 assume !(1 == ~E_7~0); 70966#L932-1 assume { :end_inline_reset_delta_events } true; 70944#L1178-2 [2024-11-09 16:07:52,024 INFO L747 eck$LassoCheckResult]: Loop: 70944#L1178-2 assume !false; 70933#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70902#L744-1 assume !false; 70894#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 70837#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 70827#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 70825#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 70822#L641 assume !(0 != eval_~tmp~0#1); 70823#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 71878#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 71876#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 71874#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 71872#L774-3 assume !(0 == ~T2_E~0); 71870#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 71868#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 71865#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 71863#L794-3 assume !(0 == ~T6_E~0); 71861#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 71859#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 71857#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 71856#L814-3 assume !(0 == ~E_2~0); 71855#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 71854#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 71853#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71852#L834-3 assume !(0 == ~E_6~0); 71851#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 71850#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71849#L376-27 assume !(1 == ~m_pc~0); 71733#L376-29 is_master_triggered_~__retres1~0#1 := 0; 71730#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71727#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 71725#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 71723#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71721#L395-27 assume !(1 == ~t1_pc~0); 71719#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 71717#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71715#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 71713#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 71711#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71709#L414-27 assume !(1 == ~t2_pc~0); 71707#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 71704#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71702#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 71700#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 71698#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71696#L433-27 assume !(1 == ~t3_pc~0); 71694#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 71692#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71690#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 71688#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 71686#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71683#L452-27 assume !(1 == ~t4_pc~0); 71681#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 71678#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71676#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 71674#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 71672#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71670#L471-27 assume !(1 == ~t5_pc~0); 71668#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 71666#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71664#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 71662#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 71660#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 71657#L490-27 assume !(1 == ~t6_pc~0); 71655#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 71652#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 71650#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71648#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 71646#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 71643#L509-27 assume !(1 == ~t7_pc~0); 71641#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 71638#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71636#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 71634#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 71632#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71629#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 71392#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 71624#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 71622#L867-3 assume !(1 == ~T3_E~0); 71620#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 71618#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 71616#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 71612#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 71610#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 71608#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 71606#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 71604#L907-3 assume !(1 == ~E_3~0); 71601#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 71599#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 71184#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 71180#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 71178#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 71176#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 71167#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 71165#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 71163#L1197 assume !(0 == start_simulation_~tmp~3#1); 71161#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 71046#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 71037#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 71035#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 71033#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 71032#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 71000#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 70967#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 70944#L1178-2 [2024-11-09 16:07:52,025 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:52,025 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2024-11-09 16:07:52,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:52,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834707803] [2024-11-09 16:07:52,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:52,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:52,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:52,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:52,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:52,119 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834707803] [2024-11-09 16:07:52,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1834707803] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:52,119 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:52,119 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:52,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1646277141] [2024-11-09 16:07:52,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:52,119 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:52,120 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:52,120 INFO L85 PathProgramCache]: Analyzing trace with hash 1162954138, now seen corresponding path program 1 times [2024-11-09 16:07:52,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:52,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744783374] [2024-11-09 16:07:52,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:52,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:52,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:52,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:52,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:52,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744783374] [2024-11-09 16:07:52,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744783374] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:52,147 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:52,147 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:52,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [557003551] [2024-11-09 16:07:52,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:52,148 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:52,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:52,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:52,148 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:52,149 INFO L87 Difference]: Start difference. First operand 18124 states and 26165 transitions. cyclomatic complexity: 8073 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:52,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:52,272 INFO L93 Difference]: Finished difference Result 34071 states and 48958 transitions. [2024-11-09 16:07:52,272 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34071 states and 48958 transitions. [2024-11-09 16:07:52,393 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 33720 [2024-11-09 16:07:52,486 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34071 states to 34071 states and 48958 transitions. [2024-11-09 16:07:52,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34071 [2024-11-09 16:07:52,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34071 [2024-11-09 16:07:52,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34071 states and 48958 transitions. [2024-11-09 16:07:52,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:52,546 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34071 states and 48958 transitions. [2024-11-09 16:07:52,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34071 states and 48958 transitions. [2024-11-09 16:07:52,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34071 to 34007. [2024-11-09 16:07:52,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34007 states, 34007 states have (on average 1.437762813538389) internal successors, (48894), 34006 states have internal predecessors, (48894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:53,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34007 states to 34007 states and 48894 transitions. [2024-11-09 16:07:53,053 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34007 states and 48894 transitions. [2024-11-09 16:07:53,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:53,054 INFO L425 stractBuchiCegarLoop]: Abstraction has 34007 states and 48894 transitions. [2024-11-09 16:07:53,054 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-09 16:07:53,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34007 states and 48894 transitions. [2024-11-09 16:07:53,295 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 33656 [2024-11-09 16:07:53,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:53,295 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:53,296 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:53,296 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:53,296 INFO L745 eck$LassoCheckResult]: Stem: 120774#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 120775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 121393#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 121394#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 121365#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 121366#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121027#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 120845#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 120846#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 120827#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 120828#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 121363#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 121154#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 121155#L769 assume !(0 == ~M_E~0); 121177#L769-2 assume !(0 == ~T1_E~0); 121178#L774-1 assume !(0 == ~T2_E~0); 121207#L779-1 assume !(0 == ~T3_E~0); 121345#L784-1 assume !(0 == ~T4_E~0); 121152#L789-1 assume !(0 == ~T5_E~0); 121153#L794-1 assume !(0 == ~T6_E~0); 121269#L799-1 assume !(0 == ~T7_E~0); 121157#L804-1 assume !(0 == ~E_M~0); 121158#L809-1 assume !(0 == ~E_1~0); 121202#L814-1 assume !(0 == ~E_2~0); 120561#L819-1 assume !(0 == ~E_3~0); 120562#L824-1 assume !(0 == ~E_4~0); 120919#L829-1 assume !(0 == ~E_5~0); 121433#L834-1 assume !(0 == ~E_6~0); 120697#L839-1 assume !(0 == ~E_7~0); 120698#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121107#L376 assume !(1 == ~m_pc~0); 121091#L376-2 is_master_triggered_~__retres1~0#1 := 0; 121090#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121328#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 120639#L955 assume !(0 != activate_threads_~tmp~1#1); 120640#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121019#L395 assume !(1 == ~t1_pc~0); 121179#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 121329#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120591#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 120592#L963 assume !(0 != activate_threads_~tmp___0~0#1); 121113#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121114#L414 assume !(1 == ~t2_pc~0); 120700#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 120701#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 120925#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 120926#L971 assume !(0 != activate_threads_~tmp___1~0#1); 121372#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 121024#L433 assume !(1 == ~t3_pc~0); 120814#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 120815#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120559#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 120560#L979 assume !(0 != activate_threads_~tmp___2~0#1); 120665#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120666#L452 assume !(1 == ~t4_pc~0); 120823#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 120824#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 120659#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 120660#L987 assume !(0 != activate_threads_~tmp___3~0#1); 120855#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 120856#L471 assume !(1 == ~t5_pc~0); 121254#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 120838#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 120839#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121332#L995 assume !(0 != activate_threads_~tmp___4~0#1); 121420#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121421#L490 assume !(1 == ~t6_pc~0); 121111#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 121112#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 120913#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 120914#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 121035#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 121000#L509 assume !(1 == ~t7_pc~0); 121001#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 120797#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 120798#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 120862#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 120863#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121380#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 120646#L857-2 assume !(1 == ~T1_E~0); 120647#L862-1 assume !(1 == ~T2_E~0); 120929#L867-1 assume !(1 == ~T3_E~0); 120934#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 121025#L877-1 assume !(1 == ~T5_E~0); 121229#L882-1 assume !(1 == ~T6_E~0); 121397#L887-1 assume !(1 == ~T7_E~0); 129835#L892-1 assume !(1 == ~E_M~0); 129833#L897-1 assume !(1 == ~E_1~0); 129831#L902-1 assume !(1 == ~E_2~0); 129829#L907-1 assume !(1 == ~E_3~0); 129827#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 129825#L917-1 assume !(1 == ~E_5~0); 129823#L922-1 assume !(1 == ~E_6~0); 128799#L927-1 assume !(1 == ~E_7~0); 129787#L932-1 assume { :end_inline_reset_delta_events } true; 129785#L1178-2 [2024-11-09 16:07:53,297 INFO L747 eck$LassoCheckResult]: Loop: 129785#L1178-2 assume !false; 129683#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 129681#L744-1 assume !false; 129679#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 129677#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 129669#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 129666#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 129664#L641 assume !(0 != eval_~tmp~0#1); 129665#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 137363#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 137362#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 137361#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 137360#L774-3 assume !(0 == ~T2_E~0); 137359#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 137358#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 137357#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 137356#L794-3 assume !(0 == ~T6_E~0); 137355#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 137354#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 137353#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 137352#L814-3 assume !(0 == ~E_2~0); 137351#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 137350#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 137349#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 137348#L834-3 assume !(0 == ~E_6~0); 137347#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 137346#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137344#L376-27 assume !(1 == ~m_pc~0); 137342#L376-29 is_master_triggered_~__retres1~0#1 := 0; 137339#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137337#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 137335#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 137333#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 137330#L395-27 assume !(1 == ~t1_pc~0); 137328#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 137326#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 137323#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 137319#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 137316#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 137313#L414-27 assume !(1 == ~t2_pc~0); 137310#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 137306#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 137303#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 137300#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 137297#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 137293#L433-27 assume !(1 == ~t3_pc~0); 137290#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 137287#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 137284#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 137280#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 137277#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 137273#L452-27 assume !(1 == ~t4_pc~0); 137270#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 137266#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137263#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 137260#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 137257#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 137253#L471-27 assume !(1 == ~t5_pc~0); 137248#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 137244#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 137240#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 137235#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 137232#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 137229#L490-27 assume !(1 == ~t6_pc~0); 137226#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 137224#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 137222#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 137220#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 137217#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 137214#L509-27 assume !(1 == ~t7_pc~0); 137210#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 137206#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 137202#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 137198#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 137195#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137192#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 130435#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 137186#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 137181#L867-3 assume !(1 == ~T3_E~0); 137177#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 137173#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 137168#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 130422#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 137159#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 137155#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 137151#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 137146#L907-3 assume !(1 == ~E_3~0); 137142#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 137137#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 137133#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 134131#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 137126#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 136884#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 136720#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 136716#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 121009#L1197 assume !(0 == start_simulation_~tmp~3#1); 121010#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 129808#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 129799#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 129796#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 129794#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 129792#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 129790#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 129788#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 129785#L1178-2 [2024-11-09 16:07:53,297 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:53,297 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2024-11-09 16:07:53,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:53,297 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558316818] [2024-11-09 16:07:53,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:53,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:53,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:53,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:53,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:53,344 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558316818] [2024-11-09 16:07:53,344 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558316818] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:53,344 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:53,344 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:07:53,344 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1444522722] [2024-11-09 16:07:53,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:53,344 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:53,345 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:53,345 INFO L85 PathProgramCache]: Analyzing trace with hash 1162954138, now seen corresponding path program 2 times [2024-11-09 16:07:53,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:53,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878619579] [2024-11-09 16:07:53,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:53,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:53,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:53,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:53,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:53,371 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [878619579] [2024-11-09 16:07:53,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [878619579] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:53,372 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:53,372 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:53,372 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [349613214] [2024-11-09 16:07:53,372 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:53,372 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:53,372 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:53,373 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:07:53,373 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:07:53,373 INFO L87 Difference]: Start difference. First operand 34007 states and 48894 transitions. cyclomatic complexity: 14951 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:53,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:53,719 INFO L93 Difference]: Finished difference Result 35354 states and 50241 transitions. [2024-11-09 16:07:53,719 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35354 states and 50241 transitions. [2024-11-09 16:07:53,972 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35000 [2024-11-09 16:07:54,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35354 states to 35354 states and 50241 transitions. [2024-11-09 16:07:54,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35354 [2024-11-09 16:07:54,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35354 [2024-11-09 16:07:54,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35354 states and 50241 transitions. [2024-11-09 16:07:54,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:54,104 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35354 states and 50241 transitions. [2024-11-09 16:07:54,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35354 states and 50241 transitions. [2024-11-09 16:07:54,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35354 to 35354. [2024-11-09 16:07:54,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35354 states, 35354 states have (on average 1.4210838943259603) internal successors, (50241), 35353 states have internal predecessors, (50241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:54,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35354 states to 35354 states and 50241 transitions. [2024-11-09 16:07:54,543 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35354 states and 50241 transitions. [2024-11-09 16:07:54,544 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:07:54,544 INFO L425 stractBuchiCegarLoop]: Abstraction has 35354 states and 50241 transitions. [2024-11-09 16:07:54,544 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-09 16:07:54,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35354 states and 50241 transitions. [2024-11-09 16:07:54,835 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35000 [2024-11-09 16:07:54,835 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:54,835 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:54,837 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:54,837 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:54,837 INFO L745 eck$LassoCheckResult]: Stem: 190138#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 190139#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 190776#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 190777#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 190747#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 190748#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 190391#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 190208#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 190209#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 190189#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 190190#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 190745#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 190526#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 190527#L769 assume !(0 == ~M_E~0); 190553#L769-2 assume !(0 == ~T1_E~0); 190554#L774-1 assume !(0 == ~T2_E~0); 190584#L779-1 assume !(0 == ~T3_E~0); 190729#L784-1 assume !(0 == ~T4_E~0); 190524#L789-1 assume !(0 == ~T5_E~0); 190525#L794-1 assume !(0 == ~T6_E~0); 190641#L799-1 assume !(0 == ~T7_E~0); 190530#L804-1 assume !(0 == ~E_M~0); 190531#L809-1 assume !(0 == ~E_1~0); 190579#L814-1 assume !(0 == ~E_2~0); 189931#L819-1 assume !(0 == ~E_3~0); 189932#L824-1 assume !(0 == ~E_4~0); 190281#L829-1 assume !(0 == ~E_5~0); 190822#L834-1 assume !(0 == ~E_6~0); 190061#L839-1 assume !(0 == ~E_7~0); 190062#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 190473#L376 assume !(1 == ~m_pc~0); 190458#L376-2 is_master_triggered_~__retres1~0#1 := 0; 190457#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 190712#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 190007#L955 assume !(0 != activate_threads_~tmp~1#1); 190008#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190384#L395 assume !(1 == ~t1_pc~0); 190555#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 190713#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189961#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 189962#L963 assume !(0 != activate_threads_~tmp___0~0#1); 190477#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190478#L414 assume !(1 == ~t2_pc~0); 190064#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 190065#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 190287#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 190288#L971 assume !(0 != activate_threads_~tmp___1~0#1); 190753#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 190388#L433 assume !(1 == ~t3_pc~0); 190177#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 190178#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189929#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 189930#L979 assume !(0 != activate_threads_~tmp___2~0#1); 190031#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 190032#L452 assume !(1 == ~t4_pc~0); 190185#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 190186#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 190025#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 190026#L987 assume !(0 != activate_threads_~tmp___3~0#1); 190218#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 190219#L471 assume !(1 == ~t5_pc~0); 190626#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 190200#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 190201#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 190716#L995 assume !(0 != activate_threads_~tmp___4~0#1); 190809#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 190810#L490 assume !(1 == ~t6_pc~0); 190475#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 190476#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190275#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 190276#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 190398#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 190365#L509 assume !(1 == ~t7_pc~0); 190366#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 190160#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 190161#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 190225#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 190226#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 190763#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 190014#L857-2 assume !(1 == ~T1_E~0); 190015#L862-1 assume !(1 == ~T2_E~0); 190291#L867-1 assume !(1 == ~T3_E~0); 190296#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 190389#L877-1 assume !(1 == ~T5_E~0); 190602#L882-1 assume !(1 == ~T6_E~0); 190783#L887-1 assume !(1 == ~T7_E~0); 190664#L892-1 assume !(1 == ~E_M~0); 190665#L897-1 assume !(1 == ~E_1~0); 190312#L902-1 assume !(1 == ~E_2~0); 190313#L907-1 assume !(1 == ~E_3~0); 190617#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 190609#L917-1 assume !(1 == ~E_5~0); 190610#L922-1 assume !(1 == ~E_6~0); 190825#L927-1 assume !(1 == ~E_7~0); 198822#L932-1 assume { :end_inline_reset_delta_events } true; 198820#L1178-2 [2024-11-09 16:07:54,838 INFO L747 eck$LassoCheckResult]: Loop: 198820#L1178-2 assume !false; 198696#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 198693#L744-1 assume !false; 198691#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 198689#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 198681#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 198678#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 198676#L641 assume !(0 != eval_~tmp~0#1); 198677#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 199075#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199073#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 199071#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 199069#L774-3 assume !(0 == ~T2_E~0); 199066#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 199064#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 199062#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 199060#L794-3 assume !(0 == ~T6_E~0); 199058#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 199056#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 199054#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 199052#L814-3 assume !(0 == ~E_2~0); 199050#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 199048#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 199046#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 199044#L834-3 assume !(0 == ~E_6~0); 199041#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 199039#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199037#L376-27 assume !(1 == ~m_pc~0); 199035#L376-29 is_master_triggered_~__retres1~0#1 := 0; 199032#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 199030#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 199028#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 199026#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 199024#L395-27 assume !(1 == ~t1_pc~0); 199022#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 199020#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199018#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 199015#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 199013#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199011#L414-27 assume !(1 == ~t2_pc~0); 199009#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 199006#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199004#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 199002#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 199000#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 198998#L433-27 assume !(1 == ~t3_pc~0); 198996#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 198994#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 198992#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 198990#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 198988#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 198986#L452-27 assume 1 == ~t4_pc~0; 198983#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 198981#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 198977#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198975#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 198973#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 198971#L471-27 assume !(1 == ~t5_pc~0); 198968#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 198966#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 198965#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 198964#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 198963#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 198961#L490-27 assume !(1 == ~t6_pc~0); 198959#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 198957#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198955#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 198953#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 198950#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 198948#L509-27 assume !(1 == ~t7_pc~0); 198946#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 200043#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 200037#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 198893#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 198890#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198888#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 196775#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 198882#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 198880#L867-3 assume !(1 == ~T3_E~0); 198878#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 198876#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 198874#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 198870#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 198868#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 198866#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 198864#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 198862#L907-3 assume !(1 == ~E_3~0); 198860#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 198858#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 198856#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 196743#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 198853#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 198851#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 198842#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 198840#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 198839#L1197 assume !(0 == start_simulation_~tmp~3#1); 198837#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 198836#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 198828#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 198827#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 198826#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 198825#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 198824#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 198823#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 198820#L1178-2 [2024-11-09 16:07:54,838 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:54,838 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2024-11-09 16:07:54,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:54,839 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574189774] [2024-11-09 16:07:54,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:54,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:54,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:54,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:54,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:54,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1574189774] [2024-11-09 16:07:54,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1574189774] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:54,886 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:54,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:54,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987375110] [2024-11-09 16:07:54,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:54,887 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:54,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:54,887 INFO L85 PathProgramCache]: Analyzing trace with hash 2138332507, now seen corresponding path program 1 times [2024-11-09 16:07:54,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:54,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470719651] [2024-11-09 16:07:54,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:54,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:54,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:54,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:54,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:54,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470719651] [2024-11-09 16:07:54,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [470719651] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:54,926 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:54,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:54,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948664699] [2024-11-09 16:07:54,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:54,926 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:54,926 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:54,926 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:54,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:54,927 INFO L87 Difference]: Start difference. First operand 35354 states and 50241 transitions. cyclomatic complexity: 14951 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:55,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:55,147 INFO L93 Difference]: Finished difference Result 44340 states and 63028 transitions. [2024-11-09 16:07:55,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44340 states and 63028 transitions. [2024-11-09 16:07:55,273 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 43944 [2024-11-09 16:07:55,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44340 states to 44340 states and 63028 transitions. [2024-11-09 16:07:55,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44340 [2024-11-09 16:07:55,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44340 [2024-11-09 16:07:55,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44340 states and 63028 transitions. [2024-11-09 16:07:55,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:55,546 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44340 states and 63028 transitions. [2024-11-09 16:07:55,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44340 states and 63028 transitions. [2024-11-09 16:07:55,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44340 to 19046. [2024-11-09 16:07:55,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19046 states, 19046 states have (on average 1.4274388323007456) internal successors, (27187), 19045 states have internal predecessors, (27187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:55,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19046 states to 19046 states and 27187 transitions. [2024-11-09 16:07:55,932 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19046 states and 27187 transitions. [2024-11-09 16:07:55,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:55,936 INFO L425 stractBuchiCegarLoop]: Abstraction has 19046 states and 27187 transitions. [2024-11-09 16:07:55,936 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-09 16:07:55,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19046 states and 27187 transitions. [2024-11-09 16:07:55,978 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18832 [2024-11-09 16:07:55,979 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:55,979 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:55,980 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:55,980 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:55,980 INFO L745 eck$LassoCheckResult]: Stem: 269843#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 269844#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 270456#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 270457#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 270426#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 270427#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 270090#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 269912#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 269913#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 269893#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 269894#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 270425#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 270220#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 270221#L769 assume !(0 == ~M_E~0); 270240#L769-2 assume !(0 == ~T1_E~0); 270241#L774-1 assume !(0 == ~T2_E~0); 270271#L779-1 assume !(0 == ~T3_E~0); 270407#L784-1 assume !(0 == ~T4_E~0); 270218#L789-1 assume !(0 == ~T5_E~0); 270219#L794-1 assume !(0 == ~T6_E~0); 270332#L799-1 assume !(0 == ~T7_E~0); 270223#L804-1 assume !(0 == ~E_M~0); 270224#L809-1 assume !(0 == ~E_1~0); 270266#L814-1 assume !(0 == ~E_2~0); 269636#L819-1 assume !(0 == ~E_3~0); 269637#L824-1 assume !(0 == ~E_4~0); 269984#L829-1 assume !(0 == ~E_5~0); 270499#L834-1 assume !(0 == ~E_6~0); 269766#L839-1 assume !(0 == ~E_7~0); 269767#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 270170#L376 assume !(1 == ~m_pc~0); 270160#L376-2 is_master_triggered_~__retres1~0#1 := 0; 270159#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270389#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 269711#L955 assume !(0 != activate_threads_~tmp~1#1); 269712#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270083#L395 assume !(1 == ~t1_pc~0); 270242#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 270392#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 269664#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 269665#L963 assume !(0 != activate_threads_~tmp___0~0#1); 270176#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270177#L414 assume !(1 == ~t2_pc~0); 269769#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 269770#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 269990#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 269991#L971 assume !(0 != activate_threads_~tmp___1~0#1); 270433#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 270087#L433 assume !(1 == ~t3_pc~0); 269880#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 269881#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 269630#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 269631#L979 assume !(0 != activate_threads_~tmp___2~0#1); 269735#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 269736#L452 assume !(1 == ~t4_pc~0); 269889#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 269890#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 269729#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 269730#L987 assume !(0 != activate_threads_~tmp___3~0#1); 269922#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 269923#L471 assume !(1 == ~t5_pc~0); 270316#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 269907#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 269908#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 270393#L995 assume !(0 != activate_threads_~tmp___4~0#1); 270489#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 270490#L490 assume !(1 == ~t6_pc~0); 270172#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 270173#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 269978#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 269979#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 270100#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 270063#L509 assume !(1 == ~t7_pc~0); 270064#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 269866#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 269867#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 269929#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 269930#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 270442#L857 assume !(1 == ~M_E~0); 269716#L857-2 assume !(1 == ~T1_E~0); 269717#L862-1 assume !(1 == ~T2_E~0); 269994#L867-1 assume !(1 == ~T3_E~0); 269999#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 270088#L877-1 assume !(1 == ~T5_E~0); 270290#L882-1 assume !(1 == ~T6_E~0); 270460#L887-1 assume !(1 == ~T7_E~0); 270353#L892-1 assume !(1 == ~E_M~0); 270354#L897-1 assume !(1 == ~E_1~0); 270017#L902-1 assume !(1 == ~E_2~0); 270018#L907-1 assume !(1 == ~E_3~0); 270305#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 270297#L917-1 assume !(1 == ~E_5~0); 270298#L922-1 assume !(1 == ~E_6~0); 270502#L927-1 assume !(1 == ~E_7~0); 270285#L932-1 assume { :end_inline_reset_delta_events } true; 270286#L1178-2 [2024-11-09 16:07:55,981 INFO L747 eck$LassoCheckResult]: Loop: 270286#L1178-2 assume !false; 276129#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 276127#L744-1 assume !false; 276124#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 275985#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 275976#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 275974#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 275971#L641 assume !(0 != eval_~tmp~0#1); 275968#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 275966#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 275964#L769-3 assume !(0 == ~M_E~0); 275962#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 275960#L774-3 assume !(0 == ~T2_E~0); 275958#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 275955#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 275944#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 275935#L794-3 assume !(0 == ~T6_E~0); 275924#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 275915#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 275913#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 275911#L814-3 assume !(0 == ~E_2~0); 275908#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 275906#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 275904#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 275902#L834-3 assume !(0 == ~E_6~0); 275900#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 275898#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 275896#L376-27 assume 1 == ~m_pc~0; 275893#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 275891#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 275889#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 275887#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 275885#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 275883#L395-27 assume !(1 == ~t1_pc~0); 275881#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 275879#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 275877#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 275875#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 275863#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 275859#L414-27 assume 1 == ~t2_pc~0; 275854#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 275849#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 275844#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 275840#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 275835#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 275831#L433-27 assume !(1 == ~t3_pc~0); 275827#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 275823#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 275818#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 275814#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 275810#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 275806#L452-27 assume 1 == ~t4_pc~0; 275801#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 275797#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 275792#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 275788#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 275784#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 275780#L471-27 assume !(1 == ~t5_pc~0); 275776#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 275772#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 275768#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 275764#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 275758#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 275753#L490-27 assume !(1 == ~t6_pc~0); 275748#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 275743#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 275738#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 275734#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 275730#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 275726#L509-27 assume 1 == ~t7_pc~0; 275721#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 275716#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 275710#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 275705#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 275700#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 275696#L857-3 assume !(1 == ~M_E~0); 274108#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 275689#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 275685#L867-3 assume !(1 == ~T3_E~0); 275681#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 275676#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 275672#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 275667#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 275629#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 275618#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 275614#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 275610#L907-3 assume !(1 == ~E_3~0); 275607#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 275604#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 275600#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 275597#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 275596#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 275595#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 275585#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 275581#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 274362#L1197 assume !(0 == start_simulation_~tmp~3#1); 274363#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 276709#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 276700#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 276698#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 276695#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 276693#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 276692#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 276688#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 270286#L1178-2 [2024-11-09 16:07:55,981 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:55,981 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2024-11-09 16:07:55,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:55,981 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304040708] [2024-11-09 16:07:55,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:55,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:55,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:56,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:56,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:56,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304040708] [2024-11-09 16:07:56,029 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [304040708] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:56,029 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:56,030 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:56,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758350557] [2024-11-09 16:07:56,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:56,030 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:56,030 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:56,030 INFO L85 PathProgramCache]: Analyzing trace with hash 1617182998, now seen corresponding path program 1 times [2024-11-09 16:07:56,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:56,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616988317] [2024-11-09 16:07:56,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:56,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:56,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:56,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:56,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:56,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616988317] [2024-11-09 16:07:56,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1616988317] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:56,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:56,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:56,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [230481702] [2024-11-09 16:07:56,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:56,057 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:56,057 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:56,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:07:56,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:07:56,057 INFO L87 Difference]: Start difference. First operand 19046 states and 27187 transitions. cyclomatic complexity: 8157 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:56,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:56,385 INFO L93 Difference]: Finished difference Result 30242 states and 43038 transitions. [2024-11-09 16:07:56,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30242 states and 43038 transitions. [2024-11-09 16:07:56,507 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 29888 [2024-11-09 16:07:56,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30242 states to 30242 states and 43038 transitions. [2024-11-09 16:07:56,588 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30242 [2024-11-09 16:07:56,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30242 [2024-11-09 16:07:56,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30242 states and 43038 transitions. [2024-11-09 16:07:56,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:56,636 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30242 states and 43038 transitions. [2024-11-09 16:07:56,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30242 states and 43038 transitions. [2024-11-09 16:07:56,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30242 to 21486. [2024-11-09 16:07:56,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21486 states, 21486 states have (on average 1.4271153309131528) internal successors, (30663), 21485 states have internal predecessors, (30663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:56,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21486 states to 21486 states and 30663 transitions. [2024-11-09 16:07:56,916 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21486 states and 30663 transitions. [2024-11-09 16:07:56,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:07:56,917 INFO L425 stractBuchiCegarLoop]: Abstraction has 21486 states and 30663 transitions. [2024-11-09 16:07:56,917 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-09 16:07:56,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21486 states and 30663 transitions. [2024-11-09 16:07:56,977 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21200 [2024-11-09 16:07:56,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:56,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:56,979 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:56,979 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:56,979 INFO L745 eck$LassoCheckResult]: Stem: 319139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 319140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 319783#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 319784#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 319748#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 319749#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 319394#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 319209#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 319210#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 319191#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 319192#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 319747#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 319532#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 319533#L769 assume !(0 == ~M_E~0); 319552#L769-2 assume !(0 == ~T1_E~0); 319553#L774-1 assume !(0 == ~T2_E~0); 319583#L779-1 assume !(0 == ~T3_E~0); 319728#L784-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 319729#L789-1 assume !(0 == ~T5_E~0); 319939#L794-1 assume !(0 == ~T6_E~0); 319916#L799-1 assume !(0 == ~T7_E~0); 319917#L804-1 assume !(0 == ~E_M~0); 319577#L809-1 assume !(0 == ~E_1~0); 319578#L814-1 assume !(0 == ~E_2~0); 318930#L819-1 assume !(0 == ~E_3~0); 318931#L824-1 assume !(0 == ~E_4~0); 319908#L829-1 assume !(0 == ~E_5~0); 319909#L834-1 assume !(0 == ~E_6~0); 319065#L839-1 assume !(0 == ~E_7~0); 319066#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 319646#L376 assume !(1 == ~m_pc~0); 319461#L376-2 is_master_triggered_~__retres1~0#1 := 0; 319460#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 319704#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 319705#L955 assume !(0 != activate_threads_~tmp~1#1); 319937#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 319554#L395 assume !(1 == ~t1_pc~0); 319555#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 319730#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 319731#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 319774#L963 assume !(0 != activate_threads_~tmp___0~0#1); 319775#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 319925#L414 assume !(1 == ~t2_pc~0); 319926#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 319914#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 319915#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 319755#L971 assume !(0 != activate_threads_~tmp___1~0#1); 319756#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 319936#L433 assume !(1 == ~t3_pc~0); 319178#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 319179#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 318928#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 318929#L979 assume !(0 != activate_threads_~tmp___2~0#1); 319033#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 319034#L452 assume !(1 == ~t4_pc~0); 319187#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 319188#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 319027#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 319028#L987 assume !(0 != activate_threads_~tmp___3~0#1); 319219#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 319220#L471 assume !(1 == ~t5_pc~0); 319627#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 319202#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 319203#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 319912#L995 assume !(0 != activate_threads_~tmp___4~0#1); 319913#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 319863#L490 assume !(1 == ~t6_pc~0); 319864#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 319519#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 319520#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 319525#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 319526#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 319934#L509 assume !(1 == ~t7_pc~0); 319762#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 319933#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 319929#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 319930#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 319840#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319841#L857 assume !(1 == ~M_E~0); 319016#L857-2 assume !(1 == ~T1_E~0); 319017#L862-1 assume !(1 == ~T2_E~0); 319299#L867-1 assume !(1 == ~T3_E~0); 319300#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 319392#L877-1 assume !(1 == ~T5_E~0); 319602#L882-1 assume !(1 == ~T6_E~0); 319789#L887-1 assume !(1 == ~T7_E~0); 319664#L892-1 assume !(1 == ~E_M~0); 319665#L897-1 assume !(1 == ~E_1~0); 319316#L902-1 assume !(1 == ~E_2~0); 319317#L907-1 assume !(1 == ~E_3~0); 319617#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 319609#L917-1 assume !(1 == ~E_5~0); 319610#L922-1 assume !(1 == ~E_6~0); 319831#L927-1 assume !(1 == ~E_7~0); 319597#L932-1 assume { :end_inline_reset_delta_events } true; 319598#L1178-2 [2024-11-09 16:07:56,979 INFO L747 eck$LassoCheckResult]: Loop: 319598#L1178-2 assume !false; 324476#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 324469#L744-1 assume !false; 324327#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 323896#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 323887#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 323885#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 323882#L641 assume !(0 != eval_~tmp~0#1); 323880#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 323878#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 323875#L769-3 assume !(0 == ~M_E~0); 323873#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 323871#L774-3 assume !(0 == ~T2_E~0); 323869#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 323866#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 323865#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 323864#L794-3 assume !(0 == ~T6_E~0); 323863#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 323862#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 323861#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 323860#L814-3 assume !(0 == ~E_2~0); 323859#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 323858#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 323857#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 323856#L834-3 assume !(0 == ~E_6~0); 323855#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 323854#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 323853#L376-27 assume !(1 == ~m_pc~0); 323852#L376-29 is_master_triggered_~__retres1~0#1 := 0; 323850#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 323849#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 323848#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 323847#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 323846#L395-27 assume !(1 == ~t1_pc~0); 323845#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 323844#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 323843#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 323842#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 323841#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 323840#L414-27 assume 1 == ~t2_pc~0; 323838#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 323837#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 323836#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 323835#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 323834#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 323833#L433-27 assume !(1 == ~t3_pc~0); 323832#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 323831#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 323830#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 323829#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 323828#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 323827#L452-27 assume 1 == ~t4_pc~0; 323825#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 323824#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 323823#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 323822#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 323821#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 323820#L471-27 assume !(1 == ~t5_pc~0); 323819#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 323818#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 323817#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 323816#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 323815#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 323814#L490-27 assume !(1 == ~t6_pc~0); 323813#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 323812#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 323811#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 323810#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 323809#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 323808#L509-27 assume 1 == ~t7_pc~0; 323806#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 323804#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 323802#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 323800#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 323799#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 323798#L857-3 assume !(1 == ~M_E~0); 322427#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 323797#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 323796#L867-3 assume !(1 == ~T3_E~0); 323794#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 323791#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 323789#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 323787#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 323784#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 323782#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 323780#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 323744#L907-3 assume !(1 == ~E_3~0); 322988#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 322987#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 322986#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 322985#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 322984#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 322980#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 322972#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 322817#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 322689#L1197 assume !(0 == start_simulation_~tmp~3#1); 322690#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 324520#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 324511#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 324509#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 324507#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 324505#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 324503#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 324501#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 319598#L1178-2 [2024-11-09 16:07:56,980 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:56,980 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2024-11-09 16:07:56,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:56,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482130597] [2024-11-09 16:07:56,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:56,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:56,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:57,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:57,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:57,026 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482130597] [2024-11-09 16:07:57,026 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [482130597] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:57,026 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:57,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:57,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2084486962] [2024-11-09 16:07:57,026 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:57,026 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:57,027 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:57,027 INFO L85 PathProgramCache]: Analyzing trace with hash -225130793, now seen corresponding path program 1 times [2024-11-09 16:07:57,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:57,028 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439381004] [2024-11-09 16:07:57,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:57,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:57,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:57,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:57,063 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:57,063 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439381004] [2024-11-09 16:07:57,063 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1439381004] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:57,063 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:57,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:57,064 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369703681] [2024-11-09 16:07:57,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:57,064 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:57,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:57,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:07:57,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:07:57,065 INFO L87 Difference]: Start difference. First operand 21486 states and 30663 transitions. cyclomatic complexity: 9193 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:57,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:57,355 INFO L93 Difference]: Finished difference Result 27790 states and 39425 transitions. [2024-11-09 16:07:57,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27790 states and 39425 transitions. [2024-11-09 16:07:57,437 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27520 [2024-11-09 16:07:57,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27790 states to 27790 states and 39425 transitions. [2024-11-09 16:07:57,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27790 [2024-11-09 16:07:57,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27790 [2024-11-09 16:07:57,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27790 states and 39425 transitions. [2024-11-09 16:07:57,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:57,534 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27790 states and 39425 transitions. [2024-11-09 16:07:57,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27790 states and 39425 transitions. [2024-11-09 16:07:57,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27790 to 19046. [2024-11-09 16:07:57,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19046 states, 19046 states have (on average 1.4222933949385699) internal successors, (27089), 19045 states have internal predecessors, (27089), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:57,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19046 states to 19046 states and 27089 transitions. [2024-11-09 16:07:57,710 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19046 states and 27089 transitions. [2024-11-09 16:07:57,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:07:57,711 INFO L425 stractBuchiCegarLoop]: Abstraction has 19046 states and 27089 transitions. [2024-11-09 16:07:57,711 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-09 16:07:57,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19046 states and 27089 transitions. [2024-11-09 16:07:57,754 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18832 [2024-11-09 16:07:57,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:57,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:57,755 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:57,755 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:57,755 INFO L745 eck$LassoCheckResult]: Stem: 368425#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 368426#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 369026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 369027#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 369000#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 369001#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 368676#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 368495#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 368496#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 368477#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 368478#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 368999#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 368798#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 368799#L769 assume !(0 == ~M_E~0); 368819#L769-2 assume !(0 == ~T1_E~0); 368820#L774-1 assume !(0 == ~T2_E~0); 368853#L779-1 assume !(0 == ~T3_E~0); 368984#L784-1 assume !(0 == ~T4_E~0); 368796#L789-1 assume !(0 == ~T5_E~0); 368797#L794-1 assume !(0 == ~T6_E~0); 368909#L799-1 assume !(0 == ~T7_E~0); 368801#L804-1 assume !(0 == ~E_M~0); 368802#L809-1 assume !(0 == ~E_1~0); 368844#L814-1 assume !(0 == ~E_2~0); 368216#L819-1 assume !(0 == ~E_3~0); 368217#L824-1 assume !(0 == ~E_4~0); 368568#L829-1 assume !(0 == ~E_5~0); 369058#L834-1 assume !(0 == ~E_6~0); 368349#L839-1 assume !(0 == ~E_7~0); 368350#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 368750#L376 assume !(1 == ~m_pc~0); 368739#L376-2 is_master_triggered_~__retres1~0#1 := 0; 368738#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 368966#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 368293#L955 assume !(0 != activate_threads_~tmp~1#1); 368294#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 368668#L395 assume !(1 == ~t1_pc~0); 368821#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 368967#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 368246#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 368247#L963 assume !(0 != activate_threads_~tmp___0~0#1); 368754#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 368755#L414 assume !(1 == ~t2_pc~0); 368352#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 368353#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 368574#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 368575#L971 assume !(0 != activate_threads_~tmp___1~0#1); 369007#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 368673#L433 assume !(1 == ~t3_pc~0); 368465#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 368466#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 368214#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 368215#L979 assume !(0 != activate_threads_~tmp___2~0#1); 368318#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 368319#L452 assume !(1 == ~t4_pc~0); 368473#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 368474#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 368312#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 368313#L987 assume !(0 != activate_threads_~tmp___3~0#1); 368505#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 368506#L471 assume !(1 == ~t5_pc~0); 368896#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 368488#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 368489#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 368971#L995 assume !(0 != activate_threads_~tmp___4~0#1); 369048#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 369049#L490 assume !(1 == ~t6_pc~0); 368752#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 368753#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 368562#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 368563#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 368683#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 368650#L509 assume !(1 == ~t7_pc~0); 368651#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 368448#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 368449#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 368512#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 368513#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 369015#L857 assume !(1 == ~M_E~0); 368300#L857-2 assume !(1 == ~T1_E~0); 368301#L862-1 assume !(1 == ~T2_E~0); 368578#L867-1 assume !(1 == ~T3_E~0); 368583#L872-1 assume !(1 == ~T4_E~0); 368674#L877-1 assume !(1 == ~T5_E~0); 368872#L882-1 assume !(1 == ~T6_E~0); 369030#L887-1 assume !(1 == ~T7_E~0); 368933#L892-1 assume !(1 == ~E_M~0); 368934#L897-1 assume !(1 == ~E_1~0); 368598#L902-1 assume !(1 == ~E_2~0); 368599#L907-1 assume !(1 == ~E_3~0); 368886#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 368879#L917-1 assume !(1 == ~E_5~0); 368880#L922-1 assume !(1 == ~E_6~0); 369063#L927-1 assume !(1 == ~E_7~0); 368867#L932-1 assume { :end_inline_reset_delta_events } true; 368868#L1178-2 [2024-11-09 16:07:57,755 INFO L747 eck$LassoCheckResult]: Loop: 368868#L1178-2 assume !false; 371020#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 371014#L744-1 assume !false; 371010#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 370820#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 370811#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 370808#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 370805#L641 assume !(0 != eval_~tmp~0#1); 370803#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 370801#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 370799#L769-3 assume !(0 == ~M_E~0); 370797#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 370794#L774-3 assume !(0 == ~T2_E~0); 370792#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 370790#L784-3 assume !(0 == ~T4_E~0); 370788#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 370786#L794-3 assume !(0 == ~T6_E~0); 370784#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 370782#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 370780#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 370778#L814-3 assume !(0 == ~E_2~0); 370776#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 370750#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 370737#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 370726#L834-3 assume !(0 == ~E_6~0); 370718#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 370711#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 370704#L376-27 assume !(1 == ~m_pc~0); 370699#L376-29 is_master_triggered_~__retres1~0#1 := 0; 370696#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 370694#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 370685#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 370683#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 370681#L395-27 assume !(1 == ~t1_pc~0); 370678#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 370676#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 370674#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 370672#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 370670#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 370668#L414-27 assume 1 == ~t2_pc~0; 370665#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 370663#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 370661#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 370659#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 370657#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 370655#L433-27 assume !(1 == ~t3_pc~0); 370653#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 370651#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 370649#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 370647#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 370645#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 370643#L452-27 assume !(1 == ~t4_pc~0); 370641#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 370638#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 370636#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 370633#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 370631#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 370629#L471-27 assume !(1 == ~t5_pc~0); 370627#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 370625#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 370623#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 370621#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 370619#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 370617#L490-27 assume !(1 == ~t6_pc~0); 370615#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 370613#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 370611#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 370608#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 370606#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 370604#L509-27 assume 1 == ~t7_pc~0; 370601#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 370598#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 370595#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 370592#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 370590#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 370588#L857-3 assume !(1 == ~M_E~0); 370443#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 370585#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 370583#L867-3 assume !(1 == ~T3_E~0); 370580#L872-3 assume !(1 == ~T4_E~0); 370578#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 370576#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 370574#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 370572#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 370570#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 370567#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 370565#L907-3 assume !(1 == ~E_3~0); 370563#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 370561#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 370559#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 370557#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 370555#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 370553#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 370544#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 370543#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 370503#L1197 assume !(0 == start_simulation_~tmp~3#1); 370504#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 371191#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 371182#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 371122#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 371115#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 371055#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 371046#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 371036#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 368868#L1178-2 [2024-11-09 16:07:57,756 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:57,756 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2024-11-09 16:07:57,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:57,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807369180] [2024-11-09 16:07:57,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:57,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:57,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:57,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:57,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:57,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807369180] [2024-11-09 16:07:57,794 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807369180] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:57,794 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:57,794 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:57,795 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244989992] [2024-11-09 16:07:57,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:57,795 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:57,795 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:57,795 INFO L85 PathProgramCache]: Analyzing trace with hash 1518702552, now seen corresponding path program 1 times [2024-11-09 16:07:57,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:57,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923264869] [2024-11-09 16:07:57,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:57,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:57,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:57,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:57,820 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:57,820 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923264869] [2024-11-09 16:07:57,820 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1923264869] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:57,820 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:57,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:57,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840741231] [2024-11-09 16:07:57,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:57,821 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:57,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:57,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:07:57,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:07:57,822 INFO L87 Difference]: Start difference. First operand 19046 states and 27089 transitions. cyclomatic complexity: 8059 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:58,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:58,203 INFO L93 Difference]: Finished difference Result 30270 states and 42575 transitions. [2024-11-09 16:07:58,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30270 states and 42575 transitions. [2024-11-09 16:07:58,299 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 29876 [2024-11-09 16:07:58,362 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30270 states to 30270 states and 42575 transitions. [2024-11-09 16:07:58,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30270 [2024-11-09 16:07:58,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30270 [2024-11-09 16:07:58,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30270 states and 42575 transitions. [2024-11-09 16:07:58,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:58,398 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30270 states and 42575 transitions. [2024-11-09 16:07:58,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30270 states and 42575 transitions. [2024-11-09 16:07:58,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30270 to 21486. [2024-11-09 16:07:58,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21486 states, 21486 states have (on average 1.412082286139812) internal successors, (30340), 21485 states have internal predecessors, (30340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:58,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21486 states to 21486 states and 30340 transitions. [2024-11-09 16:07:58,589 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21486 states and 30340 transitions. [2024-11-09 16:07:58,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:07:58,590 INFO L425 stractBuchiCegarLoop]: Abstraction has 21486 states and 30340 transitions. [2024-11-09 16:07:58,590 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-09 16:07:58,590 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21486 states and 30340 transitions. [2024-11-09 16:07:58,636 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21200 [2024-11-09 16:07:58,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:58,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:58,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:58,637 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:58,638 INFO L745 eck$LassoCheckResult]: Stem: 417749#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 417750#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 418397#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 418398#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 418367#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 418368#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 418002#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 417817#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 417818#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 417799#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 417800#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 418366#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 418138#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 418139#L769 assume !(0 == ~M_E~0); 418158#L769-2 assume !(0 == ~T1_E~0); 418159#L774-1 assume !(0 == ~T2_E~0); 418191#L779-1 assume !(0 == ~T3_E~0); 418346#L784-1 assume !(0 == ~T4_E~0); 418136#L789-1 assume !(0 == ~T5_E~0); 418137#L794-1 assume !(0 == ~T6_E~0); 418256#L799-1 assume !(0 == ~T7_E~0); 418141#L804-1 assume !(0 == ~E_M~0); 418142#L809-1 assume !(0 == ~E_1~0); 418185#L814-1 assume !(0 == ~E_2~0); 417546#L819-1 assume !(0 == ~E_3~0); 417547#L824-1 assume 0 == ~E_4~0;~E_4~0 := 1; 417888#L829-1 assume !(0 == ~E_5~0); 418438#L834-1 assume !(0 == ~E_6~0); 418439#L839-1 assume !(0 == ~E_7~0); 418262#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 418263#L376 assume !(1 == ~m_pc~0); 418077#L376-2 is_master_triggered_~__retres1~0#1 := 0; 418076#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 418326#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 418327#L955 assume !(0 != activate_threads_~tmp~1#1); 417992#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 417993#L395 assume !(1 == ~t1_pc~0); 418330#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 418331#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 417574#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 417575#L963 assume !(0 != activate_threads_~tmp___0~0#1); 418094#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 418095#L414 assume !(1 == ~t2_pc~0); 417676#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 417677#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 417896#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 417897#L971 assume !(0 != activate_threads_~tmp___1~0#1); 418450#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 418451#L433 assume !(1 == ~t3_pc~0); 417789#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 417790#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 417540#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 417541#L979 assume !(0 != activate_threads_~tmp___2~0#1); 417642#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 417643#L452 assume !(1 == ~t4_pc~0); 418558#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 418557#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 418556#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 418555#L987 assume !(0 != activate_threads_~tmp___3~0#1); 418554#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 418553#L471 assume !(1 == ~t5_pc~0); 418552#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 418551#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 418550#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 418549#L995 assume !(0 != activate_threads_~tmp___4~0#1); 418548#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 418547#L490 assume !(1 == ~t6_pc~0); 418546#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 418545#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 418544#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 418543#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 418542#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 418541#L509 assume !(1 == ~t7_pc~0); 418539#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 418537#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 418535#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 418533#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 418532#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 418531#L857 assume !(1 == ~M_E~0); 418530#L857-2 assume !(1 == ~T1_E~0); 418529#L862-1 assume !(1 == ~T2_E~0); 418528#L867-1 assume !(1 == ~T3_E~0); 418527#L872-1 assume !(1 == ~T4_E~0); 418526#L877-1 assume !(1 == ~T5_E~0); 418525#L882-1 assume !(1 == ~T6_E~0); 418524#L887-1 assume !(1 == ~T7_E~0); 418523#L892-1 assume !(1 == ~E_M~0); 418522#L897-1 assume !(1 == ~E_1~0); 418521#L902-1 assume !(1 == ~E_2~0); 418520#L907-1 assume !(1 == ~E_3~0); 418519#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 418217#L917-1 assume !(1 == ~E_5~0); 418218#L922-1 assume !(1 == ~E_6~0); 418445#L927-1 assume !(1 == ~E_7~0); 418205#L932-1 assume { :end_inline_reset_delta_events } true; 418206#L1178-2 [2024-11-09 16:07:58,638 INFO L747 eck$LassoCheckResult]: Loop: 418206#L1178-2 assume !false; 426288#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 426285#L744-1 assume !false; 426283#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 426281#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 426267#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 426266#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 426264#L641 assume !(0 != eval_~tmp~0#1); 426265#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 427935#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 427927#L769-3 assume !(0 == ~M_E~0); 427920#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 427916#L774-3 assume !(0 == ~T2_E~0); 427907#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 427899#L784-3 assume !(0 == ~T4_E~0); 427892#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 427884#L794-3 assume !(0 == ~T6_E~0); 427877#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 427870#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 427862#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 427855#L814-3 assume !(0 == ~E_2~0); 427848#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 427838#L824-3 assume !(0 == ~E_4~0); 427839#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 428181#L834-3 assume !(0 == ~E_6~0); 428180#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 428179#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 428178#L376-27 assume 1 == ~m_pc~0; 428176#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 428175#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 428173#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 428171#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 428169#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 428167#L395-27 assume !(1 == ~t1_pc~0); 428164#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 428162#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 428160#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 428158#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 428156#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 428154#L414-27 assume 1 == ~t2_pc~0; 428151#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 428149#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 428147#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 428145#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 428143#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 428141#L433-27 assume !(1 == ~t3_pc~0); 428138#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 428136#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 428134#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 428132#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 428130#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 428078#L452-27 assume !(1 == ~t4_pc~0); 427805#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 427986#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 427985#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 427984#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 427982#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 427981#L471-27 assume !(1 == ~t5_pc~0); 427980#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 427979#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 427977#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 427975#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 427973#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 427970#L490-27 assume !(1 == ~t6_pc~0); 427968#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 427966#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 427964#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 427962#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 427960#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 427957#L509-27 assume 1 == ~t7_pc~0; 427956#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 427951#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 427946#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 427940#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 427934#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 427926#L857-3 assume !(1 == ~M_E~0); 421838#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 427915#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 427906#L867-3 assume !(1 == ~T3_E~0); 427898#L872-3 assume !(1 == ~T4_E~0); 427891#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 427883#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 427876#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 427869#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 427861#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 427854#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 427847#L907-3 assume !(1 == ~E_3~0); 427766#L912-3 assume !(1 == ~E_4~0); 427759#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 427752#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 427746#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 426733#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 426730#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 426721#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 426719#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 421662#L1197 assume !(0 == start_simulation_~tmp~3#1); 421663#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 426600#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 426591#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 426589#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 426586#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 426584#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 426582#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 426576#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 418206#L1178-2 [2024-11-09 16:07:58,638 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:58,638 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2024-11-09 16:07:58,639 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:58,639 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320888222] [2024-11-09 16:07:58,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:58,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:58,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:58,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:58,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:58,668 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320888222] [2024-11-09 16:07:58,668 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320888222] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:58,668 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:58,669 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:58,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848575700] [2024-11-09 16:07:58,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:58,669 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:58,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:58,669 INFO L85 PathProgramCache]: Analyzing trace with hash -955540905, now seen corresponding path program 1 times [2024-11-09 16:07:58,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:58,672 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607255054] [2024-11-09 16:07:58,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:58,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:58,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:58,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:58,693 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:58,693 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607255054] [2024-11-09 16:07:58,693 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607255054] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:58,693 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:58,693 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:58,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2066699518] [2024-11-09 16:07:58,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:58,694 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:58,694 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:58,694 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:07:58,694 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:07:58,694 INFO L87 Difference]: Start difference. First operand 21486 states and 30340 transitions. cyclomatic complexity: 8870 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:58,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:58,906 INFO L93 Difference]: Finished difference Result 27322 states and 38330 transitions. [2024-11-09 16:07:58,906 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27322 states and 38330 transitions. [2024-11-09 16:07:58,990 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27044 [2024-11-09 16:07:59,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27322 states to 27322 states and 38330 transitions. [2024-11-09 16:07:59,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27322 [2024-11-09 16:07:59,107 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27322 [2024-11-09 16:07:59,107 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27322 states and 38330 transitions. [2024-11-09 16:07:59,122 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:59,122 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27322 states and 38330 transitions. [2024-11-09 16:07:59,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27322 states and 38330 transitions. [2024-11-09 16:07:59,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27322 to 19046. [2024-11-09 16:07:59,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19046 states, 19046 states have (on average 1.4053344534285415) internal successors, (26766), 19045 states have internal predecessors, (26766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:59,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19046 states to 19046 states and 26766 transitions. [2024-11-09 16:07:59,298 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19046 states and 26766 transitions. [2024-11-09 16:07:59,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:07:59,299 INFO L425 stractBuchiCegarLoop]: Abstraction has 19046 states and 26766 transitions. [2024-11-09 16:07:59,299 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-09 16:07:59,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19046 states and 26766 transitions. [2024-11-09 16:07:59,340 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18832 [2024-11-09 16:07:59,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:59,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:59,342 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:59,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:59,342 INFO L745 eck$LassoCheckResult]: Stem: 466568#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 466569#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 467209#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 467210#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 467178#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 467179#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 466821#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 466638#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 466639#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 466621#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 466622#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 467176#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 466954#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 466955#L769 assume !(0 == ~M_E~0); 466977#L769-2 assume !(0 == ~T1_E~0); 466978#L774-1 assume !(0 == ~T2_E~0); 467012#L779-1 assume !(0 == ~T3_E~0); 467160#L784-1 assume !(0 == ~T4_E~0); 466952#L789-1 assume !(0 == ~T5_E~0); 466953#L794-1 assume !(0 == ~T6_E~0); 467078#L799-1 assume !(0 == ~T7_E~0); 466957#L804-1 assume !(0 == ~E_M~0); 466958#L809-1 assume !(0 == ~E_1~0); 467005#L814-1 assume !(0 == ~E_2~0); 466362#L819-1 assume !(0 == ~E_3~0); 466363#L824-1 assume !(0 == ~E_4~0); 466712#L829-1 assume !(0 == ~E_5~0); 467249#L834-1 assume !(0 == ~E_6~0); 466490#L839-1 assume !(0 == ~E_7~0); 466491#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 466905#L376 assume !(1 == ~m_pc~0); 466895#L376-2 is_master_triggered_~__retres1~0#1 := 0; 466894#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 467142#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 466437#L955 assume !(0 != activate_threads_~tmp~1#1); 466438#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 466813#L395 assume !(1 == ~t1_pc~0); 466979#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 467144#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 466390#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 466391#L963 assume !(0 != activate_threads_~tmp___0~0#1); 466910#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 466911#L414 assume !(1 == ~t2_pc~0); 466493#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 466494#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 466719#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 466720#L971 assume !(0 != activate_threads_~tmp___1~0#1); 467185#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 466818#L433 assume !(1 == ~t3_pc~0); 466608#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 466609#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 466358#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 466359#L979 assume !(0 != activate_threads_~tmp___2~0#1); 466460#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 466461#L452 assume !(1 == ~t4_pc~0); 466617#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 466618#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 466454#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 466455#L987 assume !(0 != activate_threads_~tmp___3~0#1); 466648#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 466649#L471 assume !(1 == ~t5_pc~0); 467062#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 466631#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 466632#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 467146#L995 assume !(0 != activate_threads_~tmp___4~0#1); 467239#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 467240#L490 assume !(1 == ~t6_pc~0); 466907#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 466908#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 466706#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 466707#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 466832#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 466794#L509 assume !(1 == ~t7_pc~0); 466795#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 466594#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 466595#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 466655#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 466656#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 467193#L857 assume !(1 == ~M_E~0); 466442#L857-2 assume !(1 == ~T1_E~0); 466443#L862-1 assume !(1 == ~T2_E~0); 466723#L867-1 assume !(1 == ~T3_E~0); 466728#L872-1 assume !(1 == ~T4_E~0); 466819#L877-1 assume !(1 == ~T5_E~0); 467033#L882-1 assume !(1 == ~T6_E~0); 467215#L887-1 assume !(1 == ~T7_E~0); 467101#L892-1 assume !(1 == ~E_M~0); 467102#L897-1 assume !(1 == ~E_1~0); 466746#L902-1 assume !(1 == ~E_2~0); 466747#L907-1 assume !(1 == ~E_3~0); 467051#L912-1 assume !(1 == ~E_4~0); 467042#L917-1 assume !(1 == ~E_5~0); 467043#L922-1 assume !(1 == ~E_6~0); 467252#L927-1 assume !(1 == ~E_7~0); 467027#L932-1 assume { :end_inline_reset_delta_events } true; 467028#L1178-2 [2024-11-09 16:07:59,342 INFO L747 eck$LassoCheckResult]: Loop: 467028#L1178-2 assume !false; 478397#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 478395#L744-1 assume !false; 478386#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 478347#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 478336#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 478334#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 478331#L641 assume !(0 != eval_~tmp~0#1); 478332#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 480200#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 480196#L769-3 assume !(0 == ~M_E~0); 480154#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 480153#L774-3 assume !(0 == ~T2_E~0); 480150#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 480146#L784-3 assume !(0 == ~T4_E~0); 480141#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 480137#L794-3 assume !(0 == ~T6_E~0); 478855#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 478854#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 478853#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 478852#L814-3 assume !(0 == ~E_2~0); 478851#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 478850#L824-3 assume !(0 == ~E_4~0); 478849#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 478848#L834-3 assume !(0 == ~E_6~0); 478847#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 478846#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 478845#L376-27 assume !(1 == ~m_pc~0); 478844#L376-29 is_master_triggered_~__retres1~0#1 := 0; 478841#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 478840#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 478839#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 478838#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 478837#L395-27 assume !(1 == ~t1_pc~0); 478836#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 478835#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 478834#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 478833#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 478832#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 478831#L414-27 assume !(1 == ~t2_pc~0); 478830#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 478828#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 478827#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 478826#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 478825#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 478824#L433-27 assume !(1 == ~t3_pc~0); 478823#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 478822#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 478821#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 478820#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 478819#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 478817#L452-27 assume !(1 == ~t4_pc~0); 478815#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 478814#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 478813#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 478812#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 478811#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 478810#L471-27 assume !(1 == ~t5_pc~0); 478808#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 478805#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 478803#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 478801#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 478799#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 478797#L490-27 assume !(1 == ~t6_pc~0); 478795#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 478792#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 478790#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 478788#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 478786#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 478784#L509-27 assume 1 == ~t7_pc~0; 478782#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 478783#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 478818#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 478772#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 478770#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 478768#L857-3 assume !(1 == ~M_E~0); 471017#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 478765#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 478763#L867-3 assume !(1 == ~T3_E~0); 478761#L872-3 assume !(1 == ~T4_E~0); 478759#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 478757#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 478754#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 478752#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 478750#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 478748#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 478746#L907-3 assume !(1 == ~E_3~0); 478744#L912-3 assume !(1 == ~E_4~0); 478742#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 478740#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 478738#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 478736#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 478734#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 478725#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 478723#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 471119#L1197 assume !(0 == start_simulation_~tmp~3#1); 471120#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 478717#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 478708#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 478706#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 478702#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 478700#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 478698#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 478696#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 467028#L1178-2 [2024-11-09 16:07:59,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:59,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2024-11-09 16:07:59,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:59,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49282120] [2024-11-09 16:07:59,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:59,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:59,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:59,354 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:59,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:59,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:59,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:59,389 INFO L85 PathProgramCache]: Analyzing trace with hash 1874755417, now seen corresponding path program 1 times [2024-11-09 16:07:59,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:59,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931585342] [2024-11-09 16:07:59,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:59,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:59,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:59,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:59,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:59,413 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [931585342] [2024-11-09 16:07:59,413 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [931585342] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:59,413 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:59,413 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:59,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1640218742] [2024-11-09 16:07:59,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:59,413 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:59,413 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:59,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:59,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:59,414 INFO L87 Difference]: Start difference. First operand 19046 states and 26766 transitions. cyclomatic complexity: 7736 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:59,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:59,627 INFO L93 Difference]: Finished difference Result 21486 states and 30175 transitions. [2024-11-09 16:07:59,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21486 states and 30175 transitions. [2024-11-09 16:07:59,706 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21200 [2024-11-09 16:07:59,753 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21486 states to 21486 states and 30175 transitions. [2024-11-09 16:07:59,753 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21486 [2024-11-09 16:07:59,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21486 [2024-11-09 16:07:59,767 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21486 states and 30175 transitions. [2024-11-09 16:07:59,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:59,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21486 states and 30175 transitions. [2024-11-09 16:07:59,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21486 states and 30175 transitions. [2024-11-09 16:07:59,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21486 to 21486. [2024-11-09 16:07:59,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21486 states, 21486 states have (on average 1.4044028669831519) internal successors, (30175), 21485 states have internal predecessors, (30175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:59,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21486 states to 21486 states and 30175 transitions. [2024-11-09 16:07:59,995 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21486 states and 30175 transitions. [2024-11-09 16:07:59,995 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:59,995 INFO L425 stractBuchiCegarLoop]: Abstraction has 21486 states and 30175 transitions. [2024-11-09 16:07:59,995 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-09 16:07:59,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21486 states and 30175 transitions. [2024-11-09 16:08:00,055 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21200 [2024-11-09 16:08:00,055 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:00,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:00,057 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:00,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:00,057 INFO L745 eck$LassoCheckResult]: Stem: 507110#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 507111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 507759#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 507760#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 507722#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 507723#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 507368#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 507180#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 507181#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 507162#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 507163#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 507719#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 507506#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 507507#L769 assume !(0 == ~M_E~0); 507528#L769-2 assume !(0 == ~T1_E~0); 507529#L774-1 assume !(0 == ~T2_E~0); 507561#L779-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 507802#L784-1 assume !(0 == ~T4_E~0); 507504#L789-1 assume !(0 == ~T5_E~0); 507505#L794-1 assume !(0 == ~T6_E~0); 507621#L799-1 assume !(0 == ~T7_E~0); 507883#L804-1 assume !(0 == ~E_M~0); 507915#L809-1 assume !(0 == ~E_1~0); 507731#L814-1 assume !(0 == ~E_2~0); 507732#L819-1 assume !(0 == ~E_3~0); 507253#L824-1 assume !(0 == ~E_4~0); 507254#L829-1 assume !(0 == ~E_5~0); 507800#L834-1 assume !(0 == ~E_6~0); 507031#L839-1 assume !(0 == ~E_7~0); 507032#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 507626#L376 assume !(1 == ~m_pc~0); 507441#L376-2 is_master_triggered_~__retres1~0#1 := 0; 507440#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 507681#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 507682#L955 assume !(0 != activate_threads_~tmp~1#1); 507912#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 507530#L395 assume !(1 == ~t1_pc~0); 507531#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 507706#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 507707#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 507746#L963 assume !(0 != activate_threads_~tmp___0~0#1); 507747#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 507911#L414 assume !(1 == ~t2_pc~0); 507034#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 507035#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 507262#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 507263#L971 assume !(0 != activate_threads_~tmp___1~0#1); 507807#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 507365#L433 assume !(1 == ~t3_pc~0); 507152#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 507153#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 507908#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 507907#L979 assume !(0 != activate_threads_~tmp___2~0#1); 507906#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 507862#L452 assume !(1 == ~t4_pc~0); 507848#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 507491#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 506994#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 506995#L987 assume !(0 != activate_threads_~tmp___3~0#1); 507190#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 507191#L471 assume !(1 == ~t5_pc~0); 507605#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 507175#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 507176#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 507879#L995 assume !(0 != activate_threads_~tmp___4~0#1); 507880#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 507833#L490 assume !(1 == ~t6_pc~0); 507834#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 507496#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 507497#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 507899#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 507898#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 507897#L509 assume !(1 == ~t7_pc~0); 507896#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 507902#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 507856#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 507857#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 507891#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 507890#L857 assume !(1 == ~M_E~0); 507889#L857-2 assume !(1 == ~T1_E~0); 507266#L862-1 assume !(1 == ~T2_E~0); 507267#L867-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 507272#L872-1 assume !(1 == ~T4_E~0); 507366#L877-1 assume !(1 == ~T5_E~0); 507581#L882-1 assume !(1 == ~T6_E~0); 507766#L887-1 assume !(1 == ~T7_E~0); 507645#L892-1 assume !(1 == ~E_M~0); 507646#L897-1 assume !(1 == ~E_1~0); 507292#L902-1 assume !(1 == ~E_2~0); 507293#L907-1 assume !(1 == ~E_3~0); 507597#L912-1 assume !(1 == ~E_4~0); 507588#L917-1 assume !(1 == ~E_5~0); 507589#L922-1 assume !(1 == ~E_6~0); 507803#L927-1 assume !(1 == ~E_7~0); 507576#L932-1 assume { :end_inline_reset_delta_events } true; 507577#L1178-2 [2024-11-09 16:08:00,058 INFO L747 eck$LassoCheckResult]: Loop: 507577#L1178-2 assume !false; 511639#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 511638#L744-1 assume !false; 511637#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 511636#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 511627#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 511625#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 511622#L641 assume !(0 != eval_~tmp~0#1); 511620#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 511618#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 511616#L769-3 assume !(0 == ~M_E~0); 511614#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 511612#L774-3 assume !(0 == ~T2_E~0); 511609#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 511607#L784-3 assume !(0 == ~T4_E~0); 511605#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 511603#L794-3 assume !(0 == ~T6_E~0); 511601#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 511598#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 511596#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 511594#L814-3 assume !(0 == ~E_2~0); 511592#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 511590#L824-3 assume !(0 == ~E_4~0); 511588#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 511586#L834-3 assume !(0 == ~E_6~0); 511584#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 511582#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 511580#L376-27 assume !(1 == ~m_pc~0); 511578#L376-29 is_master_triggered_~__retres1~0#1 := 0; 511575#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 511572#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 511570#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 511568#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 511566#L395-27 assume !(1 == ~t1_pc~0); 511564#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 511562#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 511560#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 511558#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 511556#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 511554#L414-27 assume !(1 == ~t2_pc~0); 511552#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 511548#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 511546#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 511544#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 511542#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 511540#L433-27 assume !(1 == ~t3_pc~0); 511538#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 511536#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 511534#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 511532#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 511530#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 511528#L452-27 assume !(1 == ~t4_pc~0); 511525#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 511523#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 511521#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 511519#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 511517#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 511515#L471-27 assume !(1 == ~t5_pc~0); 511513#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 511509#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 511507#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 511505#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 511503#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 511500#L490-27 assume !(1 == ~t6_pc~0); 511498#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 511496#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 511495#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 511493#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 511492#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 511491#L509-27 assume 1 == ~t7_pc~0; 511490#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 511488#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 511486#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 511483#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 511482#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 511480#L857-3 assume !(1 == ~M_E~0); 511131#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 511476#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 511474#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 511471#L872-3 assume !(1 == ~T4_E~0); 511469#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 511467#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 511465#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 511463#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 511461#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 511459#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 511457#L907-3 assume !(1 == ~E_3~0); 511455#L912-3 assume !(1 == ~E_4~0); 511452#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 511450#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 511448#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 511446#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 511444#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 511435#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 511433#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 511430#L1197 assume !(0 == start_simulation_~tmp~3#1); 511431#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 511781#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 511773#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 511772#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 511771#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 511770#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 511769#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 511768#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 507577#L1178-2 [2024-11-09 16:08:00,058 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:00,058 INFO L85 PathProgramCache]: Analyzing trace with hash -1895340795, now seen corresponding path program 1 times [2024-11-09 16:08:00,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:00,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760412012] [2024-11-09 16:08:00,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:00,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:00,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:00,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:00,097 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:00,097 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760412012] [2024-11-09 16:08:00,098 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760412012] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:00,098 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:00,098 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:00,098 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190131272] [2024-11-09 16:08:00,098 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:00,098 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:00,099 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:00,099 INFO L85 PathProgramCache]: Analyzing trace with hash 1812715803, now seen corresponding path program 1 times [2024-11-09 16:08:00,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:00,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218835922] [2024-11-09 16:08:00,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:00,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:00,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:00,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:00,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:00,128 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [218835922] [2024-11-09 16:08:00,128 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [218835922] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:00,128 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:00,128 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:00,128 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1144213390] [2024-11-09 16:08:00,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:00,129 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:00,129 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:00,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:08:00,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:08:00,129 INFO L87 Difference]: Start difference. First operand 21486 states and 30175 transitions. cyclomatic complexity: 8705 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:00,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:00,245 INFO L93 Difference]: Finished difference Result 27803 states and 38940 transitions. [2024-11-09 16:08:00,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27803 states and 38940 transitions. [2024-11-09 16:08:00,349 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27520 [2024-11-09 16:08:00,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27803 states to 27803 states and 38940 transitions. [2024-11-09 16:08:00,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27803 [2024-11-09 16:08:00,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27803 [2024-11-09 16:08:00,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27803 states and 38940 transitions. [2024-11-09 16:08:00,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:00,451 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27803 states and 38940 transitions. [2024-11-09 16:08:00,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27803 states and 38940 transitions. [2024-11-09 16:08:00,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27803 to 19046. [2024-11-09 16:08:00,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19046 states, 19046 states have (on average 1.4036018061535231) internal successors, (26733), 19045 states have internal predecessors, (26733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:00,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19046 states to 19046 states and 26733 transitions. [2024-11-09 16:08:00,682 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19046 states and 26733 transitions. [2024-11-09 16:08:00,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:08:00,682 INFO L425 stractBuchiCegarLoop]: Abstraction has 19046 states and 26733 transitions. [2024-11-09 16:08:00,682 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-09 16:08:00,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19046 states and 26733 transitions. [2024-11-09 16:08:00,801 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18832 [2024-11-09 16:08:00,802 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:00,802 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:00,803 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:00,803 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:00,804 INFO L745 eck$LassoCheckResult]: Stem: 556407#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 556408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 557041#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 557042#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 557008#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 557009#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 556659#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 556479#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 556480#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 556461#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 556462#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 557007#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 556787#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 556788#L769 assume !(0 == ~M_E~0); 556809#L769-2 assume !(0 == ~T1_E~0); 556810#L774-1 assume !(0 == ~T2_E~0); 556843#L779-1 assume !(0 == ~T3_E~0); 556989#L784-1 assume !(0 == ~T4_E~0); 556785#L789-1 assume !(0 == ~T5_E~0); 556786#L794-1 assume !(0 == ~T6_E~0); 556906#L799-1 assume !(0 == ~T7_E~0); 556790#L804-1 assume !(0 == ~E_M~0); 556791#L809-1 assume !(0 == ~E_1~0); 556834#L814-1 assume !(0 == ~E_2~0); 556197#L819-1 assume !(0 == ~E_3~0); 556198#L824-1 assume !(0 == ~E_4~0); 556552#L829-1 assume !(0 == ~E_5~0); 557085#L834-1 assume !(0 == ~E_6~0); 556331#L839-1 assume !(0 == ~E_7~0); 556332#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 556739#L376 assume !(1 == ~m_pc~0); 556724#L376-2 is_master_triggered_~__retres1~0#1 := 0; 556723#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 556968#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 556274#L955 assume !(0 != activate_threads_~tmp~1#1); 556275#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 556652#L395 assume !(1 == ~t1_pc~0); 556811#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 556969#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 556227#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 556228#L963 assume !(0 != activate_threads_~tmp___0~0#1); 556743#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 556744#L414 assume !(1 == ~t2_pc~0); 556334#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 556335#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 556559#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 556560#L971 assume !(0 != activate_threads_~tmp___1~0#1); 557016#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 556656#L433 assume !(1 == ~t3_pc~0); 556448#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 556449#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 556195#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 556196#L979 assume !(0 != activate_threads_~tmp___2~0#1); 556300#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 556301#L452 assume !(1 == ~t4_pc~0); 556457#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 556458#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 556294#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 556295#L987 assume !(0 != activate_threads_~tmp___3~0#1); 556490#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 556491#L471 assume !(1 == ~t5_pc~0); 556886#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 556472#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 556473#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 556973#L995 assume !(0 != activate_threads_~tmp___4~0#1); 557074#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 557075#L490 assume !(1 == ~t6_pc~0); 556741#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 556742#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 556546#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 556547#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 556666#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 556632#L509 assume !(1 == ~t7_pc~0); 556633#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 557017#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 557136#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 556497#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 556498#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 557027#L857 assume !(1 == ~M_E~0); 556281#L857-2 assume !(1 == ~T1_E~0); 556282#L862-1 assume !(1 == ~T2_E~0); 556563#L867-1 assume !(1 == ~T3_E~0); 556568#L872-1 assume !(1 == ~T4_E~0); 556657#L877-1 assume !(1 == ~T5_E~0); 556864#L882-1 assume !(1 == ~T6_E~0); 557045#L887-1 assume !(1 == ~T7_E~0); 556929#L892-1 assume !(1 == ~E_M~0); 556930#L897-1 assume !(1 == ~E_1~0); 556584#L902-1 assume !(1 == ~E_2~0); 556585#L907-1 assume !(1 == ~E_3~0); 556877#L912-1 assume !(1 == ~E_4~0); 556870#L917-1 assume !(1 == ~E_5~0); 556871#L922-1 assume !(1 == ~E_6~0); 557088#L927-1 assume !(1 == ~E_7~0); 556859#L932-1 assume { :end_inline_reset_delta_events } true; 556860#L1178-2 [2024-11-09 16:08:00,804 INFO L747 eck$LassoCheckResult]: Loop: 556860#L1178-2 assume !false; 565355#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 565353#L744-1 assume !false; 565351#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 565348#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 565331#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 565330#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 565326#L641 assume !(0 != eval_~tmp~0#1); 565327#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 567600#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 567598#L769-3 assume !(0 == ~M_E~0); 567596#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 567594#L774-3 assume !(0 == ~T2_E~0); 567592#L779-3 assume !(0 == ~T3_E~0); 567590#L784-3 assume !(0 == ~T4_E~0); 567588#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 567586#L794-3 assume !(0 == ~T6_E~0); 567584#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 567581#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 567579#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 567577#L814-3 assume !(0 == ~E_2~0); 567575#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 567573#L824-3 assume !(0 == ~E_4~0); 567572#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 567568#L834-3 assume !(0 == ~E_6~0); 567566#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 567564#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 567562#L376-27 assume 1 == ~m_pc~0; 567558#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 567556#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567555#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 567554#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 567550#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567548#L395-27 assume !(1 == ~t1_pc~0); 567546#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 567545#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567542#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 567541#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 567540#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567537#L414-27 assume 1 == ~t2_pc~0; 567533#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 567531#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567529#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567527#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 567525#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567523#L433-27 assume !(1 == ~t3_pc~0); 567522#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 567294#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567293#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 567292#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 567291#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567289#L452-27 assume !(1 == ~t4_pc~0); 567286#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 567284#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567282#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 567280#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 567278#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 567276#L471-27 assume !(1 == ~t5_pc~0); 567274#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 567272#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 567270#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 567268#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 567266#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 567264#L490-27 assume !(1 == ~t6_pc~0); 567262#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 567260#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 567258#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 567256#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 567254#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 567252#L509-27 assume 1 == ~t7_pc~0; 567248#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 567245#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 567242#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 567239#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 567237#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 567231#L857-3 assume !(1 == ~M_E~0); 562057#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 567227#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 567225#L867-3 assume !(1 == ~T3_E~0); 567223#L872-3 assume !(1 == ~T4_E~0); 567221#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 567182#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 567178#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 567175#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 567172#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 567169#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 567166#L907-3 assume !(1 == ~E_3~0); 567162#L912-3 assume !(1 == ~E_4~0); 567159#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 567157#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 567145#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 567142#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 567140#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 567131#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 567129#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 562209#L1197 assume !(0 == start_simulation_~tmp~3#1); 562210#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 566088#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 566079#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 566077#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 566075#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 566073#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 565961#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 565956#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 556860#L1178-2 [2024-11-09 16:08:00,804 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:00,805 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2024-11-09 16:08:00,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:00,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252674834] [2024-11-09 16:08:00,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:00,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:00,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:00,812 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:00,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:00,829 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:00,829 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:00,829 INFO L85 PathProgramCache]: Analyzing trace with hash 1398844377, now seen corresponding path program 1 times [2024-11-09 16:08:00,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:00,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793378597] [2024-11-09 16:08:00,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:00,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:00,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:00,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:00,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:00,853 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793378597] [2024-11-09 16:08:00,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1793378597] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:00,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:00,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:00,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156599842] [2024-11-09 16:08:00,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:00,853 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:00,853 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:00,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:00,854 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:00,854 INFO L87 Difference]: Start difference. First operand 19046 states and 26733 transitions. cyclomatic complexity: 7703 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:00,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:00,958 INFO L93 Difference]: Finished difference Result 28590 states and 39943 transitions. [2024-11-09 16:08:00,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28590 states and 39943 transitions. [2024-11-09 16:08:01,048 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28256 [2024-11-09 16:08:01,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28590 states to 28590 states and 39943 transitions. [2024-11-09 16:08:01,107 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28590 [2024-11-09 16:08:01,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28590 [2024-11-09 16:08:01,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28590 states and 39943 transitions. [2024-11-09 16:08:01,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:01,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28590 states and 39943 transitions. [2024-11-09 16:08:01,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28590 states and 39943 transitions. [2024-11-09 16:08:01,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28590 to 28574. [2024-11-09 16:08:01,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28574 states, 28574 states have (on average 1.3973192412682858) internal successors, (39927), 28573 states have internal predecessors, (39927), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:01,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28574 states to 28574 states and 39927 transitions. [2024-11-09 16:08:01,362 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28574 states and 39927 transitions. [2024-11-09 16:08:01,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:01,362 INFO L425 stractBuchiCegarLoop]: Abstraction has 28574 states and 39927 transitions. [2024-11-09 16:08:01,362 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-09 16:08:01,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28574 states and 39927 transitions. [2024-11-09 16:08:01,432 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28240 [2024-11-09 16:08:01,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:01,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:01,434 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:01,434 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:01,434 INFO L745 eck$LassoCheckResult]: Stem: 604050#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 604051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 604702#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 604703#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 604668#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 604669#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 604307#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 604119#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 604120#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 604103#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 604104#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 604667#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 604442#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 604443#L769 assume !(0 == ~M_E~0); 604465#L769-2 assume !(0 == ~T1_E~0); 604466#L774-1 assume !(0 == ~T2_E~0); 604502#L779-1 assume !(0 == ~T3_E~0); 604647#L784-1 assume !(0 == ~T4_E~0); 604439#L789-1 assume !(0 == ~T5_E~0); 604440#L794-1 assume !(0 == ~T6_E~0); 604562#L799-1 assume !(0 == ~T7_E~0); 604445#L804-1 assume !(0 == ~E_M~0); 604446#L809-1 assume !(0 == ~E_1~0); 604493#L814-1 assume !(0 == ~E_2~0); 603843#L819-1 assume 0 == ~E_3~0;~E_3~0 := 1; 603844#L824-1 assume !(0 == ~E_4~0); 604817#L829-1 assume !(0 == ~E_5~0); 604818#L834-1 assume !(0 == ~E_6~0); 603971#L839-1 assume !(0 == ~E_7~0); 603972#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 604567#L376 assume !(1 == ~m_pc~0); 604377#L376-2 is_master_triggered_~__retres1~0#1 := 0; 604376#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 604623#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 604624#L955 assume !(0 != activate_threads_~tmp~1#1); 604847#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 604467#L395 assume !(1 == ~t1_pc~0); 604468#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 604648#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 604649#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 604691#L963 assume !(0 != activate_threads_~tmp___0~0#1); 604692#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 604846#L414 assume !(1 == ~t2_pc~0); 603974#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 603975#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 604821#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 604675#L971 assume !(0 != activate_threads_~tmp___1~0#1); 604676#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 604844#L433 assume !(1 == ~t3_pc~0); 604090#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 604091#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 603837#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 603838#L979 assume !(0 != activate_threads_~tmp___2~0#1); 604843#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 604805#L452 assume !(1 == ~t4_pc~0); 604792#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 604424#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 603934#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 603935#L987 assume !(0 != activate_threads_~tmp___3~0#1); 604129#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 604130#L471 assume !(1 == ~t5_pc~0); 604545#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 604114#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 604115#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 604819#L995 assume !(0 != activate_threads_~tmp___4~0#1); 604820#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 604780#L490 assume !(1 == ~t6_pc~0); 604781#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 604430#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 604431#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 604437#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 604438#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 604839#L509 assume !(1 == ~t7_pc~0); 604677#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 604076#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 604077#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 604833#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 604758#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 604759#L857 assume !(1 == ~M_E~0); 603922#L857-2 assume !(1 == ~T1_E~0); 603923#L862-1 assume !(1 == ~T2_E~0); 604205#L867-1 assume !(1 == ~T3_E~0); 604304#L872-1 assume !(1 == ~T4_E~0); 604305#L877-1 assume !(1 == ~T5_E~0); 604520#L882-1 assume !(1 == ~T6_E~0); 604706#L887-1 assume !(1 == ~T7_E~0); 604584#L892-1 assume !(1 == ~E_M~0); 604585#L897-1 assume !(1 == ~E_1~0); 604230#L902-1 assume !(1 == ~E_2~0); 604231#L907-1 assume 1 == ~E_3~0;~E_3~0 := 2; 604534#L912-1 assume !(1 == ~E_4~0); 604526#L917-1 assume !(1 == ~E_5~0); 604527#L922-1 assume !(1 == ~E_6~0); 604746#L927-1 assume !(1 == ~E_7~0); 604515#L932-1 assume { :end_inline_reset_delta_events } true; 604516#L1178-2 [2024-11-09 16:08:01,434 INFO L747 eck$LassoCheckResult]: Loop: 604516#L1178-2 assume !false; 621616#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 621613#L744-1 assume !false; 621611#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 621609#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 621600#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 621598#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 621595#L641 assume !(0 != eval_~tmp~0#1); 621596#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 621900#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 621899#L769-3 assume !(0 == ~M_E~0); 621898#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 621897#L774-3 assume !(0 == ~T2_E~0); 621896#L779-3 assume !(0 == ~T3_E~0); 621895#L784-3 assume !(0 == ~T4_E~0); 621894#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 621893#L794-3 assume !(0 == ~T6_E~0); 621892#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 621891#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 621889#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 621887#L814-3 assume !(0 == ~E_2~0); 621884#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 621882#L824-3 assume !(0 == ~E_4~0); 621880#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 621877#L834-3 assume !(0 == ~E_6~0); 621875#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 621873#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 621871#L376-27 assume !(1 == ~m_pc~0); 621869#L376-29 is_master_triggered_~__retres1~0#1 := 0; 621866#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 621864#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 621862#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 621860#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 621858#L395-27 assume !(1 == ~t1_pc~0); 621856#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 621854#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 621851#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 621849#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 621847#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 621845#L414-27 assume !(1 == ~t2_pc~0); 621843#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 621840#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 621838#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 621836#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 621834#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 621832#L433-27 assume !(1 == ~t3_pc~0); 621830#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 621827#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 621825#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 621823#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 621821#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 621819#L452-27 assume !(1 == ~t4_pc~0); 621816#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 621814#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 621812#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 621810#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 621808#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 621806#L471-27 assume !(1 == ~t5_pc~0); 621804#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 621802#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 621800#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 621798#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 621796#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 621794#L490-27 assume !(1 == ~t6_pc~0); 621792#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 621788#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 621786#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 621784#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 621782#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 621779#L509-27 assume !(1 == ~t7_pc~0); 621775#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 621771#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 621769#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 621767#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 621764#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 621762#L857-3 assume !(1 == ~M_E~0); 621758#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 621756#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 621754#L867-3 assume !(1 == ~T3_E~0); 621752#L872-3 assume !(1 == ~T4_E~0); 621750#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 621748#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 621747#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 621746#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 621745#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 621743#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 621740#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 621737#L912-3 assume !(1 == ~E_4~0); 621735#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 621733#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 621731#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 621729#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 621727#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 621718#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 621716#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 621713#L1197 assume !(0 == start_simulation_~tmp~3#1); 621710#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 621708#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 621698#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 621696#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 621694#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 621692#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 621690#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 621688#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 604516#L1178-2 [2024-11-09 16:08:01,435 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:01,435 INFO L85 PathProgramCache]: Analyzing trace with hash -1756125947, now seen corresponding path program 1 times [2024-11-09 16:08:01,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:01,435 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510710248] [2024-11-09 16:08:01,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:01,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:01,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:01,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:01,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:01,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510710248] [2024-11-09 16:08:01,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [510710248] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:01,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:01,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:01,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1564416626] [2024-11-09 16:08:01,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:01,469 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:01,469 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:01,469 INFO L85 PathProgramCache]: Analyzing trace with hash -613600224, now seen corresponding path program 1 times [2024-11-09 16:08:01,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:01,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114896545] [2024-11-09 16:08:01,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:01,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:01,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:01,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:01,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:01,509 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [114896545] [2024-11-09 16:08:01,509 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [114896545] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:01,509 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:01,509 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:08:01,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563773386] [2024-11-09 16:08:01,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:01,509 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:01,510 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:01,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:08:01,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:08:01,510 INFO L87 Difference]: Start difference. First operand 28574 states and 39927 transitions. cyclomatic complexity: 11369 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:01,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:01,658 INFO L93 Difference]: Finished difference Result 39059 states and 54472 transitions. [2024-11-09 16:08:01,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39059 states and 54472 transitions. [2024-11-09 16:08:01,945 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 37988 [2024-11-09 16:08:02,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39059 states to 39059 states and 54472 transitions. [2024-11-09 16:08:02,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39059 [2024-11-09 16:08:02,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39059 [2024-11-09 16:08:02,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39059 states and 54472 transitions. [2024-11-09 16:08:02,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:02,071 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39059 states and 54472 transitions. [2024-11-09 16:08:02,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39059 states and 54472 transitions. [2024-11-09 16:08:02,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39059 to 27326. [2024-11-09 16:08:02,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27326 states, 27326 states have (on average 1.3960330820464026) internal successors, (38148), 27325 states have internal predecessors, (38148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:02,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27326 states to 27326 states and 38148 transitions. [2024-11-09 16:08:02,324 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27326 states and 38148 transitions. [2024-11-09 16:08:02,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:08:02,324 INFO L425 stractBuchiCegarLoop]: Abstraction has 27326 states and 38148 transitions. [2024-11-09 16:08:02,324 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-09 16:08:02,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27326 states and 38148 transitions. [2024-11-09 16:08:02,389 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27064 [2024-11-09 16:08:02,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:02,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:02,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:02,391 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:02,391 INFO L745 eck$LassoCheckResult]: Stem: 671694#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 671695#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 672355#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 672356#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 672319#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 672320#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 671951#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 671764#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 671765#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 671746#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 671747#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 672318#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 672093#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 672094#L769 assume !(0 == ~M_E~0); 672112#L769-2 assume !(0 == ~T1_E~0); 672113#L774-1 assume !(0 == ~T2_E~0); 672146#L779-1 assume !(0 == ~T3_E~0); 672301#L784-1 assume !(0 == ~T4_E~0); 672090#L789-1 assume !(0 == ~T5_E~0); 672091#L794-1 assume !(0 == ~T6_E~0); 672211#L799-1 assume !(0 == ~T7_E~0); 672096#L804-1 assume !(0 == ~E_M~0); 672097#L809-1 assume !(0 == ~E_1~0); 672137#L814-1 assume !(0 == ~E_2~0); 671488#L819-1 assume !(0 == ~E_3~0); 671489#L824-1 assume !(0 == ~E_4~0); 671837#L829-1 assume !(0 == ~E_5~0); 672400#L834-1 assume !(0 == ~E_6~0); 671616#L839-1 assume !(0 == ~E_7~0); 671617#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 672039#L376 assume !(1 == ~m_pc~0); 672030#L376-2 is_master_triggered_~__retres1~0#1 := 0; 672029#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 672280#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 671562#L955 assume !(0 != activate_threads_~tmp~1#1); 671563#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 671944#L395 assume !(1 == ~t1_pc~0); 672114#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 672283#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 671516#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 671517#L963 assume !(0 != activate_threads_~tmp___0~0#1); 672047#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 672048#L414 assume !(1 == ~t2_pc~0); 671619#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 671620#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 671845#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 671846#L971 assume !(0 != activate_threads_~tmp___1~0#1); 672327#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 671948#L433 assume !(1 == ~t3_pc~0); 671736#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 671737#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 671482#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 671483#L979 assume !(0 != activate_threads_~tmp___2~0#1); 671585#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 671586#L452 assume !(1 == ~t4_pc~0); 671742#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 671743#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 671579#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 671580#L987 assume !(0 != activate_threads_~tmp___3~0#1); 671774#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 671775#L471 assume !(1 == ~t5_pc~0); 672192#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 671758#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 671759#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 672284#L995 assume !(0 != activate_threads_~tmp___4~0#1); 672390#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 672391#L490 assume !(1 == ~t6_pc~0); 672043#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 672044#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 671831#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 671832#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 671962#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 671924#L509 assume !(1 == ~t7_pc~0); 671925#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 671720#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 671721#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 671781#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 671782#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 672339#L857 assume !(1 == ~M_E~0); 671567#L857-2 assume !(1 == ~T1_E~0); 671568#L862-1 assume !(1 == ~T2_E~0); 671849#L867-1 assume !(1 == ~T3_E~0); 671854#L872-1 assume !(1 == ~T4_E~0); 671949#L877-1 assume !(1 == ~T5_E~0); 672168#L882-1 assume !(1 == ~T6_E~0); 672361#L887-1 assume !(1 == ~T7_E~0); 672239#L892-1 assume !(1 == ~E_M~0); 672240#L897-1 assume !(1 == ~E_1~0); 671875#L902-1 assume !(1 == ~E_2~0); 671876#L907-1 assume !(1 == ~E_3~0); 672184#L912-1 assume !(1 == ~E_4~0); 672174#L917-1 assume !(1 == ~E_5~0); 672175#L922-1 assume !(1 == ~E_6~0); 672403#L927-1 assume !(1 == ~E_7~0); 672162#L932-1 assume { :end_inline_reset_delta_events } true; 672163#L1178-2 [2024-11-09 16:08:02,391 INFO L747 eck$LassoCheckResult]: Loop: 672163#L1178-2 assume !false; 677578#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 677576#L744-1 assume !false; 677574#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 676256#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 676247#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 676245#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 676241#L641 assume !(0 != eval_~tmp~0#1); 676239#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 676237#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 676234#L769-3 assume !(0 == ~M_E~0); 676232#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 676230#L774-3 assume !(0 == ~T2_E~0); 676228#L779-3 assume !(0 == ~T3_E~0); 676226#L784-3 assume !(0 == ~T4_E~0); 676224#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 676222#L794-3 assume !(0 == ~T6_E~0); 676219#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 676217#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 676215#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 676213#L814-3 assume !(0 == ~E_2~0); 676211#L819-3 assume !(0 == ~E_3~0); 676209#L824-3 assume !(0 == ~E_4~0); 676207#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 676205#L834-3 assume !(0 == ~E_6~0); 676203#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 676201#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 676186#L376-27 assume 1 == ~m_pc~0; 676179#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 676173#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 676168#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 676163#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 676156#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 676151#L395-27 assume !(1 == ~t1_pc~0); 676146#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 676141#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 676124#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 676114#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 676107#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 676103#L414-27 assume !(1 == ~t2_pc~0); 676098#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 676088#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 676086#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 676084#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 676081#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 676076#L433-27 assume !(1 == ~t3_pc~0); 676071#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 676067#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 676063#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 676059#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 676055#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 676049#L452-27 assume !(1 == ~t4_pc~0); 676044#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 676040#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 676036#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 676032#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 676028#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 676024#L471-27 assume !(1 == ~t5_pc~0); 676020#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 676016#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 676012#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 676008#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 676004#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 676000#L490-27 assume !(1 == ~t6_pc~0); 675996#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 675991#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 675987#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 675983#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 675979#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 675975#L509-27 assume 1 == ~t7_pc~0; 675968#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 675961#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 675954#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 675947#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 675943#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 675939#L857-3 assume !(1 == ~M_E~0); 675634#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 675933#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 675929#L867-3 assume !(1 == ~T3_E~0); 675925#L872-3 assume !(1 == ~T4_E~0); 675921#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 675917#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 675911#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 675907#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 675903#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 675899#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 675895#L907-3 assume !(1 == ~E_3~0); 675848#L912-3 assume !(1 == ~E_4~0); 675844#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 675840#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 675829#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 675820#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 675819#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 675809#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 675806#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 675767#L1197 assume !(0 == start_simulation_~tmp~3#1); 675768#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 678323#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 678312#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 678308#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 678304#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 678300#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 678295#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 678292#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 672163#L1178-2 [2024-11-09 16:08:02,392 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:02,392 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 3 times [2024-11-09 16:08:02,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:02,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298235619] [2024-11-09 16:08:02,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:02,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:02,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:02,399 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:02,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:02,415 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:02,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:02,416 INFO L85 PathProgramCache]: Analyzing trace with hash -1193623908, now seen corresponding path program 1 times [2024-11-09 16:08:02,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:02,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737021963] [2024-11-09 16:08:02,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:02,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:02,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:02,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:02,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:02,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737021963] [2024-11-09 16:08:02,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [737021963] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:02,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:02,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:08:02,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [222476646] [2024-11-09 16:08:02,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:02,450 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:02,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:02,450 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:08:02,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:08:02,450 INFO L87 Difference]: Start difference. First operand 27326 states and 38148 transitions. cyclomatic complexity: 10838 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:02,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:02,558 INFO L93 Difference]: Finished difference Result 27598 states and 38420 transitions. [2024-11-09 16:08:02,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27598 states and 38420 transitions. [2024-11-09 16:08:02,647 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27336 [2024-11-09 16:08:02,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27598 states to 27598 states and 38420 transitions. [2024-11-09 16:08:02,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27598 [2024-11-09 16:08:02,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27598 [2024-11-09 16:08:02,726 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27598 states and 38420 transitions. [2024-11-09 16:08:02,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:02,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27598 states and 38420 transitions. [2024-11-09 16:08:02,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27598 states and 38420 transitions. [2024-11-09 16:08:03,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27598 to 27470. [2024-11-09 16:08:03,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27470 states, 27470 states have (on average 1.3939570440480524) internal successors, (38292), 27469 states have internal predecessors, (38292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:03,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27470 states to 27470 states and 38292 transitions. [2024-11-09 16:08:03,142 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27470 states and 38292 transitions. [2024-11-09 16:08:03,142 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:08:03,142 INFO L425 stractBuchiCegarLoop]: Abstraction has 27470 states and 38292 transitions. [2024-11-09 16:08:03,143 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-09 16:08:03,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27470 states and 38292 transitions. [2024-11-09 16:08:03,205 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27208 [2024-11-09 16:08:03,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:03,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:03,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:03,206 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:03,207 INFO L745 eck$LassoCheckResult]: Stem: 726628#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 726629#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 727271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 727272#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 727245#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 727246#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 726882#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 726696#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 726697#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 726680#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 726681#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 727244#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 727018#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 727019#L769 assume !(0 == ~M_E~0); 727039#L769-2 assume !(0 == ~T1_E~0); 727040#L774-1 assume !(0 == ~T2_E~0); 727075#L779-1 assume !(0 == ~T3_E~0); 727227#L784-1 assume !(0 == ~T4_E~0); 727016#L789-1 assume !(0 == ~T5_E~0); 727017#L794-1 assume !(0 == ~T6_E~0); 727141#L799-1 assume !(0 == ~T7_E~0); 727022#L804-1 assume !(0 == ~E_M~0); 727023#L809-1 assume !(0 == ~E_1~0); 727066#L814-1 assume !(0 == ~E_2~0); 726420#L819-1 assume !(0 == ~E_3~0); 726421#L824-1 assume !(0 == ~E_4~0); 726768#L829-1 assume !(0 == ~E_5~0); 727306#L834-1 assume !(0 == ~E_6~0); 726549#L839-1 assume !(0 == ~E_7~0); 726550#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 726964#L376 assume !(1 == ~m_pc~0); 726954#L376-2 is_master_triggered_~__retres1~0#1 := 0; 726953#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 727205#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 726494#L955 assume !(0 != activate_threads_~tmp~1#1); 726495#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 726874#L395 assume !(1 == ~t1_pc~0); 727041#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 727209#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 726448#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 726449#L963 assume !(0 != activate_threads_~tmp___0~0#1); 726970#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 726971#L414 assume !(1 == ~t2_pc~0); 726552#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 726553#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 726775#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 726776#L971 assume !(0 != activate_threads_~tmp___1~0#1); 727251#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 726879#L433 assume !(1 == ~t3_pc~0); 726668#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 726669#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 726414#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 726415#L979 assume !(0 != activate_threads_~tmp___2~0#1); 726517#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 726518#L452 assume !(1 == ~t4_pc~0); 726676#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 726677#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 726511#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 726512#L987 assume !(0 != activate_threads_~tmp___3~0#1); 726706#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 726707#L471 assume !(1 == ~t5_pc~0); 727123#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 726691#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 726692#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 727210#L995 assume !(0 != activate_threads_~tmp___4~0#1); 727295#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 727296#L490 assume !(1 == ~t6_pc~0); 726967#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 726968#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 726762#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 726763#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 726892#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 726853#L509 assume !(1 == ~t7_pc~0); 726854#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 726654#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 726655#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 726713#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 726714#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 727261#L857 assume !(1 == ~M_E~0); 726499#L857-2 assume !(1 == ~T1_E~0); 726500#L862-1 assume !(1 == ~T2_E~0); 726779#L867-1 assume !(1 == ~T3_E~0); 726785#L872-1 assume !(1 == ~T4_E~0); 726880#L877-1 assume !(1 == ~T5_E~0); 727096#L882-1 assume !(1 == ~T6_E~0); 727277#L887-1 assume !(1 == ~T7_E~0); 727166#L892-1 assume !(1 == ~E_M~0); 727167#L897-1 assume !(1 == ~E_1~0); 726804#L902-1 assume !(1 == ~E_2~0); 726805#L907-1 assume !(1 == ~E_3~0); 727113#L912-1 assume !(1 == ~E_4~0); 727102#L917-1 assume !(1 == ~E_5~0); 727103#L922-1 assume !(1 == ~E_6~0); 727309#L927-1 assume !(1 == ~E_7~0); 727091#L932-1 assume { :end_inline_reset_delta_events } true; 727092#L1178-2 [2024-11-09 16:08:03,207 INFO L747 eck$LassoCheckResult]: Loop: 727092#L1178-2 assume !false; 743676#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 743663#L744-1 assume !false; 743661#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 740559#L584 assume !(0 == ~m_st~0); 740555#L588 assume !(0 == ~t1_st~0); 740556#L592 assume !(0 == ~t2_st~0); 740558#L596 assume !(0 == ~t3_st~0); 740553#L600 assume !(0 == ~t4_st~0); 740554#L604 assume !(0 == ~t5_st~0); 740557#L608 assume !(0 == ~t6_st~0); 740551#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 740552#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 746264#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 746262#L641 assume !(0 != eval_~tmp~0#1); 746260#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 746258#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 746256#L769-3 assume !(0 == ~M_E~0); 746254#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 746252#L774-3 assume !(0 == ~T2_E~0); 746250#L779-3 assume !(0 == ~T3_E~0); 746248#L784-3 assume !(0 == ~T4_E~0); 746246#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 746244#L794-3 assume !(0 == ~T6_E~0); 746242#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 746240#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 746238#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 746236#L814-3 assume !(0 == ~E_2~0); 746234#L819-3 assume !(0 == ~E_3~0); 746232#L824-3 assume !(0 == ~E_4~0); 746230#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 746228#L834-3 assume !(0 == ~E_6~0); 746226#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 746224#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 746222#L376-27 assume 1 == ~m_pc~0; 746219#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 746215#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 746212#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 746209#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 746206#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 746202#L395-27 assume !(1 == ~t1_pc~0); 746199#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 746196#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 746193#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 746190#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 746187#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 746183#L414-27 assume 1 == ~t2_pc~0; 746179#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 746175#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 746172#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 746169#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 746166#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 746163#L433-27 assume !(1 == ~t3_pc~0); 746160#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 746157#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 746154#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 746151#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 746147#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 746144#L452-27 assume !(1 == ~t4_pc~0); 746139#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 746136#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 746133#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 746130#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 746127#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 746123#L471-27 assume !(1 == ~t5_pc~0); 746120#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 746117#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 746114#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 746111#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 746108#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 746105#L490-27 assume !(1 == ~t6_pc~0); 746102#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 746099#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 746096#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 746093#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 746090#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 746086#L509-27 assume !(1 == ~t7_pc~0); 746082#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 746076#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 746070#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 746065#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 746059#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 746056#L857-3 assume !(1 == ~M_E~0); 746052#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 746050#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 746048#L867-3 assume !(1 == ~T3_E~0); 746046#L872-3 assume !(1 == ~T4_E~0); 746044#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 746042#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 746040#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 746038#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 746036#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 746034#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 746032#L907-3 assume !(1 == ~E_3~0); 746030#L912-3 assume !(1 == ~E_4~0); 746028#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 746025#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 746021#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 746019#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 746010#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 746001#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 745733#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 745724#L1197 assume !(0 == start_simulation_~tmp~3#1); 745717#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 745604#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 745596#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 743700#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 743696#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 743694#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 743692#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 743691#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 727092#L1178-2 [2024-11-09 16:08:03,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:03,208 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 4 times [2024-11-09 16:08:03,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:03,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [636376721] [2024-11-09 16:08:03,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:03,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:03,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:03,215 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:03,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:03,236 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:03,237 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:03,237 INFO L85 PathProgramCache]: Analyzing trace with hash -1205304210, now seen corresponding path program 1 times [2024-11-09 16:08:03,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:03,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600119747] [2024-11-09 16:08:03,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:03,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:03,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:03,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:03,308 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:03,308 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600119747] [2024-11-09 16:08:03,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600119747] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:03,308 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:03,308 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:08:03,308 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1024247392] [2024-11-09 16:08:03,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:03,309 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:03,309 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:03,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:08:03,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:08:03,310 INFO L87 Difference]: Start difference. First operand 27470 states and 38292 transitions. cyclomatic complexity: 10838 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:03,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:03,504 INFO L93 Difference]: Finished difference Result 28022 states and 38683 transitions. [2024-11-09 16:08:03,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28022 states and 38683 transitions. [2024-11-09 16:08:03,590 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27760 [2024-11-09 16:08:03,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28022 states to 28022 states and 38683 transitions. [2024-11-09 16:08:03,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28022 [2024-11-09 16:08:03,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28022 [2024-11-09 16:08:03,656 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28022 states and 38683 transitions. [2024-11-09 16:08:03,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:03,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28022 states and 38683 transitions. [2024-11-09 16:08:03,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28022 states and 38683 transitions. [2024-11-09 16:08:03,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28022 to 28022. [2024-11-09 16:08:03,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28022 states, 28022 states have (on average 1.3804510741560203) internal successors, (38683), 28021 states have internal predecessors, (38683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:03,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28022 states to 28022 states and 38683 transitions. [2024-11-09 16:08:03,879 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28022 states and 38683 transitions. [2024-11-09 16:08:03,879 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:08:03,880 INFO L425 stractBuchiCegarLoop]: Abstraction has 28022 states and 38683 transitions. [2024-11-09 16:08:03,880 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-09 16:08:03,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28022 states and 38683 transitions. [2024-11-09 16:08:04,100 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27760 [2024-11-09 16:08:04,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:04,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:04,101 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:04,101 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:04,101 INFO L745 eck$LassoCheckResult]: Stem: 782128#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 782129#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 782758#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 782759#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 782724#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 782725#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 782377#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 782196#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 782197#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 782180#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 782181#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 782723#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 782511#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 782512#L769 assume !(0 == ~M_E~0); 782535#L769-2 assume !(0 == ~T1_E~0); 782536#L774-1 assume !(0 == ~T2_E~0); 782568#L779-1 assume !(0 == ~T3_E~0); 782706#L784-1 assume !(0 == ~T4_E~0); 782509#L789-1 assume !(0 == ~T5_E~0); 782510#L794-1 assume !(0 == ~T6_E~0); 782627#L799-1 assume !(0 == ~T7_E~0); 782514#L804-1 assume !(0 == ~E_M~0); 782515#L809-1 assume !(0 == ~E_1~0); 782561#L814-1 assume !(0 == ~E_2~0); 781916#L819-1 assume !(0 == ~E_3~0); 781917#L824-1 assume !(0 == ~E_4~0); 782269#L829-1 assume !(0 == ~E_5~0); 782794#L834-1 assume !(0 == ~E_6~0); 782050#L839-1 assume !(0 == ~E_7~0); 782051#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 782457#L376 assume !(1 == ~m_pc~0); 782442#L376-2 is_master_triggered_~__retres1~0#1 := 0; 782441#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 782688#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 781994#L955 assume !(0 != activate_threads_~tmp~1#1); 781995#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 782370#L395 assume !(1 == ~t1_pc~0); 782537#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 782689#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 781946#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 781947#L963 assume !(0 != activate_threads_~tmp___0~0#1); 782463#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 782464#L414 assume !(1 == ~t2_pc~0); 782053#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 782054#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 782276#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 782277#L971 assume !(0 != activate_threads_~tmp___1~0#1); 782733#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 782374#L433 assume !(1 == ~t3_pc~0); 782168#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 782169#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 781914#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 781915#L979 assume !(0 != activate_threads_~tmp___2~0#1); 782018#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 782019#L452 assume !(1 == ~t4_pc~0); 782176#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 782177#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 782012#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 782013#L987 assume !(0 != activate_threads_~tmp___3~0#1); 782206#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 782207#L471 assume !(1 == ~t5_pc~0); 782613#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 782189#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 782190#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 782693#L995 assume !(0 != activate_threads_~tmp___4~0#1); 782782#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 782783#L490 assume !(1 == ~t6_pc~0); 782461#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 782462#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 782263#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 782264#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 782384#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 782351#L509 assume !(1 == ~t7_pc~0); 782352#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 782151#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 782152#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 782213#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 782214#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 782746#L857 assume !(1 == ~M_E~0); 782001#L857-2 assume !(1 == ~T1_E~0); 782002#L862-1 assume !(1 == ~T2_E~0); 782280#L867-1 assume !(1 == ~T3_E~0); 782286#L872-1 assume !(1 == ~T4_E~0); 782375#L877-1 assume !(1 == ~T5_E~0); 782588#L882-1 assume !(1 == ~T6_E~0); 782762#L887-1 assume !(1 == ~T7_E~0); 782650#L892-1 assume !(1 == ~E_M~0); 782651#L897-1 assume !(1 == ~E_1~0); 782301#L902-1 assume !(1 == ~E_2~0); 782302#L907-1 assume !(1 == ~E_3~0); 782603#L912-1 assume !(1 == ~E_4~0); 782595#L917-1 assume !(1 == ~E_5~0); 782596#L922-1 assume !(1 == ~E_6~0); 782797#L927-1 assume !(1 == ~E_7~0); 782583#L932-1 assume { :end_inline_reset_delta_events } true; 782584#L1178-2 [2024-11-09 16:08:04,102 INFO L747 eck$LassoCheckResult]: Loop: 782584#L1178-2 assume !false; 791610#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 791569#L744-1 assume !false; 791562#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 791453#L584 assume !(0 == ~m_st~0); 791449#L588 assume !(0 == ~t1_st~0); 791450#L592 assume !(0 == ~t2_st~0); 791452#L596 assume !(0 == ~t3_st~0); 791447#L600 assume !(0 == ~t4_st~0); 791448#L604 assume !(0 == ~t5_st~0); 791451#L608 assume !(0 == ~t6_st~0); 791445#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 791446#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 791000#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 791001#L641 assume !(0 != eval_~tmp~0#1); 792941#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 792936#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 792932#L769-3 assume !(0 == ~M_E~0); 792928#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 792924#L774-3 assume !(0 == ~T2_E~0); 792920#L779-3 assume !(0 == ~T3_E~0); 792914#L784-3 assume !(0 == ~T4_E~0); 792908#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 792902#L794-3 assume !(0 == ~T6_E~0); 792896#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 792889#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 792882#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 792876#L814-3 assume !(0 == ~E_2~0); 792869#L819-3 assume !(0 == ~E_3~0); 792863#L824-3 assume !(0 == ~E_4~0); 792856#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 792851#L834-3 assume !(0 == ~E_6~0); 792845#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 792841#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 792836#L376-27 assume 1 == ~m_pc~0; 792830#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 792803#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 792800#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 792798#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 792796#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 792794#L395-27 assume !(1 == ~t1_pc~0); 792792#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 792790#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 792788#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 792786#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 792784#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 792782#L414-27 assume !(1 == ~t2_pc~0); 792780#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 792777#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 792775#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 792773#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 792771#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 792769#L433-27 assume !(1 == ~t3_pc~0); 792757#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 792752#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 792747#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 792741#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 792736#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 792718#L452-27 assume !(1 == ~t4_pc~0); 792715#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 792713#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 792711#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 792709#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 792707#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 792703#L471-27 assume !(1 == ~t5_pc~0); 792701#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 792699#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 792697#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 792694#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 792692#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 792691#L490-27 assume !(1 == ~t6_pc~0); 792690#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 792686#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 792684#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 792682#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 792681#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 792673#L509-27 assume 1 == ~t7_pc~0; 792664#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 792657#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 792650#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 792643#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 792637#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 792632#L857-3 assume !(1 == ~M_E~0); 792626#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 792277#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 792274#L867-3 assume !(1 == ~T3_E~0); 792272#L872-3 assume !(1 == ~T4_E~0); 792269#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 792267#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 792265#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 792263#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 792261#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 792259#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 792257#L907-3 assume !(1 == ~E_3~0); 792255#L912-3 assume !(1 == ~E_4~0); 792253#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 792251#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 792249#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 792247#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 792245#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 792236#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 792234#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 792202#L1197 assume !(0 == start_simulation_~tmp~3#1); 792046#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 791679#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 791670#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 791668#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 791664#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 791662#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 791660#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 791659#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 782584#L1178-2 [2024-11-09 16:08:04,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:04,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 5 times [2024-11-09 16:08:04,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:04,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698482366] [2024-11-09 16:08:04,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:04,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:04,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:04,115 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:04,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:04,152 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:04,152 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:04,156 INFO L85 PathProgramCache]: Analyzing trace with hash 498103214, now seen corresponding path program 1 times [2024-11-09 16:08:04,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:04,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585170401] [2024-11-09 16:08:04,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:04,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:04,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:04,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:04,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:04,234 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585170401] [2024-11-09 16:08:04,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [585170401] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:04,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:04,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:08:04,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134171020] [2024-11-09 16:08:04,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:04,235 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:04,235 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:04,235 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:08:04,235 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:08:04,236 INFO L87 Difference]: Start difference. First operand 28022 states and 38683 transitions. cyclomatic complexity: 10677 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:04,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:04,502 INFO L93 Difference]: Finished difference Result 29057 states and 39718 transitions. [2024-11-09 16:08:04,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29057 states and 39718 transitions. [2024-11-09 16:08:04,621 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28792 [2024-11-09 16:08:04,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29057 states to 29057 states and 39718 transitions. [2024-11-09 16:08:04,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29057 [2024-11-09 16:08:04,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29057 [2024-11-09 16:08:04,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29057 states and 39718 transitions. [2024-11-09 16:08:04,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:04,737 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29057 states and 39718 transitions. [2024-11-09 16:08:04,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29057 states and 39718 transitions. [2024-11-09 16:08:04,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29057 to 29057. [2024-11-09 16:08:05,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29057 states, 29057 states have (on average 1.366899542278969) internal successors, (39718), 29056 states have internal predecessors, (39718), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:05,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29057 states to 29057 states and 39718 transitions. [2024-11-09 16:08:05,052 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29057 states and 39718 transitions. [2024-11-09 16:08:05,052 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:08:05,053 INFO L425 stractBuchiCegarLoop]: Abstraction has 29057 states and 39718 transitions. [2024-11-09 16:08:05,053 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-09 16:08:05,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29057 states and 39718 transitions. [2024-11-09 16:08:05,135 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28792 [2024-11-09 16:08:05,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:05,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:05,137 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:05,137 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:05,138 INFO L745 eck$LassoCheckResult]: Stem: 839212#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 839213#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 839888#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 839889#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 839854#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 839855#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 839470#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 839283#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 839284#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 839265#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 839266#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 839852#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 839617#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 839618#L769 assume !(0 == ~M_E~0); 839639#L769-2 assume !(0 == ~T1_E~0); 839640#L774-1 assume !(0 == ~T2_E~0); 839677#L779-1 assume !(0 == ~T3_E~0); 839837#L784-1 assume !(0 == ~T4_E~0); 839615#L789-1 assume !(0 == ~T5_E~0); 839616#L794-1 assume !(0 == ~T6_E~0); 839743#L799-1 assume !(0 == ~T7_E~0); 839620#L804-1 assume !(0 == ~E_M~0); 839621#L809-1 assume !(0 == ~E_1~0); 839669#L814-1 assume !(0 == ~E_2~0); 839003#L819-1 assume !(0 == ~E_3~0); 839004#L824-1 assume !(0 == ~E_4~0); 839356#L829-1 assume !(0 == ~E_5~0); 839933#L834-1 assume !(0 == ~E_6~0); 839135#L839-1 assume !(0 == ~E_7~0); 839136#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 839565#L376 assume !(1 == ~m_pc~0); 839549#L376-2 is_master_triggered_~__retres1~0#1 := 0; 839548#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 839814#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 839079#L955 assume !(0 != activate_threads_~tmp~1#1); 839080#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 839462#L395 assume !(1 == ~t1_pc~0); 839641#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 839815#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 839033#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 839034#L963 assume !(0 != activate_threads_~tmp___0~0#1); 839570#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 839571#L414 assume !(1 == ~t2_pc~0); 839138#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 839863#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 840012#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 839861#L971 assume !(0 != activate_threads_~tmp___1~0#1); 839862#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 839467#L433 assume !(1 == ~t3_pc~0); 839253#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 839254#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 839001#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 839002#L979 assume !(0 != activate_threads_~tmp___2~0#1); 839104#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 839105#L452 assume !(1 == ~t4_pc~0); 839261#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 839262#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 839098#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 839099#L987 assume !(0 != activate_threads_~tmp___3~0#1); 839293#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 839294#L471 assume !(1 == ~t5_pc~0); 839726#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 839275#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 839276#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 839819#L995 assume !(0 != activate_threads_~tmp___4~0#1); 839919#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 839920#L490 assume !(1 == ~t6_pc~0); 839568#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 839569#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 839350#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 839351#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 839478#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 839439#L509 assume !(1 == ~t7_pc~0); 839440#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 839234#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 839235#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 839300#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 839301#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 839872#L857 assume !(1 == ~M_E~0); 839086#L857-2 assume !(1 == ~T1_E~0); 839087#L862-1 assume !(1 == ~T2_E~0); 839368#L867-1 assume !(1 == ~T3_E~0); 839374#L872-1 assume !(1 == ~T4_E~0); 839468#L877-1 assume !(1 == ~T5_E~0); 839699#L882-1 assume !(1 == ~T6_E~0); 839893#L887-1 assume !(1 == ~T7_E~0); 839773#L892-1 assume !(1 == ~E_M~0); 839774#L897-1 assume !(1 == ~E_1~0); 839390#L902-1 assume !(1 == ~E_2~0); 839391#L907-1 assume !(1 == ~E_3~0); 839713#L912-1 assume !(1 == ~E_4~0); 839705#L917-1 assume !(1 == ~E_5~0); 839706#L922-1 assume !(1 == ~E_6~0); 839936#L927-1 assume !(1 == ~E_7~0); 839694#L932-1 assume { :end_inline_reset_delta_events } true; 839695#L1178-2 [2024-11-09 16:08:05,138 INFO L747 eck$LassoCheckResult]: Loop: 839695#L1178-2 assume !false; 855171#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 855167#L744-1 assume !false; 854559#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 854549#L584 assume !(0 == ~m_st~0); 854545#L588 assume !(0 == ~t1_st~0); 854546#L592 assume !(0 == ~t2_st~0); 854548#L596 assume !(0 == ~t3_st~0); 854543#L600 assume !(0 == ~t4_st~0); 854544#L604 assume !(0 == ~t5_st~0); 854547#L608 assume !(0 == ~t6_st~0); 854541#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 854542#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 855453#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 855451#L641 assume !(0 != eval_~tmp~0#1); 855449#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 855447#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 855445#L769-3 assume !(0 == ~M_E~0); 855443#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 855441#L774-3 assume !(0 == ~T2_E~0); 855438#L779-3 assume !(0 == ~T3_E~0); 855436#L784-3 assume !(0 == ~T4_E~0); 855434#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 855431#L794-3 assume !(0 == ~T6_E~0); 855429#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 855427#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 855425#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 855423#L814-3 assume !(0 == ~E_2~0); 855421#L819-3 assume !(0 == ~E_3~0); 855419#L824-3 assume !(0 == ~E_4~0); 855417#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 855414#L834-3 assume !(0 == ~E_6~0); 855412#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 855410#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 855408#L376-27 assume 1 == ~m_pc~0; 855405#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 855403#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 855401#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 855399#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 855397#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 855395#L395-27 assume !(1 == ~t1_pc~0); 855393#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 855391#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 855389#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 855387#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 855385#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 855383#L414-27 assume 1 == ~t2_pc~0; 855381#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 855382#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 855464#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 855370#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 855368#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 855366#L433-27 assume !(1 == ~t3_pc~0); 855363#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 855361#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 855358#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 855356#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 855354#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 855352#L452-27 assume !(1 == ~t4_pc~0); 855349#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 855347#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 855345#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 855343#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 855341#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 855339#L471-27 assume !(1 == ~t5_pc~0); 855337#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 855335#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 855333#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 855331#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 855329#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 855327#L490-27 assume !(1 == ~t6_pc~0); 855326#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 855325#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 855324#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 855323#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 855322#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 855321#L509-27 assume 1 == ~t7_pc~0; 855320#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 855318#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 855316#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 855313#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 855312#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 855311#L857-3 assume !(1 == ~M_E~0); 854004#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 855310#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 855309#L867-3 assume !(1 == ~T3_E~0); 855306#L872-3 assume !(1 == ~T4_E~0); 855304#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 855302#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 855300#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 855297#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 855295#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 855293#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 855291#L907-3 assume !(1 == ~E_3~0); 855289#L912-3 assume !(1 == ~E_4~0); 855287#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 855285#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 855283#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 855281#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 855279#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 855270#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 855269#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 855265#L1197 assume !(0 == start_simulation_~tmp~3#1); 855262#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 855260#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 855251#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 855248#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 855246#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 855244#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 855242#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 855240#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 839695#L1178-2 [2024-11-09 16:08:05,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:05,139 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 6 times [2024-11-09 16:08:05,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:05,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884813764] [2024-11-09 16:08:05,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:05,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:05,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:05,150 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:05,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:05,171 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:05,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:05,172 INFO L85 PathProgramCache]: Analyzing trace with hash 120460397, now seen corresponding path program 1 times [2024-11-09 16:08:05,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:05,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929894114] [2024-11-09 16:08:05,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:05,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:05,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:05,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:05,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:05,247 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929894114] [2024-11-09 16:08:05,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [929894114] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:05,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:05,247 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:08:05,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489224762] [2024-11-09 16:08:05,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:05,248 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:05,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:05,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:08:05,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:08:05,248 INFO L87 Difference]: Start difference. First operand 29057 states and 39718 transitions. cyclomatic complexity: 10677 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:05,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:05,472 INFO L93 Difference]: Finished difference Result 29417 states and 39853 transitions. [2024-11-09 16:08:05,472 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29417 states and 39853 transitions. [2024-11-09 16:08:05,584 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29152 [2024-11-09 16:08:05,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29417 states to 29417 states and 39853 transitions. [2024-11-09 16:08:05,654 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29417 [2024-11-09 16:08:05,670 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29417 [2024-11-09 16:08:05,671 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29417 states and 39853 transitions. [2024-11-09 16:08:05,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:05,858 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29417 states and 39853 transitions. [2024-11-09 16:08:05,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29417 states and 39853 transitions. [2024-11-09 16:08:06,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29417 to 29417. [2024-11-09 16:08:06,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29417 states, 29417 states have (on average 1.3547608525682429) internal successors, (39853), 29416 states have internal predecessors, (39853), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:06,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29417 states to 29417 states and 39853 transitions. [2024-11-09 16:08:06,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29417 states and 39853 transitions. [2024-11-09 16:08:06,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:08:06,070 INFO L425 stractBuchiCegarLoop]: Abstraction has 29417 states and 39853 transitions. [2024-11-09 16:08:06,070 INFO L332 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-09 16:08:06,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29417 states and 39853 transitions. [2024-11-09 16:08:06,136 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29152 [2024-11-09 16:08:06,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:06,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:06,137 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:06,137 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:06,137 INFO L745 eck$LassoCheckResult]: Stem: 897692#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 897693#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 898342#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 898343#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 898313#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 898314#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 897951#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 897764#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 897765#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 897747#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 897748#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 898312#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 898085#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 898086#L769 assume !(0 == ~M_E~0); 898106#L769-2 assume !(0 == ~T1_E~0); 898107#L774-1 assume !(0 == ~T2_E~0); 898142#L779-1 assume !(0 == ~T3_E~0); 898296#L784-1 assume !(0 == ~T4_E~0); 898082#L789-1 assume !(0 == ~T5_E~0); 898083#L794-1 assume !(0 == ~T6_E~0); 898200#L799-1 assume !(0 == ~T7_E~0); 898088#L804-1 assume !(0 == ~E_M~0); 898089#L809-1 assume !(0 == ~E_1~0); 898132#L814-1 assume !(0 == ~E_2~0); 897485#L819-1 assume !(0 == ~E_3~0); 897486#L824-1 assume !(0 == ~E_4~0); 897836#L829-1 assume !(0 == ~E_5~0); 898390#L834-1 assume !(0 == ~E_6~0); 897615#L839-1 assume !(0 == ~E_7~0); 897616#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 898036#L376 assume !(1 == ~m_pc~0); 898024#L376-2 is_master_triggered_~__retres1~0#1 := 0; 898023#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 898276#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 897559#L955 assume !(0 != activate_threads_~tmp~1#1); 897560#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 897942#L395 assume !(1 == ~t1_pc~0); 898108#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 898277#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 897515#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 897516#L963 assume !(0 != activate_threads_~tmp___0~0#1); 898041#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 898042#L414 assume !(1 == ~t2_pc~0); 897618#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 898322#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 898452#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 898320#L971 assume !(0 != activate_threads_~tmp___1~0#1); 898321#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 897948#L433 assume !(1 == ~t3_pc~0); 897734#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 897735#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 897483#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 897484#L979 assume !(0 != activate_threads_~tmp___2~0#1); 897583#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 897584#L452 assume !(1 == ~t4_pc~0); 897743#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 897744#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 897577#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 897578#L987 assume !(0 != activate_threads_~tmp___3~0#1); 897774#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 897775#L471 assume !(1 == ~t5_pc~0); 898185#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 897756#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 897757#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 898281#L995 assume !(0 != activate_threads_~tmp___4~0#1); 898378#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 898379#L490 assume !(1 == ~t6_pc~0); 898039#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 898040#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 897830#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 897831#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 897960#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 897923#L509 assume !(1 == ~t7_pc~0); 897924#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 897714#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 897715#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 897781#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 897782#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 898330#L857 assume !(1 == ~M_E~0); 897566#L857-2 assume !(1 == ~T1_E~0); 897567#L862-1 assume !(1 == ~T2_E~0); 897847#L867-1 assume !(1 == ~T3_E~0); 897853#L872-1 assume !(1 == ~T4_E~0); 897949#L877-1 assume !(1 == ~T5_E~0); 898160#L882-1 assume !(1 == ~T6_E~0); 898349#L887-1 assume !(1 == ~T7_E~0); 898229#L892-1 assume !(1 == ~E_M~0); 898230#L897-1 assume !(1 == ~E_1~0); 897869#L902-1 assume !(1 == ~E_2~0); 897870#L907-1 assume !(1 == ~E_3~0); 898174#L912-1 assume !(1 == ~E_4~0); 898166#L917-1 assume !(1 == ~E_5~0); 898167#L922-1 assume !(1 == ~E_6~0); 898393#L927-1 assume !(1 == ~E_7~0); 898156#L932-1 assume { :end_inline_reset_delta_events } true; 897520#L1178-2 [2024-11-09 16:08:06,137 INFO L747 eck$LassoCheckResult]: Loop: 897520#L1178-2 assume !false; 898143#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 898144#L744-1 assume !false; 898273#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 924756#L584 assume !(0 == ~m_st~0); 924752#L588 assume !(0 == ~t1_st~0); 924753#L592 assume !(0 == ~t2_st~0); 924755#L596 assume !(0 == ~t3_st~0); 924750#L600 assume !(0 == ~t4_st~0); 924751#L604 assume !(0 == ~t5_st~0); 924754#L608 assume !(0 == ~t6_st~0); 924748#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 924749#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 925308#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 925307#L641 assume !(0 != eval_~tmp~0#1); 925306#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 925305#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 925304#L769-3 assume !(0 == ~M_E~0); 925302#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 925301#L774-3 assume !(0 == ~T2_E~0); 925300#L779-3 assume !(0 == ~T3_E~0); 925299#L784-3 assume !(0 == ~T4_E~0); 925297#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 925296#L794-3 assume !(0 == ~T6_E~0); 925295#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 925293#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 925292#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 925291#L814-3 assume !(0 == ~E_2~0); 925290#L819-3 assume !(0 == ~E_3~0); 925289#L824-3 assume !(0 == ~E_4~0); 925288#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 925287#L834-3 assume !(0 == ~E_6~0); 925286#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 925285#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 925284#L376-27 assume 1 == ~m_pc~0; 925282#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 925281#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 925280#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 925279#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 925278#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 925277#L395-27 assume !(1 == ~t1_pc~0); 925276#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 925274#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 925271#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 925269#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 925267#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 925265#L414-27 assume 1 == ~t2_pc~0; 925263#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 925264#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 925294#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 925252#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 925250#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 925247#L433-27 assume !(1 == ~t3_pc~0); 925245#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 925244#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 925240#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 925238#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 925236#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 925234#L452-27 assume !(1 == ~t4_pc~0); 925230#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 925228#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 925226#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 925224#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 925222#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 925220#L471-27 assume !(1 == ~t5_pc~0); 925218#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 925216#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 925213#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 925211#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 925209#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 925207#L490-27 assume !(1 == ~t6_pc~0); 925205#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 925203#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 925201#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 925198#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 925196#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 925194#L509-27 assume 1 == ~t7_pc~0; 925192#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 925193#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 925309#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 925182#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 925180#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 925178#L857-3 assume !(1 == ~M_E~0); 925074#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 925175#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 925171#L867-3 assume !(1 == ~T3_E~0); 925169#L872-3 assume !(1 == ~T4_E~0); 925167#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 925165#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 925162#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 925160#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 925159#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 925158#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 925157#L907-3 assume !(1 == ~E_3~0); 925156#L912-3 assume !(1 == ~E_4~0); 925155#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 925154#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 925153#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 925152#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 925151#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 925141#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 924746#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 924207#L1197 assume !(0 == start_simulation_~tmp~3#1); 924208#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 926326#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 926317#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 897513#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 897514#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 898284#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 898028#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 897519#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 897520#L1178-2 [2024-11-09 16:08:06,138 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:06,138 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 7 times [2024-11-09 16:08:06,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:06,138 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272968555] [2024-11-09 16:08:06,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:06,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:06,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:06,144 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:06,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:06,158 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:06,158 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:06,158 INFO L85 PathProgramCache]: Analyzing trace with hash 1507245807, now seen corresponding path program 1 times [2024-11-09 16:08:06,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:06,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609584046] [2024-11-09 16:08:06,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:06,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:06,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:06,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:06,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:06,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [609584046] [2024-11-09 16:08:06,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [609584046] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:06,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:06,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:08:06,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229563812] [2024-11-09 16:08:06,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:06,198 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:06,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:06,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:08:06,198 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:08:06,199 INFO L87 Difference]: Start difference. First operand 29417 states and 39853 transitions. cyclomatic complexity: 10452 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:06,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:06,358 INFO L93 Difference]: Finished difference Result 29513 states and 39628 transitions. [2024-11-09 16:08:06,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29513 states and 39628 transitions. [2024-11-09 16:08:06,445 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29248 [2024-11-09 16:08:06,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29513 states to 29513 states and 39628 transitions. [2024-11-09 16:08:06,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29513 [2024-11-09 16:08:06,516 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29513 [2024-11-09 16:08:06,516 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29513 states and 39628 transitions. [2024-11-09 16:08:06,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:06,533 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29513 states and 39628 transitions. [2024-11-09 16:08:06,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29513 states and 39628 transitions. [2024-11-09 16:08:06,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29513 to 29513. [2024-11-09 16:08:06,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29513 states, 29513 states have (on average 1.3427303222308813) internal successors, (39628), 29512 states have internal predecessors, (39628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:06,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29513 states to 29513 states and 39628 transitions. [2024-11-09 16:08:06,753 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29513 states and 39628 transitions. [2024-11-09 16:08:06,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:08:06,754 INFO L425 stractBuchiCegarLoop]: Abstraction has 29513 states and 39628 transitions. [2024-11-09 16:08:06,754 INFO L332 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-09 16:08:06,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29513 states and 39628 transitions. [2024-11-09 16:08:06,933 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29248 [2024-11-09 16:08:06,933 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:06,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:06,934 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:06,934 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:06,934 INFO L745 eck$LassoCheckResult]: Stem: 956629#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 956630#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 957276#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 957277#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 957247#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 957248#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 956888#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 956700#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 956701#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 956683#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 956684#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 957246#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 957026#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 957027#L769 assume !(0 == ~M_E~0); 957048#L769-2 assume !(0 == ~T1_E~0); 957049#L774-1 assume !(0 == ~T2_E~0); 957080#L779-1 assume !(0 == ~T3_E~0); 957233#L784-1 assume !(0 == ~T4_E~0); 957023#L789-1 assume !(0 == ~T5_E~0); 957024#L794-1 assume !(0 == ~T6_E~0); 957144#L799-1 assume !(0 == ~T7_E~0); 957029#L804-1 assume !(0 == ~E_M~0); 957030#L809-1 assume !(0 == ~E_1~0); 957072#L814-1 assume !(0 == ~E_2~0); 956423#L819-1 assume !(0 == ~E_3~0); 956424#L824-1 assume !(0 == ~E_4~0); 956773#L829-1 assume !(0 == ~E_5~0); 957316#L834-1 assume !(0 == ~E_6~0); 956553#L839-1 assume !(0 == ~E_7~0); 956554#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 956976#L376 assume !(1 == ~m_pc~0); 956961#L376-2 is_master_triggered_~__retres1~0#1 := 0; 956960#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 957213#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 956497#L955 assume !(0 != activate_threads_~tmp~1#1); 956498#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 956878#L395 assume !(1 == ~t1_pc~0); 957050#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 957214#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 956453#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 956454#L963 assume !(0 != activate_threads_~tmp___0~0#1); 956981#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 956982#L414 assume !(1 == ~t2_pc~0); 956556#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 957255#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 957386#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 957253#L971 assume !(0 != activate_threads_~tmp___1~0#1); 957254#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 956884#L433 assume !(1 == ~t3_pc~0); 956671#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 956672#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 956421#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 956422#L979 assume !(0 != activate_threads_~tmp___2~0#1); 956522#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 956523#L452 assume !(1 == ~t4_pc~0); 956679#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 956680#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 956516#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 956517#L987 assume !(0 != activate_threads_~tmp___3~0#1); 956710#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 956711#L471 assume !(1 == ~t5_pc~0); 957128#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 956693#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 956694#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 957217#L995 assume !(0 != activate_threads_~tmp___4~0#1); 957305#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 957306#L490 assume !(1 == ~t6_pc~0); 956979#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 956980#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 956767#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 956768#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 956896#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 956859#L509 assume !(1 == ~t7_pc~0); 956860#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 956652#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 956653#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 956717#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 956718#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 957263#L857 assume !(1 == ~M_E~0); 956504#L857-2 assume !(1 == ~T1_E~0); 956505#L862-1 assume !(1 == ~T2_E~0); 956784#L867-1 assume !(1 == ~T3_E~0); 956790#L872-1 assume !(1 == ~T4_E~0); 956885#L877-1 assume !(1 == ~T5_E~0); 957102#L882-1 assume !(1 == ~T6_E~0); 957282#L887-1 assume !(1 == ~T7_E~0); 957173#L892-1 assume !(1 == ~E_M~0); 957174#L897-1 assume !(1 == ~E_1~0); 956806#L902-1 assume !(1 == ~E_2~0); 956807#L907-1 assume !(1 == ~E_3~0); 957116#L912-1 assume !(1 == ~E_4~0); 957109#L917-1 assume !(1 == ~E_5~0); 957110#L922-1 assume !(1 == ~E_6~0); 957320#L927-1 assume !(1 == ~E_7~0); 957097#L932-1 assume { :end_inline_reset_delta_events } true; 957098#L1178-2 [2024-11-09 16:08:06,935 INFO L747 eck$LassoCheckResult]: Loop: 957098#L1178-2 assume !false; 969135#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 969131#L744-1 assume !false; 969129#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 969127#L584 assume !(0 == ~m_st~0); 969123#L588 assume !(0 == ~t1_st~0); 969124#L592 assume !(0 == ~t2_st~0); 969126#L596 assume !(0 == ~t3_st~0); 969121#L600 assume !(0 == ~t4_st~0); 969122#L604 assume !(0 == ~t5_st~0); 969125#L608 assume !(0 == ~t6_st~0); 969119#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 969120#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 970178#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 970176#L641 assume !(0 != eval_~tmp~0#1); 970173#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 970171#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 970169#L769-3 assume !(0 == ~M_E~0); 970167#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 970165#L774-3 assume !(0 == ~T2_E~0); 970163#L779-3 assume !(0 == ~T3_E~0); 970161#L784-3 assume !(0 == ~T4_E~0); 970159#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 970157#L794-3 assume !(0 == ~T6_E~0); 970155#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 970153#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 970149#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 970147#L814-3 assume !(0 == ~E_2~0); 970145#L819-3 assume !(0 == ~E_3~0); 970143#L824-3 assume !(0 == ~E_4~0); 970140#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 970138#L834-3 assume !(0 == ~E_6~0); 970135#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 970133#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 970131#L376-27 assume 1 == ~m_pc~0; 970128#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 970125#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 970123#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 970119#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 970117#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 970115#L395-27 assume !(1 == ~t1_pc~0); 970113#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 970110#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 970108#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 970106#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 970103#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 970101#L414-27 assume 1 == ~t2_pc~0; 970099#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 970100#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 970183#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 970090#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 970088#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 970086#L433-27 assume !(1 == ~t3_pc~0); 970084#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 970082#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 970080#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 970076#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 970074#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 970072#L452-27 assume !(1 == ~t4_pc~0); 970069#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 970066#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 970064#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 970063#L987-27 assume !(0 != activate_threads_~tmp___3~0#1); 970059#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 970057#L471-27 assume !(1 == ~t5_pc~0); 970055#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 970054#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 970051#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 970050#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 970049#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 970047#L490-27 assume !(1 == ~t6_pc~0); 970045#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 970043#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 970042#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 970039#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 970038#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 970037#L509-27 assume 1 == ~t7_pc~0; 970036#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 970035#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 970033#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 970029#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 970026#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 970022#L857-3 assume !(1 == ~M_E~0); 969785#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 970015#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 970012#L867-3 assume !(1 == ~T3_E~0); 970009#L872-3 assume !(1 == ~T4_E~0); 970008#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 970007#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 970006#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 970004#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 970003#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 970002#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 970001#L907-3 assume !(1 == ~E_3~0); 970000#L912-3 assume !(1 == ~E_4~0); 969999#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 969998#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 969997#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 969996#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 969995#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 969987#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 969986#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 969984#L1197 assume !(0 == start_simulation_~tmp~3#1); 969985#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 969194#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 969185#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 969183#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 969181#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 969179#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 969177#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 969175#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 957098#L1178-2 [2024-11-09 16:08:06,935 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:06,935 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 8 times [2024-11-09 16:08:06,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:06,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837543915] [2024-11-09 16:08:06,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:06,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:06,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:06,942 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:06,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:06,955 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:06,956 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:06,956 INFO L85 PathProgramCache]: Analyzing trace with hash 1491727089, now seen corresponding path program 1 times [2024-11-09 16:08:06,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:06,956 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451389904] [2024-11-09 16:08:06,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:06,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:06,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:07,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:07,000 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:07,000 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451389904] [2024-11-09 16:08:07,000 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [451389904] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:07,000 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:07,000 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:08:07,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217773234] [2024-11-09 16:08:07,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:07,001 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:07,001 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:07,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:08:07,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:08:07,001 INFO L87 Difference]: Start difference. First operand 29513 states and 39628 transitions. cyclomatic complexity: 10131 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:07,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:07,200 INFO L93 Difference]: Finished difference Result 30077 states and 40027 transitions. [2024-11-09 16:08:07,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30077 states and 40027 transitions. [2024-11-09 16:08:07,290 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29812 [2024-11-09 16:08:07,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30077 states to 30077 states and 40027 transitions. [2024-11-09 16:08:07,340 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30077 [2024-11-09 16:08:07,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30077 [2024-11-09 16:08:07,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30077 states and 40027 transitions. [2024-11-09 16:08:07,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:07,366 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30077 states and 40027 transitions. [2024-11-09 16:08:07,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30077 states and 40027 transitions. [2024-11-09 16:08:07,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30077 to 30077. [2024-11-09 16:08:07,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30077 states, 30077 states have (on average 1.3308175682415135) internal successors, (40027), 30076 states have internal predecessors, (40027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:07,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30077 states to 30077 states and 40027 transitions. [2024-11-09 16:08:07,582 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30077 states and 40027 transitions. [2024-11-09 16:08:07,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:08:07,583 INFO L425 stractBuchiCegarLoop]: Abstraction has 30077 states and 40027 transitions. [2024-11-09 16:08:07,583 INFO L332 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-09 16:08:07,583 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30077 states and 40027 transitions. [2024-11-09 16:08:07,649 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29812 [2024-11-09 16:08:07,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:07,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:07,650 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:07,650 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:07,651 INFO L745 eck$LassoCheckResult]: Stem: 1016228#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1016229#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1016893#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1016894#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1016860#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1016861#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1016494#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1016302#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1016303#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1016284#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1016285#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1016859#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1016634#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1016635#L769 assume !(0 == ~M_E~0); 1016655#L769-2 assume !(0 == ~T1_E~0); 1016656#L774-1 assume !(0 == ~T2_E~0); 1016694#L779-1 assume !(0 == ~T3_E~0); 1016843#L784-1 assume !(0 == ~T4_E~0); 1016632#L789-1 assume !(0 == ~T5_E~0); 1016633#L794-1 assume !(0 == ~T6_E~0); 1016760#L799-1 assume !(0 == ~T7_E~0); 1016637#L804-1 assume !(0 == ~E_M~0); 1016638#L809-1 assume !(0 == ~E_1~0); 1016685#L814-1 assume !(0 == ~E_2~0); 1016021#L819-1 assume !(0 == ~E_3~0); 1016022#L824-1 assume !(0 == ~E_4~0); 1016375#L829-1 assume !(0 == ~E_5~0); 1016946#L834-1 assume !(0 == ~E_6~0); 1016151#L839-1 assume !(0 == ~E_7~0); 1016152#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1016583#L376 assume !(1 == ~m_pc~0); 1016569#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1016568#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1016827#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1016095#L955 assume !(0 != activate_threads_~tmp~1#1); 1016096#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1016486#L395 assume !(1 == ~t1_pc~0); 1016657#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1016828#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1016051#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1016052#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1016588#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1016589#L414 assume !(1 == ~t2_pc~0); 1016154#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1016870#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1017021#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1016868#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1016869#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1016491#L433 assume !(1 == ~t3_pc~0); 1016271#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1016272#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1016019#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1016020#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1016120#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1016121#L452 assume !(1 == ~t4_pc~0); 1016280#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1016281#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1016114#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1016115#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1016312#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1016313#L471 assume !(1 == ~t5_pc~0); 1016742#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1016294#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1016295#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1016831#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1016935#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1016936#L490 assume !(1 == ~t6_pc~0); 1016586#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1016587#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1016369#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1016370#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1016502#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1016466#L509 assume !(1 == ~t7_pc~0); 1016467#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1016251#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1016252#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1016319#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1016320#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1016877#L857 assume !(1 == ~M_E~0); 1016102#L857-2 assume !(1 == ~T1_E~0); 1016103#L862-1 assume !(1 == ~T2_E~0); 1016388#L867-1 assume !(1 == ~T3_E~0); 1016394#L872-1 assume !(1 == ~T4_E~0); 1016492#L877-1 assume !(1 == ~T5_E~0); 1016716#L882-1 assume !(1 == ~T6_E~0); 1016900#L887-1 assume !(1 == ~T7_E~0); 1016787#L892-1 assume !(1 == ~E_M~0); 1016788#L897-1 assume !(1 == ~E_1~0); 1016411#L902-1 assume !(1 == ~E_2~0); 1016412#L907-1 assume !(1 == ~E_3~0); 1016731#L912-1 assume !(1 == ~E_4~0); 1016724#L917-1 assume !(1 == ~E_5~0); 1016725#L922-1 assume !(1 == ~E_6~0); 1016950#L927-1 assume !(1 == ~E_7~0); 1016711#L932-1 assume { :end_inline_reset_delta_events } true; 1016712#L1178-2 [2024-11-09 16:08:07,651 INFO L747 eck$LassoCheckResult]: Loop: 1016712#L1178-2 assume !false; 1031456#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1031454#L744-1 assume !false; 1031451#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1031449#L584 assume !(0 == ~m_st~0); 1031445#L588 assume !(0 == ~t1_st~0); 1031446#L592 assume !(0 == ~t2_st~0); 1031448#L596 assume !(0 == ~t3_st~0); 1031443#L600 assume !(0 == ~t4_st~0); 1031444#L604 assume !(0 == ~t5_st~0); 1031447#L608 assume !(0 == ~t6_st~0); 1031441#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1031442#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1032285#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1032284#L641 assume !(0 != eval_~tmp~0#1); 1032283#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1032282#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1032281#L769-3 assume !(0 == ~M_E~0); 1032279#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1032277#L774-3 assume !(0 == ~T2_E~0); 1032275#L779-3 assume !(0 == ~T3_E~0); 1032273#L784-3 assume !(0 == ~T4_E~0); 1032271#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1032269#L794-3 assume !(0 == ~T6_E~0); 1032267#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1032265#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1032263#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1032261#L814-3 assume !(0 == ~E_2~0); 1032259#L819-3 assume !(0 == ~E_3~0); 1032257#L824-3 assume !(0 == ~E_4~0); 1032255#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1032253#L834-3 assume !(0 == ~E_6~0); 1032251#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1032242#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1032240#L376-27 assume !(1 == ~m_pc~0); 1032238#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1032234#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1032233#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1032231#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1032225#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1032220#L395-27 assume !(1 == ~t1_pc~0); 1032215#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1032210#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1032116#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1032108#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 1032101#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1032093#L414-27 assume 1 == ~t2_pc~0; 1032091#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1032092#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1032122#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1032066#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1032064#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1032062#L433-27 assume !(1 == ~t3_pc~0); 1032060#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1032057#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1032055#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1032053#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1032051#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1032049#L452-27 assume !(1 == ~t4_pc~0); 1032046#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1032044#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1032042#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1032039#L987-27 assume !(0 != activate_threads_~tmp___3~0#1); 1032037#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1032035#L471-27 assume !(1 == ~t5_pc~0); 1032033#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1032031#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1032029#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1032027#L995-27 assume !(0 != activate_threads_~tmp___4~0#1); 1032025#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1032023#L490-27 assume !(1 == ~t6_pc~0); 1032021#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1032019#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1032017#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1032015#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 1032013#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1032011#L509-27 assume 1 == ~t7_pc~0; 1032009#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1032010#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1032144#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1031998#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1031996#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1031994#L857-3 assume !(1 == ~M_E~0); 1031990#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1031987#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1031985#L867-3 assume !(1 == ~T3_E~0); 1031982#L872-3 assume !(1 == ~T4_E~0); 1031980#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1031978#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1031976#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1031974#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1031972#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1031970#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1031968#L907-3 assume !(1 == ~E_3~0); 1031966#L912-3 assume !(1 == ~E_4~0); 1031964#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1031962#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1031960#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1031958#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1031956#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1031947#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1031945#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1031943#L1197 assume !(0 == start_simulation_~tmp~3#1); 1031941#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1031940#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1031932#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1031931#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1031930#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1031929#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1031928#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1031926#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1016712#L1178-2 [2024-11-09 16:08:07,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:07,652 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 9 times [2024-11-09 16:08:07,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:07,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007827551] [2024-11-09 16:08:07,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:07,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:07,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:07,658 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:07,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:07,672 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:07,672 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:07,672 INFO L85 PathProgramCache]: Analyzing trace with hash -1247979980, now seen corresponding path program 1 times [2024-11-09 16:08:07,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:07,672 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709777843] [2024-11-09 16:08:07,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:07,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:07,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:07,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:07,712 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:07,712 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [709777843] [2024-11-09 16:08:07,712 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [709777843] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:07,712 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:07,712 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:08:07,712 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852028009] [2024-11-09 16:08:07,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:07,713 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:07,713 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:07,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:08:07,713 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:08:07,713 INFO L87 Difference]: Start difference. First operand 30077 states and 40027 transitions. cyclomatic complexity: 9966 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:07,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:07,907 INFO L93 Difference]: Finished difference Result 31112 states and 41062 transitions. [2024-11-09 16:08:07,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31112 states and 41062 transitions. [2024-11-09 16:08:07,994 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30844 [2024-11-09 16:08:08,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31112 states to 31112 states and 41062 transitions. [2024-11-09 16:08:08,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31112 [2024-11-09 16:08:08,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31112 [2024-11-09 16:08:08,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31112 states and 41062 transitions. [2024-11-09 16:08:08,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:08,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31112 states and 41062 transitions. [2024-11-09 16:08:08,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31112 states and 41062 transitions. [2024-11-09 16:08:08,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31112 to 31112. [2024-11-09 16:08:08,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31112 states, 31112 states have (on average 1.3198122910773977) internal successors, (41062), 31111 states have internal predecessors, (41062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:08,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31112 states to 31112 states and 41062 transitions. [2024-11-09 16:08:08,414 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31112 states and 41062 transitions. [2024-11-09 16:08:08,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:08:08,414 INFO L425 stractBuchiCegarLoop]: Abstraction has 31112 states and 41062 transitions. [2024-11-09 16:08:08,414 INFO L332 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2024-11-09 16:08:08,414 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31112 states and 41062 transitions. [2024-11-09 16:08:08,483 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30844 [2024-11-09 16:08:08,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:08,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:08,484 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:08,484 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:08,485 INFO L745 eck$LassoCheckResult]: Stem: 1077433#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1077434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1078105#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1078106#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1078070#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1078071#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1077690#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1077504#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1077505#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1077486#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1077487#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1078067#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1077830#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1077831#L769 assume !(0 == ~M_E~0); 1077850#L769-2 assume !(0 == ~T1_E~0); 1077851#L774-1 assume !(0 == ~T2_E~0); 1077884#L779-1 assume !(0 == ~T3_E~0); 1078049#L784-1 assume !(0 == ~T4_E~0); 1077828#L789-1 assume !(0 == ~T5_E~0); 1077829#L794-1 assume !(0 == ~T6_E~0); 1077952#L799-1 assume !(0 == ~T7_E~0); 1077833#L804-1 assume !(0 == ~E_M~0); 1077834#L809-1 assume !(0 == ~E_1~0); 1077876#L814-1 assume !(0 == ~E_2~0); 1077222#L819-1 assume !(0 == ~E_3~0); 1077223#L824-1 assume !(0 == ~E_4~0); 1077577#L829-1 assume !(0 == ~E_5~0); 1078153#L834-1 assume !(0 == ~E_6~0); 1077354#L839-1 assume !(0 == ~E_7~0); 1077355#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1077779#L376 assume !(1 == ~m_pc~0); 1077767#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1077777#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1078209#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1077297#L955 assume !(0 != activate_threads_~tmp~1#1); 1077298#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1077682#L395 assume !(1 == ~t1_pc~0); 1077852#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1078035#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1077250#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1077251#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1077785#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1077786#L414 assume !(1 == ~t2_pc~0); 1077357#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1078081#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1077585#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1077586#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1078080#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1077687#L433 assume !(1 == ~t3_pc~0); 1077476#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1077477#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1077216#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1077217#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1077322#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1077323#L452 assume !(1 == ~t4_pc~0); 1077482#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1077483#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1077316#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1077317#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1077514#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1077515#L471 assume !(1 == ~t5_pc~0); 1077937#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1077497#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1077498#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1078036#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1078142#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1078143#L490 assume !(1 == ~t6_pc~0); 1077782#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1077783#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1077571#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1077572#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1077702#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1077661#L509 assume !(1 == ~t7_pc~0); 1077662#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1078082#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1078210#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1077521#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1077522#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1078092#L857 assume !(1 == ~M_E~0); 1077302#L857-2 assume !(1 == ~T1_E~0); 1077303#L862-1 assume !(1 == ~T2_E~0); 1077589#L867-1 assume !(1 == ~T3_E~0); 1077595#L872-1 assume !(1 == ~T4_E~0); 1077688#L877-1 assume !(1 == ~T5_E~0); 1077910#L882-1 assume !(1 == ~T6_E~0); 1078112#L887-1 assume !(1 == ~T7_E~0); 1077984#L892-1 assume !(1 == ~E_M~0); 1077985#L897-1 assume !(1 == ~E_1~0); 1077614#L902-1 assume !(1 == ~E_2~0); 1077615#L907-1 assume !(1 == ~E_3~0); 1077927#L912-1 assume !(1 == ~E_4~0); 1077916#L917-1 assume !(1 == ~E_5~0); 1077917#L922-1 assume !(1 == ~E_6~0); 1078157#L927-1 assume !(1 == ~E_7~0); 1077905#L932-1 assume { :end_inline_reset_delta_events } true; 1077906#L1178-2 [2024-11-09 16:08:08,485 INFO L747 eck$LassoCheckResult]: Loop: 1077906#L1178-2 assume !false; 1093176#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1093174#L744-1 assume !false; 1093172#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1093170#L584 assume !(0 == ~m_st~0); 1093166#L588 assume !(0 == ~t1_st~0); 1093167#L592 assume !(0 == ~t2_st~0); 1093169#L596 assume !(0 == ~t3_st~0); 1093164#L600 assume !(0 == ~t4_st~0); 1093165#L604 assume !(0 == ~t5_st~0); 1093168#L608 assume !(0 == ~t6_st~0); 1093162#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1093163#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1101681#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1101679#L641 assume !(0 != eval_~tmp~0#1); 1101677#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1101675#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1101673#L769-3 assume !(0 == ~M_E~0); 1101671#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1101669#L774-3 assume !(0 == ~T2_E~0); 1101667#L779-3 assume !(0 == ~T3_E~0); 1101665#L784-3 assume !(0 == ~T4_E~0); 1101663#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1101661#L794-3 assume !(0 == ~T6_E~0); 1101659#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1101657#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1101655#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1101651#L814-3 assume !(0 == ~E_2~0); 1101649#L819-3 assume !(0 == ~E_3~0); 1101647#L824-3 assume !(0 == ~E_4~0); 1101645#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1101642#L834-3 assume !(0 == ~E_6~0); 1101640#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1101636#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1101634#L376-27 assume 1 == ~m_pc~0; 1101632#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1101633#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1101700#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1101622#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1101618#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1101616#L395-27 assume !(1 == ~t1_pc~0); 1101614#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1101612#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1101609#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1101607#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 1101606#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1101605#L414-27 assume 1 == ~t2_pc~0; 1101603#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1101604#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1101786#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1101592#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1101590#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1101588#L433-27 assume !(1 == ~t3_pc~0); 1101585#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1101583#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1101581#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1101579#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1101577#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1101575#L452-27 assume !(1 == ~t4_pc~0); 1101570#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1101568#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1101566#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1101564#L987-27 assume !(0 != activate_threads_~tmp___3~0#1); 1101561#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1101559#L471-27 assume !(1 == ~t5_pc~0); 1101557#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1101556#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1101555#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1101553#L995-27 assume !(0 != activate_threads_~tmp___4~0#1); 1101552#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1101551#L490-27 assume !(1 == ~t6_pc~0); 1101550#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1101549#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1101548#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1101547#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 1101546#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1101545#L509-27 assume !(1 == ~t7_pc~0); 1101543#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1101541#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1101539#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1101538#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1101536#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1101535#L857-3 assume !(1 == ~M_E~0); 1101292#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1101534#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1101533#L867-3 assume !(1 == ~T3_E~0); 1101531#L872-3 assume !(1 == ~T4_E~0); 1101529#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1101527#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1101525#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1101522#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1101520#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1101518#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1101516#L907-3 assume !(1 == ~E_3~0); 1101514#L912-3 assume !(1 == ~E_4~0); 1101512#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1101508#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1101506#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1101504#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1101502#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1101492#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1101490#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1101487#L1197 assume !(0 == start_simulation_~tmp~3#1); 1101488#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1101804#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1101796#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1101795#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1101794#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1101793#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1101792#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1101791#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1077906#L1178-2 [2024-11-09 16:08:08,485 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:08,485 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 10 times [2024-11-09 16:08:08,486 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:08,486 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237976755] [2024-11-09 16:08:08,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:08,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:08,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:08,493 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:08,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:08,507 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:08,508 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:08,508 INFO L85 PathProgramCache]: Analyzing trace with hash -1947584522, now seen corresponding path program 1 times [2024-11-09 16:08:08,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:08,508 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988868679] [2024-11-09 16:08:08,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:08,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:08,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:08,515 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:08,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:08,530 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:08,530 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:08,530 INFO L85 PathProgramCache]: Analyzing trace with hash 6687410, now seen corresponding path program 1 times [2024-11-09 16:08:08,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:08,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728322609] [2024-11-09 16:08:08,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:08,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:08,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:08,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:08,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:08,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1728322609] [2024-11-09 16:08:08,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1728322609] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:08,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:08,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:08,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [612835439] [2024-11-09 16:08:08,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:09,969 INFO L204 LassoAnalysis]: Preferences: [2024-11-09 16:08:09,970 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-09 16:08:09,970 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-09 16:08:09,970 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-09 16:08:09,970 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-09 16:08:09,970 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:09,970 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-09 16:08:09,970 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-09 16:08:09,970 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.07.cil-1.c_Iteration31_Loop [2024-11-09 16:08:09,971 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-09 16:08:09,971 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-09 16:08:09,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:09,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:09,999 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,000 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,002 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,004 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,005 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,007 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,009 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,010 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,012 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,016 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,018 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,020 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,022 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,024 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,028 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,030 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,035 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,036 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,038 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,040 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,042 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,043 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,047 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,048 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,053 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,056 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,058 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,059 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,063 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,066 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,071 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,072 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,074 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,076 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,078 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,079 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,081 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,083 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,085 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,089 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,090 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,092 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,094 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,095 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,098 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,099 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,101 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,103 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,104 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,111 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,113 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,117 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,119 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,120 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,122 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,125 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,126 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,128 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,130 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,132 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,134 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,136 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,139 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,143 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,144 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,146 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,147 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,148 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,150 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,152 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,153 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,155 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,157 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,158 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,159 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,163 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,164 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,165 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,170 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,172 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,176 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,177 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,184 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,185 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,189 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,190 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,194 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,197 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,198 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,200 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:10,680 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-09 16:08:10,680 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-09 16:08:10,682 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:10,682 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:10,684 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:10,686 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-09 16:08:10,688 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:10,688 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:10,707 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:10,707 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:10,724 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-09 16:08:10,725 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:10,725 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:10,726 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:10,731 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-09 16:08:10,732 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:10,732 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:10,759 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:10,759 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:10,776 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:10,776 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:10,776 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:10,778 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:10,779 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-09 16:08:10,783 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:10,784 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:10,797 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:10,797 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:10,811 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-09 16:08:10,812 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:10,813 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:10,814 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:10,815 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-09 16:08:10,816 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:10,816 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:10,839 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:10,839 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:10,851 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-09 16:08:10,852 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:10,852 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:10,853 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:10,855 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-09 16:08:10,856 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:10,857 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:10,871 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:10,872 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:10,884 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-09 16:08:10,885 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:10,885 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:10,888 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:10,889 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-09 16:08:10,890 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:10,890 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:10,904 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:10,904 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:10,917 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:10,918 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:10,918 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:10,922 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:10,925 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-09 16:08:10,926 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:10,927 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:10,941 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:10,941 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:10,951 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:10,952 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:10,952 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:10,956 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:10,957 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-09 16:08:10,960 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:10,960 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:10,973 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:10,973 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret22#1=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret22#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:10,987 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:10,988 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:10,988 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:10,992 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:10,992 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-09 16:08:10,993 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:10,993 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:11,005 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:11,006 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:11,016 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:11,017 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:11,017 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:11,019 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:11,020 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-09 16:08:11,021 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:11,021 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:11,033 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:11,033 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_8~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_8~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:11,044 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:11,045 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:11,045 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:11,047 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:11,048 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-09 16:08:11,049 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:11,049 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:11,068 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:11,069 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_3~0=-1} Honda state: {~E_3~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:11,079 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:11,079 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:11,080 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:11,081 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:11,085 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-09 16:08:11,086 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:11,086 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:11,098 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:11,098 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:11,109 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-09 16:08:11,109 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:11,110 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:11,112 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:11,113 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-09 16:08:11,113 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:11,113 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:11,125 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:11,125 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:11,135 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:11,136 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:11,136 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:11,140 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:11,143 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-09 16:08:11,143 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:11,144 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:11,162 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:11,162 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t7_pc~0=4} Honda state: {~t7_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:11,173 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-11-09 16:08:11,174 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:11,174 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:11,175 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:11,177 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-09 16:08:11,178 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:11,178 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:11,196 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:08:11,197 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:08:11,208 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-11-09 16:08:11,209 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:11,209 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:11,210 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:11,211 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-09 16:08:11,212 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:08:11,212 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:11,234 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:11,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:11,235 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:11,236 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:11,237 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-09 16:08:11,243 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-09 16:08:11,243 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:08:11,261 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-09 16:08:11,278 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:11,278 INFO L204 LassoAnalysis]: Preferences: [2024-11-09 16:08:11,278 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-09 16:08:11,278 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-09 16:08:11,278 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-09 16:08:11,278 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-09 16:08:11,278 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:11,278 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-09 16:08:11,278 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-09 16:08:11,278 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.07.cil-1.c_Iteration31_Loop [2024-11-09 16:08:11,278 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-09 16:08:11,279 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-09 16:08:11,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,291 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,293 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,294 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,297 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,299 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,301 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,302 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,304 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,305 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,307 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,309 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,315 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,317 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,319 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,321 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,324 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,326 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,329 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,332 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,334 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,335 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,337 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,339 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,340 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,344 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,348 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,352 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,353 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,355 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,356 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,361 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,364 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,368 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,370 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,372 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,377 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,379 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,382 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,388 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,390 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,392 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,394 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,395 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,398 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,399 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,401 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,403 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,405 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,408 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,409 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,413 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,414 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,416 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,420 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,421 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,423 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,424 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,426 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,427 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,429 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,430 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,432 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,436 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,440 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,442 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,444 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,445 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,448 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,449 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,450 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,452 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,454 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,455 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,457 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,458 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,460 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,461 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,466 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,468 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,470 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,473 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,475 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,478 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,480 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,483 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,485 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,488 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,493 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,495 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:08:11,957 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-09 16:08:11,964 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-09 16:08:11,966 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:11,966 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:11,967 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:11,969 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-09 16:08:11,970 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:11,981 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:11,982 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:11,982 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:11,982 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:11,983 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:11,987 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:11,987 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:11,990 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,001 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:12,001 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,002 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,003 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,004 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-09 16:08:12,005 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,015 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,016 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,016 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,016 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,016 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,017 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,017 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,018 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,030 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:12,030 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,030 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,031 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,033 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-09 16:08:12,034 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,045 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,046 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,046 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,046 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,046 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,046 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,046 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,047 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,058 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-09 16:08:12,059 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,059 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,061 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,062 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-09 16:08:12,064 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,075 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,075 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,075 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,075 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-09 16:08:12,075 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,079 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-09 16:08:12,079 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,081 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,103 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:12,104 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,104 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,106 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,112 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,114 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-09 16:08:12,137 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,138 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,138 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,138 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,138 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,138 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,138 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,140 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,152 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:12,152 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,153 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,154 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,155 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-09 16:08:12,156 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,166 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,166 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,166 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,166 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,166 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,167 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,167 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,168 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,178 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:12,179 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,179 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,180 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,181 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-09 16:08:12,182 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,191 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,192 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,192 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,192 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,192 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,192 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,192 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,194 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,204 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-11-09 16:08:12,204 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,205 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,206 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,208 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-09 16:08:12,208 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,219 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,219 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,220 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,220 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,220 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,221 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,221 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,222 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,233 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2024-11-09 16:08:12,233 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,233 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,234 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,235 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-09 16:08:12,237 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,247 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,247 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,248 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,248 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,248 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,248 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,248 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,250 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,260 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:12,260 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,260 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,262 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,263 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-11-09 16:08:12,264 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,274 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,274 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,274 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,274 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,275 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,275 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,275 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,277 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,288 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2024-11-09 16:08:12,288 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,288 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,289 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,290 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-11-09 16:08:12,291 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,301 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,301 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,302 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,302 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,302 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,302 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,302 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,303 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,313 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:12,314 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,314 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,317 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,318 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-11-09 16:08:12,319 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,329 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,329 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,329 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,329 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-09 16:08:12,329 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,330 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-09 16:08:12,330 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,332 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,342 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2024-11-09 16:08:12,342 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,343 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,344 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,345 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2024-11-09 16:08:12,346 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,366 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,367 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,367 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,367 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,367 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,367 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,368 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,369 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,379 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2024-11-09 16:08:12,379 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,380 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,381 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,382 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2024-11-09 16:08:12,383 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,393 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,393 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,394 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,394 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,394 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,394 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,394 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,395 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,406 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2024-11-09 16:08:12,406 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,406 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,408 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,409 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2024-11-09 16:08:12,410 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,421 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,421 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,421 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,421 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-09 16:08:12,421 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,422 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-09 16:08:12,422 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,424 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,435 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2024-11-09 16:08:12,435 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,435 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,437 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,438 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2024-11-09 16:08:12,440 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,450 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,450 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,450 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,451 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,451 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,451 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,451 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,453 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,463 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Ended with exit code 0 [2024-11-09 16:08:12,464 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,464 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,465 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,466 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2024-11-09 16:08:12,467 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,477 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,477 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,477 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,477 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-09 16:08:12,477 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,480 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-09 16:08:12,480 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,482 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:08:12,492 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2024-11-09 16:08:12,492 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,492 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,494 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,495 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2024-11-09 16:08:12,496 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:08:12,506 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:08:12,506 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:08:12,506 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:08:12,506 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:08:12,506 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:08:12,508 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:08:12,508 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:08:12,509 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-09 16:08:12,512 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-09 16:08:12,512 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-09 16:08:12,514 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:12,514 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:12,515 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:12,517 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2024-11-09 16:08:12,520 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-09 16:08:12,520 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-09 16:08:12,520 INFO L474 LassoAnalysis]: Proved termination. [2024-11-09 16:08:12,521 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_5~0) = -1*~E_5~0 + 1 Supporting invariants [] [2024-11-09 16:08:12,531 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Ended with exit code 0 [2024-11-09 16:08:12,537 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-09 16:08:12,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:12,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:12,629 INFO L255 TraceCheckSpWp]: Trace formula consists of 271 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-09 16:08:12,632 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-09 16:08:12,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:12,810 INFO L255 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-09 16:08:12,812 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-09 16:08:13,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:13,024 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-09 16:08:13,025 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31112 states and 41062 transitions. cyclomatic complexity: 9966 Second operand has 5 states, 5 states have (on average 41.2) internal successors, (206), 5 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:13,546 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31112 states and 41062 transitions. cyclomatic complexity: 9966. Second operand has 5 states, 5 states have (on average 41.2) internal successors, (206), 5 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 86802 states and 115209 transitions. Complement of second has 5 states. [2024-11-09 16:08:13,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-09 16:08:13,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 41.2) internal successors, (206), 5 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:13,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1112 transitions. [2024-11-09 16:08:13,551 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1112 transitions. Stem has 95 letters. Loop has 111 letters. [2024-11-09 16:08:13,554 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-09 16:08:13,554 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1112 transitions. Stem has 206 letters. Loop has 111 letters. [2024-11-09 16:08:13,555 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-09 16:08:13,555 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1112 transitions. Stem has 95 letters. Loop has 222 letters. [2024-11-09 16:08:13,558 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-09 16:08:13,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86802 states and 115209 transitions. [2024-11-09 16:08:14,038 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2024-11-09 16:08:14,197 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 58368 [2024-11-09 16:08:14,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86802 states to 86754 states and 115161 transitions. [2024-11-09 16:08:14,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 58845 [2024-11-09 16:08:14,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 58958 [2024-11-09 16:08:14,506 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86754 states and 115161 transitions. [2024-11-09 16:08:14,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-09 16:08:14,508 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86754 states and 115161 transitions. [2024-11-09 16:08:14,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86754 states and 115161 transitions. [2024-11-09 16:08:15,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86754 to 86593. [2024-11-09 16:08:15,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86593 states, 86593 states have (on average 1.3267585139676417) internal successors, (114888), 86592 states have internal predecessors, (114888), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:15,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86593 states to 86593 states and 114888 transitions. [2024-11-09 16:08:15,963 INFO L240 hiAutomatonCegarLoop]: Abstraction has 86593 states and 114888 transitions. [2024-11-09 16:08:15,963 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:15,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:15,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:15,964 INFO L87 Difference]: Start difference. First operand 86593 states and 114888 transitions. Second operand has 3 states, 3 states have (on average 68.66666666666667) internal successors, (206), 3 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:16,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:16,507 INFO L93 Difference]: Finished difference Result 163909 states and 214824 transitions. [2024-11-09 16:08:16,507 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 163909 states and 214824 transitions. [2024-11-09 16:08:17,123 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 110656 [2024-11-09 16:08:18,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 163909 states to 163909 states and 214824 transitions. [2024-11-09 16:08:18,391 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111405 [2024-11-09 16:08:18,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111405 [2024-11-09 16:08:18,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 163909 states and 214824 transitions. [2024-11-09 16:08:18,471 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-09 16:08:18,471 INFO L218 hiAutomatonCegarLoop]: Abstraction has 163909 states and 214824 transitions. [2024-11-09 16:08:18,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163909 states and 214824 transitions. [2024-11-09 16:08:20,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163909 to 155389. [2024-11-09 16:08:20,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 155389 states, 155389 states have (on average 1.315305459202389) internal successors, (204384), 155388 states have internal predecessors, (204384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:20,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155389 states to 155389 states and 204384 transitions. [2024-11-09 16:08:20,547 INFO L240 hiAutomatonCegarLoop]: Abstraction has 155389 states and 204384 transitions. [2024-11-09 16:08:20,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:20,547 INFO L425 stractBuchiCegarLoop]: Abstraction has 155389 states and 204384 transitions. [2024-11-09 16:08:20,547 INFO L332 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2024-11-09 16:08:20,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 155389 states and 204384 transitions. [2024-11-09 16:08:20,974 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 104976 [2024-11-09 16:08:20,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:20,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:20,977 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:20,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:20,978 INFO L745 eck$LassoCheckResult]: Stem: 1446683#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1446684#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1447974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1447975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1447912#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1447913#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1447154#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1446811#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1446812#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1446780#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1446781#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1447909#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1447438#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1447439#L769 assume !(0 == ~M_E~0); 1447479#L769-2 assume !(0 == ~T1_E~0); 1447480#L774-1 assume !(0 == ~T2_E~0); 1447541#L779-1 assume !(0 == ~T3_E~0); 1447875#L784-1 assume !(0 == ~T4_E~0); 1447433#L789-1 assume !(0 == ~T5_E~0); 1447434#L794-1 assume !(0 == ~T6_E~0); 1447677#L799-1 assume !(0 == ~T7_E~0); 1447442#L804-1 assume !(0 == ~E_M~0); 1447443#L809-1 assume !(0 == ~E_1~0); 1447525#L814-1 assume !(0 == ~E_2~0); 1446293#L819-1 assume !(0 == ~E_3~0); 1446294#L824-1 assume !(0 == ~E_4~0); 1446941#L829-1 assume !(0 == ~E_5~0); 1448079#L834-1 assume !(0 == ~E_6~0); 1446528#L839-1 assume !(0 == ~E_7~0); 1446529#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1447335#L376 assume !(1 == ~m_pc~0); 1447314#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1447331#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1448287#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1446433#L955 assume !(0 != activate_threads_~tmp~1#1); 1446434#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1447137#L395 assume !(1 == ~t1_pc~0); 1447481#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1447840#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1446344#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1446345#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1447346#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1447347#L414 assume !(1 == ~t2_pc~0); 1446531#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1447929#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1448262#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1447927#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1447928#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1447149#L433 assume !(1 == ~t3_pc~0); 1446764#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1446765#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1446283#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1446284#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1446474#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1446475#L452 assume !(1 == ~t4_pc~0); 1446774#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1446775#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1446464#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1446465#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1446826#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1446827#L471 assume !(1 == ~t5_pc~0); 1447641#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1446801#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1446802#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1447841#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1448057#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1448058#L490 assume !(1 == ~t6_pc~0); 1447341#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1447342#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1446931#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1446932#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1447179#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1447096#L509 assume !(1 == ~t7_pc~0); 1447097#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1447932#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1448286#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1446838#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1446839#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1447947#L857 assume !(1 == ~M_E~0); 1446441#L857-2 assume !(1 == ~T1_E~0); 1446442#L862-1 assume !(1 == ~T2_E~0); 1446961#L867-1 assume !(1 == ~T3_E~0); 1446972#L872-1 assume !(1 == ~T4_E~0); 1447150#L877-1 assume !(1 == ~T5_E~0); 1447583#L882-1 assume !(1 == ~T6_E~0); 1447982#L887-1 assume !(1 == ~T7_E~0); 1447733#L892-1 assume !(1 == ~E_M~0); 1447734#L897-1 assume !(1 == ~E_1~0); 1447009#L902-1 assume !(1 == ~E_2~0); 1447010#L907-1 assume !(1 == ~E_3~0); 1447618#L912-1 assume !(1 == ~E_4~0); 1447598#L917-1 assume !(1 == ~E_5~0); 1447599#L922-1 assume !(1 == ~E_6~0); 1448085#L927-1 assume !(1 == ~E_7~0); 1447574#L932-1 assume { :end_inline_reset_delta_events } true; 1447575#L1178-2 assume !false; 1476576#L1179 [2024-11-09 16:08:20,978 INFO L747 eck$LassoCheckResult]: Loop: 1476576#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1547170#L744-1 assume !false; 1547168#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1547167#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1516953#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1547164#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1547163#L641 assume 0 != eval_~tmp~0#1; 1547162#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1517010#L649 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1; 1547157#L80 assume 0 == ~m_pc~0; 1547155#L105-1 assume !false; 1547154#L92 havoc master_#t~nondet4#1;~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1547153#L376-3 assume !(1 == ~m_pc~0); 1547152#L376-5 is_master_triggered_~__retres1~0#1 := 0; 1547072#L387-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1547069#is_master_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1547067#L955-3 assume !(0 != activate_threads_~tmp~1#1); 1547063#L955-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1547061#L395-3 assume !(1 == ~t1_pc~0); 1547059#L395-5 is_transmit1_triggered_~__retres1~1#1 := 0; 1547057#L406-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1547055#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1547053#L963-3 assume !(0 != activate_threads_~tmp___0~0#1); 1547051#L963-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1547045#L414-3 assume 1 == ~t2_pc~0; 1547046#L415-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1547047#L425-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1547156#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1547035#L971-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1547033#L971-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1547031#L433-3 assume !(1 == ~t3_pc~0); 1547029#L433-5 is_transmit3_triggered_~__retres1~3#1 := 0; 1547027#L444-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1547026#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1547025#L979-3 assume !(0 != activate_threads_~tmp___2~0#1); 1547024#L979-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1547022#L452-3 assume !(1 == ~t4_pc~0); 1547017#L452-5 is_transmit4_triggered_~__retres1~4#1 := 0; 1547015#L463-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1547013#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1547011#L987-3 assume !(0 != activate_threads_~tmp___3~0#1); 1547008#L987-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1547006#L471-3 assume !(1 == ~t5_pc~0); 1547003#L471-5 is_transmit5_triggered_~__retres1~5#1 := 0; 1547001#L482-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1546999#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1546997#L995-3 assume !(0 != activate_threads_~tmp___4~0#1); 1546994#L995-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1546992#L490-3 assume !(1 == ~t6_pc~0); 1546989#L490-5 is_transmit6_triggered_~__retres1~6#1 := 0; 1546987#L501-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1546985#is_transmit6_triggered_returnLabel#2 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1546983#L1003-3 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1546981#L1003-5 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1546953#L509-3 assume 1 == ~t7_pc~0; 1546951#L510-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1546952#L520-1 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1547344#is_transmit7_triggered_returnLabel#2 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1546942#L1011-3 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1546940#L1011-5 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true; 1517028#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 1517021#master_returnLabel#1 havoc master_#t~nondet4#1;assume { :end_inline_master } true; 1517009#L649-2 havoc eval_~tmp_ndt_1~0#1; 1517001#L646-1 assume !(0 == ~t1_st~0); 1516992#L660-1 assume !(0 == ~t2_st~0); 1516985#L674-1 assume !(0 == ~t3_st~0); 1516976#L688-1 assume !(0 == ~t4_st~0); 1516970#L702-1 assume !(0 == ~t5_st~0); 1516964#L716-1 assume !(0 == ~t6_st~0); 1516958#L730-1 assume !(0 == ~t7_st~0); 1516955#L744-1 assume !false; 1516954#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1516952#L584 assume !(0 == ~m_st~0); 1516951#L588 assume !(0 == ~t1_st~0); 1516950#L592 assume !(0 == ~t2_st~0); 1516949#L596 assume !(0 == ~t3_st~0); 1516948#L600 assume !(0 == ~t4_st~0); 1516947#L604 assume !(0 == ~t5_st~0); 1516946#L608 assume !(0 == ~t6_st~0); 1516944#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1516943#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1516942#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1516940#L641 assume !(0 != eval_~tmp~0#1); 1516939#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1516938#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1516937#L769-3 assume !(0 == ~M_E~0); 1516936#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1516935#L774-3 assume !(0 == ~T2_E~0); 1516934#L779-3 assume !(0 == ~T3_E~0); 1516933#L784-3 assume !(0 == ~T4_E~0); 1516932#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1516931#L794-3 assume !(0 == ~T6_E~0); 1516930#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1516929#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1516928#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1516927#L814-3 assume !(0 == ~E_2~0); 1516926#L819-3 assume !(0 == ~E_3~0); 1516925#L824-3 assume !(0 == ~E_4~0); 1516924#L829-3 assume !(0 == ~E_5~0); 1516923#L834-3 assume !(0 == ~E_6~0); 1516922#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1516921#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1516920#L376-27 assume !(1 == ~m_pc~0); 1516919#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1517475#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1517473#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1514767#L955-27 assume !(0 != activate_threads_~tmp~1#1); 1514759#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1514752#L395-27 assume !(1 == ~t1_pc~0); 1514744#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1514736#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1514728#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1514720#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 1514713#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1514707#L414-27 assume !(1 == ~t2_pc~0); 1514702#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1514698#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1514692#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1514646#L971-27 assume !(0 != activate_threads_~tmp___1~0#1); 1514643#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1514641#L433-27 assume !(1 == ~t3_pc~0); 1514639#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1514637#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1514635#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1514633#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1514631#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1514629#L452-27 assume !(1 == ~t4_pc~0); 1514626#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1514604#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1514594#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1514585#L987-27 assume !(0 != activate_threads_~tmp___3~0#1); 1514574#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1514564#L471-27 assume !(1 == ~t5_pc~0); 1514556#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1514550#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1514528#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1514527#L995-27 assume !(0 != activate_threads_~tmp___4~0#1); 1514524#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1514522#L490-27 assume !(1 == ~t6_pc~0); 1514520#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1514508#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1514498#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1514490#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 1514484#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1514257#L509-27 assume 1 == ~t7_pc~0; 1514255#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1514256#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1514273#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1514244#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1514215#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1514209#L857-3 assume !(1 == ~M_E~0); 1511945#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1514172#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1514170#L867-3 assume !(1 == ~T3_E~0); 1514168#L872-3 assume !(1 == ~T4_E~0); 1514166#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1514163#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1514161#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1514160#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1514156#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1514154#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1514152#L907-3 assume !(1 == ~E_3~0); 1514151#L912-3 assume !(1 == ~E_4~0); 1514148#L917-3 assume !(1 == ~E_5~0); 1514147#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1514145#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1514144#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1514141#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1514142#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1516543#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1516540#L1197 assume !(0 == start_simulation_~tmp~3#1); 1516541#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1547349#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1517024#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1547347#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1547346#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1547345#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1547343#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1547342#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1547341#L1178-2 assume !false; 1476576#L1179 [2024-11-09 16:08:20,979 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:20,979 INFO L85 PathProgramCache]: Analyzing trace with hash -1048388199, now seen corresponding path program 1 times [2024-11-09 16:08:20,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:20,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821288173] [2024-11-09 16:08:20,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:20,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:20,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:20,989 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:20,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:21,006 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:21,007 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:21,007 INFO L85 PathProgramCache]: Analyzing trace with hash 1166756889, now seen corresponding path program 1 times [2024-11-09 16:08:21,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:21,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435866762] [2024-11-09 16:08:21,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:21,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:21,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:21,046 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:21,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:21,047 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435866762] [2024-11-09 16:08:21,047 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435866762] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:21,047 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:21,047 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:21,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1835974175] [2024-11-09 16:08:21,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:21,048 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:21,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:21,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:21,048 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:21,048 INFO L87 Difference]: Start difference. First operand 155389 states and 204384 transitions. cyclomatic complexity: 49043 Second operand has 3 states, 3 states have (on average 60.0) internal successors, (180), 3 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:22,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:22,578 INFO L93 Difference]: Finished difference Result 292573 states and 382680 transitions. [2024-11-09 16:08:22,578 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 292573 states and 382680 transitions. [2024-11-09 16:08:24,369 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 197920 [2024-11-09 16:08:25,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 292573 states to 292573 states and 382680 transitions. [2024-11-09 16:08:25,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 199309 [2024-11-09 16:08:25,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 199309 [2024-11-09 16:08:25,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 292573 states and 382680 transitions. [2024-11-09 16:08:25,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-09 16:08:25,148 INFO L218 hiAutomatonCegarLoop]: Abstraction has 292573 states and 382680 transitions. [2024-11-09 16:08:25,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292573 states and 382680 transitions. [2024-11-09 16:08:27,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292573 to 284221. [2024-11-09 16:08:28,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284221 states, 284221 states have (on average 1.3112894543330718) internal successors, (372696), 284220 states have internal predecessors, (372696), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:28,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284221 states to 284221 states and 372696 transitions. [2024-11-09 16:08:28,656 INFO L240 hiAutomatonCegarLoop]: Abstraction has 284221 states and 372696 transitions. [2024-11-09 16:08:28,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:28,657 INFO L425 stractBuchiCegarLoop]: Abstraction has 284221 states and 372696 transitions. [2024-11-09 16:08:28,657 INFO L332 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2024-11-09 16:08:28,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284221 states and 372696 transitions. [2024-11-09 16:08:30,157 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 192352 [2024-11-09 16:08:30,157 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:30,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:30,159 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:30,159 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:30,160 INFO L745 eck$LassoCheckResult]: Stem: 1894644#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1894645#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1895930#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1895931#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1895870#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1895871#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1895109#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1894767#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1894768#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1894736#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1894737#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1895869#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1895388#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1895389#L769 assume !(0 == ~M_E~0); 1895433#L769-2 assume !(0 == ~T1_E~0); 1895434#L774-1 assume !(0 == ~T2_E~0); 1895501#L779-1 assume !(0 == ~T3_E~0); 1895831#L784-1 assume !(0 == ~T4_E~0); 1895385#L789-1 assume !(0 == ~T5_E~0); 1895386#L794-1 assume !(0 == ~T6_E~0); 1895633#L799-1 assume !(0 == ~T7_E~0); 1895392#L804-1 assume !(0 == ~E_M~0); 1895393#L809-1 assume !(0 == ~E_1~0); 1895486#L814-1 assume !(0 == ~E_2~0); 1894253#L819-1 assume !(0 == ~E_3~0); 1894254#L824-1 assume !(0 == ~E_4~0); 1894896#L829-1 assume !(0 == ~E_5~0); 1896020#L834-1 assume !(0 == ~E_6~0); 1894497#L839-1 assume !(0 == ~E_7~0); 1894498#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1895278#L376 assume !(1 == ~m_pc~0); 1895252#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1895275#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1896120#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1894397#L955 assume !(0 != activate_threads_~tmp~1#1); 1894398#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1895096#L395 assume !(1 == ~t1_pc~0); 1895435#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1895790#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1894308#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1894309#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1895287#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1895288#L414 assume !(1 == ~t2_pc~0); 1894500#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1895889#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1894913#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1894914#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1895886#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1895105#L433 assume !(1 == ~t3_pc~0); 1894715#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1894716#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1894251#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1894252#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1894442#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1894443#L452 assume !(1 == ~t4_pc~0); 1894730#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1894731#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1894432#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1894433#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1894782#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1894783#L471 assume !(1 == ~t5_pc~0); 1895604#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1894752#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1894753#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1895797#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1896001#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1896002#L490 assume !(1 == ~t6_pc~0); 1895285#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1895286#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1894886#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1894887#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1895123#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1895055#L509 assume !(1 == ~t7_pc~0); 1895056#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1894685#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1894686#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1894794#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1894795#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1895904#L857 assume !(1 == ~M_E~0); 1894409#L857-2 assume !(1 == ~T1_E~0); 1894410#L862-1 assume !(1 == ~T2_E~0); 1894919#L867-1 assume !(1 == ~T3_E~0); 1894930#L872-1 assume !(1 == ~T4_E~0); 1895106#L877-1 assume !(1 == ~T5_E~0); 1895548#L882-1 assume !(1 == ~T6_E~0); 1895938#L887-1 assume !(1 == ~T7_E~0); 1895690#L892-1 assume !(1 == ~E_M~0); 1895691#L897-1 assume !(1 == ~E_1~0); 1894961#L902-1 assume !(1 == ~E_2~0); 1894962#L907-1 assume !(1 == ~E_3~0); 1895579#L912-1 assume !(1 == ~E_4~0); 1895560#L917-1 assume !(1 == ~E_5~0); 1895561#L922-1 assume !(1 == ~E_6~0); 1896027#L927-1 assume !(1 == ~E_7~0); 1895537#L932-1 assume { :end_inline_reset_delta_events } true; 1895538#L1178-2 assume !false; 1916609#L1179 [2024-11-09 16:08:30,160 INFO L747 eck$LassoCheckResult]: Loop: 1916609#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2048374#L744-1 assume !false; 2048373#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2048372#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2048071#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2048371#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2048369#L641 assume 0 != eval_~tmp~0#1; 2048367#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2048038#L649 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1; 2048329#L80 assume 0 == ~m_pc~0; 2048327#L105-1 assume !false; 2048325#L92 havoc master_#t~nondet4#1;~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2048323#L376-3 assume !(1 == ~m_pc~0); 2048319#L376-5 is_master_triggered_~__retres1~0#1 := 0; 2048317#L387-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2048315#is_master_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2048312#L955-3 assume !(0 != activate_threads_~tmp~1#1); 2048309#L955-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2048307#L395-3 assume !(1 == ~t1_pc~0); 2048305#L395-5 is_transmit1_triggered_~__retres1~1#1 := 0; 2048303#L406-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2048301#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2048297#L963-3 assume !(0 != activate_threads_~tmp___0~0#1); 2048295#L963-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2048290#L414-3 assume !(1 == ~t2_pc~0); 2048287#L414-5 is_transmit2_triggered_~__retres1~2#1 := 0; 2048285#L425-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2048283#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2048281#L971-3 assume !(0 != activate_threads_~tmp___1~0#1); 2048277#L971-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2048275#L433-3 assume !(1 == ~t3_pc~0); 2048273#L433-5 is_transmit3_triggered_~__retres1~3#1 := 0; 2048271#L444-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2048267#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2048265#L979-3 assume !(0 != activate_threads_~tmp___2~0#1); 2048263#L979-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2048261#L452-3 assume !(1 == ~t4_pc~0); 2048257#L452-5 is_transmit4_triggered_~__retres1~4#1 := 0; 2048255#L463-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2048254#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2048250#L987-3 assume !(0 != activate_threads_~tmp___3~0#1); 2048248#L987-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2048246#L471-3 assume !(1 == ~t5_pc~0); 2048245#L471-5 is_transmit5_triggered_~__retres1~5#1 := 0; 2048244#L482-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2048242#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2048241#L995-3 assume !(0 != activate_threads_~tmp___4~0#1); 2048240#L995-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2048237#L490-3 assume !(1 == ~t6_pc~0); 2048235#L490-5 is_transmit6_triggered_~__retres1~6#1 := 0; 2048233#L501-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2048232#is_transmit6_triggered_returnLabel#2 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2048229#L1003-3 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2048228#L1003-5 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2048227#L509-3 assume 1 == ~t7_pc~0; 2048226#L510-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2048225#L520-1 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2048223#is_transmit7_triggered_returnLabel#2 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2048218#L1011-3 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2048217#L1011-5 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true; 2048216#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 2048214#master_returnLabel#1 havoc master_#t~nondet4#1;assume { :end_inline_master } true; 2048036#L649-2 havoc eval_~tmp_ndt_1~0#1; 2048033#L646-1 assume !(0 == ~t1_st~0); 2048030#L660-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2032589#L677 assume 0 != eval_~tmp_ndt_3~0#1;~t2_st~0 := 1;assume { :begin_inline_transmit2 } true; 2048026#L160 assume 0 == ~t2_pc~0; 2072604#L171-1 assume !false; 2032597#L172 ~t2_pc~0 := 1;~t2_st~0 := 2; 2032593#transmit2_returnLabel#1 assume { :end_inline_transmit2 } true; 2032587#L677-2 havoc eval_~tmp_ndt_3~0#1; 2032585#L674-1 assume !(0 == ~t3_st~0); 2032586#L688-1 assume !(0 == ~t4_st~0); 2048524#L702-1 assume !(0 == ~t5_st~0); 2048520#L716-1 assume !(0 == ~t6_st~0); 2048517#L730-1 assume !(0 == ~t7_st~0); 2048518#L744-1 assume !false; 2064884#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2064883#L584 assume !(0 == ~m_st~0); 2064881#L588 assume !(0 == ~t1_st~0); 2064880#L592 assume !(0 == ~t2_st~0); 2064879#L596 assume !(0 == ~t3_st~0); 2064878#L600 assume !(0 == ~t4_st~0); 2064877#L604 assume !(0 == ~t5_st~0); 2064876#L608 assume !(0 == ~t6_st~0); 2064873#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 2064872#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2064871#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2064869#L641 assume !(0 != eval_~tmp~0#1); 2064867#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2064865#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2064864#L769-3 assume !(0 == ~M_E~0); 2064861#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2064859#L774-3 assume !(0 == ~T2_E~0); 2064857#L779-3 assume !(0 == ~T3_E~0); 2064855#L784-3 assume !(0 == ~T4_E~0); 2064852#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2064850#L794-3 assume !(0 == ~T6_E~0); 2064847#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2064845#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2064843#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2064841#L814-3 assume !(0 == ~E_2~0); 2064839#L819-3 assume !(0 == ~E_3~0); 2064837#L824-3 assume !(0 == ~E_4~0); 2064833#L829-3 assume !(0 == ~E_5~0); 2064829#L834-3 assume !(0 == ~E_6~0); 2064826#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2064824#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2064822#L376-27 assume !(1 == ~m_pc~0); 2064820#L376-29 is_master_triggered_~__retres1~0#1 := 0; 2071462#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2071271#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2027993#L955-27 assume !(0 != activate_threads_~tmp~1#1); 2027991#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2027990#L395-27 assume !(1 == ~t1_pc~0); 2027988#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2027986#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2027984#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2027982#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 2027980#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2027978#L414-27 assume 1 == ~t2_pc~0; 2027974#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2027972#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2027970#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2027967#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2027965#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2027963#L433-27 assume !(1 == ~t3_pc~0); 2027961#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2027959#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2027957#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2027955#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 2027953#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2027951#L452-27 assume !(1 == ~t4_pc~0); 2027948#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2027946#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2027944#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2027942#L987-27 assume !(0 != activate_threads_~tmp___3~0#1); 2027940#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2027938#L471-27 assume !(1 == ~t5_pc~0); 2027934#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2027932#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2027930#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2027928#L995-27 assume !(0 != activate_threads_~tmp___4~0#1); 2027925#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2027923#L490-27 assume !(1 == ~t6_pc~0); 2027921#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2027920#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2027918#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2027916#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 2027914#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2027913#L509-27 assume 1 == ~t7_pc~0; 2027911#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2027912#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2028001#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2027902#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2027900#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2027898#L857-3 assume !(1 == ~M_E~0); 2026006#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2027895#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2027892#L867-3 assume !(1 == ~T3_E~0); 2027890#L872-3 assume !(1 == ~T4_E~0); 2027888#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2027886#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2027884#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2027882#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2027880#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2027878#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2027876#L907-3 assume !(1 == ~E_3~0); 2027874#L912-3 assume !(1 == ~E_4~0); 2027872#L917-3 assume !(1 == ~E_5~0); 2027870#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1996248#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2027867#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2027864#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2027865#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2027854#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2027821#L1197 assume !(0 == start_simulation_~tmp~3#1); 2027822#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2048397#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2048174#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2048393#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 2048392#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2048388#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2048386#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2048384#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 2048383#L1178-2 assume !false; 1916609#L1179 [2024-11-09 16:08:30,161 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:30,165 INFO L85 PathProgramCache]: Analyzing trace with hash -1048388199, now seen corresponding path program 2 times [2024-11-09 16:08:30,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:30,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488188572] [2024-11-09 16:08:30,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:30,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:30,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:30,177 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:08:30,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:08:30,195 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:08:30,195 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:30,195 INFO L85 PathProgramCache]: Analyzing trace with hash 1968465104, now seen corresponding path program 1 times [2024-11-09 16:08:30,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:30,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618807376] [2024-11-09 16:08:30,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:30,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:30,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:30,221 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:30,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:30,221 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1618807376] [2024-11-09 16:08:30,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1618807376] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:30,221 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:30,221 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:30,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226919890] [2024-11-09 16:08:30,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:30,222 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:30,222 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:30,222 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:30,222 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:30,223 INFO L87 Difference]: Start difference. First operand 284221 states and 372696 transitions. cyclomatic complexity: 88523 Second operand has 3 states, 3 states have (on average 62.0) internal successors, (186), 3 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:32,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:32,120 INFO L93 Difference]: Finished difference Result 322391 states and 422678 transitions. [2024-11-09 16:08:32,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322391 states and 422678 transitions. [2024-11-09 16:08:33,242 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 218912 [2024-11-09 16:08:34,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322391 states to 322391 states and 422678 transitions. [2024-11-09 16:08:34,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 220334 [2024-11-09 16:08:34,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 220334 [2024-11-09 16:08:34,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322391 states and 422678 transitions. [2024-11-09 16:08:34,788 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-09 16:08:34,788 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322391 states and 422678 transitions. [2024-11-09 16:08:34,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322391 states and 422678 transitions.