./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/kundu2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3061b6dc Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/kundu2.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-assert-order-craig-3061b6d-m [2024-11-19 15:02:11,697 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-19 15:02:11,769 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-19 15:02:11,773 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-19 15:02:11,773 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-19 15:02:11,797 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-19 15:02:11,797 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-19 15:02:11,797 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-19 15:02:11,798 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-19 15:02:11,798 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-19 15:02:11,799 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-19 15:02:11,799 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-19 15:02:11,800 INFO L153 SettingsManager]: * Use SBE=true [2024-11-19 15:02:11,800 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-19 15:02:11,800 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-19 15:02:11,801 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-19 15:02:11,801 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-19 15:02:11,801 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-19 15:02:11,802 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-19 15:02:11,802 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-19 15:02:11,802 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-19 15:02:11,805 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-19 15:02:11,805 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-19 15:02:11,805 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-19 15:02:11,806 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-19 15:02:11,806 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-19 15:02:11,806 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-19 15:02:11,806 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-19 15:02:11,807 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-19 15:02:11,807 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-19 15:02:11,807 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-19 15:02:11,808 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-19 15:02:11,808 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-19 15:02:11,812 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-19 15:02:11,813 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-19 15:02:11,813 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-19 15:02:11,813 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-19 15:02:11,814 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-19 15:02:11,814 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-19 15:02:11,814 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf [2024-11-19 15:02:12,038 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-19 15:02:12,062 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-19 15:02:12,065 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-19 15:02:12,066 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-19 15:02:12,067 INFO L274 PluginConnector]: CDTParser initialized [2024-11-19 15:02:12,068 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/kundu2.cil.c [2024-11-19 15:02:13,562 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-19 15:02:13,762 INFO L384 CDTParser]: Found 1 translation units. [2024-11-19 15:02:13,762 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu2.cil.c [2024-11-19 15:02:13,773 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a94d8508a/1c402cdd2a2e4d78b2c87edfce65f09a/FLAGc22340612 [2024-11-19 15:02:13,786 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a94d8508a/1c402cdd2a2e4d78b2c87edfce65f09a [2024-11-19 15:02:13,790 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-19 15:02:13,791 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-19 15:02:13,792 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-19 15:02:13,793 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-19 15:02:13,797 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-19 15:02:13,797 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 03:02:13" (1/1) ... [2024-11-19 15:02:13,798 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3e24c328 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:13, skipping insertion in model container [2024-11-19 15:02:13,799 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 03:02:13" (1/1) ... [2024-11-19 15:02:13,831 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-19 15:02:14,050 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 15:02:14,062 INFO L200 MainTranslator]: Completed pre-run [2024-11-19 15:02:14,098 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 15:02:14,115 INFO L204 MainTranslator]: Completed translation [2024-11-19 15:02:14,116 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14 WrapperNode [2024-11-19 15:02:14,116 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-19 15:02:14,117 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-19 15:02:14,117 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-19 15:02:14,117 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-19 15:02:14,124 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,136 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,184 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 49, statements flattened = 535 [2024-11-19 15:02:14,185 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-19 15:02:14,186 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-19 15:02:14,186 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-19 15:02:14,186 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-19 15:02:14,195 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,196 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,199 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,239 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-19 15:02:14,240 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,240 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,250 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,262 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,264 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,266 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,297 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-19 15:02:14,298 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-19 15:02:14,299 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-19 15:02:14,299 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-19 15:02:14,299 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (1/1) ... [2024-11-19 15:02:14,310 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:02:14,322 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:02:14,339 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:02:14,347 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-19 15:02:14,402 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-19 15:02:14,402 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-19 15:02:14,402 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-19 15:02:14,402 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-19 15:02:14,504 INFO L238 CfgBuilder]: Building ICFG [2024-11-19 15:02:14,506 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-19 15:02:15,036 INFO L? ?]: Removed 101 outVars from TransFormulas that were not future-live. [2024-11-19 15:02:15,036 INFO L287 CfgBuilder]: Performing block encoding [2024-11-19 15:02:15,054 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-19 15:02:15,055 INFO L316 CfgBuilder]: Removed 5 assume(true) statements. [2024-11-19 15:02:15,055 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:02:15 BoogieIcfgContainer [2024-11-19 15:02:15,056 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-19 15:02:15,057 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-19 15:02:15,057 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-19 15:02:15,061 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-19 15:02:15,062 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:02:15,062 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 03:02:13" (1/3) ... [2024-11-19 15:02:15,064 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4c97c307 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 03:02:15, skipping insertion in model container [2024-11-19 15:02:15,064 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:02:15,064 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:14" (2/3) ... [2024-11-19 15:02:15,064 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4c97c307 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 03:02:15, skipping insertion in model container [2024-11-19 15:02:15,065 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:02:15,065 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:02:15" (3/3) ... [2024-11-19 15:02:15,066 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu2.cil.c [2024-11-19 15:02:15,125 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-19 15:02:15,125 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-19 15:02:15,126 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-19 15:02:15,126 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-19 15:02:15,126 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-19 15:02:15,126 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-19 15:02:15,126 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-19 15:02:15,126 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-19 15:02:15,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 194 states, 193 states have (on average 1.4922279792746114) internal successors, (288), 193 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:15,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2024-11-19 15:02:15,155 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:15,155 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:15,163 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:15,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:15,163 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-19 15:02:15,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 194 states, 193 states have (on average 1.4922279792746114) internal successors, (288), 193 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:15,172 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2024-11-19 15:02:15,173 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:15,173 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:15,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:15,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:15,185 INFO L745 eck$LassoCheckResult]: Stem: 130#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 137#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 189#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 176#L304true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 79#L304-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 15#L309-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 148#L314-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77#fire_delta_events_returnLabel#1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4#L117true assume !(1 == ~P_1_pc~0); 19#L117-2true is_P_1_triggered_~__retres1~0#1 := 0; 147#L128true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 43#is_P_1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 128#L477true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 166#L477-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 84#L185true assume 1 == ~P_2_pc~0; 53#L186true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 54#L196true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 93#is_P_2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 80#L485true assume !(0 != activate_threads_~tmp___0~1#1); 108#L485-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 123#L267true assume 1 == ~C_1_pc~0; 122#L268true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 23#L288true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 188#is_C_1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 116#L493true assume !(0 != activate_threads_~tmp___1~1#1); 149#L493-2true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 184#reset_delta_events_returnLabel#1true assume { :end_inline_reset_delta_events } true; 145#L547-2true [2024-11-19 15:02:15,186 INFO L747 eck$LassoCheckResult]: Loop: 145#L547-2true assume !false; 151#L548true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 73#L396true assume false; 70#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34#fire_delta_events_returnLabel#2true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 30#L117-6true assume !(1 == ~P_1_pc~0); 35#L117-8true is_P_1_triggered_~__retres1~0#1 := 0; 194#L128-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38#is_P_1_triggered_returnLabel#3true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21#L477-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 56#L477-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 36#L185-6true assume !(1 == ~P_2_pc~0); 51#L185-8true is_P_2_triggered_~__retres1~1#1 := 0; 187#L196-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 191#is_P_2_triggered_returnLabel#3true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 141#L485-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 98#L485-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 69#L267-6true assume 1 == ~C_1_pc~0; 179#L268-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 142#L288-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 99#is_C_1_triggered_returnLabel#3true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 144#L493-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 27#L493-8true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81#reset_delta_events_returnLabel#2true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 183#L327-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 90#L344-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 175#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 91#L566true assume !(0 == start_simulation_~tmp~3#1); 41#L566-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31#L327-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 161#L344-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 32#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 78#L521true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 138#L528true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 112#L579true assume !(0 != start_simulation_~tmp___0~2#1); 145#L547-2true [2024-11-19 15:02:15,194 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:15,194 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2024-11-19 15:02:15,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:15,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538079428] [2024-11-19 15:02:15,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:15,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:15,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:15,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:15,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:15,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538079428] [2024-11-19 15:02:15,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [538079428] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:15,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:15,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:15,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1967876888] [2024-11-19 15:02:15,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:15,449 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:15,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:15,450 INFO L85 PathProgramCache]: Analyzing trace with hash 2086830017, now seen corresponding path program 1 times [2024-11-19 15:02:15,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:15,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586961755] [2024-11-19 15:02:15,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:15,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:15,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:15,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:15,495 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:15,495 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [586961755] [2024-11-19 15:02:15,495 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [586961755] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:15,495 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:15,496 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:02:15,496 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2016315750] [2024-11-19 15:02:15,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:15,497 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:15,498 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:15,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:15,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:15,538 INFO L87 Difference]: Start difference. First operand has 194 states, 193 states have (on average 1.4922279792746114) internal successors, (288), 193 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:15,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:15,571 INFO L93 Difference]: Finished difference Result 186 states and 268 transitions. [2024-11-19 15:02:15,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 268 transitions. [2024-11-19 15:02:15,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2024-11-19 15:02:15,582 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 178 states and 260 transitions. [2024-11-19 15:02:15,584 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2024-11-19 15:02:15,584 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2024-11-19 15:02:15,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 260 transitions. [2024-11-19 15:02:15,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:15,586 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178 states and 260 transitions. [2024-11-19 15:02:15,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 260 transitions. [2024-11-19 15:02:15,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2024-11-19 15:02:15,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4606741573033708) internal successors, (260), 177 states have internal predecessors, (260), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:15,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 260 transitions. [2024-11-19 15:02:15,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 260 transitions. [2024-11-19 15:02:15,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:15,697 INFO L425 stractBuchiCegarLoop]: Abstraction has 178 states and 260 transitions. [2024-11-19 15:02:15,698 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-19 15:02:15,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 260 transitions. [2024-11-19 15:02:15,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2024-11-19 15:02:15,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:15,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:15,705 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:15,707 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:15,707 INFO L745 eck$LassoCheckResult]: Stem: 479#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 503#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 498#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 499#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 559#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 448#L309-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 449#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 529#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 398#L117 assume !(1 == ~P_1_pc~0); 399#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 461#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 520#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 476#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 477#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 553#L185 assume 1 == ~P_2_pc~0; 535#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 512#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 536#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 560#L485 assume !(0 != activate_threads_~tmp___0~1#1); 403#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 404#L267 assume 1 == ~C_1_pc~0; 457#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 458#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 475#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 438#L493 assume !(0 != activate_threads_~tmp___1~1#1); 439#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 530#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 422#L547-2 [2024-11-19 15:02:15,708 INFO L747 eck$LassoCheckResult]: Loop: 422#L547-2 assume !false; 523#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 532#L396 assume !false; 528#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 451#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 412#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 429#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 430#L361 assume !(0 != eval_~tmp___2~0#1); 549#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 556#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 502#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 488#L117-6 assume 1 == ~P_1_pc~0; 489#L118-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 504#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 507#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 462#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 463#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 505#L185-6 assume 1 == ~P_2_pc~0; 408#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 409#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 566#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 517#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 518#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 554#L267-6 assume 1 == ~C_1_pc~0; 555#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 391#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 519#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 521#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 482#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 483#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 558#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 472#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 561#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 562#L566 assume !(0 == start_simulation_~tmp~3#1); 513#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 491#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 485#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 493#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 494#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 509#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 510#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 421#L579 assume !(0 != start_simulation_~tmp___0~2#1); 422#L547-2 [2024-11-19 15:02:15,709 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:15,709 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2024-11-19 15:02:15,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:15,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450645987] [2024-11-19 15:02:15,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:15,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:15,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:15,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:15,773 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:15,774 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1450645987] [2024-11-19 15:02:15,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1450645987] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:15,774 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:15,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:15,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094412400] [2024-11-19 15:02:15,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:15,775 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:15,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:15,776 INFO L85 PathProgramCache]: Analyzing trace with hash 1120930777, now seen corresponding path program 1 times [2024-11-19 15:02:15,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:15,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431405576] [2024-11-19 15:02:15,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:15,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:15,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:15,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:15,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:15,903 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431405576] [2024-11-19 15:02:15,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431405576] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:15,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:15,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:15,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880183886] [2024-11-19 15:02:15,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:15,905 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:15,905 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:15,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:15,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:15,906 INFO L87 Difference]: Start difference. First operand 178 states and 260 transitions. cyclomatic complexity: 83 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:15,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:15,928 INFO L93 Difference]: Finished difference Result 178 states and 259 transitions. [2024-11-19 15:02:15,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178 states and 259 transitions. [2024-11-19 15:02:15,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2024-11-19 15:02:15,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178 states to 178 states and 259 transitions. [2024-11-19 15:02:15,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2024-11-19 15:02:15,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2024-11-19 15:02:15,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 259 transitions. [2024-11-19 15:02:15,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:15,935 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178 states and 259 transitions. [2024-11-19 15:02:15,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 259 transitions. [2024-11-19 15:02:15,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2024-11-19 15:02:15,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4550561797752808) internal successors, (259), 177 states have internal predecessors, (259), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:15,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 259 transitions. [2024-11-19 15:02:15,944 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 259 transitions. [2024-11-19 15:02:15,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:15,945 INFO L425 stractBuchiCegarLoop]: Abstraction has 178 states and 259 transitions. [2024-11-19 15:02:15,945 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-19 15:02:15,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 259 transitions. [2024-11-19 15:02:15,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2024-11-19 15:02:15,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:15,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:15,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:15,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:15,949 INFO L745 eck$LassoCheckResult]: Stem: 844#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 868#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 863#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 864#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 923#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 811#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 812#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 894#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 763#L117 assume !(1 == ~P_1_pc~0); 764#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 826#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 885#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 841#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 842#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 918#L185 assume 1 == ~P_2_pc~0; 899#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 877#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 900#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 924#L485 assume !(0 != activate_threads_~tmp___0~1#1); 766#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 767#L267 assume 1 == ~C_1_pc~0; 822#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 823#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 835#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 803#L493 assume !(0 != activate_threads_~tmp___1~1#1); 804#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 895#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 787#L547-2 [2024-11-19 15:02:15,949 INFO L747 eck$LassoCheckResult]: Loop: 787#L547-2 assume !false; 887#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 897#L396 assume !false; 892#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 815#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 777#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 794#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 795#L361 assume !(0 != eval_~tmp___2~0#1); 913#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 921#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 867#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 853#L117-6 assume 1 == ~P_1_pc~0; 854#L118-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 869#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 872#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 827#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 828#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 870#L185-6 assume 1 == ~P_2_pc~0; 773#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 774#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 931#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 882#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 883#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 919#L267-6 assume 1 == ~C_1_pc~0; 920#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 756#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 884#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 886#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 847#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 848#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 925#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 838#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 926#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 927#L566 assume !(0 == start_simulation_~tmp~3#1); 878#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 856#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 850#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 858#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 859#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 874#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 875#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 786#L579 assume !(0 != start_simulation_~tmp___0~2#1); 787#L547-2 [2024-11-19 15:02:15,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:15,950 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2024-11-19 15:02:15,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:15,950 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066921238] [2024-11-19 15:02:15,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:15,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:15,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:16,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:16,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:16,043 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066921238] [2024-11-19 15:02:16,043 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1066921238] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:16,043 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:16,043 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:16,043 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [870537845] [2024-11-19 15:02:16,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:16,044 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:16,044 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:16,044 INFO L85 PathProgramCache]: Analyzing trace with hash 1120930777, now seen corresponding path program 2 times [2024-11-19 15:02:16,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:16,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806923884] [2024-11-19 15:02:16,045 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:02:16,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:16,055 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:02:16,056 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:02:16,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:16,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:16,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [806923884] [2024-11-19 15:02:16,126 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [806923884] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:16,126 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:16,126 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:16,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [579305386] [2024-11-19 15:02:16,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:16,127 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:16,128 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:16,128 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:02:16,128 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:02:16,129 INFO L87 Difference]: Start difference. First operand 178 states and 259 transitions. cyclomatic complexity: 82 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:16,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:16,243 INFO L93 Difference]: Finished difference Result 190 states and 271 transitions. [2024-11-19 15:02:16,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 190 states and 271 transitions. [2024-11-19 15:02:16,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2024-11-19 15:02:16,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 190 states to 190 states and 271 transitions. [2024-11-19 15:02:16,248 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 190 [2024-11-19 15:02:16,249 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 190 [2024-11-19 15:02:16,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 190 states and 271 transitions. [2024-11-19 15:02:16,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:16,254 INFO L218 hiAutomatonCegarLoop]: Abstraction has 190 states and 271 transitions. [2024-11-19 15:02:16,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190 states and 271 transitions. [2024-11-19 15:02:16,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190 to 190. [2024-11-19 15:02:16,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 190 states, 190 states have (on average 1.4263157894736842) internal successors, (271), 189 states have internal predecessors, (271), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:16,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 271 transitions. [2024-11-19 15:02:16,261 INFO L240 hiAutomatonCegarLoop]: Abstraction has 190 states and 271 transitions. [2024-11-19 15:02:16,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:02:16,262 INFO L425 stractBuchiCegarLoop]: Abstraction has 190 states and 271 transitions. [2024-11-19 15:02:16,262 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-19 15:02:16,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 190 states and 271 transitions. [2024-11-19 15:02:16,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2024-11-19 15:02:16,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:16,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:16,265 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:16,265 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:16,265 INFO L745 eck$LassoCheckResult]: Stem: 1223#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1224#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1247#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1242#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1243#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1307#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1190#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1191#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1273#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1142#L117 assume !(1 == ~P_1_pc~0); 1143#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1205#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1264#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1220#L477 assume !(0 != activate_threads_~tmp~1#1); 1221#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1299#L185 assume 1 == ~P_2_pc~0; 1280#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1256#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1281#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1308#L485 assume !(0 != activate_threads_~tmp___0~1#1); 1147#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1148#L267 assume 1 == ~C_1_pc~0; 1201#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1202#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1219#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1182#L493 assume !(0 != activate_threads_~tmp___1~1#1); 1183#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1275#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1166#L547-2 [2024-11-19 15:02:16,266 INFO L747 eck$LassoCheckResult]: Loop: 1166#L547-2 assume !false; 1267#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1277#L396 assume !false; 1271#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1195#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1156#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1173#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1174#L361 assume !(0 != eval_~tmp___2~0#1); 1293#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1302#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1246#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1236#L117-6 assume 1 == ~P_1_pc~0; 1237#L118-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 1274#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1320#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1318#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 1207#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1248#L185-6 assume 1 == ~P_2_pc~0; 1152#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1153#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1314#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1261#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1262#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1300#L267-6 assume 1 == ~C_1_pc~0; 1301#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1135#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1263#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1265#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1225#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1226#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1306#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1216#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1309#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1310#L566 assume !(0 == start_simulation_~tmp~3#1); 1257#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1232#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1229#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1234#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1235#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1252#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1253#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1165#L579 assume !(0 != start_simulation_~tmp___0~2#1); 1166#L547-2 [2024-11-19 15:02:16,266 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:16,266 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2024-11-19 15:02:16,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:16,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801535352] [2024-11-19 15:02:16,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:16,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:16,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:16,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:16,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:16,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [801535352] [2024-11-19 15:02:16,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [801535352] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:16,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:16,313 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-19 15:02:16,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213267708] [2024-11-19 15:02:16,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:16,314 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:16,314 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:16,314 INFO L85 PathProgramCache]: Analyzing trace with hash 1120930777, now seen corresponding path program 3 times [2024-11-19 15:02:16,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:16,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1633526231] [2024-11-19 15:02:16,314 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 15:02:16,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:16,327 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 15:02:16,328 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:02:16,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:16,366 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:16,367 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1633526231] [2024-11-19 15:02:16,367 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1633526231] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:16,367 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:16,367 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:16,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440299631] [2024-11-19 15:02:16,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:16,369 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:16,370 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:16,370 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:02:16,370 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:02:16,370 INFO L87 Difference]: Start difference. First operand 190 states and 271 transitions. cyclomatic complexity: 82 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:16,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:16,482 INFO L93 Difference]: Finished difference Result 475 states and 665 transitions. [2024-11-19 15:02:16,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 475 states and 665 transitions. [2024-11-19 15:02:16,488 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 412 [2024-11-19 15:02:16,491 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 475 states to 475 states and 665 transitions. [2024-11-19 15:02:16,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 475 [2024-11-19 15:02:16,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 475 [2024-11-19 15:02:16,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 475 states and 665 transitions. [2024-11-19 15:02:16,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:16,496 INFO L218 hiAutomatonCegarLoop]: Abstraction has 475 states and 665 transitions. [2024-11-19 15:02:16,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 475 states and 665 transitions. [2024-11-19 15:02:16,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 475 to 433. [2024-11-19 15:02:16,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 433 states, 433 states have (on average 1.4087759815242493) internal successors, (610), 432 states have internal predecessors, (610), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:16,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 610 transitions. [2024-11-19 15:02:16,520 INFO L240 hiAutomatonCegarLoop]: Abstraction has 433 states and 610 transitions. [2024-11-19 15:02:16,520 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:02:16,522 INFO L425 stractBuchiCegarLoop]: Abstraction has 433 states and 610 transitions. [2024-11-19 15:02:16,522 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-19 15:02:16,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 433 states and 610 transitions. [2024-11-19 15:02:16,525 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 396 [2024-11-19 15:02:16,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:16,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:16,529 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:16,530 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:16,530 INFO L745 eck$LassoCheckResult]: Stem: 1901#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1924#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1919#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1920#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1991#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1867#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1868#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1954#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1818#L117 assume !(1 == ~P_1_pc~0); 1819#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1882#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1942#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1897#L477 assume !(0 != activate_threads_~tmp~1#1); 1898#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1982#L185 assume !(1 == ~P_2_pc~0); 1933#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 1934#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1963#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1992#L485 assume !(0 != activate_threads_~tmp___0~1#1); 1820#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1821#L267 assume 1 == ~C_1_pc~0; 1878#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1879#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1891#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1856#L493 assume !(0 != activate_threads_~tmp___1~1#1); 1857#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1958#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1841#L547-2 [2024-11-19 15:02:16,530 INFO L747 eck$LassoCheckResult]: Loop: 1841#L547-2 assume !false; 1944#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1961#L396 assume !false; 1951#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1871#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1831#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1847#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1848#L361 assume !(0 != eval_~tmp___2~0#1); 1976#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1985#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1923#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1910#L117-6 assume !(1 == ~P_1_pc~0); 1911#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 1925#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1929#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1883#L477-6 assume !(0 != activate_threads_~tmp~1#1); 1884#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1926#L185-6 assume !(1 == ~P_2_pc~0); 1927#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 1960#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2000#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1939#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1940#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1983#L267-6 assume 1 == ~C_1_pc~0; 1984#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1813#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1941#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1943#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1904#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1905#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1993#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1894#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1994#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1995#L566 assume !(0 == start_simulation_~tmp~3#1); 1935#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1912#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1907#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1914#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1915#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1931#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1932#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1840#L579 assume !(0 != start_simulation_~tmp___0~2#1); 1841#L547-2 [2024-11-19 15:02:16,532 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:16,532 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2024-11-19 15:02:16,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:16,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985025866] [2024-11-19 15:02:16,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:16,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:16,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:16,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:16,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:16,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [985025866] [2024-11-19 15:02:16,590 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [985025866] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:16,590 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:16,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-19 15:02:16,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552040047] [2024-11-19 15:02:16,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:16,591 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:16,591 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:16,592 INFO L85 PathProgramCache]: Analyzing trace with hash -784916195, now seen corresponding path program 1 times [2024-11-19 15:02:16,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:16,592 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020323869] [2024-11-19 15:02:16,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:16,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:16,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:16,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:16,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:16,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020323869] [2024-11-19 15:02:16,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2020323869] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:16,640 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:16,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:16,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1743831323] [2024-11-19 15:02:16,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:16,641 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:16,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:16,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:02:16,642 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:02:16,642 INFO L87 Difference]: Start difference. First operand 433 states and 610 transitions. cyclomatic complexity: 179 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:16,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:16,765 INFO L93 Difference]: Finished difference Result 1179 states and 1624 transitions. [2024-11-19 15:02:16,765 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1179 states and 1624 transitions. [2024-11-19 15:02:16,772 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1099 [2024-11-19 15:02:16,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1179 states to 1179 states and 1624 transitions. [2024-11-19 15:02:16,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1179 [2024-11-19 15:02:16,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1179 [2024-11-19 15:02:16,809 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1179 states and 1624 transitions. [2024-11-19 15:02:16,811 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:16,811 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1179 states and 1624 transitions. [2024-11-19 15:02:16,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1179 states and 1624 transitions. [2024-11-19 15:02:16,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1179 to 1120. [2024-11-19 15:02:16,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1120 states, 1120 states have (on average 1.3857142857142857) internal successors, (1552), 1119 states have internal predecessors, (1552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:16,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1120 states to 1120 states and 1552 transitions. [2024-11-19 15:02:16,833 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2024-11-19 15:02:16,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:02:16,834 INFO L425 stractBuchiCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2024-11-19 15:02:16,834 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-19 15:02:16,834 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1120 states and 1552 transitions. [2024-11-19 15:02:16,840 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1078 [2024-11-19 15:02:16,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:16,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:16,842 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:16,842 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:16,842 INFO L745 eck$LassoCheckResult]: Stem: 3527#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3528#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3551#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3545#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3546#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3625#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3494#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3495#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3580#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3443#L117 assume !(1 == ~P_1_pc~0); 3444#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 3507#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3569#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3523#L477 assume !(0 != activate_threads_~tmp~1#1); 3524#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3615#L185 assume !(1 == ~P_2_pc~0); 3560#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 3561#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3589#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3626#L485 assume !(0 != activate_threads_~tmp___0~1#1); 3445#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3446#L267 assume !(1 == ~C_1_pc~0); 3508#L267-2 assume 2 == ~C_1_pc~0; 3619#L278 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3517#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3518#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3482#L493 assume !(0 != activate_threads_~tmp___1~1#1); 3483#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3584#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 3644#L547-2 [2024-11-19 15:02:16,842 INFO L747 eck$LassoCheckResult]: Loop: 3644#L547-2 assume !false; 4406#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 4402#L396 assume !false; 4400#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4398#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4396#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4392#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4387#L361 assume !(0 != eval_~tmp___2~0#1); 4388#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4498#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4496#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4494#L117-6 assume !(1 == ~P_1_pc~0); 4492#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 4486#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 4483#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4480#L477-6 assume !(0 != activate_threads_~tmp~1#1); 4478#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 4475#L185-6 assume !(1 == ~P_2_pc~0); 4473#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 4469#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 4466#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4463#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 4460#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 4457#L267-6 assume !(1 == ~C_1_pc~0); 4455#L267-8 assume !(2 == ~C_1_pc~0); 4452#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 4446#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 4444#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4442#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 4440#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4439#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4436#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4430#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4428#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4425#L566 assume !(0 == start_simulation_~tmp~3#1); 4422#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4418#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4416#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4415#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4414#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4412#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4410#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4408#L579 assume !(0 != start_simulation_~tmp___0~2#1); 3644#L547-2 [2024-11-19 15:02:16,843 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:16,843 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2024-11-19 15:02:16,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:16,844 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220016456] [2024-11-19 15:02:16,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:16,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:16,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:16,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:16,890 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:16,890 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220016456] [2024-11-19 15:02:16,891 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1220016456] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:16,891 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:16,891 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:16,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1134577590] [2024-11-19 15:02:16,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:16,891 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:16,891 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:16,892 INFO L85 PathProgramCache]: Analyzing trace with hash -1417336067, now seen corresponding path program 1 times [2024-11-19 15:02:16,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:16,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217000957] [2024-11-19 15:02:16,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:16,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:16,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:16,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:16,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:16,955 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217000957] [2024-11-19 15:02:16,956 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217000957] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:16,956 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:16,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:16,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255309988] [2024-11-19 15:02:16,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:16,957 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:16,957 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:16,957 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:16,957 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:16,958 INFO L87 Difference]: Start difference. First operand 1120 states and 1552 transitions. cyclomatic complexity: 436 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:17,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:17,010 INFO L93 Difference]: Finished difference Result 1488 states and 2031 transitions. [2024-11-19 15:02:17,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2031 transitions. [2024-11-19 15:02:17,019 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1441 [2024-11-19 15:02:17,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2031 transitions. [2024-11-19 15:02:17,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-19 15:02:17,029 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-19 15:02:17,030 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2031 transitions. [2024-11-19 15:02:17,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:17,032 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2031 transitions. [2024-11-19 15:02:17,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2031 transitions. [2024-11-19 15:02:17,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1464. [2024-11-19 15:02:17,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.3668032786885247) internal successors, (2001), 1463 states have internal predecessors, (2001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:17,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2001 transitions. [2024-11-19 15:02:17,057 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2024-11-19 15:02:17,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:17,059 INFO L425 stractBuchiCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2024-11-19 15:02:17,059 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-19 15:02:17,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2001 transitions. [2024-11-19 15:02:17,066 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1417 [2024-11-19 15:02:17,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:17,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:17,067 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:17,067 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:17,067 INFO L745 eck$LassoCheckResult]: Stem: 6140#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6168#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6162#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6163#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6246#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6109#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6110#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6201#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6060#L117 assume !(1 == ~P_1_pc~0); 6061#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 6121#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6189#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6137#L477 assume !(0 != activate_threads_~tmp~1#1); 6138#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6239#L185 assume !(1 == ~P_2_pc~0); 6179#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 6180#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6210#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6247#L485 assume !(0 != activate_threads_~tmp___0~1#1); 6062#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6063#L267 assume !(1 == ~C_1_pc~0); 6122#L267-2 assume !(2 == ~C_1_pc~0); 6209#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 6131#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6132#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6098#L493 assume !(0 != activate_threads_~tmp___1~1#1); 6099#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6205#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 6265#L547-2 [2024-11-19 15:02:17,068 INFO L747 eck$LassoCheckResult]: Loop: 6265#L547-2 assume !false; 7352#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 7306#L396 assume !false; 7348#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7344#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7341#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7339#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7336#L361 assume !(0 != eval_~tmp___2~0#1); 7337#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7429#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7428#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 7427#L117-6 assume !(1 == ~P_1_pc~0); 7426#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 7425#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 7424#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7422#L477-6 assume !(0 != activate_threads_~tmp~1#1); 7421#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 7420#L185-6 assume !(1 == ~P_2_pc~0); 7419#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 7417#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 7415#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7413#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 7411#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 7409#L267-6 assume !(1 == ~C_1_pc~0); 7407#L267-8 assume !(2 == ~C_1_pc~0); 7405#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 7403#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 7401#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7399#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 7397#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7395#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7391#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7388#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7386#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7374#L566 assume !(0 == start_simulation_~tmp~3#1); 7371#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7367#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7365#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7363#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 7361#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7359#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7357#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 7355#L579 assume !(0 != start_simulation_~tmp___0~2#1); 6265#L547-2 [2024-11-19 15:02:17,070 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:17,070 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2024-11-19 15:02:17,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:17,070 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685759685] [2024-11-19 15:02:17,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:17,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:17,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:17,079 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:17,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:17,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:17,111 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:17,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1417336067, now seen corresponding path program 2 times [2024-11-19 15:02:17,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:17,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369690127] [2024-11-19 15:02:17,112 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:02:17,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:17,121 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:02:17,122 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:02:17,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:17,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:17,159 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369690127] [2024-11-19 15:02:17,159 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [369690127] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:17,159 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:17,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:17,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1289947580] [2024-11-19 15:02:17,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:17,159 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:17,160 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:17,160 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:02:17,160 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:02:17,160 INFO L87 Difference]: Start difference. First operand 1464 states and 2001 transitions. cyclomatic complexity: 541 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:17,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:17,213 INFO L93 Difference]: Finished difference Result 1548 states and 2085 transitions. [2024-11-19 15:02:17,213 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1548 states and 2085 transitions. [2024-11-19 15:02:17,223 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1501 [2024-11-19 15:02:17,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1548 states to 1548 states and 2085 transitions. [2024-11-19 15:02:17,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1548 [2024-11-19 15:02:17,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1548 [2024-11-19 15:02:17,233 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1548 states and 2085 transitions. [2024-11-19 15:02:17,235 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:17,235 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1548 states and 2085 transitions. [2024-11-19 15:02:17,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1548 states and 2085 transitions. [2024-11-19 15:02:17,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1548 to 1500. [2024-11-19 15:02:17,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1500 states, 1500 states have (on average 1.358) internal successors, (2037), 1499 states have internal predecessors, (2037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:17,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 2037 transitions. [2024-11-19 15:02:17,262 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2024-11-19 15:02:17,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:02:17,264 INFO L425 stractBuchiCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2024-11-19 15:02:17,264 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-19 15:02:17,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1500 states and 2037 transitions. [2024-11-19 15:02:17,270 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2024-11-19 15:02:17,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:17,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:17,271 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:17,271 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:17,272 INFO L745 eck$LassoCheckResult]: Stem: 9163#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 9164#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 9191#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9184#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9185#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 9274#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 9131#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 9132#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9228#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 9080#L117 assume !(1 == ~P_1_pc~0); 9081#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 9141#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 9212#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9159#L477 assume !(0 != activate_threads_~tmp~1#1); 9160#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 9262#L185 assume !(1 == ~P_2_pc~0); 9201#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 9202#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 9235#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9275#L485 assume !(0 != activate_threads_~tmp___0~1#1); 9085#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 9086#L267 assume !(1 == ~C_1_pc~0); 9145#L267-2 assume !(2 == ~C_1_pc~0); 9233#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 9157#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 9158#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9118#L493 assume !(0 != activate_threads_~tmp___1~1#1); 9119#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9229#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 9293#L547-2 [2024-11-19 15:02:17,272 INFO L747 eck$LassoCheckResult]: Loop: 9293#L547-2 assume !false; 10400#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 10394#L396 assume !false; 9224#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9134#L327 assume !(0 == ~P_1_st~0); 9093#L331 assume !(0 == ~P_2_st~0); 9095#L335 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 9142#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9109#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9110#L361 assume !(0 != eval_~tmp___2~0#1); 10550#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10572#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10571#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10570#L117-6 assume !(1 == ~P_1_pc~0); 10569#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 10568#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10567#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10566#L477-6 assume !(0 != activate_threads_~tmp~1#1); 10565#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10564#L185-6 assume !(1 == ~P_2_pc~0); 10563#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 10562#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10561#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9208#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 9209#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 9263#L267-6 assume !(1 == ~C_1_pc~0); 9264#L267-8 assume !(2 == ~C_1_pc~0); 10560#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 10559#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10558#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10557#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10556#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9272#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9273#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9154#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 9278#L566 assume !(0 == start_simulation_~tmp~3#1); 9203#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9179#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9169#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9175#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 9176#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10416#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10415#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10414#L579 assume !(0 != start_simulation_~tmp___0~2#1); 9293#L547-2 [2024-11-19 15:02:17,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:17,273 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2024-11-19 15:02:17,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:17,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085272617] [2024-11-19 15:02:17,273 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:02:17,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:17,283 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:02:17,284 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:02:17,284 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:17,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:17,292 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:17,292 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:17,292 INFO L85 PathProgramCache]: Analyzing trace with hash -657003932, now seen corresponding path program 1 times [2024-11-19 15:02:17,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:17,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1886796534] [2024-11-19 15:02:17,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:17,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:17,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:17,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:17,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:17,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1886796534] [2024-11-19 15:02:17,331 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1886796534] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:17,331 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:17,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:17,332 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446046768] [2024-11-19 15:02:17,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:17,332 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:17,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:17,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:17,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:17,333 INFO L87 Difference]: Start difference. First operand 1500 states and 2037 transitions. cyclomatic complexity: 541 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:17,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:17,378 INFO L93 Difference]: Finished difference Result 2325 states and 3118 transitions. [2024-11-19 15:02:17,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2325 states and 3118 transitions. [2024-11-19 15:02:17,394 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2024-11-19 15:02:17,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2325 states to 2325 states and 3118 transitions. [2024-11-19 15:02:17,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2325 [2024-11-19 15:02:17,408 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2325 [2024-11-19 15:02:17,408 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2325 states and 3118 transitions. [2024-11-19 15:02:17,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:17,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2024-11-19 15:02:17,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2325 states and 3118 transitions. [2024-11-19 15:02:17,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2325 to 2325. [2024-11-19 15:02:17,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2325 states, 2325 states have (on average 1.3410752688172043) internal successors, (3118), 2324 states have internal predecessors, (3118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:17,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2325 states to 2325 states and 3118 transitions. [2024-11-19 15:02:17,481 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2024-11-19 15:02:17,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:17,483 INFO L425 stractBuchiCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2024-11-19 15:02:17,483 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-19 15:02:17,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2325 states and 3118 transitions. [2024-11-19 15:02:17,496 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2024-11-19 15:02:17,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:17,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:17,498 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:17,499 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:17,499 INFO L745 eck$LassoCheckResult]: Stem: 12993#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 12994#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 13021#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13015#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13016#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 13103#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 12961#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 12962#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13055#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 12911#L117 assume !(1 == ~P_1_pc~0); 12912#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 12972#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 13042#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12989#L477 assume !(0 != activate_threads_~tmp~1#1); 12990#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 13094#L185 assume !(1 == ~P_2_pc~0); 13031#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 13032#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 13064#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13104#L485 assume !(0 != activate_threads_~tmp___0~1#1); 12913#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 12914#L267 assume !(1 == ~C_1_pc~0); 12974#L267-2 assume !(2 == ~C_1_pc~0); 13063#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 12987#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 12988#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12949#L493 assume !(0 != activate_threads_~tmp___1~1#1); 12950#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13059#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 13120#L547-2 assume !false; 14397#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 14037#L396 [2024-11-19 15:02:17,499 INFO L747 eck$LassoCheckResult]: Loop: 14037#L396 assume !false; 14389#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14390#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14383#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14384#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14376#L361 assume 0 != eval_~tmp___2~0#1; 14377#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 14367#L370 assume !(0 != eval_~tmp~0#1); 14369#L366 assume !(0 == ~P_2_st~0); 14040#L381 assume !(0 == ~C_1_st~0); 14037#L396 [2024-11-19 15:02:17,500 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:17,500 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 1 times [2024-11-19 15:02:17,503 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:17,503 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558848173] [2024-11-19 15:02:17,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:17,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:17,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:17,511 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:17,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:17,522 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:17,525 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:17,525 INFO L85 PathProgramCache]: Analyzing trace with hash -658298241, now seen corresponding path program 1 times [2024-11-19 15:02:17,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:17,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611666848] [2024-11-19 15:02:17,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:17,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:17,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:17,531 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:17,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:17,537 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:17,539 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:17,539 INFO L85 PathProgramCache]: Analyzing trace with hash -1216568596, now seen corresponding path program 1 times [2024-11-19 15:02:17,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:17,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1555734011] [2024-11-19 15:02:17,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:17,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:17,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:17,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:17,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:17,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1555734011] [2024-11-19 15:02:17,575 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1555734011] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:17,575 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:17,576 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:17,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193510127] [2024-11-19 15:02:17,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:17,640 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:17,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:17,640 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:17,641 INFO L87 Difference]: Start difference. First operand 2325 states and 3118 transitions. cyclomatic complexity: 800 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:17,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:17,693 INFO L93 Difference]: Finished difference Result 3877 states and 5120 transitions. [2024-11-19 15:02:17,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3877 states and 5120 transitions. [2024-11-19 15:02:17,716 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3725 [2024-11-19 15:02:17,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3877 states to 3877 states and 5120 transitions. [2024-11-19 15:02:17,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3877 [2024-11-19 15:02:17,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3877 [2024-11-19 15:02:17,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3877 states and 5120 transitions. [2024-11-19 15:02:17,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:17,745 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3877 states and 5120 transitions. [2024-11-19 15:02:17,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3877 states and 5120 transitions. [2024-11-19 15:02:17,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3877 to 3793. [2024-11-19 15:02:17,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3793 states, 3793 states have (on average 1.3229633535460057) internal successors, (5018), 3792 states have internal predecessors, (5018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:17,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3793 states to 3793 states and 5018 transitions. [2024-11-19 15:02:17,807 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3793 states and 5018 transitions. [2024-11-19 15:02:17,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:17,808 INFO L425 stractBuchiCegarLoop]: Abstraction has 3793 states and 5018 transitions. [2024-11-19 15:02:17,808 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-19 15:02:17,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3793 states and 5018 transitions. [2024-11-19 15:02:17,821 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2024-11-19 15:02:17,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:17,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:17,822 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:17,822 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:17,823 INFO L745 eck$LassoCheckResult]: Stem: 19206#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 19207#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 19236#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19229#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19230#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 19330#L304-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 19172#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 19173#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19327#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 19328#L117 assume !(1 == ~P_1_pc~0); 19181#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 19182#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 19257#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 19258#L477 assume !(0 != activate_threads_~tmp~1#1); 19315#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 19316#L185 assume !(1 == ~P_2_pc~0); 19245#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 19246#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 19357#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19358#L485 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 19333#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 19188#L267 assume !(1 == ~C_1_pc~0); 19189#L267-2 assume !(2 == ~C_1_pc~0); 19285#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 19286#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 19361#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19362#L493 assume !(0 != activate_threads_~tmp___1~1#1); 19280#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19281#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 21257#L547-2 assume !false; 21233#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 21234#L396 [2024-11-19 15:02:17,823 INFO L747 eck$LassoCheckResult]: Loop: 21234#L396 assume !false; 22119#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22118#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22117#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22116#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22115#L361 assume 0 != eval_~tmp___2~0#1; 22114#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 22113#L370 assume !(0 != eval_~tmp~0#1); 22112#L366 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 22110#L385 assume !(0 != eval_~tmp___0~0#1); 22111#L381 assume !(0 == ~C_1_st~0); 21234#L396 [2024-11-19 15:02:17,823 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:17,823 INFO L85 PathProgramCache]: Analyzing trace with hash -131921874, now seen corresponding path program 1 times [2024-11-19 15:02:17,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:17,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143576867] [2024-11-19 15:02:17,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:17,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:17,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:17,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:17,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:17,844 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1143576867] [2024-11-19 15:02:17,844 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1143576867] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:17,844 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:17,844 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:17,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1697591990] [2024-11-19 15:02:17,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:17,845 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:17,845 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:17,845 INFO L85 PathProgramCache]: Analyzing trace with hash 1067448397, now seen corresponding path program 1 times [2024-11-19 15:02:17,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:17,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [521477273] [2024-11-19 15:02:17,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:17,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:17,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:17,849 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:17,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:17,852 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:17,899 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:17,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:17,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:17,900 INFO L87 Difference]: Start difference. First operand 3793 states and 5018 transitions. cyclomatic complexity: 1232 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:17,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:17,920 INFO L93 Difference]: Finished difference Result 3768 states and 4990 transitions. [2024-11-19 15:02:17,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3768 states and 4990 transitions. [2024-11-19 15:02:17,937 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2024-11-19 15:02:17,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3768 states to 3768 states and 4990 transitions. [2024-11-19 15:02:17,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3768 [2024-11-19 15:02:17,956 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3768 [2024-11-19 15:02:17,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3768 states and 4990 transitions. [2024-11-19 15:02:17,961 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:17,961 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2024-11-19 15:02:17,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3768 states and 4990 transitions. [2024-11-19 15:02:18,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3768 to 3768. [2024-11-19 15:02:18,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3768 states, 3768 states have (on average 1.3243099787685775) internal successors, (4990), 3767 states have internal predecessors, (4990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:18,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3768 states to 3768 states and 4990 transitions. [2024-11-19 15:02:18,059 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2024-11-19 15:02:18,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:18,063 INFO L425 stractBuchiCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2024-11-19 15:02:18,063 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-19 15:02:18,063 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3768 states and 4990 transitions. [2024-11-19 15:02:18,081 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2024-11-19 15:02:18,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:18,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:18,082 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:18,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:18,082 INFO L745 eck$LassoCheckResult]: Stem: 26770#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 26771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 26800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26793#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26794#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 26886#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 26738#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 26739#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26835#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 26688#L117 assume !(1 == ~P_1_pc~0); 26689#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 26748#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 26820#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26766#L477 assume !(0 != activate_threads_~tmp~1#1); 26767#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 26875#L185 assume !(1 == ~P_2_pc~0); 26809#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 26810#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 26845#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26887#L485 assume !(0 != activate_threads_~tmp___0~1#1); 26692#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 26693#L267 assume !(1 == ~C_1_pc~0); 26754#L267-2 assume !(2 == ~C_1_pc~0); 26843#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 26764#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 26765#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26724#L493 assume !(0 != activate_threads_~tmp___1~1#1); 26725#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26839#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 26906#L547-2 assume !false; 29767#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 29116#L396 [2024-11-19 15:02:18,082 INFO L747 eck$LassoCheckResult]: Loop: 29116#L396 assume !false; 29114#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 29108#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 29100#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 29099#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29096#L361 assume 0 != eval_~tmp___2~0#1; 29086#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 29074#L370 assume !(0 != eval_~tmp~0#1); 29076#L366 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 28479#L385 assume !(0 != eval_~tmp___0~0#1); 29106#L381 assume !(0 == ~C_1_st~0); 29116#L396 [2024-11-19 15:02:18,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:18,083 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 2 times [2024-11-19 15:02:18,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:18,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995775220] [2024-11-19 15:02:18,084 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:02:18,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:18,094 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:02:18,095 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:02:18,095 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:18,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:18,106 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:18,106 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:18,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1067448397, now seen corresponding path program 2 times [2024-11-19 15:02:18,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:18,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402856675] [2024-11-19 15:02:18,107 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:02:18,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:18,111 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:02:18,111 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:02:18,111 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:18,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:18,115 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:18,115 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:18,115 INFO L85 PathProgramCache]: Analyzing trace with hash 940936576, now seen corresponding path program 1 times [2024-11-19 15:02:18,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:18,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122218586] [2024-11-19 15:02:18,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:18,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:18,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:18,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:18,145 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:18,145 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122218586] [2024-11-19 15:02:18,145 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [122218586] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:18,145 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:18,145 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:02:18,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1865112507] [2024-11-19 15:02:18,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:18,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:18,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:18,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:18,199 INFO L87 Difference]: Start difference. First operand 3768 states and 4990 transitions. cyclomatic complexity: 1229 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:18,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:18,266 INFO L93 Difference]: Finished difference Result 6578 states and 8632 transitions. [2024-11-19 15:02:18,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6578 states and 8632 transitions. [2024-11-19 15:02:18,303 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6355 [2024-11-19 15:02:18,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6578 states to 6578 states and 8632 transitions. [2024-11-19 15:02:18,340 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6578 [2024-11-19 15:02:18,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6578 [2024-11-19 15:02:18,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6578 states and 8632 transitions. [2024-11-19 15:02:18,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:18,356 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2024-11-19 15:02:18,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6578 states and 8632 transitions. [2024-11-19 15:02:18,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6578 to 6578. [2024-11-19 15:02:18,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6578 states, 6578 states have (on average 1.3122529644268774) internal successors, (8632), 6577 states have internal predecessors, (8632), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:18,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6578 states to 6578 states and 8632 transitions. [2024-11-19 15:02:18,477 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2024-11-19 15:02:18,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:18,477 INFO L425 stractBuchiCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2024-11-19 15:02:18,477 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-19 15:02:18,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6578 states and 8632 transitions. [2024-11-19 15:02:18,498 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6355 [2024-11-19 15:02:18,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:18,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:18,498 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:18,498 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:18,499 INFO L745 eck$LassoCheckResult]: Stem: 37122#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 37123#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 37149#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37143#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37144#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 37235#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 37092#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 37093#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37185#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 37042#L117 assume !(1 == ~P_1_pc~0); 37043#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 37103#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 37170#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 37118#L477 assume !(0 != activate_threads_~tmp~1#1); 37119#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 37225#L185 assume !(1 == ~P_2_pc~0); 37159#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 37160#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 37195#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 37236#L485 assume !(0 != activate_threads_~tmp___0~1#1); 37046#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 37047#L267 assume !(1 == ~C_1_pc~0); 37106#L267-2 assume !(2 == ~C_1_pc~0); 37193#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 37116#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 37117#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37078#L493 assume !(0 != activate_threads_~tmp___1~1#1); 37079#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37189#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 37250#L547-2 assume !false; 38091#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 38071#L396 [2024-11-19 15:02:18,499 INFO L747 eck$LassoCheckResult]: Loop: 38071#L396 assume !false; 41221#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 41219#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 41217#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 41215#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 41214#L361 assume 0 != eval_~tmp___2~0#1; 41212#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 41210#L370 assume !(0 != eval_~tmp~0#1); 40958#L366 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 40956#L385 assume !(0 != eval_~tmp___0~0#1); 38073#L381 assume 0 == ~C_1_st~0;havoc eval_#t~nondet8#1;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 38057#L400 assume !(0 != eval_~tmp___1~0#1); 38071#L396 [2024-11-19 15:02:18,499 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:18,499 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 3 times [2024-11-19 15:02:18,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:18,499 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581565406] [2024-11-19 15:02:18,499 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 15:02:18,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:18,505 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 15:02:18,506 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:02:18,506 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:18,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:18,512 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:18,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:18,513 INFO L85 PathProgramCache]: Analyzing trace with hash -1268840153, now seen corresponding path program 1 times [2024-11-19 15:02:18,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:18,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351432963] [2024-11-19 15:02:18,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:18,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:18,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:18,516 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:18,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:18,518 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:18,518 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:18,518 INFO L85 PathProgramCache]: Analyzing trace with hash -895739308, now seen corresponding path program 1 times [2024-11-19 15:02:18,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:18,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749817047] [2024-11-19 15:02:18,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:18,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:18,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:18,525 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:18,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:18,535 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:19,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:19,284 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:19,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:19,404 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.11 03:02:19 BoogieIcfgContainer [2024-11-19 15:02:19,404 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-19 15:02:19,405 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-19 15:02:19,405 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-19 15:02:19,405 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-19 15:02:19,405 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:02:15" (3/4) ... [2024-11-19 15:02:19,411 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-19 15:02:19,482 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-19 15:02:19,484 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-19 15:02:19,485 INFO L158 Benchmark]: Toolchain (without parser) took 5694.09ms. Allocated memory was 155.2MB in the beginning and 299.9MB in the end (delta: 144.7MB). Free memory was 81.7MB in the beginning and 176.5MB in the end (delta: -94.8MB). Peak memory consumption was 51.5MB. Max. memory is 16.1GB. [2024-11-19 15:02:19,485 INFO L158 Benchmark]: CDTParser took 0.27ms. Allocated memory is still 155.2MB. Free memory is still 104.6MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-19 15:02:19,485 INFO L158 Benchmark]: CACSL2BoogieTranslator took 323.58ms. Allocated memory is still 155.2MB. Free memory was 81.3MB in the beginning and 65.3MB in the end (delta: 16.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-19 15:02:19,486 INFO L158 Benchmark]: Boogie Procedure Inliner took 68.38ms. Allocated memory is still 155.2MB. Free memory was 65.3MB in the beginning and 62.4MB in the end (delta: 2.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-19 15:02:19,486 INFO L158 Benchmark]: Boogie Preprocessor took 111.98ms. Allocated memory was 155.2MB in the beginning and 207.6MB in the end (delta: 52.4MB). Free memory was 62.4MB in the beginning and 177.2MB in the end (delta: -114.8MB). Peak memory consumption was 10.9MB. Max. memory is 16.1GB. [2024-11-19 15:02:19,486 INFO L158 Benchmark]: RCFGBuilder took 757.26ms. Allocated memory is still 207.6MB. Free memory was 177.2MB in the beginning and 145.8MB in the end (delta: 31.5MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. [2024-11-19 15:02:19,487 INFO L158 Benchmark]: BuchiAutomizer took 4347.55ms. Allocated memory was 207.6MB in the beginning and 299.9MB in the end (delta: 92.3MB). Free memory was 144.7MB in the beginning and 181.7MB in the end (delta: -37.0MB). Peak memory consumption was 55.3MB. Max. memory is 16.1GB. [2024-11-19 15:02:19,487 INFO L158 Benchmark]: Witness Printer took 79.86ms. Allocated memory is still 299.9MB. Free memory was 181.7MB in the beginning and 176.5MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-19 15:02:19,488 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27ms. Allocated memory is still 155.2MB. Free memory is still 104.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 323.58ms. Allocated memory is still 155.2MB. Free memory was 81.3MB in the beginning and 65.3MB in the end (delta: 16.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 68.38ms. Allocated memory is still 155.2MB. Free memory was 65.3MB in the beginning and 62.4MB in the end (delta: 2.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 111.98ms. Allocated memory was 155.2MB in the beginning and 207.6MB in the end (delta: 52.4MB). Free memory was 62.4MB in the beginning and 177.2MB in the end (delta: -114.8MB). Peak memory consumption was 10.9MB. Max. memory is 16.1GB. * RCFGBuilder took 757.26ms. Allocated memory is still 207.6MB. Free memory was 177.2MB in the beginning and 145.8MB in the end (delta: 31.5MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 4347.55ms. Allocated memory was 207.6MB in the beginning and 299.9MB in the end (delta: 92.3MB). Free memory was 144.7MB in the beginning and 181.7MB in the end (delta: -37.0MB). Peak memory consumption was 55.3MB. Max. memory is 16.1GB. * Witness Printer took 79.86ms. Allocated memory is still 299.9MB. Free memory was 181.7MB in the beginning and 176.5MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6578 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.2s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 2.3s. Construction of modules took 0.3s. Büchi inclusion checks took 1.3s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.5s AutomataMinimizationTime, 11 MinimizatonAttempts, 257 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2677 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2677 mSDsluCounter, 5835 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3091 mSDsCounter, 111 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 302 IncrementalHoareTripleChecker+Invalid, 413 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 111 mSolverCounterUnsat, 2744 mSDtfsCounter, 302 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 356]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L195] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L197] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L287] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L289] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 356]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L195] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L197] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L287] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L289] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-19 15:02:19,519 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)