./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3061b6dc Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-assert-order-craig-3061b6d-m [2024-11-19 14:23:25,545 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-19 14:23:25,621 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-19 14:23:25,627 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-19 14:23:25,628 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-19 14:23:25,654 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-19 14:23:25,655 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-19 14:23:25,655 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-19 14:23:25,656 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-19 14:23:25,656 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-19 14:23:25,657 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-19 14:23:25,657 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-19 14:23:25,657 INFO L153 SettingsManager]: * Use SBE=true [2024-11-19 14:23:25,658 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-19 14:23:25,658 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-19 14:23:25,660 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-19 14:23:25,661 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-19 14:23:25,661 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-19 14:23:25,661 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-19 14:23:25,662 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-19 14:23:25,662 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-19 14:23:25,666 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-19 14:23:25,666 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-19 14:23:25,667 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-19 14:23:25,667 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-19 14:23:25,667 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-19 14:23:25,668 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-19 14:23:25,668 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-19 14:23:25,668 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-19 14:23:25,668 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-19 14:23:25,669 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-19 14:23:25,669 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-19 14:23:25,669 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-19 14:23:25,669 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-19 14:23:25,670 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-19 14:23:25,670 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-19 14:23:25,670 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-19 14:23:25,671 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-19 14:23:25,675 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-19 14:23:25,676 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2024-11-19 14:23:25,944 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-19 14:23:25,972 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-19 14:23:25,975 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-19 14:23:25,977 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-19 14:23:25,978 INFO L274 PluginConnector]: CDTParser initialized [2024-11-19 14:23:25,979 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2024-11-19 14:23:27,426 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-19 14:23:27,629 INFO L384 CDTParser]: Found 1 translation units. [2024-11-19 14:23:27,630 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2024-11-19 14:23:27,637 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/65e6f793c/4729a79030fb4afb84a822ec85828c49/FLAG1527f77e6 [2024-11-19 14:23:28,007 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/65e6f793c/4729a79030fb4afb84a822ec85828c49 [2024-11-19 14:23:28,010 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-19 14:23:28,011 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-19 14:23:28,012 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-19 14:23:28,012 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-19 14:23:28,016 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-19 14:23:28,017 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,017 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6ec64b39 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28, skipping insertion in model container [2024-11-19 14:23:28,018 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,034 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-19 14:23:28,234 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 14:23:28,247 INFO L200 MainTranslator]: Completed pre-run [2024-11-19 14:23:28,267 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 14:23:28,286 INFO L204 MainTranslator]: Completed translation [2024-11-19 14:23:28,286 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28 WrapperNode [2024-11-19 14:23:28,286 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-19 14:23:28,287 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-19 14:23:28,288 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-19 14:23:28,288 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-19 14:23:28,294 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,301 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,318 INFO L138 Inliner]: procedures = 18, calls = 19, calls flagged for inlining = 7, calls inlined = 8, statements flattened = 78 [2024-11-19 14:23:28,319 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-19 14:23:28,320 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-19 14:23:28,320 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-19 14:23:28,320 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-19 14:23:28,330 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,330 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,332 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,348 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [2, 5]. 71 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 1 writes are split as follows [0, 1]. [2024-11-19 14:23:28,348 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,349 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,357 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,360 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,362 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,363 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,365 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-19 14:23:28,366 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-19 14:23:28,366 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-19 14:23:28,366 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-19 14:23:28,368 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (1/1) ... [2024-11-19 14:23:28,374 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:28,384 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:28,402 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:23:28,409 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-19 14:23:28,459 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-19 14:23:28,459 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-19 14:23:28,460 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2024-11-19 14:23:28,460 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-11-19 14:23:28,460 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-11-19 14:23:28,460 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2024-11-19 14:23:28,460 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-19 14:23:28,460 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-19 14:23:28,461 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-11-19 14:23:28,461 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2024-11-19 14:23:28,461 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-11-19 14:23:28,558 INFO L238 CfgBuilder]: Building ICFG [2024-11-19 14:23:28,561 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-19 14:23:28,782 INFO L? ?]: Removed 18 outVars from TransFormulas that were not future-live. [2024-11-19 14:23:28,783 INFO L287 CfgBuilder]: Performing block encoding [2024-11-19 14:23:28,804 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-19 14:23:28,805 INFO L316 CfgBuilder]: Removed 3 assume(true) statements. [2024-11-19 14:23:28,805 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 02:23:28 BoogieIcfgContainer [2024-11-19 14:23:28,806 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-19 14:23:28,807 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-19 14:23:28,807 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-19 14:23:28,811 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-19 14:23:28,812 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 14:23:28,812 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 02:23:28" (1/3) ... [2024-11-19 14:23:28,813 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4989ea59 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 02:23:28, skipping insertion in model container [2024-11-19 14:23:28,814 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 14:23:28,814 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:23:28" (2/3) ... [2024-11-19 14:23:28,815 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4989ea59 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 02:23:28, skipping insertion in model container [2024-11-19 14:23:28,815 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 14:23:28,815 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 02:23:28" (3/3) ... [2024-11-19 14:23:28,817 INFO L332 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2024-11-19 14:23:28,885 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-19 14:23:28,885 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-19 14:23:28,885 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-19 14:23:28,887 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-19 14:23:28,888 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-19 14:23:28,888 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-19 14:23:28,888 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-19 14:23:28,888 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-19 14:23:28,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:28,912 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2024-11-19 14:23:28,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:28,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:28,918 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-11-19 14:23:28,918 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-19 14:23:28,918 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-19 14:23:28,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:28,920 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2024-11-19 14:23:28,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:28,922 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:28,922 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-11-19 14:23:28,922 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-19 14:23:28,930 INFO L745 eck$LassoCheckResult]: Stem: 27#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 28#L27-3true [2024-11-19 14:23:28,930 INFO L747 eck$LassoCheckResult]: Loop: 28#L27-3true assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5#L27-2true main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 28#L27-3true [2024-11-19 14:23:28,937 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:28,937 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2024-11-19 14:23:28,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:28,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [471540516] [2024-11-19 14:23:28,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:23:28,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:29,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:29,056 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:29,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:29,087 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:29,089 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:29,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2024-11-19 14:23:29,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:29,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437338337] [2024-11-19 14:23:29,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:23:29,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:29,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:29,101 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:29,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:29,110 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:29,111 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:29,111 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2024-11-19 14:23:29,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:29,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247564538] [2024-11-19 14:23:29,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:23:29,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:29,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:29,145 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:29,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:29,168 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:29,513 INFO L204 LassoAnalysis]: Preferences: [2024-11-19 14:23:29,514 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-19 14:23:29,514 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-19 14:23:29,514 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-19 14:23:29,514 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-19 14:23:29,514 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:29,515 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-19 14:23:29,516 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-19 14:23:29,516 INFO L132 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2024-11-19 14:23:29,516 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-19 14:23:29,516 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-19 14:23:29,535 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:29,543 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:29,564 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:29,568 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:29,572 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:29,574 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:29,582 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:29,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:29,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:29,746 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:29,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:29,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:23:30,038 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-19 14:23:30,042 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-19 14:23:30,044 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:30,044 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:30,046 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:23:30,048 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-19 14:23:30,049 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 14:23:30,063 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 14:23:30,063 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 14:23:30,064 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 14:23:30,064 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 14:23:30,064 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 14:23:30,066 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 14:23:30,066 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 14:23:30,070 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 14:23:30,086 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-19 14:23:30,087 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:30,088 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:30,090 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:23:30,091 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-19 14:23:30,093 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 14:23:30,106 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 14:23:30,107 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 14:23:30,107 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 14:23:30,107 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 14:23:30,113 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-19 14:23:30,113 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-19 14:23:30,120 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 14:23:30,135 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-19 14:23:30,135 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:30,135 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:30,137 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:23:30,138 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-19 14:23:30,139 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 14:23:30,149 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 14:23:30,150 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 14:23:30,150 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 14:23:30,150 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 14:23:30,152 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-19 14:23:30,152 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-19 14:23:30,155 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 14:23:30,171 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-11-19 14:23:30,172 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:30,172 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:30,174 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:23:30,175 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-19 14:23:30,176 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 14:23:30,189 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 14:23:30,189 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 14:23:30,189 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 14:23:30,189 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 14:23:30,189 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 14:23:30,190 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 14:23:30,191 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 14:23:30,192 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 14:23:30,205 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2024-11-19 14:23:30,206 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:30,206 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:30,207 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:23:30,208 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-19 14:23:30,209 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 14:23:30,219 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 14:23:30,219 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 14:23:30,219 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 14:23:30,219 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 14:23:30,219 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 14:23:30,220 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 14:23:30,220 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 14:23:30,221 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 14:23:30,233 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2024-11-19 14:23:30,233 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:30,234 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:30,235 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:23:30,237 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-19 14:23:30,238 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 14:23:30,251 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 14:23:30,251 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 14:23:30,251 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 14:23:30,251 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 14:23:30,251 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 14:23:30,252 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 14:23:30,252 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 14:23:30,253 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 14:23:30,268 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-11-19 14:23:30,269 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:30,269 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:30,271 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:23:30,274 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-19 14:23:30,274 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 14:23:30,286 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 14:23:30,287 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 14:23:30,287 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 14:23:30,287 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 14:23:30,288 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 14:23:30,289 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 14:23:30,291 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 14:23:30,294 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 14:23:30,309 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-19 14:23:30,310 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:30,310 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:30,311 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:23:30,313 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-19 14:23:30,314 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 14:23:30,327 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 14:23:30,327 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 14:23:30,327 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 14:23:30,327 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 14:23:30,330 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-19 14:23:30,330 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-19 14:23:30,335 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 14:23:30,349 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2024-11-19 14:23:30,350 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:30,350 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:30,351 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:23:30,352 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-19 14:23:30,353 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 14:23:30,366 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 14:23:30,366 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 14:23:30,366 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 14:23:30,366 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 14:23:30,379 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-19 14:23:30,379 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-19 14:23:30,389 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-19 14:23:30,414 INFO L443 ModelExtractionUtils]: Simplification made 7 calls to the SMT solver. [2024-11-19 14:23:30,414 INFO L444 ModelExtractionUtils]: 5 out of 16 variables were initially zero. Simplification set additionally 7 variables to zero. [2024-11-19 14:23:30,416 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:23:30,416 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:30,418 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:23:30,420 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-19 14:23:30,420 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-19 14:23:30,437 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2024-11-19 14:23:30,437 INFO L474 LassoAnalysis]: Proved termination. [2024-11-19 14:23:30,438 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~#array~0#1.offset) = 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~#array~0#1.offset Supporting invariants [] [2024-11-19 14:23:30,453 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-19 14:23:30,467 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2024-11-19 14:23:30,476 WARN L976 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #length [2024-11-19 14:23:30,477 WARN L976 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] [2024-11-19 14:23:30,479 WARN L976 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: ~#array~0!offset [2024-11-19 14:23:30,499 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:30,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:30,517 INFO L255 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-19 14:23:30,518 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:30,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:30,533 INFO L255 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-19 14:23:30,533 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:30,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:30,583 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-19 14:23:30,585 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:30,640 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 54 states and 77 transitions. Complement of second has 6 states. [2024-11-19 14:23:30,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-19 14:23:30,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:30,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 38 transitions. [2024-11-19 14:23:30,654 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 38 transitions. Stem has 2 letters. Loop has 2 letters. [2024-11-19 14:23:30,654 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-19 14:23:30,654 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 38 transitions. Stem has 4 letters. Loop has 2 letters. [2024-11-19 14:23:30,655 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-19 14:23:30,655 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 38 transitions. Stem has 2 letters. Loop has 4 letters. [2024-11-19 14:23:30,655 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-19 14:23:30,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 77 transitions. [2024-11-19 14:23:30,659 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2024-11-19 14:23:30,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 25 states and 35 transitions. [2024-11-19 14:23:30,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2024-11-19 14:23:30,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2024-11-19 14:23:30,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 35 transitions. [2024-11-19 14:23:30,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:30,666 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2024-11-19 14:23:30,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 35 transitions. [2024-11-19 14:23:30,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2024-11-19 14:23:30,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.4) internal successors, (35), 24 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:30,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 35 transitions. [2024-11-19 14:23:30,689 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2024-11-19 14:23:30,689 INFO L425 stractBuchiCegarLoop]: Abstraction has 25 states and 35 transitions. [2024-11-19 14:23:30,689 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-19 14:23:30,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 35 transitions. [2024-11-19 14:23:30,690 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2024-11-19 14:23:30,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:30,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:30,691 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2024-11-19 14:23:30,691 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:30,691 INFO L745 eck$LassoCheckResult]: Stem: 157#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 146#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 149#L27-4 main_~i~0#1 := 0; 150#L32-3 [2024-11-19 14:23:30,692 INFO L747 eck$LassoCheckResult]: Loop: 150#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 155#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 144#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 150#L32-3 [2024-11-19 14:23:30,696 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:30,697 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2024-11-19 14:23:30,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:30,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972937713] [2024-11-19 14:23:30,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:23:30,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:30,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:30,708 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:30,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:30,724 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:30,724 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:30,724 INFO L85 PathProgramCache]: Analyzing trace with hash 54361, now seen corresponding path program 1 times [2024-11-19 14:23:30,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:30,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738192565] [2024-11-19 14:23:30,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:23:30,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:30,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:30,741 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:30,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:30,754 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:30,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:30,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1807958031, now seen corresponding path program 1 times [2024-11-19 14:23:30,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:30,758 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086263845] [2024-11-19 14:23:30,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:23:30,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:30,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:30,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:30,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:30,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086263845] [2024-11-19 14:23:30,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086263845] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 14:23:30,923 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 14:23:30,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 14:23:30,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618468701] [2024-11-19 14:23:30,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 14:23:30,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:30,983 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 14:23:30,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-19 14:23:30,986 INFO L87 Difference]: Start difference. First operand 25 states and 35 transitions. cyclomatic complexity: 13 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:31,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:31,056 INFO L93 Difference]: Finished difference Result 44 states and 51 transitions. [2024-11-19 14:23:31,056 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 51 transitions. [2024-11-19 14:23:31,057 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:31,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 32 states and 38 transitions. [2024-11-19 14:23:31,058 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2024-11-19 14:23:31,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2024-11-19 14:23:31,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 38 transitions. [2024-11-19 14:23:31,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:31,061 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 38 transitions. [2024-11-19 14:23:31,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 38 transitions. [2024-11-19 14:23:31,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 20. [2024-11-19 14:23:31,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.2) internal successors, (24), 19 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:31,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2024-11-19 14:23:31,063 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20 states and 24 transitions. [2024-11-19 14:23:31,065 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 14:23:31,066 INFO L425 stractBuchiCegarLoop]: Abstraction has 20 states and 24 transitions. [2024-11-19 14:23:31,066 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-19 14:23:31,066 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 24 transitions. [2024-11-19 14:23:31,066 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:31,067 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:31,067 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:31,067 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2024-11-19 14:23:31,067 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:31,067 INFO L745 eck$LassoCheckResult]: Stem: 231#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 220#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 223#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 224#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 225#L27-4 main_~i~0#1 := 0; 226#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 230#L34 [2024-11-19 14:23:31,067 INFO L747 eck$LassoCheckResult]: Loop: 230#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 218#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 227#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 230#L34 [2024-11-19 14:23:31,068 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:31,068 INFO L85 PathProgramCache]: Analyzing trace with hash 1809669547, now seen corresponding path program 1 times [2024-11-19 14:23:31,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:31,070 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782421791] [2024-11-19 14:23:31,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:23:31,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:31,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:31,088 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:31,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:31,107 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:31,108 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:31,108 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 2 times [2024-11-19 14:23:31,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:31,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190056053] [2024-11-19 14:23:31,108 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:23:31,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:31,116 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:23:31,116 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:31,116 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:31,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:31,126 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:31,126 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:31,126 INFO L85 PathProgramCache]: Analyzing trace with hash 1436021995, now seen corresponding path program 1 times [2024-11-19 14:23:31,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:31,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65147456] [2024-11-19 14:23:31,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:23:31,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:31,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:31,243 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:31,243 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:31,243 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [65147456] [2024-11-19 14:23:31,243 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [65147456] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:31,244 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [542654013] [2024-11-19 14:23:31,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:23:31,244 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:31,244 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:31,246 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:31,247 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-19 14:23:31,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:31,292 INFO L255 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-19 14:23:31,293 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:31,358 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:31,358 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:31,405 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:31,405 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [542654013] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:31,405 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:31,405 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2024-11-19 14:23:31,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432365606] [2024-11-19 14:23:31,406 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:31,460 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:31,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2024-11-19 14:23:31,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2024-11-19 14:23:31,462 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. cyclomatic complexity: 7 Second operand has 11 states, 10 states have (on average 2.2) internal successors, (22), 11 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:31,513 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-19 14:23:31,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:31,604 INFO L93 Difference]: Finished difference Result 62 states and 73 transitions. [2024-11-19 14:23:31,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 73 transitions. [2024-11-19 14:23:31,606 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:31,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 46 states and 54 transitions. [2024-11-19 14:23:31,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2024-11-19 14:23:31,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2024-11-19 14:23:31,611 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 54 transitions. [2024-11-19 14:23:31,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:31,611 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46 states and 54 transitions. [2024-11-19 14:23:31,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 54 transitions. [2024-11-19 14:23:31,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 28. [2024-11-19 14:23:31,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.1785714285714286) internal successors, (33), 27 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:31,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2024-11-19 14:23:31,613 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 33 transitions. [2024-11-19 14:23:31,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-19 14:23:31,614 INFO L425 stractBuchiCegarLoop]: Abstraction has 28 states and 33 transitions. [2024-11-19 14:23:31,615 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-19 14:23:31,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 33 transitions. [2024-11-19 14:23:31,615 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:31,615 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:31,615 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:31,616 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1] [2024-11-19 14:23:31,616 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:31,616 INFO L745 eck$LassoCheckResult]: Stem: 386#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 373#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 374#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 387#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 388#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 377#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 378#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 379#L27-4 main_~i~0#1 := 0; 380#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 392#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 381#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 382#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 385#L34 [2024-11-19 14:23:31,616 INFO L747 eck$LassoCheckResult]: Loop: 385#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 372#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 390#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 385#L34 [2024-11-19 14:23:31,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:31,617 INFO L85 PathProgramCache]: Analyzing trace with hash 780824429, now seen corresponding path program 2 times [2024-11-19 14:23:31,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:31,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443625861] [2024-11-19 14:23:31,617 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:23:31,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:31,642 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:23:31,645 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:31,645 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:31,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:31,666 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:31,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:31,670 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 3 times [2024-11-19 14:23:31,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:31,670 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953095418] [2024-11-19 14:23:31,670 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:31,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:31,676 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 14:23:31,677 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:31,677 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:31,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:31,687 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:31,687 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:31,688 INFO L85 PathProgramCache]: Analyzing trace with hash -2264087, now seen corresponding path program 3 times [2024-11-19 14:23:31,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:31,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418513591] [2024-11-19 14:23:31,688 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:31,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:31,705 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2024-11-19 14:23:31,706 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:31,838 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:31,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:31,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418513591] [2024-11-19 14:23:31,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418513591] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:31,839 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [509321799] [2024-11-19 14:23:31,839 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:31,839 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:31,839 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:31,841 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:31,842 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-19 14:23:31,901 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2024-11-19 14:23:31,901 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:31,902 INFO L255 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-11-19 14:23:31,903 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:31,990 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:31,990 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:32,066 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:32,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [509321799] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:32,067 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:32,067 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 13 [2024-11-19 14:23:32,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1288211188] [2024-11-19 14:23:32,067 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:32,125 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:32,125 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2024-11-19 14:23:32,125 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2024-11-19 14:23:32,126 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. cyclomatic complexity: 8 Second operand has 14 states, 13 states have (on average 2.3076923076923075) internal successors, (30), 14 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:32,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:32,274 INFO L93 Difference]: Finished difference Result 88 states and 103 transitions. [2024-11-19 14:23:32,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88 states and 103 transitions. [2024-11-19 14:23:32,277 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:32,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88 states to 60 states and 70 transitions. [2024-11-19 14:23:32,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2024-11-19 14:23:32,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2024-11-19 14:23:32,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 70 transitions. [2024-11-19 14:23:32,278 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:32,278 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 70 transitions. [2024-11-19 14:23:32,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 70 transitions. [2024-11-19 14:23:32,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 36. [2024-11-19 14:23:32,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.1666666666666667) internal successors, (42), 35 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:32,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 42 transitions. [2024-11-19 14:23:32,285 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 42 transitions. [2024-11-19 14:23:32,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-19 14:23:32,287 INFO L425 stractBuchiCegarLoop]: Abstraction has 36 states and 42 transitions. [2024-11-19 14:23:32,287 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-19 14:23:32,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 42 transitions. [2024-11-19 14:23:32,288 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:32,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:32,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:32,288 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1] [2024-11-19 14:23:32,288 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:32,289 INFO L745 eck$LassoCheckResult]: Stem: 610#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 596#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 597#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 611#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 612#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 600#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 601#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 616#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 615#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 602#L27-4 main_~i~0#1 := 0; 603#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 624#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 604#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 605#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 609#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 618#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 623#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 608#L34 [2024-11-19 14:23:32,289 INFO L747 eck$LassoCheckResult]: Loop: 608#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 595#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 614#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 608#L34 [2024-11-19 14:23:32,289 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:32,289 INFO L85 PathProgramCache]: Analyzing trace with hash -79873369, now seen corresponding path program 4 times [2024-11-19 14:23:32,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:32,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807661420] [2024-11-19 14:23:32,290 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:23:32,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:32,317 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:23:32,317 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:32,317 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:32,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:32,337 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:32,339 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:32,339 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 4 times [2024-11-19 14:23:32,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:32,340 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973804507] [2024-11-19 14:23:32,340 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:23:32,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:32,347 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:23:32,347 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:32,347 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:32,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:32,352 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:32,353 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:32,353 INFO L85 PathProgramCache]: Analyzing trace with hash -95607185, now seen corresponding path program 5 times [2024-11-19 14:23:32,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:32,353 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85196508] [2024-11-19 14:23:32,353 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:32,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:32,375 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2024-11-19 14:23:32,379 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:32,561 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 9 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:32,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:32,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [85196508] [2024-11-19 14:23:32,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [85196508] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:32,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [942214368] [2024-11-19 14:23:32,562 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:32,562 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:32,563 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:32,566 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:32,567 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-19 14:23:32,636 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2024-11-19 14:23:32,636 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:32,637 INFO L255 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-11-19 14:23:32,638 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:32,833 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:32,834 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:32,959 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:32,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [942214368] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:32,960 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:32,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 19 [2024-11-19 14:23:32,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1518951230] [2024-11-19 14:23:32,960 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:33,014 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:33,015 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2024-11-19 14:23:33,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=305, Unknown=0, NotChecked=0, Total=380 [2024-11-19 14:23:33,015 INFO L87 Difference]: Start difference. First operand 36 states and 42 transitions. cyclomatic complexity: 9 Second operand has 20 states, 19 states have (on average 2.1578947368421053) internal successors, (41), 20 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:33,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:33,419 INFO L93 Difference]: Finished difference Result 134 states and 155 transitions. [2024-11-19 14:23:33,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134 states and 155 transitions. [2024-11-19 14:23:33,421 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:33,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134 states to 74 states and 86 transitions. [2024-11-19 14:23:33,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65 [2024-11-19 14:23:33,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65 [2024-11-19 14:23:33,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 86 transitions. [2024-11-19 14:23:33,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:33,426 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74 states and 86 transitions. [2024-11-19 14:23:33,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 86 transitions. [2024-11-19 14:23:33,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 44. [2024-11-19 14:23:33,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.1590909090909092) internal successors, (51), 43 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:33,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 51 transitions. [2024-11-19 14:23:33,432 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 51 transitions. [2024-11-19 14:23:33,433 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2024-11-19 14:23:33,433 INFO L425 stractBuchiCegarLoop]: Abstraction has 44 states and 51 transitions. [2024-11-19 14:23:33,433 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-19 14:23:33,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 51 transitions. [2024-11-19 14:23:33,435 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:33,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:33,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:33,435 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1] [2024-11-19 14:23:33,435 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:33,436 INFO L745 eck$LassoCheckResult]: Stem: 953#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 937#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 938#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 951#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 952#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 941#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 942#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 962#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 961#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 958#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 957#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 943#L27-4 main_~i~0#1 := 0; 944#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 949#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 936#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 946#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 972#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 970#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 969#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 966#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 964#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 963#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 956#L34 [2024-11-19 14:23:33,436 INFO L747 eck$LassoCheckResult]: Loop: 956#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 959#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 955#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 956#L34 [2024-11-19 14:23:33,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:33,436 INFO L85 PathProgramCache]: Analyzing trace with hash 1712449137, now seen corresponding path program 6 times [2024-11-19 14:23:33,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:33,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130143108] [2024-11-19 14:23:33,436 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:23:33,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:33,468 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2024-11-19 14:23:33,468 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:33,468 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:33,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:33,485 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:33,486 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:33,486 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 5 times [2024-11-19 14:23:33,486 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:33,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823938574] [2024-11-19 14:23:33,487 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:33,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:33,490 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:23:33,490 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:33,491 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:33,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:33,494 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:33,494 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:33,495 INFO L85 PathProgramCache]: Analyzing trace with hash -49254811, now seen corresponding path program 7 times [2024-11-19 14:23:33,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:33,495 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828557820] [2024-11-19 14:23:33,495 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:33,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:33,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:33,707 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 12 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:33,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:33,708 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828557820] [2024-11-19 14:23:33,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [828557820] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:33,708 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [950241005] [2024-11-19 14:23:33,708 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:33,709 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:33,709 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:33,711 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:33,713 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-19 14:23:33,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:33,774 INFO L255 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-19 14:23:33,776 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:33,912 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:33,913 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:34,034 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:34,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [950241005] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:34,034 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:34,034 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2024-11-19 14:23:34,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776308472] [2024-11-19 14:23:34,035 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:34,083 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:34,084 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2024-11-19 14:23:34,085 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=279, Unknown=0, NotChecked=0, Total=380 [2024-11-19 14:23:34,085 INFO L87 Difference]: Start difference. First operand 44 states and 51 transitions. cyclomatic complexity: 10 Second operand has 20 states, 19 states have (on average 2.4210526315789473) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:34,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:34,307 INFO L93 Difference]: Finished difference Result 140 states and 163 transitions. [2024-11-19 14:23:34,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 163 transitions. [2024-11-19 14:23:34,308 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:34,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 88 states and 102 transitions. [2024-11-19 14:23:34,309 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77 [2024-11-19 14:23:34,310 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77 [2024-11-19 14:23:34,310 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 102 transitions. [2024-11-19 14:23:34,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:34,310 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88 states and 102 transitions. [2024-11-19 14:23:34,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 102 transitions. [2024-11-19 14:23:34,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 52. [2024-11-19 14:23:34,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1538461538461537) internal successors, (60), 51 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:34,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 60 transitions. [2024-11-19 14:23:34,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 60 transitions. [2024-11-19 14:23:34,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-11-19 14:23:34,321 INFO L425 stractBuchiCegarLoop]: Abstraction has 52 states and 60 transitions. [2024-11-19 14:23:34,321 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-19 14:23:34,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 60 transitions. [2024-11-19 14:23:34,322 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:34,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:34,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:34,323 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1] [2024-11-19 14:23:34,323 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:34,323 INFO L745 eck$LassoCheckResult]: Stem: 1315#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1298#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1299#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1313#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1314#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1302#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1303#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1326#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1325#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1324#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1323#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1320#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1319#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1304#L27-4 main_~i~0#1 := 0; 1305#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1310#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1297#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1307#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1312#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1340#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1339#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1336#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1334#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1333#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1330#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1328#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1327#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1318#L34 [2024-11-19 14:23:34,323 INFO L747 eck$LassoCheckResult]: Loop: 1318#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1321#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1317#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1318#L34 [2024-11-19 14:23:34,324 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:34,324 INFO L85 PathProgramCache]: Analyzing trace with hash -240296029, now seen corresponding path program 8 times [2024-11-19 14:23:34,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:34,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618973595] [2024-11-19 14:23:34,324 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:23:34,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:34,354 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:23:34,355 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:34,355 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:34,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:34,372 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:34,373 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:34,373 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 6 times [2024-11-19 14:23:34,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:34,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25437115] [2024-11-19 14:23:34,373 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:23:34,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:34,376 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2024-11-19 14:23:34,377 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:34,377 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:34,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:34,385 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:34,386 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:34,386 INFO L85 PathProgramCache]: Analyzing trace with hash 1051529203, now seen corresponding path program 9 times [2024-11-19 14:23:34,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:34,386 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255354711] [2024-11-19 14:23:34,387 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:34,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:34,434 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2024-11-19 14:23:34,434 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:34,649 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 22 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:34,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:34,650 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [255354711] [2024-11-19 14:23:34,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [255354711] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:34,650 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [682802407] [2024-11-19 14:23:34,650 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:34,650 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:34,651 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:34,652 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:34,654 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-11-19 14:23:34,720 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2024-11-19 14:23:34,721 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:34,722 INFO L255 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 14 conjuncts are in the unsatisfiable core [2024-11-19 14:23:34,723 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:34,889 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:34,889 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:35,051 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:35,051 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [682802407] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:35,051 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:35,051 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2024-11-19 14:23:35,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494671594] [2024-11-19 14:23:35,051 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:35,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:35,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2024-11-19 14:23:35,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=375, Unknown=0, NotChecked=0, Total=506 [2024-11-19 14:23:35,103 INFO L87 Difference]: Start difference. First operand 52 states and 60 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.4545454545454546) internal successors, (54), 23 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:35,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:35,342 INFO L93 Difference]: Finished difference Result 166 states and 193 transitions. [2024-11-19 14:23:35,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 166 states and 193 transitions. [2024-11-19 14:23:35,344 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:35,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 166 states to 102 states and 118 transitions. [2024-11-19 14:23:35,344 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2024-11-19 14:23:35,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2024-11-19 14:23:35,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 118 transitions. [2024-11-19 14:23:35,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:35,346 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102 states and 118 transitions. [2024-11-19 14:23:35,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 118 transitions. [2024-11-19 14:23:35,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 60. [2024-11-19 14:23:35,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.15) internal successors, (69), 59 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:35,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 69 transitions. [2024-11-19 14:23:35,352 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60 states and 69 transitions. [2024-11-19 14:23:35,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-11-19 14:23:35,354 INFO L425 stractBuchiCegarLoop]: Abstraction has 60 states and 69 transitions. [2024-11-19 14:23:35,354 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-19 14:23:35,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 69 transitions. [2024-11-19 14:23:35,354 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:35,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:35,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:35,355 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1] [2024-11-19 14:23:35,355 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:35,356 INFO L745 eck$LassoCheckResult]: Stem: 1744#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1729#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1745#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1732#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1733#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1759#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1758#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1757#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1756#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1755#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1754#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1751#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1750#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1734#L27-4 main_~i~0#1 := 0; 1735#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1741#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1727#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1738#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1743#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1778#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1777#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1775#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1772#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1771#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1769#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1767#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1766#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1763#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1761#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1760#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1749#L34 [2024-11-19 14:23:35,356 INFO L747 eck$LassoCheckResult]: Loop: 1749#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1752#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1748#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1749#L34 [2024-11-19 14:23:35,356 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:35,356 INFO L85 PathProgramCache]: Analyzing trace with hash 1967863157, now seen corresponding path program 10 times [2024-11-19 14:23:35,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:35,357 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873460257] [2024-11-19 14:23:35,357 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:23:35,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:35,387 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:23:35,387 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:35,387 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:35,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:35,429 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:35,430 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:35,430 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 7 times [2024-11-19 14:23:35,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:35,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071066492] [2024-11-19 14:23:35,432 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:35,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:35,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:35,436 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:35,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:35,443 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:35,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:35,443 INFO L85 PathProgramCache]: Analyzing trace with hash -1692233503, now seen corresponding path program 11 times [2024-11-19 14:23:35,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:35,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222281064] [2024-11-19 14:23:35,444 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:35,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:35,484 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2024-11-19 14:23:35,485 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:35,823 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 45 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:35,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:35,824 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222281064] [2024-11-19 14:23:35,824 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [222281064] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:35,824 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [442705687] [2024-11-19 14:23:35,824 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:35,824 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:35,824 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:35,826 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:35,828 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-11-19 14:23:35,934 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2024-11-19 14:23:35,934 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:35,935 INFO L255 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-11-19 14:23:35,937 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:36,281 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:36,281 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:36,497 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:36,497 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [442705687] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:36,497 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:36,497 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 31 [2024-11-19 14:23:36,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1825332342] [2024-11-19 14:23:36,498 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:36,546 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:36,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2024-11-19 14:23:36,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=180, Invalid=812, Unknown=0, NotChecked=0, Total=992 [2024-11-19 14:23:36,547 INFO L87 Difference]: Start difference. First operand 60 states and 69 transitions. cyclomatic complexity: 12 Second operand has 32 states, 31 states have (on average 2.2903225806451615) internal successors, (71), 32 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:37,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:37,299 INFO L93 Difference]: Finished difference Result 230 states and 266 transitions. [2024-11-19 14:23:37,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 266 transitions. [2024-11-19 14:23:37,301 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:37,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 116 states and 134 transitions. [2024-11-19 14:23:37,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101 [2024-11-19 14:23:37,302 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101 [2024-11-19 14:23:37,302 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 134 transitions. [2024-11-19 14:23:37,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:37,306 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 134 transitions. [2024-11-19 14:23:37,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 134 transitions. [2024-11-19 14:23:37,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 68. [2024-11-19 14:23:37,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1470588235294117) internal successors, (78), 67 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:37,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 78 transitions. [2024-11-19 14:23:37,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 78 transitions. [2024-11-19 14:23:37,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2024-11-19 14:23:37,311 INFO L425 stractBuchiCegarLoop]: Abstraction has 68 states and 78 transitions. [2024-11-19 14:23:37,311 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-19 14:23:37,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 78 transitions. [2024-11-19 14:23:37,312 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:37,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:37,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:37,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1] [2024-11-19 14:23:37,313 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:37,313 INFO L745 eck$LassoCheckResult]: Stem: 2333#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2316#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2331#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2332#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2319#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2320#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2348#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2347#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2346#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2345#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2344#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2343#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2342#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2341#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2338#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2337#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2321#L27-4 main_~i~0#1 := 0; 2322#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2328#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2314#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2325#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2330#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2373#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2372#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2370#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2367#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2366#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2364#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2361#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2360#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2358#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2356#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2355#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2352#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2350#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2349#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2336#L34 [2024-11-19 14:23:37,314 INFO L747 eck$LassoCheckResult]: Loop: 2336#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2339#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2335#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2336#L34 [2024-11-19 14:23:37,314 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:37,314 INFO L85 PathProgramCache]: Analyzing trace with hash -664171361, now seen corresponding path program 12 times [2024-11-19 14:23:37,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:37,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991053964] [2024-11-19 14:23:37,315 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:23:37,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:37,390 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2024-11-19 14:23:37,391 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:37,391 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:37,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:37,417 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:37,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:37,418 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 8 times [2024-11-19 14:23:37,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:37,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281838716] [2024-11-19 14:23:37,418 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:23:37,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:37,421 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:23:37,422 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:37,422 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:37,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:37,429 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:37,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:37,430 INFO L85 PathProgramCache]: Analyzing trace with hash 585363831, now seen corresponding path program 13 times [2024-11-19 14:23:37,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:37,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716589395] [2024-11-19 14:23:37,430 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:37,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:37,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:37,746 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:37,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:37,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716589395] [2024-11-19 14:23:37,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1716589395] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:37,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1524050908] [2024-11-19 14:23:37,747 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:37,747 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:37,747 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:37,752 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:37,755 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-11-19 14:23:37,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:37,832 INFO L255 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 18 conjuncts are in the unsatisfiable core [2024-11-19 14:23:37,834 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:38,050 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:38,050 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:38,228 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:38,228 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1524050908] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:38,228 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:38,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2024-11-19 14:23:38,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1976131989] [2024-11-19 14:23:38,229 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:38,273 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:38,274 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2024-11-19 14:23:38,275 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=609, Unknown=0, NotChecked=0, Total=812 [2024-11-19 14:23:38,275 INFO L87 Difference]: Start difference. First operand 68 states and 78 transitions. cyclomatic complexity: 13 Second operand has 29 states, 28 states have (on average 2.5) internal successors, (70), 29 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:38,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:38,576 INFO L93 Difference]: Finished difference Result 218 states and 253 transitions. [2024-11-19 14:23:38,576 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218 states and 253 transitions. [2024-11-19 14:23:38,578 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:38,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218 states to 130 states and 150 transitions. [2024-11-19 14:23:38,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113 [2024-11-19 14:23:38,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113 [2024-11-19 14:23:38,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130 states and 150 transitions. [2024-11-19 14:23:38,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:38,579 INFO L218 hiAutomatonCegarLoop]: Abstraction has 130 states and 150 transitions. [2024-11-19 14:23:38,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states and 150 transitions. [2024-11-19 14:23:38,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 76. [2024-11-19 14:23:38,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.144736842105263) internal successors, (87), 75 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:38,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 87 transitions. [2024-11-19 14:23:38,585 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 87 transitions. [2024-11-19 14:23:38,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2024-11-19 14:23:38,591 INFO L425 stractBuchiCegarLoop]: Abstraction has 76 states and 87 transitions. [2024-11-19 14:23:38,591 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-19 14:23:38,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 87 transitions. [2024-11-19 14:23:38,593 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:38,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:38,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:38,594 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1] [2024-11-19 14:23:38,595 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:38,595 INFO L745 eck$LassoCheckResult]: Stem: 2899#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2884#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2900#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2901#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2887#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2888#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2918#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2917#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2916#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2915#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2914#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2913#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2912#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2911#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2910#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2909#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2906#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2905#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2889#L27-4 main_~i~0#1 := 0; 2890#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2896#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2882#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2893#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2898#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2949#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2948#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2946#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2943#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2942#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2940#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2937#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2936#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2934#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2931#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2930#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2928#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2926#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2925#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2922#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2920#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2919#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2904#L34 [2024-11-19 14:23:38,595 INFO L747 eck$LassoCheckResult]: Loop: 2904#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2907#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2903#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2904#L34 [2024-11-19 14:23:38,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:38,596 INFO L85 PathProgramCache]: Analyzing trace with hash -704996231, now seen corresponding path program 14 times [2024-11-19 14:23:38,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:38,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615192657] [2024-11-19 14:23:38,596 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:23:38,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:38,639 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:23:38,640 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:38,640 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:38,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:38,672 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:38,673 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:38,673 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 9 times [2024-11-19 14:23:38,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:38,673 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896761325] [2024-11-19 14:23:38,673 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:38,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:38,680 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 14:23:38,680 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:38,680 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:38,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:38,684 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:38,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:38,686 INFO L85 PathProgramCache]: Analyzing trace with hash -152593571, now seen corresponding path program 15 times [2024-11-19 14:23:38,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:38,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008065021] [2024-11-19 14:23:38,686 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:38,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:38,742 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2024-11-19 14:23:38,742 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:39,159 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 70 proven. 86 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:39,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:39,159 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008065021] [2024-11-19 14:23:39,160 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008065021] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:39,160 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1969704315] [2024-11-19 14:23:39,160 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:39,160 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:39,160 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:39,161 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:39,162 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-11-19 14:23:39,257 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2024-11-19 14:23:39,258 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:39,259 INFO L255 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-11-19 14:23:39,260 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:39,490 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:39,490 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:39,685 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:39,685 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1969704315] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:39,686 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:39,686 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2024-11-19 14:23:39,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762430456] [2024-11-19 14:23:39,686 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:39,725 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:39,725 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2024-11-19 14:23:39,726 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=245, Invalid=747, Unknown=0, NotChecked=0, Total=992 [2024-11-19 14:23:39,726 INFO L87 Difference]: Start difference. First operand 76 states and 87 transitions. cyclomatic complexity: 14 Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 32 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:40,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:40,026 INFO L93 Difference]: Finished difference Result 244 states and 283 transitions. [2024-11-19 14:23:40,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244 states and 283 transitions. [2024-11-19 14:23:40,028 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:40,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244 states to 144 states and 166 transitions. [2024-11-19 14:23:40,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125 [2024-11-19 14:23:40,029 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125 [2024-11-19 14:23:40,029 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 166 transitions. [2024-11-19 14:23:40,030 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:40,030 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144 states and 166 transitions. [2024-11-19 14:23:40,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 166 transitions. [2024-11-19 14:23:40,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 84. [2024-11-19 14:23:40,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.1428571428571428) internal successors, (96), 83 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:40,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 96 transitions. [2024-11-19 14:23:40,034 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84 states and 96 transitions. [2024-11-19 14:23:40,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2024-11-19 14:23:40,039 INFO L425 stractBuchiCegarLoop]: Abstraction has 84 states and 96 transitions. [2024-11-19 14:23:40,039 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-19 14:23:40,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 96 transitions. [2024-11-19 14:23:40,042 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:40,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:40,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:40,043 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1] [2024-11-19 14:23:40,043 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:40,043 INFO L745 eck$LassoCheckResult]: Stem: 3536#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 3520#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 3521#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3537#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3538#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3524#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3525#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3557#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3556#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3555#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3554#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3553#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3552#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3551#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3550#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3549#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3548#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3547#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3546#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3543#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3542#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 3526#L27-4 main_~i~0#1 := 0; 3527#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3533#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3519#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3530#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3535#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3594#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3593#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3591#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3588#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3587#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3585#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3582#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3581#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3579#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3576#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3575#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3573#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3570#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3569#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3567#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3565#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3564#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3561#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3559#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3558#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3541#L34 [2024-11-19 14:23:40,043 INFO L747 eck$LassoCheckResult]: Loop: 3541#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3544#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3540#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3541#L34 [2024-11-19 14:23:40,044 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:40,044 INFO L85 PathProgramCache]: Analyzing trace with hash -1850900069, now seen corresponding path program 16 times [2024-11-19 14:23:40,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:40,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139172148] [2024-11-19 14:23:40,044 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:23:40,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:40,092 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:23:40,092 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:40,092 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:40,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:40,137 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:40,140 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:40,141 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 10 times [2024-11-19 14:23:40,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:40,141 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910950067] [2024-11-19 14:23:40,141 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:23:40,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:40,145 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:23:40,145 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:40,145 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:40,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:40,148 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:40,149 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:40,149 INFO L85 PathProgramCache]: Analyzing trace with hash -1373762821, now seen corresponding path program 17 times [2024-11-19 14:23:40,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:40,149 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742415058] [2024-11-19 14:23:40,149 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:40,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:40,179 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2024-11-19 14:23:40,179 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:40,639 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 108 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:40,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:40,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742415058] [2024-11-19 14:23:40,639 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1742415058] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:40,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1985106918] [2024-11-19 14:23:40,639 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:40,639 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:40,640 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:40,642 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:40,645 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-11-19 14:23:40,829 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2024-11-19 14:23:40,829 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:40,831 INFO L255 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-19 14:23:40,833 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:41,340 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:41,340 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:41,658 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:41,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1985106918] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:41,658 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:41,658 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 43 [2024-11-19 14:23:41,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998851363] [2024-11-19 14:23:41,659 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:41,695 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:41,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2024-11-19 14:23:41,696 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=330, Invalid=1562, Unknown=0, NotChecked=0, Total=1892 [2024-11-19 14:23:41,696 INFO L87 Difference]: Start difference. First operand 84 states and 96 transitions. cyclomatic complexity: 15 Second operand has 44 states, 43 states have (on average 2.3488372093023258) internal successors, (101), 44 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:42,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:42,650 INFO L93 Difference]: Finished difference Result 326 states and 377 transitions. [2024-11-19 14:23:42,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 326 states and 377 transitions. [2024-11-19 14:23:42,656 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:42,657 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 326 states to 158 states and 182 transitions. [2024-11-19 14:23:42,658 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 137 [2024-11-19 14:23:42,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137 [2024-11-19 14:23:42,658 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 182 transitions. [2024-11-19 14:23:42,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:42,658 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 182 transitions. [2024-11-19 14:23:42,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 182 transitions. [2024-11-19 14:23:42,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 92. [2024-11-19 14:23:42,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.141304347826087) internal successors, (105), 91 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:42,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 105 transitions. [2024-11-19 14:23:42,664 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92 states and 105 transitions. [2024-11-19 14:23:42,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-11-19 14:23:42,665 INFO L425 stractBuchiCegarLoop]: Abstraction has 92 states and 105 transitions. [2024-11-19 14:23:42,666 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-19 14:23:42,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 105 transitions. [2024-11-19 14:23:42,666 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:42,667 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:42,667 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:42,667 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1] [2024-11-19 14:23:42,667 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:42,668 INFO L745 eck$LassoCheckResult]: Stem: 4369#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4353#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4354#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4370#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4371#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4357#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4358#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4392#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4391#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4390#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4389#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4388#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4387#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4386#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4385#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4384#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4383#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4382#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4381#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4380#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4379#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4376#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4375#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4359#L27-4 main_~i~0#1 := 0; 4360#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4366#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4352#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4363#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4368#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4435#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4434#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4432#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4429#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4428#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4426#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4423#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4422#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4420#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4417#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4416#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4414#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4411#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4410#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4408#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4405#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4404#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4402#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4400#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4399#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4396#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4394#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4393#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4374#L34 [2024-11-19 14:23:42,668 INFO L747 eck$LassoCheckResult]: Loop: 4374#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4377#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4373#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4374#L34 [2024-11-19 14:23:42,668 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:42,668 INFO L85 PathProgramCache]: Analyzing trace with hash -354133123, now seen corresponding path program 18 times [2024-11-19 14:23:42,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:42,669 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278195823] [2024-11-19 14:23:42,669 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:23:42,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:42,743 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2024-11-19 14:23:42,743 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:42,743 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:42,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:42,784 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:42,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:42,788 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 11 times [2024-11-19 14:23:42,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:42,789 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391083822] [2024-11-19 14:23:42,789 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:42,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:42,792 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:23:42,792 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:42,792 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:42,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:42,795 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:42,796 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:42,796 INFO L85 PathProgramCache]: Analyzing trace with hash -1540141607, now seen corresponding path program 19 times [2024-11-19 14:23:42,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:42,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73777883] [2024-11-19 14:23:42,796 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:42,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:42,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:43,263 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 117 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:43,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:43,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73777883] [2024-11-19 14:23:43,264 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [73777883] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:43,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [287623639] [2024-11-19 14:23:43,264 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:43,264 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:43,265 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:43,267 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:43,268 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-11-19 14:23:43,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:43,358 INFO L255 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-11-19 14:23:43,360 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:43,693 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:43,693 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:43,906 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:43,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [287623639] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:43,907 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:43,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 37 [2024-11-19 14:23:43,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202319170] [2024-11-19 14:23:43,907 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:43,949 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:43,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2024-11-19 14:23:43,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=1065, Unknown=0, NotChecked=0, Total=1406 [2024-11-19 14:23:43,950 INFO L87 Difference]: Start difference. First operand 92 states and 105 transitions. cyclomatic complexity: 16 Second operand has 38 states, 37 states have (on average 2.5405405405405403) internal successors, (94), 38 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:44,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:44,365 INFO L93 Difference]: Finished difference Result 296 states and 343 transitions. [2024-11-19 14:23:44,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 296 states and 343 transitions. [2024-11-19 14:23:44,368 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:44,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 296 states to 172 states and 198 transitions. [2024-11-19 14:23:44,369 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149 [2024-11-19 14:23:44,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149 [2024-11-19 14:23:44,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 172 states and 198 transitions. [2024-11-19 14:23:44,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:44,369 INFO L218 hiAutomatonCegarLoop]: Abstraction has 172 states and 198 transitions. [2024-11-19 14:23:44,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states and 198 transitions. [2024-11-19 14:23:44,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 100. [2024-11-19 14:23:44,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.14) internal successors, (114), 99 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:44,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 114 transitions. [2024-11-19 14:23:44,373 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 114 transitions. [2024-11-19 14:23:44,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2024-11-19 14:23:44,374 INFO L425 stractBuchiCegarLoop]: Abstraction has 100 states and 114 transitions. [2024-11-19 14:23:44,375 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-19 14:23:44,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 114 transitions. [2024-11-19 14:23:44,376 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:44,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:44,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:44,376 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1] [2024-11-19 14:23:44,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:44,377 INFO L745 eck$LassoCheckResult]: Stem: 5144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 5128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 5129#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5145#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5146#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5132#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5133#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5169#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5168#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5167#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5166#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5165#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5164#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5163#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5162#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5161#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5160#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5159#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5158#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5157#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5156#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5155#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5154#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5151#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5150#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 5134#L27-4 main_~i~0#1 := 0; 5135#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5141#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5127#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5138#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5143#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5218#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5217#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5215#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5212#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5211#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5209#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5206#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5205#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5203#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5200#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5199#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5197#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5194#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5193#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5191#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5188#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5187#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5185#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5182#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5181#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5179#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5177#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5176#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5173#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5171#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5170#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5149#L34 [2024-11-19 14:23:44,377 INFO L747 eck$LassoCheckResult]: Loop: 5149#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5152#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5148#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5149#L34 [2024-11-19 14:23:44,378 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:44,378 INFO L85 PathProgramCache]: Analyzing trace with hash -726335849, now seen corresponding path program 20 times [2024-11-19 14:23:44,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:44,378 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [959928037] [2024-11-19 14:23:44,378 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:23:44,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:44,430 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:23:44,430 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:44,430 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:44,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:44,490 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:44,491 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:44,491 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 12 times [2024-11-19 14:23:44,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:44,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074064054] [2024-11-19 14:23:44,491 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:23:44,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:44,497 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2024-11-19 14:23:44,497 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:44,497 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:44,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:44,502 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:44,503 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:44,504 INFO L85 PathProgramCache]: Analyzing trace with hash -225993601, now seen corresponding path program 21 times [2024-11-19 14:23:44,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:44,504 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428941099] [2024-11-19 14:23:44,504 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:44,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:44,579 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2024-11-19 14:23:44,579 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:45,218 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 145 proven. 152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:45,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:45,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [428941099] [2024-11-19 14:23:45,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [428941099] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:45,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1467045882] [2024-11-19 14:23:45,219 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:45,219 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:45,219 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:45,221 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:45,222 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-11-19 14:23:45,418 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2024-11-19 14:23:45,419 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:45,420 INFO L255 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjuncts are in the unsatisfiable core [2024-11-19 14:23:45,422 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:45,776 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:45,776 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:46,092 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:46,092 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1467045882] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:46,092 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:46,092 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2024-11-19 14:23:46,092 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1450454088] [2024-11-19 14:23:46,092 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:46,137 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:46,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2024-11-19 14:23:46,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=395, Invalid=1245, Unknown=0, NotChecked=0, Total=1640 [2024-11-19 14:23:46,138 INFO L87 Difference]: Start difference. First operand 100 states and 114 transitions. cyclomatic complexity: 17 Second operand has 41 states, 40 states have (on average 2.55) internal successors, (102), 41 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:46,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:46,598 INFO L93 Difference]: Finished difference Result 322 states and 373 transitions. [2024-11-19 14:23:46,598 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322 states and 373 transitions. [2024-11-19 14:23:46,600 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:46,601 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322 states to 186 states and 214 transitions. [2024-11-19 14:23:46,601 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161 [2024-11-19 14:23:46,601 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161 [2024-11-19 14:23:46,601 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 214 transitions. [2024-11-19 14:23:46,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:46,601 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 214 transitions. [2024-11-19 14:23:46,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 214 transitions. [2024-11-19 14:23:46,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 108. [2024-11-19 14:23:46,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1388888888888888) internal successors, (123), 107 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:46,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 123 transitions. [2024-11-19 14:23:46,606 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 123 transitions. [2024-11-19 14:23:46,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2024-11-19 14:23:46,610 INFO L425 stractBuchiCegarLoop]: Abstraction has 108 states and 123 transitions. [2024-11-19 14:23:46,610 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-19 14:23:46,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 123 transitions. [2024-11-19 14:23:46,611 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:46,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:46,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:46,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1] [2024-11-19 14:23:46,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:46,612 INFO L745 eck$LassoCheckResult]: Stem: 5990#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 5972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 5973#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5988#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5989#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5976#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5977#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6015#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6014#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6013#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6012#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6011#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6010#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6009#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6008#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6007#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6006#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6005#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6004#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6003#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6002#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6001#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6000#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5999#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5998#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5995#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5994#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 5978#L27-4 main_~i~0#1 := 0; 5979#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5985#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5971#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5982#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5987#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6070#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6069#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6067#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6064#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6063#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6061#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6058#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6057#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6055#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6052#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6051#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6049#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6046#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6045#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6043#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6040#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6039#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6037#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6034#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6033#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6031#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6028#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6027#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6025#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6023#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6022#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6019#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6017#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6016#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5993#L34 [2024-11-19 14:23:46,612 INFO L747 eck$LassoCheckResult]: Loop: 5993#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5996#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5992#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5993#L34 [2024-11-19 14:23:46,612 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:46,612 INFO L85 PathProgramCache]: Analyzing trace with hash -2083736959, now seen corresponding path program 22 times [2024-11-19 14:23:46,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:46,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291969619] [2024-11-19 14:23:46,613 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:23:46,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:46,674 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:23:46,675 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:46,675 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:46,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:46,717 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:46,718 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:46,718 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 13 times [2024-11-19 14:23:46,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:46,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388930907] [2024-11-19 14:23:46,719 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:46,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:46,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:46,723 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:46,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:46,727 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:46,727 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:46,727 INFO L85 PathProgramCache]: Analyzing trace with hash -1445369771, now seen corresponding path program 23 times [2024-11-19 14:23:46,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:46,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956849194] [2024-11-19 14:23:46,728 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:46,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:46,773 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2024-11-19 14:23:46,774 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:47,409 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 198 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:47,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:47,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956849194] [2024-11-19 14:23:47,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956849194] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:47,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1291687933] [2024-11-19 14:23:47,410 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:47,410 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:47,410 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:47,412 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:47,413 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-11-19 14:23:47,716 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2024-11-19 14:23:47,716 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:47,720 INFO L255 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 28 conjuncts are in the unsatisfiable core [2024-11-19 14:23:47,721 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:48,587 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:48,587 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:49,090 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:49,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1291687933] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:49,090 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:49,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 55 [2024-11-19 14:23:49,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466146238] [2024-11-19 14:23:49,090 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:49,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:49,135 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2024-11-19 14:23:49,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=525, Invalid=2555, Unknown=0, NotChecked=0, Total=3080 [2024-11-19 14:23:49,136 INFO L87 Difference]: Start difference. First operand 108 states and 123 transitions. cyclomatic complexity: 18 Second operand has 56 states, 55 states have (on average 2.381818181818182) internal successors, (131), 56 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:50,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:50,633 INFO L93 Difference]: Finished difference Result 422 states and 488 transitions. [2024-11-19 14:23:50,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 422 states and 488 transitions. [2024-11-19 14:23:50,636 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:50,637 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 422 states to 200 states and 230 transitions. [2024-11-19 14:23:50,637 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173 [2024-11-19 14:23:50,638 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173 [2024-11-19 14:23:50,638 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200 states and 230 transitions. [2024-11-19 14:23:50,638 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:50,638 INFO L218 hiAutomatonCegarLoop]: Abstraction has 200 states and 230 transitions. [2024-11-19 14:23:50,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states and 230 transitions. [2024-11-19 14:23:50,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 116. [2024-11-19 14:23:50,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.1379310344827587) internal successors, (132), 115 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:50,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 132 transitions. [2024-11-19 14:23:50,641 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 132 transitions. [2024-11-19 14:23:50,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2024-11-19 14:23:50,642 INFO L425 stractBuchiCegarLoop]: Abstraction has 116 states and 132 transitions. [2024-11-19 14:23:50,642 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-19 14:23:50,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 132 transitions. [2024-11-19 14:23:50,644 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:50,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:50,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:50,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1] [2024-11-19 14:23:50,645 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:50,645 INFO L745 eck$LassoCheckResult]: Stem: 7067#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 7051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 7052#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7068#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7069#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7055#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7056#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7096#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7095#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7094#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7093#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7092#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7091#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7090#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7089#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7088#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7087#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7086#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7085#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7084#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7083#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7082#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7081#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7080#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7079#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7078#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7077#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7074#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7073#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 7057#L27-4 main_~i~0#1 := 0; 7058#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7064#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7050#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7061#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7066#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7157#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7156#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7154#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7151#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7150#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7148#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7145#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7144#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7142#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7139#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7138#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7136#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7133#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7132#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7130#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7127#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7126#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7124#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7121#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7120#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7118#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7115#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7114#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7112#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7109#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7108#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7106#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7104#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7103#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7100#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7098#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7097#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7072#L34 [2024-11-19 14:23:50,645 INFO L747 eck$LassoCheckResult]: Loop: 7072#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7075#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7071#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7072#L34 [2024-11-19 14:23:50,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:50,646 INFO L85 PathProgramCache]: Analyzing trace with hash -1447312493, now seen corresponding path program 24 times [2024-11-19 14:23:50,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:50,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352675831] [2024-11-19 14:23:50,646 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:23:50,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:50,748 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2024-11-19 14:23:50,748 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:50,748 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:50,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:50,820 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:50,821 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:50,821 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 14 times [2024-11-19 14:23:50,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:50,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399759715] [2024-11-19 14:23:50,822 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:23:50,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:50,826 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:23:50,826 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:50,826 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:50,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:50,830 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:50,831 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:50,831 INFO L85 PathProgramCache]: Analyzing trace with hash 290252291, now seen corresponding path program 25 times [2024-11-19 14:23:50,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:50,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101049335] [2024-11-19 14:23:50,831 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:50,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:50,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:51,524 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 210 proven. 206 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:51,525 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:51,525 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101049335] [2024-11-19 14:23:51,525 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101049335] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:51,525 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1141097813] [2024-11-19 14:23:51,525 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:51,526 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:51,526 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:51,528 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:51,529 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2024-11-19 14:23:51,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:51,652 INFO L255 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 30 conjuncts are in the unsatisfiable core [2024-11-19 14:23:51,653 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:52,197 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:52,198 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:52,549 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:52,550 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1141097813] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:52,550 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:52,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30] total 46 [2024-11-19 14:23:52,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440370156] [2024-11-19 14:23:52,550 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:52,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:52,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2024-11-19 14:23:52,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=515, Invalid=1647, Unknown=0, NotChecked=0, Total=2162 [2024-11-19 14:23:52,583 INFO L87 Difference]: Start difference. First operand 116 states and 132 transitions. cyclomatic complexity: 19 Second operand has 47 states, 46 states have (on average 2.5652173913043477) internal successors, (118), 47 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:53,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:53,069 INFO L93 Difference]: Finished difference Result 374 states and 433 transitions. [2024-11-19 14:23:53,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 374 states and 433 transitions. [2024-11-19 14:23:53,072 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:53,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 374 states to 214 states and 246 transitions. [2024-11-19 14:23:53,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 185 [2024-11-19 14:23:53,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 185 [2024-11-19 14:23:53,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 214 states and 246 transitions. [2024-11-19 14:23:53,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:53,080 INFO L218 hiAutomatonCegarLoop]: Abstraction has 214 states and 246 transitions. [2024-11-19 14:23:53,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states and 246 transitions. [2024-11-19 14:23:53,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 124. [2024-11-19 14:23:53,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124 states, 124 states have (on average 1.1370967741935485) internal successors, (141), 123 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:53,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 141 transitions. [2024-11-19 14:23:53,086 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124 states and 141 transitions. [2024-11-19 14:23:53,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-11-19 14:23:53,094 INFO L425 stractBuchiCegarLoop]: Abstraction has 124 states and 141 transitions. [2024-11-19 14:23:53,094 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-19 14:23:53,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124 states and 141 transitions. [2024-11-19 14:23:53,095 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:53,095 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:53,095 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:53,096 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 14, 13, 13, 1, 1, 1, 1] [2024-11-19 14:23:53,096 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:53,096 INFO L745 eck$LassoCheckResult]: Stem: 8049#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 8033#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 8034#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8050#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8051#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8037#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8038#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8080#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8079#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8078#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8077#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8076#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8075#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8074#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8073#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8072#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8071#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8070#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8069#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8068#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8067#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8066#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8065#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8064#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8063#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8062#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8061#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8060#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8059#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8056#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8055#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 8039#L27-4 main_~i~0#1 := 0; 8040#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8046#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8032#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8043#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8048#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8147#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8146#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8144#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8141#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8140#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8138#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8135#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8134#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8132#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8129#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8128#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8126#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8123#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8122#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8120#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8117#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8116#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8114#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8111#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8110#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8108#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8105#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8104#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8102#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8099#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8098#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8096#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8093#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8092#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8090#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8088#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8087#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8084#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8082#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8081#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8054#L34 [2024-11-19 14:23:53,101 INFO L747 eck$LassoCheckResult]: Loop: 8054#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8057#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8053#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8054#L34 [2024-11-19 14:23:53,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:53,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1635246469, now seen corresponding path program 26 times [2024-11-19 14:23:53,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:53,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030725635] [2024-11-19 14:23:53,102 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:23:53,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:53,183 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:23:53,184 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:53,184 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:53,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:53,236 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:53,237 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:53,237 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 15 times [2024-11-19 14:23:53,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:53,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684312270] [2024-11-19 14:23:53,238 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:53,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:53,242 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 14:23:53,242 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:53,242 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:53,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:53,246 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:53,246 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:53,247 INFO L85 PathProgramCache]: Analyzing trace with hash 2108533457, now seen corresponding path program 27 times [2024-11-19 14:23:53,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:53,247 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328810942] [2024-11-19 14:23:53,247 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:53,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:53,353 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2024-11-19 14:23:53,354 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:54,034 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 247 proven. 236 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:54,034 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:54,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [328810942] [2024-11-19 14:23:54,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [328810942] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:54,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [314272032] [2024-11-19 14:23:54,034 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:23:54,035 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:54,035 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:54,036 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:54,038 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2024-11-19 14:23:54,391 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2024-11-19 14:23:54,391 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:54,393 INFO L255 TraceCheckSpWp]: Trace formula consists of 335 conjuncts, 32 conjuncts are in the unsatisfiable core [2024-11-19 14:23:54,395 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:54,910 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:54,910 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:55,279 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:55,279 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [314272032] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:55,279 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:55,280 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32] total 49 [2024-11-19 14:23:55,280 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432526445] [2024-11-19 14:23:55,280 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:55,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:55,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2024-11-19 14:23:55,312 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=581, Invalid=1869, Unknown=0, NotChecked=0, Total=2450 [2024-11-19 14:23:55,312 INFO L87 Difference]: Start difference. First operand 124 states and 141 transitions. cyclomatic complexity: 20 Second operand has 50 states, 49 states have (on average 2.5714285714285716) internal successors, (126), 50 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:55,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:55,873 INFO L93 Difference]: Finished difference Result 400 states and 463 transitions. [2024-11-19 14:23:55,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 400 states and 463 transitions. [2024-11-19 14:23:55,876 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:55,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 400 states to 228 states and 262 transitions. [2024-11-19 14:23:55,877 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197 [2024-11-19 14:23:55,877 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 197 [2024-11-19 14:23:55,877 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228 states and 262 transitions. [2024-11-19 14:23:55,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:55,878 INFO L218 hiAutomatonCegarLoop]: Abstraction has 228 states and 262 transitions. [2024-11-19 14:23:55,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states and 262 transitions. [2024-11-19 14:23:55,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 132. [2024-11-19 14:23:55,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 132 states, 132 states have (on average 1.1363636363636365) internal successors, (150), 131 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:55,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 150 transitions. [2024-11-19 14:23:55,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 132 states and 150 transitions. [2024-11-19 14:23:55,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2024-11-19 14:23:55,882 INFO L425 stractBuchiCegarLoop]: Abstraction has 132 states and 150 transitions. [2024-11-19 14:23:55,882 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-19 14:23:55,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 132 states and 150 transitions. [2024-11-19 14:23:55,883 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:55,883 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:55,883 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:55,884 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 15, 14, 14, 1, 1, 1, 1] [2024-11-19 14:23:55,884 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:55,884 INFO L745 eck$LassoCheckResult]: Stem: 9100#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 9084#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 9085#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9101#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9102#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9088#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9089#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9133#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9132#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9131#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9130#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9129#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9128#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9127#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9126#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9125#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9124#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9123#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9122#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9121#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9120#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9119#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9118#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9117#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9116#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9115#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9114#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9113#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9112#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9111#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9110#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9107#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9106#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 9090#L27-4 main_~i~0#1 := 0; 9091#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9097#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9083#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9094#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9099#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9206#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9205#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9203#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9200#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9199#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9197#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9194#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9193#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9191#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9188#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9187#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9185#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9182#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9181#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9179#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9176#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9175#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9173#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9170#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9169#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9167#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9164#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9163#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9161#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9158#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9157#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9155#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9152#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9151#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9149#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9146#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9145#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9143#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9141#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9140#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9137#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9135#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9134#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9105#L34 [2024-11-19 14:23:55,884 INFO L747 eck$LassoCheckResult]: Loop: 9105#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9108#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9104#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9105#L34 [2024-11-19 14:23:55,885 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:55,885 INFO L85 PathProgramCache]: Analyzing trace with hash -436367217, now seen corresponding path program 28 times [2024-11-19 14:23:55,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:55,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367920346] [2024-11-19 14:23:55,885 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:23:55,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:55,949 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:23:55,950 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:55,950 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:55,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:56,000 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:56,000 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:56,000 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 16 times [2024-11-19 14:23:56,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:56,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441110677] [2024-11-19 14:23:56,001 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:23:56,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:56,004 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:23:56,004 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:56,005 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:56,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:56,008 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:56,008 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:56,008 INFO L85 PathProgramCache]: Analyzing trace with hash 1050290055, now seen corresponding path program 29 times [2024-11-19 14:23:56,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:56,008 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486087780] [2024-11-19 14:23:56,009 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:56,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:56,107 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2024-11-19 14:23:56,108 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:56,859 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:56,860 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:56,860 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [486087780] [2024-11-19 14:23:56,860 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [486087780] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:56,860 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [729207754] [2024-11-19 14:23:56,860 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:56,860 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:56,860 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:56,862 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:56,863 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2024-11-19 14:23:57,202 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2024-11-19 14:23:57,202 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:23:57,205 INFO L255 TraceCheckSpWp]: Trace formula consists of 356 conjuncts, 34 conjuncts are in the unsatisfiable core [2024-11-19 14:23:57,207 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:23:57,739 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:57,739 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:23:58,147 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:58,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [729207754] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:23:58,147 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:23:58,147 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34] total 50 [2024-11-19 14:23:58,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115300886] [2024-11-19 14:23:58,148 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:23:58,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:23:58,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2024-11-19 14:23:58,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=611, Invalid=1939, Unknown=0, NotChecked=0, Total=2550 [2024-11-19 14:23:58,191 INFO L87 Difference]: Start difference. First operand 132 states and 150 transitions. cyclomatic complexity: 21 Second operand has 51 states, 50 states have (on average 2.54) internal successors, (127), 51 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:58,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:23:58,781 INFO L93 Difference]: Finished difference Result 426 states and 493 transitions. [2024-11-19 14:23:58,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 426 states and 493 transitions. [2024-11-19 14:23:58,783 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:58,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 426 states to 242 states and 278 transitions. [2024-11-19 14:23:58,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 209 [2024-11-19 14:23:58,785 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 209 [2024-11-19 14:23:58,785 INFO L73 IsDeterministic]: Start isDeterministic. Operand 242 states and 278 transitions. [2024-11-19 14:23:58,786 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:23:58,786 INFO L218 hiAutomatonCegarLoop]: Abstraction has 242 states and 278 transitions. [2024-11-19 14:23:58,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states and 278 transitions. [2024-11-19 14:23:58,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 140. [2024-11-19 14:23:58,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140 states, 140 states have (on average 1.1357142857142857) internal successors, (159), 139 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:23:58,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 159 transitions. [2024-11-19 14:23:58,789 INFO L240 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2024-11-19 14:23:58,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2024-11-19 14:23:58,790 INFO L425 stractBuchiCegarLoop]: Abstraction has 140 states and 159 transitions. [2024-11-19 14:23:58,790 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-19 14:23:58,790 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 140 states and 159 transitions. [2024-11-19 14:23:58,791 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:23:58,791 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:23:58,791 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:23:58,795 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 16, 15, 15, 1, 1, 1, 1] [2024-11-19 14:23:58,795 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:23:58,795 INFO L745 eck$LassoCheckResult]: Stem: 10220#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 10204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 10205#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10221#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10222#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10208#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10209#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10255#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10254#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10253#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10252#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10251#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10250#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10249#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10248#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10247#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10246#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10245#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10244#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10243#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10242#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10241#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10240#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10239#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10238#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10237#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10236#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10235#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10234#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10233#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10232#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10231#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10230#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10227#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10226#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 10210#L27-4 main_~i~0#1 := 0; 10211#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10217#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10203#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10214#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10219#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10334#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10333#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10331#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10328#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10327#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10325#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10322#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10321#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10319#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10316#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10315#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10313#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10310#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10309#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10307#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10304#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10303#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10301#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10298#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10297#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10295#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10292#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10291#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10289#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10286#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10285#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10283#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10280#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10279#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10277#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10274#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10273#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10271#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10268#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10267#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10265#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10263#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10262#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10259#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10257#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10256#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10225#L34 [2024-11-19 14:23:58,799 INFO L747 eck$LassoCheckResult]: Loop: 10225#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10228#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10224#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10225#L34 [2024-11-19 14:23:58,800 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:58,800 INFO L85 PathProgramCache]: Analyzing trace with hash -1180030839, now seen corresponding path program 30 times [2024-11-19 14:23:58,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:58,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738177698] [2024-11-19 14:23:58,801 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:23:58,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:58,967 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 17 check-sat command(s) [2024-11-19 14:23:58,970 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:58,970 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:59,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:59,039 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:59,040 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:59,040 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 17 times [2024-11-19 14:23:59,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:59,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399716666] [2024-11-19 14:23:59,040 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:23:59,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:59,043 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:23:59,044 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:23:59,044 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:23:59,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:23:59,047 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:23:59,047 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:23:59,047 INFO L85 PathProgramCache]: Analyzing trace with hash 8639821, now seen corresponding path program 31 times [2024-11-19 14:23:59,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:23:59,048 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025365814] [2024-11-19 14:23:59,048 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:59,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:23:59,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:23:59,973 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 330 proven. 302 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:23:59,973 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:23:59,973 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1025365814] [2024-11-19 14:23:59,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1025365814] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:23:59,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [915673616] [2024-11-19 14:23:59,974 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:23:59,974 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:23:59,974 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:23:59,976 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:23:59,977 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-11-19 14:24:00,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:24:00,135 INFO L255 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 36 conjuncts are in the unsatisfiable core [2024-11-19 14:24:00,137 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:24:00,808 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:00,808 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:24:01,222 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:01,222 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [915673616] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:24:01,223 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:24:01,223 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36] total 55 [2024-11-19 14:24:01,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655512213] [2024-11-19 14:24:01,223 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:24:01,259 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:24:01,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2024-11-19 14:24:01,260 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=725, Invalid=2355, Unknown=0, NotChecked=0, Total=3080 [2024-11-19 14:24:01,260 INFO L87 Difference]: Start difference. First operand 140 states and 159 transitions. cyclomatic complexity: 22 Second operand has 56 states, 55 states have (on average 2.581818181818182) internal successors, (142), 56 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:01,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:24:01,873 INFO L93 Difference]: Finished difference Result 452 states and 523 transitions. [2024-11-19 14:24:01,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 452 states and 523 transitions. [2024-11-19 14:24:01,876 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:01,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 452 states to 256 states and 294 transitions. [2024-11-19 14:24:01,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2024-11-19 14:24:01,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2024-11-19 14:24:01,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 256 states and 294 transitions. [2024-11-19 14:24:01,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:24:01,879 INFO L218 hiAutomatonCegarLoop]: Abstraction has 256 states and 294 transitions. [2024-11-19 14:24:01,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states and 294 transitions. [2024-11-19 14:24:01,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 148. [2024-11-19 14:24:01,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148 states, 148 states have (on average 1.135135135135135) internal successors, (168), 147 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:01,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 168 transitions. [2024-11-19 14:24:01,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 148 states and 168 transitions. [2024-11-19 14:24:01,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-11-19 14:24:01,882 INFO L425 stractBuchiCegarLoop]: Abstraction has 148 states and 168 transitions. [2024-11-19 14:24:01,883 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-19 14:24:01,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 148 states and 168 transitions. [2024-11-19 14:24:01,883 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:01,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:24:01,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:24:01,884 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 17, 16, 16, 1, 1, 1, 1] [2024-11-19 14:24:01,884 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:24:01,885 INFO L745 eck$LassoCheckResult]: Stem: 11409#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 11393#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 11394#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11410#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11411#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11397#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11398#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11446#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11445#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11444#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11443#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11442#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11441#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11440#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11439#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11438#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11437#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11436#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11435#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11434#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11433#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11432#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11431#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11430#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11429#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11428#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11427#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11426#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11425#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11424#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11423#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11422#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11421#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11420#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11419#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11416#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11415#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 11399#L27-4 main_~i~0#1 := 0; 11400#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11406#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11392#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11403#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11408#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11531#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11530#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11528#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11525#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11524#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11522#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11519#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11518#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11516#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11513#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11512#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11510#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11507#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11506#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11504#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11501#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11500#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11498#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11495#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11494#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11492#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11489#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11488#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11486#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11483#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11482#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11480#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11477#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11476#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11474#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11471#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11470#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11468#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11465#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11464#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11462#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11459#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11458#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11456#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11454#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11453#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11450#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11448#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11447#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11414#L34 [2024-11-19 14:24:01,885 INFO L747 eck$LassoCheckResult]: Loop: 11414#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11417#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11413#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11414#L34 [2024-11-19 14:24:01,885 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:01,886 INFO L85 PathProgramCache]: Analyzing trace with hash -1481235061, now seen corresponding path program 32 times [2024-11-19 14:24:01,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:01,886 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240854645] [2024-11-19 14:24:01,886 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:24:01,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:01,955 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:24:01,955 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:01,955 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:02,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:02,026 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:02,027 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:02,027 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 18 times [2024-11-19 14:24:02,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:02,027 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609166278] [2024-11-19 14:24:02,027 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:24:02,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:02,031 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2024-11-19 14:24:02,031 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:02,031 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:02,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:02,035 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:02,035 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:02,035 INFO L85 PathProgramCache]: Analyzing trace with hash -979656437, now seen corresponding path program 33 times [2024-11-19 14:24:02,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:02,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411207484] [2024-11-19 14:24:02,035 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:24:02,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:02,212 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2024-11-19 14:24:02,212 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:24:03,084 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 376 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:03,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:24:03,084 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411207484] [2024-11-19 14:24:03,084 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1411207484] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:24:03,084 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [209925790] [2024-11-19 14:24:03,084 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:24:03,084 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:24:03,085 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:24:03,086 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:24:03,087 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-11-19 14:24:03,724 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2024-11-19 14:24:03,724 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:24:03,728 INFO L255 TraceCheckSpWp]: Trace formula consists of 398 conjuncts, 38 conjuncts are in the unsatisfiable core [2024-11-19 14:24:03,729 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:24:04,364 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:04,364 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:24:04,844 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:04,845 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [209925790] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:24:04,845 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:24:04,845 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38] total 58 [2024-11-19 14:24:04,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1604001976] [2024-11-19 14:24:04,845 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:24:04,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:24:04,890 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2024-11-19 14:24:04,890 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=803, Invalid=2619, Unknown=0, NotChecked=0, Total=3422 [2024-11-19 14:24:04,891 INFO L87 Difference]: Start difference. First operand 148 states and 168 transitions. cyclomatic complexity: 23 Second operand has 59 states, 58 states have (on average 2.586206896551724) internal successors, (150), 59 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:05,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:24:05,540 INFO L93 Difference]: Finished difference Result 478 states and 553 transitions. [2024-11-19 14:24:05,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 553 transitions. [2024-11-19 14:24:05,543 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:05,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 270 states and 310 transitions. [2024-11-19 14:24:05,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 233 [2024-11-19 14:24:05,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 233 [2024-11-19 14:24:05,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 310 transitions. [2024-11-19 14:24:05,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:24:05,546 INFO L218 hiAutomatonCegarLoop]: Abstraction has 270 states and 310 transitions. [2024-11-19 14:24:05,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 310 transitions. [2024-11-19 14:24:05,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 156. [2024-11-19 14:24:05,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 156 states, 156 states have (on average 1.1346153846153846) internal successors, (177), 155 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:05,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 177 transitions. [2024-11-19 14:24:05,549 INFO L240 hiAutomatonCegarLoop]: Abstraction has 156 states and 177 transitions. [2024-11-19 14:24:05,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2024-11-19 14:24:05,550 INFO L425 stractBuchiCegarLoop]: Abstraction has 156 states and 177 transitions. [2024-11-19 14:24:05,550 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-19 14:24:05,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156 states and 177 transitions. [2024-11-19 14:24:05,551 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:05,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:24:05,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:24:05,552 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [18, 18, 18, 17, 17, 1, 1, 1, 1] [2024-11-19 14:24:05,552 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:24:05,552 INFO L745 eck$LassoCheckResult]: Stem: 12667#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 12651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 12652#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12668#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12669#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12655#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12656#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12706#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12705#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12704#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12703#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12702#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12701#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12700#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12699#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12698#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12697#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12696#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12695#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12694#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12693#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12692#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12691#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12690#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12689#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12688#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12687#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12686#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12685#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12684#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12683#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12682#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12681#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12680#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12679#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12678#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12677#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12674#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12673#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 12657#L27-4 main_~i~0#1 := 0; 12658#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12664#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12650#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12661#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12666#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12797#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12796#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12794#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12791#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12790#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12788#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12785#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12784#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12782#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12779#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12778#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12776#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12773#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12772#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12770#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12767#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12766#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12764#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12761#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12760#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12758#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12755#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12754#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12752#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12749#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12748#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12746#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12743#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12742#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12740#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12737#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12736#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12734#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12731#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12730#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12728#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12725#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12724#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12722#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12719#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12718#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12716#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12714#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12713#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12710#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12708#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12707#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12672#L34 [2024-11-19 14:24:05,553 INFO L747 eck$LassoCheckResult]: Loop: 12672#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12675#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12671#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12672#L34 [2024-11-19 14:24:05,553 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:05,553 INFO L85 PathProgramCache]: Analyzing trace with hash -1155020915, now seen corresponding path program 34 times [2024-11-19 14:24:05,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:05,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106642369] [2024-11-19 14:24:05,554 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:24:05,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:05,658 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:24:05,658 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:05,658 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:05,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:05,745 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:05,745 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:05,745 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 19 times [2024-11-19 14:24:05,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:05,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708181575] [2024-11-19 14:24:05,746 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:24:05,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:05,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:05,751 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:05,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:05,757 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:05,757 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:05,758 INFO L85 PathProgramCache]: Analyzing trace with hash 2049943497, now seen corresponding path program 35 times [2024-11-19 14:24:05,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:05,758 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [407394641] [2024-11-19 14:24:05,758 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:24:05,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:05,898 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2024-11-19 14:24:05,898 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:24:06,929 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 459 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:06,930 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:24:06,930 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [407394641] [2024-11-19 14:24:06,930 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [407394641] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:24:06,930 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [405008474] [2024-11-19 14:24:06,930 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:24:06,930 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:24:06,930 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:24:06,931 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:24:06,932 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2024-11-19 14:24:07,522 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2024-11-19 14:24:07,522 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:24:07,526 INFO L255 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 40 conjuncts are in the unsatisfiable core [2024-11-19 14:24:07,527 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:24:08,770 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 477 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:08,770 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:24:09,552 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 477 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:09,552 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [405008474] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:24:09,552 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:24:09,553 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40] total 79 [2024-11-19 14:24:09,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699243305] [2024-11-19 14:24:09,553 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:24:09,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:24:09,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2024-11-19 14:24:09,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1050, Invalid=5270, Unknown=0, NotChecked=0, Total=6320 [2024-11-19 14:24:09,585 INFO L87 Difference]: Start difference. First operand 156 states and 177 transitions. cyclomatic complexity: 24 Second operand has 80 states, 79 states have (on average 2.4177215189873418) internal successors, (191), 80 states have internal predecessors, (191), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:11,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:24:11,703 INFO L93 Difference]: Finished difference Result 614 states and 710 transitions. [2024-11-19 14:24:11,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 614 states and 710 transitions. [2024-11-19 14:24:11,706 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:11,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 614 states to 284 states and 326 transitions. [2024-11-19 14:24:11,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245 [2024-11-19 14:24:11,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245 [2024-11-19 14:24:11,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 326 transitions. [2024-11-19 14:24:11,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:24:11,709 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284 states and 326 transitions. [2024-11-19 14:24:11,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 326 transitions. [2024-11-19 14:24:11,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 164. [2024-11-19 14:24:11,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 164 states, 164 states have (on average 1.1341463414634145) internal successors, (186), 163 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:11,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 186 transitions. [2024-11-19 14:24:11,712 INFO L240 hiAutomatonCegarLoop]: Abstraction has 164 states and 186 transitions. [2024-11-19 14:24:11,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2024-11-19 14:24:11,713 INFO L425 stractBuchiCegarLoop]: Abstraction has 164 states and 186 transitions. [2024-11-19 14:24:11,713 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-19 14:24:11,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 164 states and 186 transitions. [2024-11-19 14:24:11,714 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:11,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:24:11,714 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:24:11,715 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [19, 19, 19, 18, 18, 1, 1, 1, 1] [2024-11-19 14:24:11,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:24:11,715 INFO L745 eck$LassoCheckResult]: Stem: 14238#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 14222#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 14223#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14239#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14240#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14226#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14227#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14279#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14278#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14277#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14276#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14275#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14274#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14273#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14272#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14271#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14270#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14269#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14268#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14267#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14266#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14265#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14264#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14263#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14262#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14261#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14260#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14259#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14258#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14257#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14256#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14255#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14254#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14253#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14252#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14251#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14250#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14249#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14248#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14245#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14244#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 14228#L27-4 main_~i~0#1 := 0; 14229#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14235#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14221#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14232#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14237#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14376#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14375#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14373#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14370#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14369#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14367#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14364#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14363#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14361#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14358#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14357#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14355#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14352#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14351#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14349#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14346#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14345#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14343#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14340#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14339#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14337#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14334#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14333#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14331#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14328#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14327#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14325#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14322#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14321#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14319#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14316#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14315#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14313#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14310#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14309#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14307#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14304#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14303#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14301#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14298#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14297#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14295#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14292#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14291#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14289#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14287#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14286#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14283#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14281#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14280#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14243#L34 [2024-11-19 14:24:11,716 INFO L747 eck$LassoCheckResult]: Loop: 14243#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14246#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14242#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14243#L34 [2024-11-19 14:24:11,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:11,716 INFO L85 PathProgramCache]: Analyzing trace with hash -769572217, now seen corresponding path program 36 times [2024-11-19 14:24:11,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:11,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863700691] [2024-11-19 14:24:11,717 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:24:11,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:11,892 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2024-11-19 14:24:11,892 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:11,892 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:11,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:11,981 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:11,982 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:11,982 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 20 times [2024-11-19 14:24:11,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:11,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922910336] [2024-11-19 14:24:11,982 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:24:11,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:11,986 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:24:11,987 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:11,987 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:11,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:11,990 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:11,990 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:11,990 INFO L85 PathProgramCache]: Analyzing trace with hash 209556111, now seen corresponding path program 37 times [2024-11-19 14:24:11,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:11,991 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41448309] [2024-11-19 14:24:11,991 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:24:11,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:12,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:24:13,136 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 477 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:13,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:24:13,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [41448309] [2024-11-19 14:24:13,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [41448309] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:24:13,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [939124535] [2024-11-19 14:24:13,137 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:24:13,137 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:24:13,137 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:24:13,138 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:24:13,139 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2024-11-19 14:24:13,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:24:13,294 INFO L255 TraceCheckSpWp]: Trace formula consists of 440 conjuncts, 42 conjuncts are in the unsatisfiable core [2024-11-19 14:24:13,296 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:24:14,007 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 532 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:14,008 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:24:14,618 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 532 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:14,618 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [939124535] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:24:14,618 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:24:14,619 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42] total 64 [2024-11-19 14:24:14,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527599572] [2024-11-19 14:24:14,619 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:24:14,657 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:24:14,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2024-11-19 14:24:14,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=971, Invalid=3189, Unknown=0, NotChecked=0, Total=4160 [2024-11-19 14:24:14,659 INFO L87 Difference]: Start difference. First operand 164 states and 186 transitions. cyclomatic complexity: 25 Second operand has 65 states, 64 states have (on average 2.59375) internal successors, (166), 65 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:15,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:24:15,352 INFO L93 Difference]: Finished difference Result 530 states and 613 transitions. [2024-11-19 14:24:15,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 530 states and 613 transitions. [2024-11-19 14:24:15,354 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:15,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 530 states to 298 states and 342 transitions. [2024-11-19 14:24:15,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 257 [2024-11-19 14:24:15,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 257 [2024-11-19 14:24:15,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 298 states and 342 transitions. [2024-11-19 14:24:15,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:24:15,356 INFO L218 hiAutomatonCegarLoop]: Abstraction has 298 states and 342 transitions. [2024-11-19 14:24:15,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states and 342 transitions. [2024-11-19 14:24:15,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 172. [2024-11-19 14:24:15,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 172 states, 172 states have (on average 1.1337209302325582) internal successors, (195), 171 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:15,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 195 transitions. [2024-11-19 14:24:15,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 172 states and 195 transitions. [2024-11-19 14:24:15,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2024-11-19 14:24:15,361 INFO L425 stractBuchiCegarLoop]: Abstraction has 172 states and 195 transitions. [2024-11-19 14:24:15,361 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-19 14:24:15,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 172 states and 195 transitions. [2024-11-19 14:24:15,362 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:15,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:24:15,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:24:15,363 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [20, 20, 20, 19, 19, 1, 1, 1, 1] [2024-11-19 14:24:15,363 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:24:15,363 INFO L745 eck$LassoCheckResult]: Stem: 15634#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 15618#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 15619#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15635#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15636#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15622#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15623#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15677#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15676#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15675#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15674#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15673#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15672#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15671#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15670#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15669#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15668#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15667#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15666#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15665#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15664#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15663#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15662#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15661#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15660#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15659#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15658#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15657#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15656#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15655#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15654#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15653#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15652#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15651#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15650#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15649#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15648#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15647#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15646#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15645#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15644#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15641#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15640#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 15624#L27-4 main_~i~0#1 := 0; 15625#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15631#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15617#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15628#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15633#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15780#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15779#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15777#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15774#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15773#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15771#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15768#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15767#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15765#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15762#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15761#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15759#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15756#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15755#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15753#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15750#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15749#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15747#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15744#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15743#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15741#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15738#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15737#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15735#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15732#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15731#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15729#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15726#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15725#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15723#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15720#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15719#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15717#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15714#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15713#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15711#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15708#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15707#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15705#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15702#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15701#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15699#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15696#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15695#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15693#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15690#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15689#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15687#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15685#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15684#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15681#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15679#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15678#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15639#L34 [2024-11-19 14:24:15,363 INFO L747 eck$LassoCheckResult]: Loop: 15639#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15642#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15638#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15639#L34 [2024-11-19 14:24:15,363 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:15,364 INFO L85 PathProgramCache]: Analyzing trace with hash 297074321, now seen corresponding path program 38 times [2024-11-19 14:24:15,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:15,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131626501] [2024-11-19 14:24:15,364 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:24:15,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:15,442 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:24:15,442 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:15,443 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:15,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:15,538 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:15,539 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:15,539 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 21 times [2024-11-19 14:24:15,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:15,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1365235825] [2024-11-19 14:24:15,540 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:24:15,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:15,543 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 14:24:15,543 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:15,543 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:15,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:15,547 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:15,547 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:15,547 INFO L85 PathProgramCache]: Analyzing trace with hash -1786453435, now seen corresponding path program 39 times [2024-11-19 14:24:15,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:15,548 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339975001] [2024-11-19 14:24:15,548 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:24:15,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:15,701 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2024-11-19 14:24:15,702 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:24:16,977 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 532 proven. 458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:16,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:24:16,978 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339975001] [2024-11-19 14:24:16,978 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339975001] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:24:16,978 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1373421515] [2024-11-19 14:24:16,978 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:24:16,978 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:24:16,978 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:24:16,980 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:24:16,982 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2024-11-19 14:24:18,212 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2024-11-19 14:24:18,213 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:24:18,217 INFO L255 TraceCheckSpWp]: Trace formula consists of 461 conjuncts, 44 conjuncts are in the unsatisfiable core [2024-11-19 14:24:18,219 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:24:19,042 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 590 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:19,042 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:24:19,745 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 590 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:19,746 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1373421515] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:24:19,746 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:24:19,746 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44] total 67 [2024-11-19 14:24:19,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591974541] [2024-11-19 14:24:19,746 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:24:19,784 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:24:19,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2024-11-19 14:24:19,786 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1061, Invalid=3495, Unknown=0, NotChecked=0, Total=4556 [2024-11-19 14:24:19,786 INFO L87 Difference]: Start difference. First operand 172 states and 195 transitions. cyclomatic complexity: 26 Second operand has 68 states, 67 states have (on average 2.5970149253731343) internal successors, (174), 68 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:20,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:24:20,710 INFO L93 Difference]: Finished difference Result 556 states and 643 transitions. [2024-11-19 14:24:20,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 556 states and 643 transitions. [2024-11-19 14:24:20,712 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:20,714 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 556 states to 312 states and 358 transitions. [2024-11-19 14:24:20,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 269 [2024-11-19 14:24:20,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 269 [2024-11-19 14:24:20,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 358 transitions. [2024-11-19 14:24:20,715 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:24:20,715 INFO L218 hiAutomatonCegarLoop]: Abstraction has 312 states and 358 transitions. [2024-11-19 14:24:20,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 358 transitions. [2024-11-19 14:24:20,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 180. [2024-11-19 14:24:20,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 180 states, 180 states have (on average 1.1333333333333333) internal successors, (204), 179 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:20,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 204 transitions. [2024-11-19 14:24:20,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 180 states and 204 transitions. [2024-11-19 14:24:20,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2024-11-19 14:24:20,719 INFO L425 stractBuchiCegarLoop]: Abstraction has 180 states and 204 transitions. [2024-11-19 14:24:20,719 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-19 14:24:20,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 180 states and 204 transitions. [2024-11-19 14:24:20,720 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:20,720 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:24:20,720 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:24:20,721 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [21, 21, 21, 20, 20, 1, 1, 1, 1] [2024-11-19 14:24:20,721 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:24:20,721 INFO L745 eck$LassoCheckResult]: Stem: 17099#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 17083#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 17084#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17100#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17101#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17087#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17088#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17144#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17143#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17142#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17141#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17140#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17139#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17138#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17137#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17136#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17135#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17134#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17133#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17132#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17131#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17130#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17129#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17128#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17127#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17126#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17125#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17124#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17123#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17122#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17121#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17120#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17119#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17118#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17117#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17116#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17115#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17114#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17113#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17112#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17111#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17110#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17109#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17106#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17105#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 17089#L27-4 main_~i~0#1 := 0; 17090#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17096#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17082#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17093#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17098#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17253#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17252#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17250#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17247#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17246#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17244#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17241#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17240#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17238#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17235#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17234#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17232#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17229#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17228#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17226#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17223#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17222#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17220#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17217#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17216#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17214#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17211#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17210#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17208#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17205#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17204#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17202#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17199#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17198#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17196#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17193#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17192#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17190#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17187#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17186#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17184#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17181#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17180#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17178#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17175#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17174#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17172#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17169#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17168#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17166#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17163#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17162#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17160#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17157#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17156#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17154#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17152#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17151#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17148#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17146#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17145#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17104#L34 [2024-11-19 14:24:20,722 INFO L747 eck$LassoCheckResult]: Loop: 17104#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17107#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17103#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17104#L34 [2024-11-19 14:24:20,722 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:20,722 INFO L85 PathProgramCache]: Analyzing trace with hash -1988450429, now seen corresponding path program 40 times [2024-11-19 14:24:20,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:20,722 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858707428] [2024-11-19 14:24:20,723 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:24:20,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:20,835 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:24:20,836 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:20,836 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:20,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:20,924 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:20,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:20,925 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 22 times [2024-11-19 14:24:20,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:20,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717840344] [2024-11-19 14:24:20,925 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:24:20,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:20,929 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:24:20,929 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:20,929 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:20,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:20,933 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:20,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:20,934 INFO L85 PathProgramCache]: Analyzing trace with hash -1737737197, now seen corresponding path program 41 times [2024-11-19 14:24:20,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:20,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898472890] [2024-11-19 14:24:20,934 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:24:20,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:21,015 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2024-11-19 14:24:21,015 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:24:22,194 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 651 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:22,195 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:24:22,195 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898472890] [2024-11-19 14:24:22,195 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1898472890] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:24:22,195 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [572446227] [2024-11-19 14:24:22,195 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:24:22,195 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:24:22,195 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:24:22,196 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:24:22,198 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2024-11-19 14:24:23,185 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2024-11-19 14:24:23,185 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:24:23,190 INFO L255 TraceCheckSpWp]: Trace formula consists of 482 conjuncts, 46 conjuncts are in the unsatisfiable core [2024-11-19 14:24:23,192 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:24:24,040 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 651 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:24,040 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:24:24,681 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 651 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:24,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [572446227] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:24:24,681 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:24:24,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46] total 68 [2024-11-19 14:24:24,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915079536] [2024-11-19 14:24:24,682 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:24:24,713 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:24:24,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2024-11-19 14:24:24,714 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1103, Invalid=3589, Unknown=0, NotChecked=0, Total=4692 [2024-11-19 14:24:24,715 INFO L87 Difference]: Start difference. First operand 180 states and 204 transitions. cyclomatic complexity: 27 Second operand has 69 states, 68 states have (on average 2.573529411764706) internal successors, (175), 69 states have internal predecessors, (175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:25,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:24:25,549 INFO L93 Difference]: Finished difference Result 582 states and 673 transitions. [2024-11-19 14:24:25,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 582 states and 673 transitions. [2024-11-19 14:24:25,552 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:25,553 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 582 states to 326 states and 374 transitions. [2024-11-19 14:24:25,553 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2024-11-19 14:24:25,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2024-11-19 14:24:25,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 326 states and 374 transitions. [2024-11-19 14:24:25,554 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:24:25,554 INFO L218 hiAutomatonCegarLoop]: Abstraction has 326 states and 374 transitions. [2024-11-19 14:24:25,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326 states and 374 transitions. [2024-11-19 14:24:25,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326 to 188. [2024-11-19 14:24:25,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188 states, 188 states have (on average 1.1329787234042554) internal successors, (213), 187 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:25,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 213 transitions. [2024-11-19 14:24:25,558 INFO L240 hiAutomatonCegarLoop]: Abstraction has 188 states and 213 transitions. [2024-11-19 14:24:25,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2024-11-19 14:24:25,559 INFO L425 stractBuchiCegarLoop]: Abstraction has 188 states and 213 transitions. [2024-11-19 14:24:25,559 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-19 14:24:25,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 188 states and 213 transitions. [2024-11-19 14:24:25,560 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:25,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:24:25,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:24:25,561 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 22, 21, 21, 1, 1, 1, 1] [2024-11-19 14:24:25,561 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:24:25,561 INFO L745 eck$LassoCheckResult]: Stem: 18633#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 18617#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 18618#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18634#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18635#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18621#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18622#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18680#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18679#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18678#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18677#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18676#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18675#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18674#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18673#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18672#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18671#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18670#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18669#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18668#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18667#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18666#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18665#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18664#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18663#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18662#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18661#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18660#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18659#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18658#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18657#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18656#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18655#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18654#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18653#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18652#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18651#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18650#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18649#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18648#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18647#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18646#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18645#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18644#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18643#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18640#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18639#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 18623#L27-4 main_~i~0#1 := 0; 18624#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18630#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18616#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18627#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18632#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18795#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18794#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18792#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18789#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18788#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18786#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18783#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18782#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18780#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18777#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18776#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18774#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18771#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18770#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18768#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18765#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18764#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18762#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18759#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18758#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18756#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18753#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18752#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18750#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18747#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18746#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18744#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18741#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18740#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18738#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18735#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18734#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18732#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18729#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18728#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18726#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18723#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18722#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18720#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18717#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18716#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18714#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18711#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18710#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18708#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18705#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18704#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18702#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18699#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18698#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18696#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18693#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18692#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18690#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18688#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18687#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18684#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18682#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18681#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18638#L34 [2024-11-19 14:24:25,561 INFO L747 eck$LassoCheckResult]: Loop: 18638#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18641#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18637#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18638#L34 [2024-11-19 14:24:25,561 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:25,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1779830165, now seen corresponding path program 42 times [2024-11-19 14:24:25,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:25,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423899958] [2024-11-19 14:24:25,562 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:24:25,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:25,863 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 23 check-sat command(s) [2024-11-19 14:24:25,864 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:25,864 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:25,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:25,954 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:25,954 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:25,954 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 23 times [2024-11-19 14:24:25,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:25,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798395348] [2024-11-19 14:24:25,955 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:24:25,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:25,958 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:24:25,959 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:25,959 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:25,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:25,962 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:25,964 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:25,964 INFO L85 PathProgramCache]: Analyzing trace with hash 1549223105, now seen corresponding path program 43 times [2024-11-19 14:24:25,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:25,964 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510120493] [2024-11-19 14:24:25,964 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:24:25,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:25,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:24:27,380 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 651 proven. 548 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:27,381 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:24:27,381 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510120493] [2024-11-19 14:24:27,381 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [510120493] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:24:27,381 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [704485558] [2024-11-19 14:24:27,381 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:24:27,381 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:24:27,381 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:24:27,383 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:24:27,384 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2024-11-19 14:24:27,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:24:27,586 INFO L255 TraceCheckSpWp]: Trace formula consists of 503 conjuncts, 48 conjuncts are in the unsatisfiable core [2024-11-19 14:24:27,589 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:24:28,517 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 715 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:28,517 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:24:29,298 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 715 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:29,299 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [704485558] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:24:29,299 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:24:29,299 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 73 [2024-11-19 14:24:29,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728066983] [2024-11-19 14:24:29,299 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:24:29,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:24:29,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2024-11-19 14:24:29,337 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1253, Invalid=4149, Unknown=0, NotChecked=0, Total=5402 [2024-11-19 14:24:29,337 INFO L87 Difference]: Start difference. First operand 188 states and 213 transitions. cyclomatic complexity: 28 Second operand has 74 states, 73 states have (on average 2.6027397260273974) internal successors, (190), 74 states have internal predecessors, (190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:30,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:24:30,302 INFO L93 Difference]: Finished difference Result 608 states and 703 transitions. [2024-11-19 14:24:30,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 608 states and 703 transitions. [2024-11-19 14:24:30,304 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:30,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 608 states to 340 states and 390 transitions. [2024-11-19 14:24:30,306 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 293 [2024-11-19 14:24:30,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 293 [2024-11-19 14:24:30,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340 states and 390 transitions. [2024-11-19 14:24:30,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:24:30,307 INFO L218 hiAutomatonCegarLoop]: Abstraction has 340 states and 390 transitions. [2024-11-19 14:24:30,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states and 390 transitions. [2024-11-19 14:24:30,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 196. [2024-11-19 14:24:30,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.1326530612244898) internal successors, (222), 195 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:30,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 222 transitions. [2024-11-19 14:24:30,311 INFO L240 hiAutomatonCegarLoop]: Abstraction has 196 states and 222 transitions. [2024-11-19 14:24:30,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-11-19 14:24:30,311 INFO L425 stractBuchiCegarLoop]: Abstraction has 196 states and 222 transitions. [2024-11-19 14:24:30,311 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-19 14:24:30,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 222 transitions. [2024-11-19 14:24:30,312 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:30,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:24:30,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:24:30,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 23, 23, 22, 22, 1, 1, 1, 1] [2024-11-19 14:24:30,313 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:24:30,313 INFO L745 eck$LassoCheckResult]: Stem: 20236#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 20220#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 20221#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20237#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20238#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20224#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20225#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20285#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20284#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20283#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20282#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20281#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20280#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20279#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20278#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20277#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20276#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20275#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20274#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20273#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20272#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20271#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20270#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20269#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20268#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20267#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20266#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20265#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20264#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20263#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20262#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20261#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20260#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20259#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20258#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20257#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20256#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20255#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20254#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20253#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20252#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20251#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20250#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20249#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20248#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20247#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20246#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 20243#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 20242#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 20226#L27-4 main_~i~0#1 := 0; 20227#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20233#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20219#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20230#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20235#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20406#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20405#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20403#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20400#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20399#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20397#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20394#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20393#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20391#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20388#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20387#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20385#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20382#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20381#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20379#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20376#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20375#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20373#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20370#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20369#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20367#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20364#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20363#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20361#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20358#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20357#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20355#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20352#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20351#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20349#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20346#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20345#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20343#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20340#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20339#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20337#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20334#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20333#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20331#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20328#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20327#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20325#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20322#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20321#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20319#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20316#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20315#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20313#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20310#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20309#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20307#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20304#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20303#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20301#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20298#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20297#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20295#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20293#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20292#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20289#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20287#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20286#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20241#L34 [2024-11-19 14:24:30,314 INFO L747 eck$LassoCheckResult]: Loop: 20241#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 20244#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 20240#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 20241#L34 [2024-11-19 14:24:30,314 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:30,314 INFO L85 PathProgramCache]: Analyzing trace with hash -1359080321, now seen corresponding path program 44 times [2024-11-19 14:24:30,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:30,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1373783350] [2024-11-19 14:24:30,315 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:24:30,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:30,407 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:24:30,408 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:30,408 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:30,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:30,516 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:30,517 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:30,517 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 24 times [2024-11-19 14:24:30,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:30,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412787833] [2024-11-19 14:24:30,517 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:24:30,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:30,521 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2024-11-19 14:24:30,521 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:30,522 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:30,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:30,526 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:30,526 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:30,526 INFO L85 PathProgramCache]: Analyzing trace with hash 294903191, now seen corresponding path program 45 times [2024-11-19 14:24:30,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:30,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036487862] [2024-11-19 14:24:30,527 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:24:30,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:30,686 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2024-11-19 14:24:30,687 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:24:32,135 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 715 proven. 596 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:32,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:24:32,135 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036487862] [2024-11-19 14:24:32,135 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036487862] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:24:32,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1407635923] [2024-11-19 14:24:32,136 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:24:32,136 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:24:32,136 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:24:32,138 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:24:32,139 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2024-11-19 14:24:34,582 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2024-11-19 14:24:34,583 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:24:34,588 INFO L255 TraceCheckSpWp]: Trace formula consists of 524 conjuncts, 50 conjuncts are in the unsatisfiable core [2024-11-19 14:24:34,590 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:24:35,551 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 782 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:35,551 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:24:36,316 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 782 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:24:36,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1407635923] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:24:36,317 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:24:36,317 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50] total 76 [2024-11-19 14:24:36,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264106493] [2024-11-19 14:24:36,317 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:24:36,350 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:24:36,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2024-11-19 14:24:36,352 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1355, Invalid=4497, Unknown=0, NotChecked=0, Total=5852 [2024-11-19 14:24:36,352 INFO L87 Difference]: Start difference. First operand 196 states and 222 transitions. cyclomatic complexity: 29 Second operand has 77 states, 76 states have (on average 2.6052631578947367) internal successors, (198), 77 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:37,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:24:37,423 INFO L93 Difference]: Finished difference Result 634 states and 733 transitions. [2024-11-19 14:24:37,423 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 634 states and 733 transitions. [2024-11-19 14:24:37,426 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:37,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 634 states to 354 states and 406 transitions. [2024-11-19 14:24:37,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 305 [2024-11-19 14:24:37,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 305 [2024-11-19 14:24:37,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 354 states and 406 transitions. [2024-11-19 14:24:37,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 14:24:37,428 INFO L218 hiAutomatonCegarLoop]: Abstraction has 354 states and 406 transitions. [2024-11-19 14:24:37,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states and 406 transitions. [2024-11-19 14:24:37,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 204. [2024-11-19 14:24:37,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 204 states, 204 states have (on average 1.1323529411764706) internal successors, (231), 203 states have internal predecessors, (231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:24:37,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 231 transitions. [2024-11-19 14:24:37,432 INFO L240 hiAutomatonCegarLoop]: Abstraction has 204 states and 231 transitions. [2024-11-19 14:24:37,433 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2024-11-19 14:24:37,433 INFO L425 stractBuchiCegarLoop]: Abstraction has 204 states and 231 transitions. [2024-11-19 14:24:37,433 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-19 14:24:37,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 231 transitions. [2024-11-19 14:24:37,434 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-11-19 14:24:37,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:24:37,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:24:37,435 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 24, 24, 23, 23, 1, 1, 1, 1] [2024-11-19 14:24:37,435 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-19 14:24:37,436 INFO L745 eck$LassoCheckResult]: Stem: 21908#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 21892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 21893#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21909#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21910#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21896#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21897#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21959#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21958#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21957#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21956#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21955#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21954#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21953#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21952#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21951#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21950#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21949#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21948#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21947#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21946#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21945#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21944#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21943#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21942#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21941#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21940#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21939#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21938#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21937#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21936#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21935#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21934#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21933#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21932#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21931#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21930#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21929#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21928#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21927#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21926#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21925#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21924#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21923#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21922#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21921#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21920#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21919#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21918#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21915#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21914#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 21898#L27-4 main_~i~0#1 := 0; 21899#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21905#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21891#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21902#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21907#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22086#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22085#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22083#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22080#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22079#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22077#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22074#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22073#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22071#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22068#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22067#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22065#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22062#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22061#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22059#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22056#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22055#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22053#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22050#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22049#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22047#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22044#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22043#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22041#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22038#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22037#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22035#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22032#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22031#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22029#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22026#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22025#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22023#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22020#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22019#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22017#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22014#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22013#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22011#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22008#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22007#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22005#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22002#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22001#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21999#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21996#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21995#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21993#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21990#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21989#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21987#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21984#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21983#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21981#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21978#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21977#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21975#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21972#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21971#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21969#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21967#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21966#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21963#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21961#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21960#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21913#L34 [2024-11-19 14:24:37,436 INFO L747 eck$LassoCheckResult]: Loop: 21913#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21916#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21912#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21913#L34 [2024-11-19 14:24:37,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:37,436 INFO L85 PathProgramCache]: Analyzing trace with hash -166775655, now seen corresponding path program 46 times [2024-11-19 14:24:37,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:37,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53021454] [2024-11-19 14:24:37,437 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:24:37,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:37,556 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:24:37,556 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:24:37,556 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:37,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:37,693 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:37,693 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:37,693 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 25 times [2024-11-19 14:24:37,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:37,693 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515175898] [2024-11-19 14:24:37,693 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:24:37,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:37,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:37,698 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:24:37,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:24:37,705 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:24:37,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:24:37,708 INFO L85 PathProgramCache]: Analyzing trace with hash 863670077, now seen corresponding path program 47 times [2024-11-19 14:24:37,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:24:37,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242451967] [2024-11-19 14:24:37,709 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:24:37,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:24:37,873 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2024-11-19 14:24:37,873 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat