./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/loop-invgen/string_concat-noarr.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3061b6dc Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/loop-invgen/string_concat-noarr.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-assert-order-craig-3061b6d-m [2024-11-19 14:46:23,518 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-19 14:46:23,598 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-19 14:46:23,602 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-19 14:46:23,603 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-19 14:46:23,631 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-19 14:46:23,631 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-19 14:46:23,632 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-19 14:46:23,632 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-19 14:46:23,633 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-19 14:46:23,633 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-19 14:46:23,634 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-19 14:46:23,634 INFO L153 SettingsManager]: * Use SBE=true [2024-11-19 14:46:23,634 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-19 14:46:23,635 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-19 14:46:23,635 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-19 14:46:23,635 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-19 14:46:23,636 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-19 14:46:23,636 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-19 14:46:23,636 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-19 14:46:23,637 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-19 14:46:23,638 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-19 14:46:23,638 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-19 14:46:23,641 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-19 14:46:23,641 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-19 14:46:23,641 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-19 14:46:23,641 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-19 14:46:23,642 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-19 14:46:23,642 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-19 14:46:23,642 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-19 14:46:23,642 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-19 14:46:23,643 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-19 14:46:23,643 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-19 14:46:23,643 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-19 14:46:23,646 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-19 14:46:23,646 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-19 14:46:23,646 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-19 14:46:23,647 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-19 14:46:23,647 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-19 14:46:23,647 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 [2024-11-19 14:46:23,912 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-19 14:46:23,938 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-19 14:46:23,942 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-19 14:46:23,943 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-19 14:46:23,943 INFO L274 PluginConnector]: CDTParser initialized [2024-11-19 14:46:23,945 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2024-11-19 14:46:25,409 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-19 14:46:25,585 INFO L384 CDTParser]: Found 1 translation units. [2024-11-19 14:46:25,586 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2024-11-19 14:46:25,592 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d51886148/2de6727753fb49419b63891be76d7470/FLAG90082ad87 [2024-11-19 14:46:25,606 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d51886148/2de6727753fb49419b63891be76d7470 [2024-11-19 14:46:25,609 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-19 14:46:25,611 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-19 14:46:25,612 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-19 14:46:25,612 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-19 14:46:25,616 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-19 14:46:25,617 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,618 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1910bcb3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25, skipping insertion in model container [2024-11-19 14:46:25,618 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,635 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-19 14:46:25,833 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 14:46:25,845 INFO L200 MainTranslator]: Completed pre-run [2024-11-19 14:46:25,876 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 14:46:25,889 INFO L204 MainTranslator]: Completed translation [2024-11-19 14:46:25,890 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25 WrapperNode [2024-11-19 14:46:25,890 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-19 14:46:25,890 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-19 14:46:25,891 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-19 14:46:25,891 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-19 14:46:25,895 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,901 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,917 INFO L138 Inliner]: procedures = 16, calls = 8, calls flagged for inlining = 4, calls inlined = 4, statements flattened = 54 [2024-11-19 14:46:25,918 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-19 14:46:25,919 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-19 14:46:25,919 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-19 14:46:25,921 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-19 14:46:25,929 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,929 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,930 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,937 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-19 14:46:25,937 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,938 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,940 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,943 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,945 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,946 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,947 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-19 14:46:25,948 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-19 14:46:25,948 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-19 14:46:25,952 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-19 14:46:25,953 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (1/1) ... [2024-11-19 14:46:25,958 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:46:25,968 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:25,982 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:46:25,984 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-19 14:46:26,022 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-19 14:46:26,022 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-19 14:46:26,022 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-19 14:46:26,022 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-19 14:46:26,070 INFO L238 CfgBuilder]: Building ICFG [2024-11-19 14:46:26,072 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-19 14:46:26,191 INFO L? ?]: Removed 9 outVars from TransFormulas that were not future-live. [2024-11-19 14:46:26,192 INFO L287 CfgBuilder]: Performing block encoding [2024-11-19 14:46:26,208 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-19 14:46:26,208 INFO L316 CfgBuilder]: Removed 2 assume(true) statements. [2024-11-19 14:46:26,208 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 02:46:26 BoogieIcfgContainer [2024-11-19 14:46:26,208 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-19 14:46:26,209 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-19 14:46:26,210 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-19 14:46:26,214 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-19 14:46:26,215 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 14:46:26,216 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 02:46:25" (1/3) ... [2024-11-19 14:46:26,217 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@56675f91 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 02:46:26, skipping insertion in model container [2024-11-19 14:46:26,217 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 14:46:26,217 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 02:46:25" (2/3) ... [2024-11-19 14:46:26,219 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@56675f91 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 02:46:26, skipping insertion in model container [2024-11-19 14:46:26,219 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 14:46:26,219 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 02:46:26" (3/3) ... [2024-11-19 14:46:26,220 INFO L332 chiAutomizerObserver]: Analyzing ICFG string_concat-noarr.i [2024-11-19 14:46:26,279 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-19 14:46:26,280 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-19 14:46:26,280 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-19 14:46:26,280 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-19 14:46:26,280 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-19 14:46:26,280 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-19 14:46:26,281 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-19 14:46:26,281 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-19 14:46:26,285 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:26,302 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5 [2024-11-19 14:46:26,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:26,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:26,308 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2024-11-19 14:46:26,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-19 14:46:26,308 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-19 14:46:26,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:26,311 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5 [2024-11-19 14:46:26,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:26,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:26,311 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2024-11-19 14:46:26,312 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-19 14:46:26,319 INFO L745 eck$LassoCheckResult]: Stem: 13#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5#L26true main_~i~0#1 := 0; 16#L29-2true [2024-11-19 14:46:26,320 INFO L747 eck$LassoCheckResult]: Loop: 16#L29-2true havoc main_#t~nondet1#1; 4#L29true assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16#L29-2true [2024-11-19 14:46:26,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:26,325 INFO L85 PathProgramCache]: Analyzing trace with hash 29857, now seen corresponding path program 1 times [2024-11-19 14:46:26,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:26,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098826432] [2024-11-19 14:46:26,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:46:26,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:26,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:26,418 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:26,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:26,445 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:26,448 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:26,448 INFO L85 PathProgramCache]: Analyzing trace with hash 1254, now seen corresponding path program 1 times [2024-11-19 14:46:26,448 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:26,448 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186265795] [2024-11-19 14:46:26,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:46:26,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:26,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:26,461 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:26,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:26,469 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:26,472 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:26,473 INFO L85 PathProgramCache]: Analyzing trace with hash 28692870, now seen corresponding path program 1 times [2024-11-19 14:46:26,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:26,473 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723648106] [2024-11-19 14:46:26,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:46:26,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:26,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:26,487 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:26,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:26,497 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:26,600 INFO L204 LassoAnalysis]: Preferences: [2024-11-19 14:46:26,600 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-19 14:46:26,600 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-19 14:46:26,601 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-19 14:46:26,601 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-19 14:46:26,601 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:46:26,601 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-19 14:46:26,602 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-19 14:46:26,602 INFO L132 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2024-11-19 14:46:26,602 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-19 14:46:26,602 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-19 14:46:26,614 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:46:26,627 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:46:26,630 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:46:26,670 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-19 14:46:26,671 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-19 14:46:26,673 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:46:26,673 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:26,676 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:46:26,677 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-19 14:46:26,678 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 14:46:26,679 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 14:46:26,711 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-19 14:46:26,713 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:46:26,713 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:26,714 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:46:26,716 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-19 14:46:26,718 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-19 14:46:26,718 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 14:46:26,757 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-19 14:46:26,762 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-19 14:46:26,762 INFO L204 LassoAnalysis]: Preferences: [2024-11-19 14:46:26,762 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-19 14:46:26,762 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-19 14:46:26,762 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-19 14:46:26,763 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-19 14:46:26,763 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:46:26,763 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-19 14:46:26,763 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-19 14:46:26,763 INFO L132 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2024-11-19 14:46:26,763 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-19 14:46:26,763 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-19 14:46:26,764 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:46:26,776 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:46:26,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 14:46:26,815 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-19 14:46:26,820 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-19 14:46:26,822 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:46:26,822 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:26,823 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:46:26,825 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-19 14:46:26,826 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 14:46:26,839 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 14:46:26,839 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 14:46:26,840 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 14:46:26,840 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 14:46:26,840 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 14:46:26,842 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 14:46:26,842 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 14:46:26,845 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-19 14:46:26,849 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-19 14:46:26,850 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-19 14:46:26,851 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 14:46:26,851 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:26,874 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 14:46:26,875 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-19 14:46:26,877 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-19 14:46:26,877 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-19 14:46:26,878 INFO L474 LassoAnalysis]: Proved termination. [2024-11-19 14:46:26,879 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1) = -2*ULTIMATE.start_main_~i~0#1 + 1999999 Supporting invariants [] [2024-11-19 14:46:26,893 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-11-19 14:46:26,896 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-19 14:46:26,933 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:26,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:46:26,957 INFO L255 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-19 14:46:26,958 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:26,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:46:26,979 WARN L253 TraceCheckSpWp]: Trace formula consists of 7 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-19 14:46:26,979 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:26,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:27,018 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2024-11-19 14:46:27,020 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:27,084 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 41 states and 58 transitions. Complement of second has 6 states. [2024-11-19 14:46:27,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-19 14:46:27,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:27,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 34 transitions. [2024-11-19 14:46:27,097 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 34 transitions. Stem has 3 letters. Loop has 2 letters. [2024-11-19 14:46:27,098 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-19 14:46:27,098 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 34 transitions. Stem has 5 letters. Loop has 2 letters. [2024-11-19 14:46:27,099 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-19 14:46:27,099 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 34 transitions. Stem has 3 letters. Loop has 4 letters. [2024-11-19 14:46:27,099 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-19 14:46:27,100 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 58 transitions. [2024-11-19 14:46:27,103 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2024-11-19 14:46:27,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 18 states and 23 transitions. [2024-11-19 14:46:27,109 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2024-11-19 14:46:27,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2024-11-19 14:46:27,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 23 transitions. [2024-11-19 14:46:27,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:27,110 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18 states and 23 transitions. [2024-11-19 14:46:27,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 23 transitions. [2024-11-19 14:46:27,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 16. [2024-11-19 14:46:27,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.3125) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:27,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 21 transitions. [2024-11-19 14:46:27,135 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 21 transitions. [2024-11-19 14:46:27,135 INFO L425 stractBuchiCegarLoop]: Abstraction has 16 states and 21 transitions. [2024-11-19 14:46:27,135 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-19 14:46:27,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 21 transitions. [2024-11-19 14:46:27,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:27,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:27,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:27,138 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2024-11-19 14:46:27,138 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:27,138 INFO L745 eck$LassoCheckResult]: Stem: 102#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 109#L26 main_~i~0#1 := 0; 110#L29-2 havoc main_#t~nondet1#1; 104#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 97#L29-3 assume main_~i~0#1 >= 100; 98#L32 [2024-11-19 14:46:27,139 INFO L747 eck$LassoCheckResult]: Loop: 98#L32 assume true; 98#L32 [2024-11-19 14:46:27,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:27,139 INFO L85 PathProgramCache]: Analyzing trace with hash 889478928, now seen corresponding path program 1 times [2024-11-19 14:46:27,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:27,140 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759088153] [2024-11-19 14:46:27,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:46:27,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:27,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:46:27,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:27,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:27,214 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1759088153] [2024-11-19 14:46:27,215 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1759088153] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 14:46:27,215 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 14:46:27,216 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 14:46:27,216 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [504619269] [2024-11-19 14:46:27,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 14:46:27,219 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:27,220 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:27,220 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 1 times [2024-11-19 14:46:27,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:27,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922863123] [2024-11-19 14:46:27,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:46:27,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:27,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:27,227 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:27,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:27,229 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:27,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:27,236 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 14:46:27,237 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 14:46:27,238 INFO L87 Difference]: Start difference. First operand 16 states and 21 transitions. cyclomatic complexity: 8 Second operand has 3 states, 2 states have (on average 3.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:27,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:27,263 INFO L93 Difference]: Finished difference Result 26 states and 32 transitions. [2024-11-19 14:46:27,263 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 32 transitions. [2024-11-19 14:46:27,264 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2024-11-19 14:46:27,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 26 states and 32 transitions. [2024-11-19 14:46:27,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2024-11-19 14:46:27,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2024-11-19 14:46:27,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 32 transitions. [2024-11-19 14:46:27,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:27,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26 states and 32 transitions. [2024-11-19 14:46:27,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 32 transitions. [2024-11-19 14:46:27,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 18. [2024-11-19 14:46:27,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 17 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:27,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 23 transitions. [2024-11-19 14:46:27,271 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18 states and 23 transitions. [2024-11-19 14:46:27,272 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 14:46:27,273 INFO L425 stractBuchiCegarLoop]: Abstraction has 18 states and 23 transitions. [2024-11-19 14:46:27,273 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-19 14:46:27,273 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 23 transitions. [2024-11-19 14:46:27,273 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:27,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:27,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:27,274 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1] [2024-11-19 14:46:27,274 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:27,274 INFO L745 eck$LassoCheckResult]: Stem: 153#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 154#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 157#L26 main_~i~0#1 := 0; 158#L29-2 havoc main_#t~nondet1#1; 151#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 152#L29-2 havoc main_#t~nondet1#1; 149#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 150#L29-3 assume main_~i~0#1 >= 100; 159#L32 [2024-11-19 14:46:27,274 INFO L747 eck$LassoCheckResult]: Loop: 159#L32 assume true; 159#L32 [2024-11-19 14:46:27,275 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:27,275 INFO L85 PathProgramCache]: Analyzing trace with hash 90807307, now seen corresponding path program 1 times [2024-11-19 14:46:27,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:27,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584435696] [2024-11-19 14:46:27,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:46:27,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:27,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:46:27,323 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-19 14:46:27,364 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:27,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:27,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584435696] [2024-11-19 14:46:27,365 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584435696] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:27,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [271948787] [2024-11-19 14:46:27,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:46:27,366 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:27,366 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:27,368 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:27,370 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-19 14:46:27,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:46:27,413 INFO L255 TraceCheckSpWp]: Trace formula consists of 28 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-19 14:46:27,413 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:27,445 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:27,445 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:46:27,480 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:27,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [271948787] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:46:27,481 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:46:27,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2024-11-19 14:46:27,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [846556537] [2024-11-19 14:46:27,481 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:46:27,481 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:27,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:27,482 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 2 times [2024-11-19 14:46:27,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:27,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566523801] [2024-11-19 14:46:27,484 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:46:27,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:27,487 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:46:27,487 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:46:27,488 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:27,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:27,490 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:27,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:27,492 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-19 14:46:27,493 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2024-11-19 14:46:27,493 INFO L87 Difference]: Start difference. First operand 18 states and 23 transitions. cyclomatic complexity: 8 Second operand has 7 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 7 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:27,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:27,545 INFO L93 Difference]: Finished difference Result 60 states and 75 transitions. [2024-11-19 14:46:27,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 75 transitions. [2024-11-19 14:46:27,547 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5 [2024-11-19 14:46:27,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 60 states and 75 transitions. [2024-11-19 14:46:27,548 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2024-11-19 14:46:27,549 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2024-11-19 14:46:27,549 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 75 transitions. [2024-11-19 14:46:27,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:27,549 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 75 transitions. [2024-11-19 14:46:27,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 75 transitions. [2024-11-19 14:46:27,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 24. [2024-11-19 14:46:27,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.4583333333333333) internal successors, (35), 23 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:27,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 35 transitions. [2024-11-19 14:46:27,554 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 35 transitions. [2024-11-19 14:46:27,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-19 14:46:27,555 INFO L425 stractBuchiCegarLoop]: Abstraction has 24 states and 35 transitions. [2024-11-19 14:46:27,555 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-19 14:46:27,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 35 transitions. [2024-11-19 14:46:27,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:27,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:27,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:27,558 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 14:46:27,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:27,558 INFO L745 eck$LassoCheckResult]: Stem: 282#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 286#L26 main_~i~0#1 := 0; 287#L29-2 havoc main_#t~nondet1#1; 279#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 275#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 276#L35-2 havoc main_#t~nondet3#1; 284#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 289#L35-3 assume main_~j~0#1 >= 100; 288#L32 [2024-11-19 14:46:27,558 INFO L747 eck$LassoCheckResult]: Loop: 288#L32 assume true; 288#L32 [2024-11-19 14:46:27,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:27,559 INFO L85 PathProgramCache]: Analyzing trace with hash -1481354991, now seen corresponding path program 1 times [2024-11-19 14:46:27,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:27,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783601395] [2024-11-19 14:46:27,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:46:27,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:27,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:46:27,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:27,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:27,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783601395] [2024-11-19 14:46:27,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [783601395] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 14:46:27,604 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 14:46:27,604 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 14:46:27,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343054032] [2024-11-19 14:46:27,604 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 14:46:27,604 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:27,605 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:27,605 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 3 times [2024-11-19 14:46:27,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:27,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998738230] [2024-11-19 14:46:27,605 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:46:27,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:27,607 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 14:46:27,607 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:46:27,608 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:27,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:27,610 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:27,612 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:27,613 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 14:46:27,613 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 14:46:27,614 INFO L87 Difference]: Start difference. First operand 24 states and 35 transitions. cyclomatic complexity: 14 Second operand has 3 states, 2 states have (on average 4.5) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:27,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:27,623 INFO L93 Difference]: Finished difference Result 27 states and 37 transitions. [2024-11-19 14:46:27,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 37 transitions. [2024-11-19 14:46:27,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:27,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 22 states and 28 transitions. [2024-11-19 14:46:27,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-19 14:46:27,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-19 14:46:27,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 28 transitions. [2024-11-19 14:46:27,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:27,625 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 28 transitions. [2024-11-19 14:46:27,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 28 transitions. [2024-11-19 14:46:27,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2024-11-19 14:46:27,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:27,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2024-11-19 14:46:27,629 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2024-11-19 14:46:27,630 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 14:46:27,630 INFO L425 stractBuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2024-11-19 14:46:27,630 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-19 14:46:27,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2024-11-19 14:46:27,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:27,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:27,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:27,632 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 14:46:27,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:27,632 INFO L745 eck$LassoCheckResult]: Stem: 339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 342#L26 main_~i~0#1 := 0; 343#L29-2 havoc main_#t~nondet1#1; 337#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 334#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 335#L35-2 havoc main_#t~nondet3#1; 341#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 346#L35-2 havoc main_#t~nondet3#1; 345#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 344#L35-3 assume main_~j~0#1 >= 100; 333#L32 [2024-11-19 14:46:27,632 INFO L747 eck$LassoCheckResult]: Loop: 333#L32 assume true; 333#L32 [2024-11-19 14:46:27,632 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:27,632 INFO L85 PathProgramCache]: Analyzing trace with hash -1947921364, now seen corresponding path program 1 times [2024-11-19 14:46:27,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:27,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54274795] [2024-11-19 14:46:27,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:46:27,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:27,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:46:27,682 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:27,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:27,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54274795] [2024-11-19 14:46:27,683 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [54274795] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:27,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2123271537] [2024-11-19 14:46:27,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:46:27,683 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:27,684 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:27,685 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:27,686 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-19 14:46:27,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 14:46:27,717 INFO L255 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-19 14:46:27,718 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:27,741 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:27,742 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:46:27,763 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:27,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2123271537] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:46:27,763 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:46:27,763 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2024-11-19 14:46:27,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1676889794] [2024-11-19 14:46:27,764 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:46:27,764 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:27,764 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:27,764 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 4 times [2024-11-19 14:46:27,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:27,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613233201] [2024-11-19 14:46:27,765 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:46:27,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:27,767 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:46:27,767 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:46:27,767 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:27,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:27,768 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:27,775 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:27,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-19 14:46:27,780 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2024-11-19 14:46:27,780 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 7 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 7 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:27,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:27,796 INFO L93 Difference]: Finished difference Result 34 states and 40 transitions. [2024-11-19 14:46:27,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 40 transitions. [2024-11-19 14:46:27,798 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:27,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 28 states and 34 transitions. [2024-11-19 14:46:27,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-19 14:46:27,798 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-19 14:46:27,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 34 transitions. [2024-11-19 14:46:27,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:27,799 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 34 transitions. [2024-11-19 14:46:27,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 34 transitions. [2024-11-19 14:46:27,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2024-11-19 14:46:27,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2222222222222223) internal successors, (33), 26 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:27,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 33 transitions. [2024-11-19 14:46:27,805 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2024-11-19 14:46:27,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-19 14:46:27,806 INFO L425 stractBuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2024-11-19 14:46:27,806 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-19 14:46:27,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 33 transitions. [2024-11-19 14:46:27,807 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:27,807 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:27,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:27,807 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 1, 1, 1, 1, 1] [2024-11-19 14:46:27,808 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:27,808 INFO L745 eck$LassoCheckResult]: Stem: 461#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 462#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 468#L26 main_~i~0#1 := 0; 469#L29-2 havoc main_#t~nondet1#1; 464#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 465#L29-2 havoc main_#t~nondet1#1; 473#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 480#L29-2 havoc main_#t~nondet1#1; 479#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 478#L29-2 havoc main_#t~nondet1#1; 475#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 474#L29-2 havoc main_#t~nondet1#1; 463#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 457#L29-3 assume main_~i~0#1 >= 100; 458#L32 [2024-11-19 14:46:27,808 INFO L747 eck$LassoCheckResult]: Loop: 458#L32 assume true; 458#L32 [2024-11-19 14:46:27,808 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:27,808 INFO L85 PathProgramCache]: Analyzing trace with hash -957341060, now seen corresponding path program 2 times [2024-11-19 14:46:27,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:27,809 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858734197] [2024-11-19 14:46:27,809 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:46:27,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:27,823 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:46:27,823 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:27,927 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:27,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:27,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1858734197] [2024-11-19 14:46:27,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1858734197] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:27,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [994117068] [2024-11-19 14:46:27,928 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:46:27,928 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:27,928 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:27,930 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:27,932 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-19 14:46:27,968 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:46:27,968 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:27,969 INFO L255 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-19 14:46:27,970 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:27,999 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:27,999 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:46:28,072 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:28,072 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [994117068] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:46:28,072 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:46:28,072 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2024-11-19 14:46:28,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415534279] [2024-11-19 14:46:28,073 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:46:28,073 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:28,073 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:28,073 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 5 times [2024-11-19 14:46:28,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:28,073 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1900304706] [2024-11-19 14:46:28,073 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:46:28,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:28,076 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:46:28,076 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:46:28,076 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:28,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:28,077 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:28,079 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:28,080 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-11-19 14:46:28,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2024-11-19 14:46:28,080 INFO L87 Difference]: Start difference. First operand 27 states and 33 transitions. cyclomatic complexity: 9 Second operand has 13 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 13 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:28,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:28,183 INFO L93 Difference]: Finished difference Result 152 states and 171 transitions. [2024-11-19 14:46:28,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152 states and 171 transitions. [2024-11-19 14:46:28,185 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2024-11-19 14:46:28,190 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 152 states to 140 states and 159 transitions. [2024-11-19 14:46:28,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2024-11-19 14:46:28,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2024-11-19 14:46:28,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 140 states and 159 transitions. [2024-11-19 14:46:28,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:28,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2024-11-19 14:46:28,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states and 159 transitions. [2024-11-19 14:46:28,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 39. [2024-11-19 14:46:28,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.3076923076923077) internal successors, (51), 38 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:28,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 51 transitions. [2024-11-19 14:46:28,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2024-11-19 14:46:28,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-11-19 14:46:28,197 INFO L425 stractBuchiCegarLoop]: Abstraction has 39 states and 51 transitions. [2024-11-19 14:46:28,197 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-19 14:46:28,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 51 transitions. [2024-11-19 14:46:28,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:28,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:28,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:28,200 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 14:46:28,200 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:28,200 INFO L745 eck$LassoCheckResult]: Stem: 734#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 735#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 740#L26 main_~i~0#1 := 0; 741#L29-2 havoc main_#t~nondet1#1; 743#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 732#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 733#L35-2 havoc main_#t~nondet3#1; 739#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 746#L35-2 havoc main_#t~nondet3#1; 768#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 767#L35-2 havoc main_#t~nondet3#1; 766#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 765#L35-2 havoc main_#t~nondet3#1; 764#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 763#L35-2 havoc main_#t~nondet3#1; 745#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 742#L35-3 assume main_~j~0#1 >= 100; 731#L32 [2024-11-19 14:46:28,200 INFO L747 eck$LassoCheckResult]: Loop: 731#L32 assume true; 731#L32 [2024-11-19 14:46:28,200 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:28,200 INFO L85 PathProgramCache]: Analyzing trace with hash 606076157, now seen corresponding path program 2 times [2024-11-19 14:46:28,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:28,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252640420] [2024-11-19 14:46:28,201 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:46:28,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:28,210 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:46:28,211 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:28,303 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:28,303 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:28,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [252640420] [2024-11-19 14:46:28,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [252640420] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:28,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [896105854] [2024-11-19 14:46:28,304 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:46:28,304 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:28,304 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:28,307 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:28,308 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-19 14:46:28,347 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-19 14:46:28,347 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:28,351 INFO L255 TraceCheckSpWp]: Trace formula consists of 56 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-19 14:46:28,352 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:28,391 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:28,391 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:46:28,486 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:28,486 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [896105854] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:46:28,486 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:46:28,486 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2024-11-19 14:46:28,486 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381041244] [2024-11-19 14:46:28,487 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:46:28,487 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:28,487 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:28,487 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 6 times [2024-11-19 14:46:28,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:28,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920384955] [2024-11-19 14:46:28,488 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:46:28,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:28,491 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2024-11-19 14:46:28,491 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:46:28,492 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:28,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:28,493 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:28,496 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:28,496 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-11-19 14:46:28,496 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2024-11-19 14:46:28,497 INFO L87 Difference]: Start difference. First operand 39 states and 51 transitions. cyclomatic complexity: 15 Second operand has 13 states, 12 states have (on average 2.6666666666666665) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:28,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:28,527 INFO L93 Difference]: Finished difference Result 64 states and 76 transitions. [2024-11-19 14:46:28,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64 states and 76 transitions. [2024-11-19 14:46:28,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:28,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64 states to 52 states and 64 transitions. [2024-11-19 14:46:28,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-19 14:46:28,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-19 14:46:28,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 64 transitions. [2024-11-19 14:46:28,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:28,530 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 64 transitions. [2024-11-19 14:46:28,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 64 transitions. [2024-11-19 14:46:28,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2024-11-19 14:46:28,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.2352941176470589) internal successors, (63), 50 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:28,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 63 transitions. [2024-11-19 14:46:28,533 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 63 transitions. [2024-11-19 14:46:28,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-11-19 14:46:28,534 INFO L425 stractBuchiCegarLoop]: Abstraction has 51 states and 63 transitions. [2024-11-19 14:46:28,534 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-19 14:46:28,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 63 transitions. [2024-11-19 14:46:28,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:28,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:28,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:28,536 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 1, 1, 1, 1, 1] [2024-11-19 14:46:28,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:28,536 INFO L745 eck$LassoCheckResult]: Stem: 952#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 953#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 956#L26 main_~i~0#1 := 0; 957#L29-2 havoc main_#t~nondet1#1; 950#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 951#L29-2 havoc main_#t~nondet1#1; 961#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 980#L29-2 havoc main_#t~nondet1#1; 979#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 978#L29-2 havoc main_#t~nondet1#1; 977#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 976#L29-2 havoc main_#t~nondet1#1; 975#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 974#L29-2 havoc main_#t~nondet1#1; 973#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 972#L29-2 havoc main_#t~nondet1#1; 971#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 970#L29-2 havoc main_#t~nondet1#1; 969#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 968#L29-2 havoc main_#t~nondet1#1; 967#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 966#L29-2 havoc main_#t~nondet1#1; 965#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 964#L29-2 havoc main_#t~nondet1#1; 949#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 945#L29-3 assume main_~i~0#1 >= 100; 946#L32 [2024-11-19 14:46:28,536 INFO L747 eck$LassoCheckResult]: Loop: 946#L32 assume true; 946#L32 [2024-11-19 14:46:28,536 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:28,537 INFO L85 PathProgramCache]: Analyzing trace with hash 777893150, now seen corresponding path program 3 times [2024-11-19 14:46:28,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:28,537 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131951455] [2024-11-19 14:46:28,537 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:46:28,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:28,552 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-11-19 14:46:28,552 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:28,734 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:28,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:28,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131951455] [2024-11-19 14:46:28,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [131951455] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:28,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [220121924] [2024-11-19 14:46:28,736 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:46:28,736 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:28,736 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:28,741 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:28,743 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-19 14:46:28,792 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-11-19 14:46:28,793 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:28,794 INFO L255 TraceCheckSpWp]: Trace formula consists of 73 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-19 14:46:28,795 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:28,871 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:28,872 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:46:29,118 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:29,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [220121924] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:46:29,119 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:46:29,119 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2024-11-19 14:46:29,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119457955] [2024-11-19 14:46:29,120 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:46:29,120 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:29,120 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:29,120 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 7 times [2024-11-19 14:46:29,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:29,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519577080] [2024-11-19 14:46:29,121 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:46:29,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:29,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:29,123 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:29,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:29,124 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:29,129 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:29,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-11-19 14:46:29,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2024-11-19 14:46:29,131 INFO L87 Difference]: Start difference. First operand 51 states and 63 transitions. cyclomatic complexity: 15 Second operand has 25 states, 24 states have (on average 2.2083333333333335) internal successors, (53), 25 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:29,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:29,327 INFO L93 Difference]: Finished difference Result 518 states and 555 transitions. [2024-11-19 14:46:29,327 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 555 transitions. [2024-11-19 14:46:29,333 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 13 [2024-11-19 14:46:29,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 494 states and 531 transitions. [2024-11-19 14:46:29,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2024-11-19 14:46:29,340 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45 [2024-11-19 14:46:29,340 INFO L73 IsDeterministic]: Start isDeterministic. Operand 494 states and 531 transitions. [2024-11-19 14:46:29,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:29,340 INFO L218 hiAutomatonCegarLoop]: Abstraction has 494 states and 531 transitions. [2024-11-19 14:46:29,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 494 states and 531 transitions. [2024-11-19 14:46:29,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 494 to 75. [2024-11-19 14:46:29,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.32) internal successors, (99), 74 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:29,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 99 transitions. [2024-11-19 14:46:29,356 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 99 transitions. [2024-11-19 14:46:29,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-11-19 14:46:29,357 INFO L425 stractBuchiCegarLoop]: Abstraction has 75 states and 99 transitions. [2024-11-19 14:46:29,357 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-19 14:46:29,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 99 transitions. [2024-11-19 14:46:29,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:29,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:29,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:29,361 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 14:46:29,361 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:29,361 INFO L745 eck$LassoCheckResult]: Stem: 1696#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 1697#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 1702#L26 main_~i~0#1 := 0; 1703#L29-2 havoc main_#t~nondet1#1; 1705#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 1694#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 1695#L35-2 havoc main_#t~nondet3#1; 1701#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1708#L35-2 havoc main_#t~nondet3#1; 1766#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1765#L35-2 havoc main_#t~nondet3#1; 1764#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1763#L35-2 havoc main_#t~nondet3#1; 1762#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1761#L35-2 havoc main_#t~nondet3#1; 1760#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1759#L35-2 havoc main_#t~nondet3#1; 1758#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1757#L35-2 havoc main_#t~nondet3#1; 1756#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1755#L35-2 havoc main_#t~nondet3#1; 1754#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1753#L35-2 havoc main_#t~nondet3#1; 1752#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1751#L35-2 havoc main_#t~nondet3#1; 1750#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1749#L35-2 havoc main_#t~nondet3#1; 1707#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 1704#L35-3 assume main_~j~0#1 >= 100; 1693#L32 [2024-11-19 14:46:29,361 INFO L747 eck$LassoCheckResult]: Loop: 1693#L32 assume true; 1693#L32 [2024-11-19 14:46:29,362 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:29,362 INFO L85 PathProgramCache]: Analyzing trace with hash -2036695969, now seen corresponding path program 3 times [2024-11-19 14:46:29,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:29,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071504616] [2024-11-19 14:46:29,362 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:46:29,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:29,390 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-11-19 14:46:29,391 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:29,549 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:29,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:29,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2071504616] [2024-11-19 14:46:29,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2071504616] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:29,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1500395267] [2024-11-19 14:46:29,549 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:46:29,550 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:29,550 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:29,551 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:29,553 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-19 14:46:29,596 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-11-19 14:46:29,596 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:29,597 INFO L255 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-19 14:46:29,598 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:29,662 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:29,662 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:46:29,900 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:29,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1500395267] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:46:29,900 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:46:29,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2024-11-19 14:46:29,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086852021] [2024-11-19 14:46:29,901 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:46:29,901 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:29,901 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:29,901 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 8 times [2024-11-19 14:46:29,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:29,901 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842376812] [2024-11-19 14:46:29,902 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:46:29,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:29,903 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:46:29,903 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:46:29,903 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:29,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:29,904 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:29,912 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:29,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-11-19 14:46:29,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2024-11-19 14:46:29,913 INFO L87 Difference]: Start difference. First operand 75 states and 99 transitions. cyclomatic complexity: 27 Second operand has 25 states, 24 states have (on average 2.3333333333333335) internal successors, (56), 25 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:29,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:29,948 INFO L93 Difference]: Finished difference Result 124 states and 148 transitions. [2024-11-19 14:46:29,948 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 148 transitions. [2024-11-19 14:46:29,949 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:29,950 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 100 states and 124 transitions. [2024-11-19 14:46:29,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-19 14:46:29,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-19 14:46:29,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 124 transitions. [2024-11-19 14:46:29,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:29,950 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 124 transitions. [2024-11-19 14:46:29,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 124 transitions. [2024-11-19 14:46:29,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2024-11-19 14:46:29,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.2424242424242424) internal successors, (123), 98 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:29,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 123 transitions. [2024-11-19 14:46:29,954 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 123 transitions. [2024-11-19 14:46:29,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-11-19 14:46:29,955 INFO L425 stractBuchiCegarLoop]: Abstraction has 99 states and 123 transitions. [2024-11-19 14:46:29,955 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-19 14:46:29,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 123 transitions. [2024-11-19 14:46:29,956 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:29,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:29,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:29,957 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 22, 1, 1, 1, 1, 1] [2024-11-19 14:46:29,957 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:29,957 INFO L745 eck$LassoCheckResult]: Stem: 2094#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 2095#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 2098#L26 main_~i~0#1 := 0; 2099#L29-2 havoc main_#t~nondet1#1; 2092#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2093#L29-2 havoc main_#t~nondet1#1; 2103#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2146#L29-2 havoc main_#t~nondet1#1; 2145#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2144#L29-2 havoc main_#t~nondet1#1; 2143#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2142#L29-2 havoc main_#t~nondet1#1; 2141#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2140#L29-2 havoc main_#t~nondet1#1; 2139#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2138#L29-2 havoc main_#t~nondet1#1; 2137#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2136#L29-2 havoc main_#t~nondet1#1; 2135#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2134#L29-2 havoc main_#t~nondet1#1; 2133#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2132#L29-2 havoc main_#t~nondet1#1; 2131#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2130#L29-2 havoc main_#t~nondet1#1; 2129#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2128#L29-2 havoc main_#t~nondet1#1; 2127#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2126#L29-2 havoc main_#t~nondet1#1; 2125#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2124#L29-2 havoc main_#t~nondet1#1; 2123#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2122#L29-2 havoc main_#t~nondet1#1; 2121#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2120#L29-2 havoc main_#t~nondet1#1; 2119#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2118#L29-2 havoc main_#t~nondet1#1; 2117#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2116#L29-2 havoc main_#t~nondet1#1; 2115#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2114#L29-2 havoc main_#t~nondet1#1; 2113#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2112#L29-2 havoc main_#t~nondet1#1; 2111#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2110#L29-2 havoc main_#t~nondet1#1; 2109#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2108#L29-2 havoc main_#t~nondet1#1; 2107#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2106#L29-2 havoc main_#t~nondet1#1; 2091#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 2087#L29-3 assume main_~i~0#1 >= 100; 2088#L32 [2024-11-19 14:46:29,957 INFO L747 eck$LassoCheckResult]: Loop: 2088#L32 assume true; 2088#L32 [2024-11-19 14:46:29,958 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:29,958 INFO L85 PathProgramCache]: Analyzing trace with hash -439176862, now seen corresponding path program 4 times [2024-11-19 14:46:29,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:29,958 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108471238] [2024-11-19 14:46:29,958 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:46:29,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:29,971 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:46:29,972 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:30,407 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:30,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:30,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108471238] [2024-11-19 14:46:30,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2108471238] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:30,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [125727931] [2024-11-19 14:46:30,408 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:46:30,408 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:30,408 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:30,410 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:30,411 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-19 14:46:30,459 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:46:30,460 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:30,461 INFO L255 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-11-19 14:46:30,463 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:30,556 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:30,556 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:46:31,353 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:31,353 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [125727931] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:46:31,353 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:46:31,353 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 47 [2024-11-19 14:46:31,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334084518] [2024-11-19 14:46:31,354 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:46:31,354 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:31,355 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:31,355 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 9 times [2024-11-19 14:46:31,355 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:31,355 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829919929] [2024-11-19 14:46:31,355 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:46:31,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:31,357 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 14:46:31,357 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:46:31,357 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:31,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:31,357 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:31,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:31,364 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2024-11-19 14:46:31,365 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2024-11-19 14:46:31,366 INFO L87 Difference]: Start difference. First operand 99 states and 123 transitions. cyclomatic complexity: 27 Second operand has 48 states, 47 states have (on average 2.0851063829787235) internal successors, (98), 48 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:31,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:31,797 INFO L93 Difference]: Finished difference Result 1898 states and 1971 transitions. [2024-11-19 14:46:31,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1898 states and 1971 transitions. [2024-11-19 14:46:31,809 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25 [2024-11-19 14:46:31,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1898 states to 1850 states and 1923 transitions. [2024-11-19 14:46:31,816 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81 [2024-11-19 14:46:31,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81 [2024-11-19 14:46:31,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1850 states and 1923 transitions. [2024-11-19 14:46:31,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:31,817 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1850 states and 1923 transitions. [2024-11-19 14:46:31,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1850 states and 1923 transitions. [2024-11-19 14:46:31,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1850 to 147. [2024-11-19 14:46:31,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147 states, 147 states have (on average 1.3265306122448979) internal successors, (195), 146 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:31,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 195 transitions. [2024-11-19 14:46:31,832 INFO L240 hiAutomatonCegarLoop]: Abstraction has 147 states and 195 transitions. [2024-11-19 14:46:31,837 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-11-19 14:46:31,837 INFO L425 stractBuchiCegarLoop]: Abstraction has 147 states and 195 transitions. [2024-11-19 14:46:31,837 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-19 14:46:31,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147 states and 195 transitions. [2024-11-19 14:46:31,838 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:31,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:31,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:31,839 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 22, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 14:46:31,839 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:31,839 INFO L745 eck$LassoCheckResult]: Stem: 4436#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 4437#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 4439#L26 main_~i~0#1 := 0; 4440#L29-2 havoc main_#t~nondet1#1; 4444#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 4431#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 4432#L35-2 havoc main_#t~nondet3#1; 4438#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4443#L35-2 havoc main_#t~nondet3#1; 4575#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4574#L35-2 havoc main_#t~nondet3#1; 4573#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4572#L35-2 havoc main_#t~nondet3#1; 4571#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4570#L35-2 havoc main_#t~nondet3#1; 4569#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4568#L35-2 havoc main_#t~nondet3#1; 4567#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4566#L35-2 havoc main_#t~nondet3#1; 4565#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4564#L35-2 havoc main_#t~nondet3#1; 4563#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4562#L35-2 havoc main_#t~nondet3#1; 4561#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4560#L35-2 havoc main_#t~nondet3#1; 4559#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4558#L35-2 havoc main_#t~nondet3#1; 4557#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4556#L35-2 havoc main_#t~nondet3#1; 4555#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4554#L35-2 havoc main_#t~nondet3#1; 4553#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4552#L35-2 havoc main_#t~nondet3#1; 4551#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4550#L35-2 havoc main_#t~nondet3#1; 4549#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4548#L35-2 havoc main_#t~nondet3#1; 4547#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4546#L35-2 havoc main_#t~nondet3#1; 4545#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4544#L35-2 havoc main_#t~nondet3#1; 4543#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4542#L35-2 havoc main_#t~nondet3#1; 4541#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4540#L35-2 havoc main_#t~nondet3#1; 4539#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4538#L35-2 havoc main_#t~nondet3#1; 4537#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4536#L35-2 havoc main_#t~nondet3#1; 4535#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4534#L35-2 havoc main_#t~nondet3#1; 4442#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 4441#L35-3 assume main_~j~0#1 >= 100; 4430#L32 [2024-11-19 14:46:31,840 INFO L747 eck$LassoCheckResult]: Loop: 4430#L32 assume true; 4430#L32 [2024-11-19 14:46:31,840 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:31,840 INFO L85 PathProgramCache]: Analyzing trace with hash -173936093, now seen corresponding path program 4 times [2024-11-19 14:46:31,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:31,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304443185] [2024-11-19 14:46:31,841 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:46:31,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:31,866 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:46:31,866 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:32,303 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:32,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:32,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304443185] [2024-11-19 14:46:32,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [304443185] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:32,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1703020543] [2024-11-19 14:46:32,304 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:46:32,305 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:32,305 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:32,307 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:32,308 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-19 14:46:32,363 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:46:32,363 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:32,367 INFO L255 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-11-19 14:46:32,369 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:32,452 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:32,452 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:46:33,155 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:33,156 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1703020543] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:46:33,156 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:46:33,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2024-11-19 14:46:33,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [846769821] [2024-11-19 14:46:33,156 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:46:33,157 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:33,157 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:33,157 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 10 times [2024-11-19 14:46:33,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:33,157 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863541048] [2024-11-19 14:46:33,157 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 14:46:33,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:33,159 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 14:46:33,159 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:46:33,160 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:33,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:33,160 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:33,167 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:33,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2024-11-19 14:46:33,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2024-11-19 14:46:33,169 INFO L87 Difference]: Start difference. First operand 147 states and 195 transitions. cyclomatic complexity: 51 Second operand has 49 states, 48 states have (on average 2.1666666666666665) internal successors, (104), 49 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:33,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:33,231 INFO L93 Difference]: Finished difference Result 244 states and 292 transitions. [2024-11-19 14:46:33,231 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244 states and 292 transitions. [2024-11-19 14:46:33,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:33,234 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244 states to 196 states and 244 transitions. [2024-11-19 14:46:33,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-19 14:46:33,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-19 14:46:33,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196 states and 244 transitions. [2024-11-19 14:46:33,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:33,234 INFO L218 hiAutomatonCegarLoop]: Abstraction has 196 states and 244 transitions. [2024-11-19 14:46:33,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states and 244 transitions. [2024-11-19 14:46:33,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 195. [2024-11-19 14:46:33,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.2461538461538462) internal successors, (243), 194 states have internal predecessors, (243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:33,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 243 transitions. [2024-11-19 14:46:33,238 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 243 transitions. [2024-11-19 14:46:33,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-11-19 14:46:33,240 INFO L425 stractBuchiCegarLoop]: Abstraction has 195 states and 243 transitions. [2024-11-19 14:46:33,240 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-19 14:46:33,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 243 transitions. [2024-11-19 14:46:33,241 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:33,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:33,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:33,244 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [47, 46, 1, 1, 1, 1, 1] [2024-11-19 14:46:33,244 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:33,244 INFO L745 eck$LassoCheckResult]: Stem: 5191#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 5192#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5195#L26 main_~i~0#1 := 0; 5196#L29-2 havoc main_#t~nondet1#1; 5189#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5190#L29-2 havoc main_#t~nondet1#1; 5200#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5291#L29-2 havoc main_#t~nondet1#1; 5290#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5289#L29-2 havoc main_#t~nondet1#1; 5288#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5287#L29-2 havoc main_#t~nondet1#1; 5286#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5285#L29-2 havoc main_#t~nondet1#1; 5284#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5283#L29-2 havoc main_#t~nondet1#1; 5282#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5281#L29-2 havoc main_#t~nondet1#1; 5280#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5279#L29-2 havoc main_#t~nondet1#1; 5278#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5277#L29-2 havoc main_#t~nondet1#1; 5276#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5275#L29-2 havoc main_#t~nondet1#1; 5274#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5273#L29-2 havoc main_#t~nondet1#1; 5272#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5271#L29-2 havoc main_#t~nondet1#1; 5270#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5269#L29-2 havoc main_#t~nondet1#1; 5268#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5267#L29-2 havoc main_#t~nondet1#1; 5266#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5265#L29-2 havoc main_#t~nondet1#1; 5264#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5263#L29-2 havoc main_#t~nondet1#1; 5262#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5261#L29-2 havoc main_#t~nondet1#1; 5260#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5259#L29-2 havoc main_#t~nondet1#1; 5258#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5257#L29-2 havoc main_#t~nondet1#1; 5256#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5255#L29-2 havoc main_#t~nondet1#1; 5254#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5253#L29-2 havoc main_#t~nondet1#1; 5252#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5251#L29-2 havoc main_#t~nondet1#1; 5250#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5249#L29-2 havoc main_#t~nondet1#1; 5248#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5247#L29-2 havoc main_#t~nondet1#1; 5246#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5245#L29-2 havoc main_#t~nondet1#1; 5244#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5243#L29-2 havoc main_#t~nondet1#1; 5242#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5241#L29-2 havoc main_#t~nondet1#1; 5240#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5239#L29-2 havoc main_#t~nondet1#1; 5238#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5237#L29-2 havoc main_#t~nondet1#1; 5236#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5235#L29-2 havoc main_#t~nondet1#1; 5234#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5233#L29-2 havoc main_#t~nondet1#1; 5232#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5231#L29-2 havoc main_#t~nondet1#1; 5230#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5229#L29-2 havoc main_#t~nondet1#1; 5228#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5227#L29-2 havoc main_#t~nondet1#1; 5226#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5225#L29-2 havoc main_#t~nondet1#1; 5224#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5223#L29-2 havoc main_#t~nondet1#1; 5222#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5221#L29-2 havoc main_#t~nondet1#1; 5220#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5219#L29-2 havoc main_#t~nondet1#1; 5218#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5217#L29-2 havoc main_#t~nondet1#1; 5216#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5215#L29-2 havoc main_#t~nondet1#1; 5214#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5213#L29-2 havoc main_#t~nondet1#1; 5212#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5211#L29-2 havoc main_#t~nondet1#1; 5210#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5209#L29-2 havoc main_#t~nondet1#1; 5208#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5207#L29-2 havoc main_#t~nondet1#1; 5206#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5205#L29-2 havoc main_#t~nondet1#1; 5204#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5203#L29-2 havoc main_#t~nondet1#1; 5188#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 5184#L29-3 assume main_~i~0#1 >= 100; 5185#L32 [2024-11-19 14:46:33,244 INFO L747 eck$LassoCheckResult]: Loop: 5185#L32 assume true; 5185#L32 [2024-11-19 14:46:33,245 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:33,245 INFO L85 PathProgramCache]: Analyzing trace with hash -41810454, now seen corresponding path program 5 times [2024-11-19 14:46:33,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:33,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294986434] [2024-11-19 14:46:33,245 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:46:33,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:33,288 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-11-19 14:46:33,288 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:34,562 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:34,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:34,564 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294986434] [2024-11-19 14:46:34,564 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1294986434] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:34,565 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1909610202] [2024-11-19 14:46:34,565 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:46:34,565 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:34,565 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:34,567 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:34,569 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-19 14:46:34,641 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-11-19 14:46:34,642 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:34,643 INFO L255 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 48 conjuncts are in the unsatisfiable core [2024-11-19 14:46:34,646 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:34,808 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:34,808 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:46:37,207 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:37,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1909610202] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:46:37,207 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:46:37,208 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 95 [2024-11-19 14:46:37,208 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825816476] [2024-11-19 14:46:37,208 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:46:37,208 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:37,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:37,209 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 11 times [2024-11-19 14:46:37,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:37,209 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372807480] [2024-11-19 14:46:37,209 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:46:37,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:37,210 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:46:37,211 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:46:37,211 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:37,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:37,211 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:37,216 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:37,218 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2024-11-19 14:46:37,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2024-11-19 14:46:37,221 INFO L87 Difference]: Start difference. First operand 195 states and 243 transitions. cyclomatic complexity: 51 Second operand has 96 states, 95 states have (on average 2.042105263157895) internal successors, (194), 96 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:38,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:38,850 INFO L93 Difference]: Finished difference Result 7250 states and 7395 transitions. [2024-11-19 14:46:38,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7250 states and 7395 transitions. [2024-11-19 14:46:38,886 INFO L131 ngComponentsAnalysis]: Automaton has 49 accepting balls. 49 [2024-11-19 14:46:38,913 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7250 states to 7154 states and 7299 transitions. [2024-11-19 14:46:38,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153 [2024-11-19 14:46:38,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153 [2024-11-19 14:46:38,913 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7154 states and 7299 transitions. [2024-11-19 14:46:38,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:38,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7154 states and 7299 transitions. [2024-11-19 14:46:38,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7154 states and 7299 transitions. [2024-11-19 14:46:38,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7154 to 291. [2024-11-19 14:46:38,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 291 states, 291 states have (on average 1.3298969072164948) internal successors, (387), 290 states have internal predecessors, (387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:38,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 387 transitions. [2024-11-19 14:46:38,949 INFO L240 hiAutomatonCegarLoop]: Abstraction has 291 states and 387 transitions. [2024-11-19 14:46:38,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2024-11-19 14:46:38,952 INFO L425 stractBuchiCegarLoop]: Abstraction has 291 states and 387 transitions. [2024-11-19 14:46:38,953 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-19 14:46:38,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 387 transitions. [2024-11-19 14:46:38,954 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:38,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:38,955 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:38,959 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [47, 46, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 14:46:38,960 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:38,960 INFO L745 eck$LassoCheckResult]: Stem: 13314#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 13315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 13320#L26 main_~i~0#1 := 0; 13321#L29-2 havoc main_#t~nondet1#1; 13323#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 13312#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 13313#L35-2 havoc main_#t~nondet3#1; 13319#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13326#L35-2 havoc main_#t~nondet3#1; 13600#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13599#L35-2 havoc main_#t~nondet3#1; 13598#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13597#L35-2 havoc main_#t~nondet3#1; 13596#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13595#L35-2 havoc main_#t~nondet3#1; 13594#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13593#L35-2 havoc main_#t~nondet3#1; 13592#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13591#L35-2 havoc main_#t~nondet3#1; 13590#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13589#L35-2 havoc main_#t~nondet3#1; 13588#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13587#L35-2 havoc main_#t~nondet3#1; 13586#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13585#L35-2 havoc main_#t~nondet3#1; 13584#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13583#L35-2 havoc main_#t~nondet3#1; 13582#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13581#L35-2 havoc main_#t~nondet3#1; 13580#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13579#L35-2 havoc main_#t~nondet3#1; 13578#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13577#L35-2 havoc main_#t~nondet3#1; 13576#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13575#L35-2 havoc main_#t~nondet3#1; 13574#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13573#L35-2 havoc main_#t~nondet3#1; 13572#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13571#L35-2 havoc main_#t~nondet3#1; 13570#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13569#L35-2 havoc main_#t~nondet3#1; 13568#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13567#L35-2 havoc main_#t~nondet3#1; 13566#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13565#L35-2 havoc main_#t~nondet3#1; 13564#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13563#L35-2 havoc main_#t~nondet3#1; 13562#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13561#L35-2 havoc main_#t~nondet3#1; 13560#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13559#L35-2 havoc main_#t~nondet3#1; 13558#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13557#L35-2 havoc main_#t~nondet3#1; 13556#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13555#L35-2 havoc main_#t~nondet3#1; 13554#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13553#L35-2 havoc main_#t~nondet3#1; 13552#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13551#L35-2 havoc main_#t~nondet3#1; 13550#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13549#L35-2 havoc main_#t~nondet3#1; 13548#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13547#L35-2 havoc main_#t~nondet3#1; 13546#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13545#L35-2 havoc main_#t~nondet3#1; 13544#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13543#L35-2 havoc main_#t~nondet3#1; 13542#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13541#L35-2 havoc main_#t~nondet3#1; 13540#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13539#L35-2 havoc main_#t~nondet3#1; 13538#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13537#L35-2 havoc main_#t~nondet3#1; 13536#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13535#L35-2 havoc main_#t~nondet3#1; 13534#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13533#L35-2 havoc main_#t~nondet3#1; 13532#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13531#L35-2 havoc main_#t~nondet3#1; 13530#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13529#L35-2 havoc main_#t~nondet3#1; 13528#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13527#L35-2 havoc main_#t~nondet3#1; 13526#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13525#L35-2 havoc main_#t~nondet3#1; 13524#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13523#L35-2 havoc main_#t~nondet3#1; 13522#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13521#L35-2 havoc main_#t~nondet3#1; 13520#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13519#L35-2 havoc main_#t~nondet3#1; 13518#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13517#L35-2 havoc main_#t~nondet3#1; 13516#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13515#L35-2 havoc main_#t~nondet3#1; 13514#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13513#L35-2 havoc main_#t~nondet3#1; 13512#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13511#L35-2 havoc main_#t~nondet3#1; 13325#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 13322#L35-3 assume main_~j~0#1 >= 100; 13311#L32 [2024-11-19 14:46:38,960 INFO L747 eck$LassoCheckResult]: Loop: 13311#L32 assume true; 13311#L32 [2024-11-19 14:46:38,960 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:38,960 INFO L85 PathProgramCache]: Analyzing trace with hash -174540373, now seen corresponding path program 5 times [2024-11-19 14:46:38,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:38,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498119707] [2024-11-19 14:46:38,961 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:46:38,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:39,020 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-11-19 14:46:39,024 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:40,470 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:40,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:40,470 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1498119707] [2024-11-19 14:46:40,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1498119707] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:40,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1983329452] [2024-11-19 14:46:40,471 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 14:46:40,471 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:40,471 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:40,472 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:40,474 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-19 14:46:40,568 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-11-19 14:46:40,568 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:40,570 INFO L255 TraceCheckSpWp]: Trace formula consists of 350 conjuncts, 48 conjuncts are in the unsatisfiable core [2024-11-19 14:46:40,574 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:40,744 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:40,744 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:46:42,995 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:42,996 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1983329452] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:46:42,996 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:46:42,996 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 95 [2024-11-19 14:46:42,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395306849] [2024-11-19 14:46:42,996 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:46:42,997 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:42,997 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:42,997 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 12 times [2024-11-19 14:46:42,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:42,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2048746309] [2024-11-19 14:46:42,999 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:46:42,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:43,001 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2024-11-19 14:46:43,001 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:46:43,001 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:43,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:43,002 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:43,004 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:43,005 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2024-11-19 14:46:43,007 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2024-11-19 14:46:43,007 INFO L87 Difference]: Start difference. First operand 291 states and 387 transitions. cyclomatic complexity: 99 Second operand has 96 states, 95 states have (on average 2.0736842105263156) internal successors, (197), 96 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:43,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:43,149 INFO L93 Difference]: Finished difference Result 484 states and 580 transitions. [2024-11-19 14:46:43,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 484 states and 580 transitions. [2024-11-19 14:46:43,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:43,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 484 states to 388 states and 484 transitions. [2024-11-19 14:46:43,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-19 14:46:43,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-19 14:46:43,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 388 states and 484 transitions. [2024-11-19 14:46:43,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:43,155 INFO L218 hiAutomatonCegarLoop]: Abstraction has 388 states and 484 transitions. [2024-11-19 14:46:43,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 388 states and 484 transitions. [2024-11-19 14:46:43,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 388 to 387. [2024-11-19 14:46:43,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 387 states, 387 states have (on average 1.248062015503876) internal successors, (483), 386 states have internal predecessors, (483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:43,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 387 states to 387 states and 483 transitions. [2024-11-19 14:46:43,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 387 states and 483 transitions. [2024-11-19 14:46:43,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2024-11-19 14:46:43,162 INFO L425 stractBuchiCegarLoop]: Abstraction has 387 states and 483 transitions. [2024-11-19 14:46:43,162 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-19 14:46:43,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 387 states and 483 transitions. [2024-11-19 14:46:43,164 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:43,164 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:43,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:43,167 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 1, 1, 1, 1, 1] [2024-11-19 14:46:43,171 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:43,171 INFO L745 eck$LassoCheckResult]: Stem: 14791#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 14792#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 14795#L26 main_~i~0#1 := 0; 14796#L29-2 havoc main_#t~nondet1#1; 14789#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14790#L29-2 havoc main_#t~nondet1#1; 14800#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14987#L29-2 havoc main_#t~nondet1#1; 14986#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14985#L29-2 havoc main_#t~nondet1#1; 14984#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14983#L29-2 havoc main_#t~nondet1#1; 14982#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14981#L29-2 havoc main_#t~nondet1#1; 14980#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14979#L29-2 havoc main_#t~nondet1#1; 14978#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14977#L29-2 havoc main_#t~nondet1#1; 14976#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14975#L29-2 havoc main_#t~nondet1#1; 14974#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14973#L29-2 havoc main_#t~nondet1#1; 14972#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14971#L29-2 havoc main_#t~nondet1#1; 14970#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14969#L29-2 havoc main_#t~nondet1#1; 14968#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14967#L29-2 havoc main_#t~nondet1#1; 14966#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14965#L29-2 havoc main_#t~nondet1#1; 14964#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14963#L29-2 havoc main_#t~nondet1#1; 14962#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14961#L29-2 havoc main_#t~nondet1#1; 14960#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14959#L29-2 havoc main_#t~nondet1#1; 14958#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14957#L29-2 havoc main_#t~nondet1#1; 14956#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14955#L29-2 havoc main_#t~nondet1#1; 14954#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14953#L29-2 havoc main_#t~nondet1#1; 14952#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14951#L29-2 havoc main_#t~nondet1#1; 14950#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14949#L29-2 havoc main_#t~nondet1#1; 14948#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14947#L29-2 havoc main_#t~nondet1#1; 14946#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14945#L29-2 havoc main_#t~nondet1#1; 14944#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14943#L29-2 havoc main_#t~nondet1#1; 14942#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14941#L29-2 havoc main_#t~nondet1#1; 14940#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14939#L29-2 havoc main_#t~nondet1#1; 14938#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14937#L29-2 havoc main_#t~nondet1#1; 14936#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14935#L29-2 havoc main_#t~nondet1#1; 14934#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14933#L29-2 havoc main_#t~nondet1#1; 14932#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14931#L29-2 havoc main_#t~nondet1#1; 14930#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14929#L29-2 havoc main_#t~nondet1#1; 14928#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14927#L29-2 havoc main_#t~nondet1#1; 14926#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14925#L29-2 havoc main_#t~nondet1#1; 14924#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14923#L29-2 havoc main_#t~nondet1#1; 14922#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14921#L29-2 havoc main_#t~nondet1#1; 14920#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14919#L29-2 havoc main_#t~nondet1#1; 14918#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14917#L29-2 havoc main_#t~nondet1#1; 14916#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14915#L29-2 havoc main_#t~nondet1#1; 14914#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14913#L29-2 havoc main_#t~nondet1#1; 14912#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14911#L29-2 havoc main_#t~nondet1#1; 14910#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14909#L29-2 havoc main_#t~nondet1#1; 14908#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14907#L29-2 havoc main_#t~nondet1#1; 14906#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14905#L29-2 havoc main_#t~nondet1#1; 14904#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14903#L29-2 havoc main_#t~nondet1#1; 14902#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14901#L29-2 havoc main_#t~nondet1#1; 14900#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14899#L29-2 havoc main_#t~nondet1#1; 14898#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14897#L29-2 havoc main_#t~nondet1#1; 14896#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14895#L29-2 havoc main_#t~nondet1#1; 14894#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14893#L29-2 havoc main_#t~nondet1#1; 14892#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14891#L29-2 havoc main_#t~nondet1#1; 14890#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14889#L29-2 havoc main_#t~nondet1#1; 14888#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14887#L29-2 havoc main_#t~nondet1#1; 14886#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14885#L29-2 havoc main_#t~nondet1#1; 14884#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14883#L29-2 havoc main_#t~nondet1#1; 14882#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14881#L29-2 havoc main_#t~nondet1#1; 14880#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14879#L29-2 havoc main_#t~nondet1#1; 14878#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14877#L29-2 havoc main_#t~nondet1#1; 14876#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14875#L29-2 havoc main_#t~nondet1#1; 14874#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14873#L29-2 havoc main_#t~nondet1#1; 14872#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14871#L29-2 havoc main_#t~nondet1#1; 14870#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14869#L29-2 havoc main_#t~nondet1#1; 14868#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14867#L29-2 havoc main_#t~nondet1#1; 14866#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14865#L29-2 havoc main_#t~nondet1#1; 14864#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14863#L29-2 havoc main_#t~nondet1#1; 14862#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14861#L29-2 havoc main_#t~nondet1#1; 14860#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14859#L29-2 havoc main_#t~nondet1#1; 14858#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14857#L29-2 havoc main_#t~nondet1#1; 14856#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14855#L29-2 havoc main_#t~nondet1#1; 14854#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14853#L29-2 havoc main_#t~nondet1#1; 14852#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14851#L29-2 havoc main_#t~nondet1#1; 14850#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14849#L29-2 havoc main_#t~nondet1#1; 14848#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14847#L29-2 havoc main_#t~nondet1#1; 14846#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14845#L29-2 havoc main_#t~nondet1#1; 14844#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14843#L29-2 havoc main_#t~nondet1#1; 14842#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14841#L29-2 havoc main_#t~nondet1#1; 14840#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14839#L29-2 havoc main_#t~nondet1#1; 14838#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14837#L29-2 havoc main_#t~nondet1#1; 14836#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14835#L29-2 havoc main_#t~nondet1#1; 14834#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14833#L29-2 havoc main_#t~nondet1#1; 14832#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14831#L29-2 havoc main_#t~nondet1#1; 14830#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14829#L29-2 havoc main_#t~nondet1#1; 14828#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14827#L29-2 havoc main_#t~nondet1#1; 14826#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14825#L29-2 havoc main_#t~nondet1#1; 14824#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14823#L29-2 havoc main_#t~nondet1#1; 14822#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14821#L29-2 havoc main_#t~nondet1#1; 14820#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14819#L29-2 havoc main_#t~nondet1#1; 14818#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14817#L29-2 havoc main_#t~nondet1#1; 14816#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14815#L29-2 havoc main_#t~nondet1#1; 14814#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14813#L29-2 havoc main_#t~nondet1#1; 14812#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14811#L29-2 havoc main_#t~nondet1#1; 14810#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14809#L29-2 havoc main_#t~nondet1#1; 14808#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14807#L29-2 havoc main_#t~nondet1#1; 14806#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14805#L29-2 havoc main_#t~nondet1#1; 14804#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14803#L29-2 havoc main_#t~nondet1#1; 14788#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 14784#L29-3 assume main_~i~0#1 >= 100; 14785#L32 [2024-11-19 14:46:43,171 INFO L747 eck$LassoCheckResult]: Loop: 14785#L32 assume true; 14785#L32 [2024-11-19 14:46:43,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:43,172 INFO L85 PathProgramCache]: Analyzing trace with hash 1558585082, now seen corresponding path program 6 times [2024-11-19 14:46:43,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:43,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575819057] [2024-11-19 14:46:43,172 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:46:43,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:43,242 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2024-11-19 14:46:43,242 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:47,519 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:47,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:47,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [575819057] [2024-11-19 14:46:47,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [575819057] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:47,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [174601174] [2024-11-19 14:46:47,520 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:46:47,520 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:47,520 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:47,523 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:47,524 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-11-19 14:46:47,671 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2024-11-19 14:46:47,671 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:47,674 INFO L255 TraceCheckSpWp]: Trace formula consists of 493 conjuncts, 96 conjuncts are in the unsatisfiable core [2024-11-19 14:46:47,681 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:47,958 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:47,958 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:46:51,620 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:51,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [174601174] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:46:51,621 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:46:51,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 102 [2024-11-19 14:46:51,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116400617] [2024-11-19 14:46:51,621 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:46:51,622 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:46:51,622 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:51,622 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 13 times [2024-11-19 14:46:51,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:51,622 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [88594791] [2024-11-19 14:46:51,622 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:46:51,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:51,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:51,624 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:46:51,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:46:51,625 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:46:51,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:46:51,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2024-11-19 14:46:51,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2024-11-19 14:46:51,631 INFO L87 Difference]: Start difference. First operand 387 states and 483 transitions. cyclomatic complexity: 99 Second operand has 103 states, 102 states have (on average 2.0588235294117645) internal successors, (210), 103 states have internal predecessors, (210), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:53,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:46:53,149 INFO L93 Difference]: Finished difference Result 10592 states and 10701 transitions. [2024-11-19 14:46:53,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10592 states and 10701 transitions. [2024-11-19 14:46:53,204 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2024-11-19 14:46:53,243 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10592 states to 10580 states and 10689 transitions. [2024-11-19 14:46:53,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2024-11-19 14:46:53,246 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2024-11-19 14:46:53,246 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10580 states and 10689 transitions. [2024-11-19 14:46:53,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:46:53,256 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10580 states and 10689 transitions. [2024-11-19 14:46:53,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10580 states and 10689 transitions. [2024-11-19 14:46:53,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10580 to 399. [2024-11-19 14:46:53,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 399 states, 399 states have (on average 1.255639097744361) internal successors, (501), 398 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:46:53,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 399 states and 501 transitions. [2024-11-19 14:46:53,314 INFO L240 hiAutomatonCegarLoop]: Abstraction has 399 states and 501 transitions. [2024-11-19 14:46:53,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2024-11-19 14:46:53,316 INFO L425 stractBuchiCegarLoop]: Abstraction has 399 states and 501 transitions. [2024-11-19 14:46:53,316 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-19 14:46:53,316 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 399 states and 501 transitions. [2024-11-19 14:46:53,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:46:53,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:46:53,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:46:53,320 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 14:46:53,320 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:46:53,320 INFO L745 eck$LassoCheckResult]: Stem: 27031#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 27032#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 27037#L26 main_~i~0#1 := 0; 27038#L29-2 havoc main_#t~nondet1#1; 27040#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 27029#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 27030#L35-2 havoc main_#t~nondet3#1; 27036#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27043#L35-2 havoc main_#t~nondet3#1; 27425#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27424#L35-2 havoc main_#t~nondet3#1; 27423#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27422#L35-2 havoc main_#t~nondet3#1; 27421#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27420#L35-2 havoc main_#t~nondet3#1; 27419#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27418#L35-2 havoc main_#t~nondet3#1; 27417#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27416#L35-2 havoc main_#t~nondet3#1; 27415#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27414#L35-2 havoc main_#t~nondet3#1; 27413#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27412#L35-2 havoc main_#t~nondet3#1; 27411#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27410#L35-2 havoc main_#t~nondet3#1; 27409#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27408#L35-2 havoc main_#t~nondet3#1; 27407#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27406#L35-2 havoc main_#t~nondet3#1; 27405#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27404#L35-2 havoc main_#t~nondet3#1; 27403#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27402#L35-2 havoc main_#t~nondet3#1; 27401#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27400#L35-2 havoc main_#t~nondet3#1; 27399#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27398#L35-2 havoc main_#t~nondet3#1; 27397#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27396#L35-2 havoc main_#t~nondet3#1; 27395#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27394#L35-2 havoc main_#t~nondet3#1; 27393#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27392#L35-2 havoc main_#t~nondet3#1; 27391#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27390#L35-2 havoc main_#t~nondet3#1; 27389#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27388#L35-2 havoc main_#t~nondet3#1; 27387#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27386#L35-2 havoc main_#t~nondet3#1; 27385#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27384#L35-2 havoc main_#t~nondet3#1; 27383#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27382#L35-2 havoc main_#t~nondet3#1; 27381#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27380#L35-2 havoc main_#t~nondet3#1; 27379#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27378#L35-2 havoc main_#t~nondet3#1; 27377#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27376#L35-2 havoc main_#t~nondet3#1; 27375#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27374#L35-2 havoc main_#t~nondet3#1; 27373#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27372#L35-2 havoc main_#t~nondet3#1; 27371#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27370#L35-2 havoc main_#t~nondet3#1; 27369#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27368#L35-2 havoc main_#t~nondet3#1; 27367#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27366#L35-2 havoc main_#t~nondet3#1; 27365#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27364#L35-2 havoc main_#t~nondet3#1; 27363#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27362#L35-2 havoc main_#t~nondet3#1; 27361#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27360#L35-2 havoc main_#t~nondet3#1; 27359#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27358#L35-2 havoc main_#t~nondet3#1; 27357#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27356#L35-2 havoc main_#t~nondet3#1; 27355#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27354#L35-2 havoc main_#t~nondet3#1; 27353#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27352#L35-2 havoc main_#t~nondet3#1; 27351#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27350#L35-2 havoc main_#t~nondet3#1; 27349#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27348#L35-2 havoc main_#t~nondet3#1; 27347#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27346#L35-2 havoc main_#t~nondet3#1; 27345#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27344#L35-2 havoc main_#t~nondet3#1; 27343#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27342#L35-2 havoc main_#t~nondet3#1; 27341#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27340#L35-2 havoc main_#t~nondet3#1; 27339#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27338#L35-2 havoc main_#t~nondet3#1; 27337#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27336#L35-2 havoc main_#t~nondet3#1; 27335#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27334#L35-2 havoc main_#t~nondet3#1; 27333#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27332#L35-2 havoc main_#t~nondet3#1; 27331#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27330#L35-2 havoc main_#t~nondet3#1; 27329#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27328#L35-2 havoc main_#t~nondet3#1; 27327#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27326#L35-2 havoc main_#t~nondet3#1; 27325#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27324#L35-2 havoc main_#t~nondet3#1; 27323#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27322#L35-2 havoc main_#t~nondet3#1; 27321#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27320#L35-2 havoc main_#t~nondet3#1; 27319#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27318#L35-2 havoc main_#t~nondet3#1; 27317#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27316#L35-2 havoc main_#t~nondet3#1; 27315#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27314#L35-2 havoc main_#t~nondet3#1; 27313#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27312#L35-2 havoc main_#t~nondet3#1; 27311#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27310#L35-2 havoc main_#t~nondet3#1; 27309#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27308#L35-2 havoc main_#t~nondet3#1; 27307#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27306#L35-2 havoc main_#t~nondet3#1; 27305#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27304#L35-2 havoc main_#t~nondet3#1; 27303#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27302#L35-2 havoc main_#t~nondet3#1; 27301#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27300#L35-2 havoc main_#t~nondet3#1; 27299#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27298#L35-2 havoc main_#t~nondet3#1; 27297#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27296#L35-2 havoc main_#t~nondet3#1; 27295#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27294#L35-2 havoc main_#t~nondet3#1; 27293#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27292#L35-2 havoc main_#t~nondet3#1; 27291#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27290#L35-2 havoc main_#t~nondet3#1; 27289#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27288#L35-2 havoc main_#t~nondet3#1; 27287#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27286#L35-2 havoc main_#t~nondet3#1; 27285#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27284#L35-2 havoc main_#t~nondet3#1; 27283#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27282#L35-2 havoc main_#t~nondet3#1; 27281#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27280#L35-2 havoc main_#t~nondet3#1; 27279#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27278#L35-2 havoc main_#t~nondet3#1; 27277#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27276#L35-2 havoc main_#t~nondet3#1; 27275#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27274#L35-2 havoc main_#t~nondet3#1; 27273#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27272#L35-2 havoc main_#t~nondet3#1; 27271#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27270#L35-2 havoc main_#t~nondet3#1; 27269#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27268#L35-2 havoc main_#t~nondet3#1; 27267#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27266#L35-2 havoc main_#t~nondet3#1; 27265#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27264#L35-2 havoc main_#t~nondet3#1; 27263#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27262#L35-2 havoc main_#t~nondet3#1; 27261#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27260#L35-2 havoc main_#t~nondet3#1; 27259#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27258#L35-2 havoc main_#t~nondet3#1; 27257#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27256#L35-2 havoc main_#t~nondet3#1; 27255#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27254#L35-2 havoc main_#t~nondet3#1; 27253#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27252#L35-2 havoc main_#t~nondet3#1; 27251#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27250#L35-2 havoc main_#t~nondet3#1; 27249#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27248#L35-2 havoc main_#t~nondet3#1; 27247#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27246#L35-2 havoc main_#t~nondet3#1; 27245#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27244#L35-2 havoc main_#t~nondet3#1; 27243#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27242#L35-2 havoc main_#t~nondet3#1; 27241#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27240#L35-2 havoc main_#t~nondet3#1; 27042#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 27039#L35-3 assume main_~j~0#1 >= 100; 27028#L32 [2024-11-19 14:46:53,321 INFO L747 eck$LassoCheckResult]: Loop: 27028#L32 assume true; 27028#L32 [2024-11-19 14:46:53,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:46:53,321 INFO L85 PathProgramCache]: Analyzing trace with hash 1679145147, now seen corresponding path program 6 times [2024-11-19 14:46:53,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:46:53,322 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227005635] [2024-11-19 14:46:53,322 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:46:53,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:46:53,433 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2024-11-19 14:46:53,433 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:57,737 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:57,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 14:46:57,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227005635] [2024-11-19 14:46:57,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [227005635] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-19 14:46:57,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [80221115] [2024-11-19 14:46:57,738 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 14:46:57,739 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-19 14:46:57,739 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 14:46:57,740 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-19 14:46:57,750 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-11-19 14:46:57,904 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2024-11-19 14:46:57,904 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 14:46:57,907 INFO L255 TraceCheckSpWp]: Trace formula consists of 686 conjuncts, 96 conjuncts are in the unsatisfiable core [2024-11-19 14:46:57,911 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 14:46:58,159 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:46:58,159 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-19 14:47:01,668 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 14:47:01,668 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [80221115] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-19 14:47:01,668 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-19 14:47:01,669 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 102 [2024-11-19 14:47:01,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260537971] [2024-11-19 14:47:01,669 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-19 14:47:01,669 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 14:47:01,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:47:01,670 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 14 times [2024-11-19 14:47:01,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:47:01,670 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068790676] [2024-11-19 14:47:01,670 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 14:47:01,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:47:01,671 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 14:47:01,671 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:47:01,671 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:47:01,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:47:01,672 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:47:01,676 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 14:47:01,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2024-11-19 14:47:01,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2024-11-19 14:47:01,680 INFO L87 Difference]: Start difference. First operand 399 states and 501 transitions. cyclomatic complexity: 105 Second operand has 103 states, 102 states have (on average 2.088235294117647) internal successors, (213), 103 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:47:01,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 14:47:01,767 INFO L93 Difference]: Finished difference Result 424 states and 526 transitions. [2024-11-19 14:47:01,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 424 states and 526 transitions. [2024-11-19 14:47:01,768 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:47:01,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 424 states to 412 states and 514 transitions. [2024-11-19 14:47:01,770 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-19 14:47:01,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-19 14:47:01,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 412 states and 514 transitions. [2024-11-19 14:47:01,771 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 14:47:01,771 INFO L218 hiAutomatonCegarLoop]: Abstraction has 412 states and 514 transitions. [2024-11-19 14:47:01,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 412 states and 514 transitions. [2024-11-19 14:47:01,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 412 to 411. [2024-11-19 14:47:01,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 411 states, 411 states have (on average 1.2481751824817517) internal successors, (513), 410 states have internal predecessors, (513), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 14:47:01,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 411 states to 411 states and 513 transitions. [2024-11-19 14:47:01,776 INFO L240 hiAutomatonCegarLoop]: Abstraction has 411 states and 513 transitions. [2024-11-19 14:47:01,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2024-11-19 14:47:01,777 INFO L425 stractBuchiCegarLoop]: Abstraction has 411 states and 513 transitions. [2024-11-19 14:47:01,777 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-19 14:47:01,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 411 states and 513 transitions. [2024-11-19 14:47:01,778 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-19 14:47:01,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 14:47:01,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 14:47:01,780 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [101, 100, 1, 1, 1, 1, 1] [2024-11-19 14:47:01,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-19 14:47:01,781 INFO L745 eck$LassoCheckResult]: Stem: 29136#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 29137#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 29143#L26 main_~i~0#1 := 0; 29144#L29-2 havoc main_#t~nondet1#1; 29139#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29140#L29-2 havoc main_#t~nondet1#1; 29146#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29347#L29-2 havoc main_#t~nondet1#1; 29346#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29345#L29-2 havoc main_#t~nondet1#1; 29344#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29343#L29-2 havoc main_#t~nondet1#1; 29342#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29341#L29-2 havoc main_#t~nondet1#1; 29340#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29339#L29-2 havoc main_#t~nondet1#1; 29338#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29337#L29-2 havoc main_#t~nondet1#1; 29336#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29335#L29-2 havoc main_#t~nondet1#1; 29334#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29333#L29-2 havoc main_#t~nondet1#1; 29332#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29331#L29-2 havoc main_#t~nondet1#1; 29330#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29329#L29-2 havoc main_#t~nondet1#1; 29328#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29327#L29-2 havoc main_#t~nondet1#1; 29326#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29325#L29-2 havoc main_#t~nondet1#1; 29324#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29323#L29-2 havoc main_#t~nondet1#1; 29322#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29321#L29-2 havoc main_#t~nondet1#1; 29320#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29319#L29-2 havoc main_#t~nondet1#1; 29318#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29317#L29-2 havoc main_#t~nondet1#1; 29316#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29315#L29-2 havoc main_#t~nondet1#1; 29314#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29313#L29-2 havoc main_#t~nondet1#1; 29312#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29311#L29-2 havoc main_#t~nondet1#1; 29310#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29309#L29-2 havoc main_#t~nondet1#1; 29308#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29307#L29-2 havoc main_#t~nondet1#1; 29306#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29305#L29-2 havoc main_#t~nondet1#1; 29304#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29303#L29-2 havoc main_#t~nondet1#1; 29302#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29301#L29-2 havoc main_#t~nondet1#1; 29300#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29299#L29-2 havoc main_#t~nondet1#1; 29298#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29297#L29-2 havoc main_#t~nondet1#1; 29296#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29295#L29-2 havoc main_#t~nondet1#1; 29294#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29293#L29-2 havoc main_#t~nondet1#1; 29292#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29291#L29-2 havoc main_#t~nondet1#1; 29290#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29289#L29-2 havoc main_#t~nondet1#1; 29288#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29287#L29-2 havoc main_#t~nondet1#1; 29286#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29285#L29-2 havoc main_#t~nondet1#1; 29284#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29283#L29-2 havoc main_#t~nondet1#1; 29282#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29281#L29-2 havoc main_#t~nondet1#1; 29280#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29279#L29-2 havoc main_#t~nondet1#1; 29278#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29277#L29-2 havoc main_#t~nondet1#1; 29276#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29275#L29-2 havoc main_#t~nondet1#1; 29274#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29273#L29-2 havoc main_#t~nondet1#1; 29272#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29271#L29-2 havoc main_#t~nondet1#1; 29270#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29269#L29-2 havoc main_#t~nondet1#1; 29268#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29267#L29-2 havoc main_#t~nondet1#1; 29266#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29265#L29-2 havoc main_#t~nondet1#1; 29264#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29263#L29-2 havoc main_#t~nondet1#1; 29262#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29261#L29-2 havoc main_#t~nondet1#1; 29260#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29259#L29-2 havoc main_#t~nondet1#1; 29258#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29257#L29-2 havoc main_#t~nondet1#1; 29256#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29255#L29-2 havoc main_#t~nondet1#1; 29254#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29253#L29-2 havoc main_#t~nondet1#1; 29252#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29251#L29-2 havoc main_#t~nondet1#1; 29250#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29249#L29-2 havoc main_#t~nondet1#1; 29248#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29247#L29-2 havoc main_#t~nondet1#1; 29246#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29245#L29-2 havoc main_#t~nondet1#1; 29244#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29243#L29-2 havoc main_#t~nondet1#1; 29242#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29241#L29-2 havoc main_#t~nondet1#1; 29240#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29239#L29-2 havoc main_#t~nondet1#1; 29238#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29237#L29-2 havoc main_#t~nondet1#1; 29236#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29235#L29-2 havoc main_#t~nondet1#1; 29234#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29233#L29-2 havoc main_#t~nondet1#1; 29232#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29231#L29-2 havoc main_#t~nondet1#1; 29230#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29229#L29-2 havoc main_#t~nondet1#1; 29228#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29227#L29-2 havoc main_#t~nondet1#1; 29226#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29225#L29-2 havoc main_#t~nondet1#1; 29224#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29223#L29-2 havoc main_#t~nondet1#1; 29222#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29221#L29-2 havoc main_#t~nondet1#1; 29220#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29219#L29-2 havoc main_#t~nondet1#1; 29218#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29217#L29-2 havoc main_#t~nondet1#1; 29216#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29215#L29-2 havoc main_#t~nondet1#1; 29214#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29213#L29-2 havoc main_#t~nondet1#1; 29212#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29211#L29-2 havoc main_#t~nondet1#1; 29210#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29209#L29-2 havoc main_#t~nondet1#1; 29208#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29207#L29-2 havoc main_#t~nondet1#1; 29206#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29205#L29-2 havoc main_#t~nondet1#1; 29204#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29203#L29-2 havoc main_#t~nondet1#1; 29202#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29201#L29-2 havoc main_#t~nondet1#1; 29200#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29199#L29-2 havoc main_#t~nondet1#1; 29198#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29197#L29-2 havoc main_#t~nondet1#1; 29196#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29195#L29-2 havoc main_#t~nondet1#1; 29194#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29193#L29-2 havoc main_#t~nondet1#1; 29192#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29191#L29-2 havoc main_#t~nondet1#1; 29190#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29189#L29-2 havoc main_#t~nondet1#1; 29188#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29187#L29-2 havoc main_#t~nondet1#1; 29186#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29185#L29-2 havoc main_#t~nondet1#1; 29184#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29183#L29-2 havoc main_#t~nondet1#1; 29182#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29181#L29-2 havoc main_#t~nondet1#1; 29180#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29179#L29-2 havoc main_#t~nondet1#1; 29178#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29177#L29-2 havoc main_#t~nondet1#1; 29176#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29175#L29-2 havoc main_#t~nondet1#1; 29174#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29173#L29-2 havoc main_#t~nondet1#1; 29172#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29171#L29-2 havoc main_#t~nondet1#1; 29170#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29169#L29-2 havoc main_#t~nondet1#1; 29168#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29167#L29-2 havoc main_#t~nondet1#1; 29166#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29165#L29-2 havoc main_#t~nondet1#1; 29164#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29163#L29-2 havoc main_#t~nondet1#1; 29162#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29161#L29-2 havoc main_#t~nondet1#1; 29160#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29159#L29-2 havoc main_#t~nondet1#1; 29158#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29157#L29-2 havoc main_#t~nondet1#1; 29154#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29153#L29-2 havoc main_#t~nondet1#1; 29152#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29151#L29-2 havoc main_#t~nondet1#1; 29150#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29149#L29-2 havoc main_#t~nondet1#1; 29138#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 29132#L29-3 assume main_~i~0#1 >= 100; 29133#L32 [2024-11-19 14:47:01,781 INFO L747 eck$LassoCheckResult]: Loop: 29133#L32 assume true; 29133#L32 [2024-11-19 14:47:01,781 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:47:01,781 INFO L85 PathProgramCache]: Analyzing trace with hash -608770916, now seen corresponding path program 7 times [2024-11-19 14:47:01,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:47:01,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493561055] [2024-11-19 14:47:01,782 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 14:47:01,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:47:01,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:47:01,831 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:47:01,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:47:01,884 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:47:01,885 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:47:01,885 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 15 times [2024-11-19 14:47:01,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:47:01,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501787204] [2024-11-19 14:47:01,886 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 14:47:01,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:47:01,887 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 14:47:01,888 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 14:47:01,888 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:47:01,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:47:01,888 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:47:01,889 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 14:47:01,889 INFO L85 PathProgramCache]: Analyzing trace with hash -1692029150, now seen corresponding path program 1 times [2024-11-19 14:47:01,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 14:47:01,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810981740] [2024-11-19 14:47:01,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 14:47:01,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 14:47:01,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:47:01,933 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:47:01,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:47:01,983 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 14:47:07,047 WARN L286 SmtUtils]: Spent 5.02s on a formula simplification. DAG size of input: 735 DAG size of output: 630 (called from [L 276] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaUtils.sequentialComposition) [2024-11-19 14:47:10,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:47:10,675 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 14:47:10,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 14:47:10,865 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.11 02:47:10 BoogieIcfgContainer [2024-11-19 14:47:10,865 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-19 14:47:10,866 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-19 14:47:10,866 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-19 14:47:10,866 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-19 14:47:10,867 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 02:46:26" (3/4) ... [2024-11-19 14:47:10,869 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-19 14:47:10,935 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-19 14:47:10,935 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-19 14:47:10,936 INFO L158 Benchmark]: Toolchain (without parser) took 45324.79ms. Allocated memory was 169.9MB in the beginning and 625.0MB in the end (delta: 455.1MB). Free memory was 107.7MB in the beginning and 465.5MB in the end (delta: -357.7MB). Peak memory consumption was 98.3MB. Max. memory is 16.1GB. [2024-11-19 14:47:10,936 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 96.5MB. Free memory is still 51.1MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-19 14:47:10,936 INFO L158 Benchmark]: CACSL2BoogieTranslator took 278.02ms. Allocated memory is still 169.9MB. Free memory was 107.7MB in the beginning and 139.5MB in the end (delta: -31.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2024-11-19 14:47:10,937 INFO L158 Benchmark]: Boogie Procedure Inliner took 27.86ms. Allocated memory is still 169.9MB. Free memory was 139.5MB in the beginning and 138.0MB in the end (delta: 1.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-19 14:47:10,937 INFO L158 Benchmark]: Boogie Preprocessor took 28.25ms. Allocated memory is still 169.9MB. Free memory was 138.0MB in the beginning and 136.6MB in the end (delta: 1.4MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-19 14:47:10,937 INFO L158 Benchmark]: RCFGBuilder took 260.81ms. Allocated memory is still 169.9MB. Free memory was 136.6MB in the beginning and 126.2MB in the end (delta: 10.4MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2024-11-19 14:47:10,937 INFO L158 Benchmark]: BuchiAutomizer took 44655.87ms. Allocated memory was 169.9MB in the beginning and 625.0MB in the end (delta: 455.1MB). Free memory was 126.2MB in the beginning and 471.8MB in the end (delta: -345.6MB). Peak memory consumption was 112.6MB. Max. memory is 16.1GB. [2024-11-19 14:47:10,938 INFO L158 Benchmark]: Witness Printer took 69.37ms. Allocated memory is still 625.0MB. Free memory was 471.8MB in the beginning and 465.5MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-19 14:47:10,939 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 96.5MB. Free memory is still 51.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 278.02ms. Allocated memory is still 169.9MB. Free memory was 107.7MB in the beginning and 139.5MB in the end (delta: -31.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 27.86ms. Allocated memory is still 169.9MB. Free memory was 139.5MB in the beginning and 138.0MB in the end (delta: 1.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 28.25ms. Allocated memory is still 169.9MB. Free memory was 138.0MB in the beginning and 136.6MB in the end (delta: 1.4MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 260.81ms. Allocated memory is still 169.9MB. Free memory was 136.6MB in the beginning and 126.2MB in the end (delta: 10.4MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 44655.87ms. Allocated memory was 169.9MB in the beginning and 625.0MB in the end (delta: 455.1MB). Free memory was 126.2MB in the beginning and 471.8MB in the end (delta: -345.6MB). Peak memory consumption was 112.6MB. Max. memory is 16.1GB. * Witness Printer took 69.37ms. Allocated memory is still 625.0MB. Free memory was 471.8MB in the beginning and 465.5MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (14 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -2 * i) + 1999999) and consists of 4 locations. 14 modules have a trivial ranking function, the largest among these consists of 103 locations. The remainder module has 411 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 44.5s and 16 iterations. TraceHistogramMax:101. Analysis of lassos took 39.3s. Construction of modules took 1.5s. Büchi inclusion checks took 3.4s. Highest rank in rank-based complementation 3. Minimization of det autom 0. Minimization of nondet autom 15. Automata minimization 0.2s AutomataMinimizationTime, 15 MinimizatonAttempts, 19320 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3676 SdHoareTripleChecker+Valid, 1.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3675 mSDsluCounter, 1578 SdHoareTripleChecker+Invalid, 1.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1430 mSDsCounter, 1095 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1700 IncrementalHoareTripleChecker+Invalid, 2795 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1095 mSolverCounterUnsat, 148 mSDtfsCounter, 1700 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT1 conc0 concLT0 SILN14 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital10 mio100 ax100 hnf100 lsp100 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq160 hnf93 smp100 dnf100 smp100 tf113 neg100 sie100 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: sat Degree: 0 Time: 57ms VariablesStem: 0 VariablesLoop: 2 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 24]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int i, j; [L27] i = 0 VAL [i=0] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=1] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=2] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=3] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=4] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=5] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=6] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=7] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=8] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=9] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=10] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=11] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=12] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=13] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=14] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=15] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=16] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=17] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=18] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=19] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=20] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=21] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=22] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=23] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=24] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=25] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=26] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=27] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=28] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=29] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=30] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=31] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=32] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=33] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=34] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=35] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=36] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=37] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=38] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=39] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=40] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=41] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=42] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=43] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=44] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=45] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=46] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=47] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=48] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=49] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=50] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=51] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=52] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=53] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=54] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=55] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=56] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=57] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=58] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=59] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=60] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=61] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=62] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=63] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=64] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=65] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=66] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=67] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=68] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=69] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=70] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=71] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=72] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=73] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=74] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=75] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=76] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=77] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=78] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=79] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=80] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=81] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=82] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=83] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=84] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=85] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=86] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=87] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=88] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=89] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=90] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=91] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=92] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=93] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=94] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=95] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=96] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=97] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=98] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=99] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=100] [L29] COND FALSE !(__VERIFIER_nondet_int() && i < 1000000) [L32] COND TRUE i >= 100 Loop: [L32] STUCK: goto STUCK; End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 24]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int i, j; [L27] i = 0 VAL [i=0] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=1] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=2] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=3] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=4] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=5] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=6] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=7] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=8] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=9] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=10] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=11] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=12] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=13] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=14] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=15] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=16] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=17] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=18] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=19] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=20] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=21] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=22] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=23] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=24] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=25] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=26] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=27] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=28] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=29] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=30] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=31] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=32] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=33] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=34] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=35] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=36] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=37] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=38] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=39] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=40] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=41] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=42] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=43] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=44] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=45] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=46] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=47] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=48] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=49] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=50] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=51] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=52] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=53] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=54] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=55] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=56] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=57] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=58] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=59] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=60] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=61] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=62] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=63] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=64] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=65] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=66] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=67] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=68] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=69] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=70] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=71] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=72] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=73] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=74] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=75] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=76] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=77] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=78] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=79] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=80] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=81] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=82] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=83] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=84] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=85] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=86] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=87] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=88] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=89] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=90] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=91] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=92] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=93] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=94] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=95] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=96] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=97] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=98] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=99] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=100] [L29] COND FALSE !(__VERIFIER_nondet_int() && i < 1000000) [L32] COND TRUE i >= 100 Loop: [L32] STUCK: goto STUCK; End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-19 14:47:10,977 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2024-11-19 14:47:11,172 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2024-11-19 14:47:11,371 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2024-11-19 14:47:11,572 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2024-11-19 14:47:11,772 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2024-11-19 14:47:11,973 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2024-11-19 14:47:12,172 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-11-19 14:47:12,373 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2024-11-19 14:47:12,573 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-11-19 14:47:12,773 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2024-11-19 14:47:12,973 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-11-19 14:47:13,173 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2024-11-19 14:47:13,375 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)