./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3061b6dc Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-assert-order-craig-3061b6d-m [2024-11-19 15:02:34,097 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-19 15:02:34,172 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-19 15:02:34,178 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-19 15:02:34,178 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-19 15:02:34,203 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-19 15:02:34,205 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-19 15:02:34,205 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-19 15:02:34,206 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-19 15:02:34,207 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-19 15:02:34,208 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-19 15:02:34,208 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-19 15:02:34,208 INFO L153 SettingsManager]: * Use SBE=true [2024-11-19 15:02:34,209 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-19 15:02:34,209 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-19 15:02:34,209 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-19 15:02:34,209 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-19 15:02:34,210 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-19 15:02:34,210 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-19 15:02:34,210 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-19 15:02:34,210 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-19 15:02:34,214 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-19 15:02:34,214 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-19 15:02:34,215 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-19 15:02:34,215 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-19 15:02:34,215 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-19 15:02:34,215 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-19 15:02:34,215 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-19 15:02:34,216 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-19 15:02:34,216 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-19 15:02:34,216 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-19 15:02:34,216 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-19 15:02:34,216 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-19 15:02:34,216 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-19 15:02:34,217 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-19 15:02:34,217 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-19 15:02:34,217 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-19 15:02:34,217 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-19 15:02:34,218 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-19 15:02:34,218 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 [2024-11-19 15:02:34,474 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-19 15:02:34,501 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-19 15:02:34,504 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-19 15:02:34,505 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-19 15:02:34,506 INFO L274 PluginConnector]: CDTParser initialized [2024-11-19 15:02:34,507 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2024-11-19 15:02:36,030 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-19 15:02:36,255 INFO L384 CDTParser]: Found 1 translation units. [2024-11-19 15:02:36,256 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2024-11-19 15:02:36,269 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0642262ff/b1e3665ed5494b859c5485e3cfc51497/FLAG75a801aa4 [2024-11-19 15:02:36,601 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0642262ff/b1e3665ed5494b859c5485e3cfc51497 [2024-11-19 15:02:36,604 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-19 15:02:36,605 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-19 15:02:36,606 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-19 15:02:36,606 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-19 15:02:36,611 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-19 15:02:36,612 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 03:02:36" (1/1) ... [2024-11-19 15:02:36,612 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@76d9c210 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:36, skipping insertion in model container [2024-11-19 15:02:36,612 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 03:02:36" (1/1) ... [2024-11-19 15:02:36,646 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-19 15:02:36,940 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 15:02:36,972 INFO L200 MainTranslator]: Completed pre-run [2024-11-19 15:02:37,014 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 15:02:37,036 INFO L204 MainTranslator]: Completed translation [2024-11-19 15:02:37,036 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37 WrapperNode [2024-11-19 15:02:37,036 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-19 15:02:37,037 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-19 15:02:37,037 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-19 15:02:37,038 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-19 15:02:37,045 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,059 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,105 INFO L138 Inliner]: procedures = 34, calls = 42, calls flagged for inlining = 37, calls inlined = 65, statements flattened = 836 [2024-11-19 15:02:37,106 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-19 15:02:37,111 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-19 15:02:37,112 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-19 15:02:37,112 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-19 15:02:37,121 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,121 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,125 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,146 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-19 15:02:37,146 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,147 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,156 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,169 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,171 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,174 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,178 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-19 15:02:37,178 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-19 15:02:37,179 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-19 15:02:37,179 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-19 15:02:37,179 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (1/1) ... [2024-11-19 15:02:37,189 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:02:37,203 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:02:37,220 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:02:37,221 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-19 15:02:37,256 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-19 15:02:37,256 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-19 15:02:37,256 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-19 15:02:37,256 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-19 15:02:37,324 INFO L238 CfgBuilder]: Building ICFG [2024-11-19 15:02:37,326 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-19 15:02:38,092 INFO L? ?]: Removed 148 outVars from TransFormulas that were not future-live. [2024-11-19 15:02:38,092 INFO L287 CfgBuilder]: Performing block encoding [2024-11-19 15:02:38,119 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-19 15:02:38,120 INFO L316 CfgBuilder]: Removed 6 assume(true) statements. [2024-11-19 15:02:38,120 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:02:38 BoogieIcfgContainer [2024-11-19 15:02:38,120 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-19 15:02:38,122 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-19 15:02:38,122 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-19 15:02:38,127 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-19 15:02:38,127 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:02:38,128 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 03:02:36" (1/3) ... [2024-11-19 15:02:38,129 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b836b23 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 03:02:38, skipping insertion in model container [2024-11-19 15:02:38,130 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:02:38,130 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:37" (2/3) ... [2024-11-19 15:02:38,131 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b836b23 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 03:02:38, skipping insertion in model container [2024-11-19 15:02:38,131 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:02:38,131 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:02:38" (3/3) ... [2024-11-19 15:02:38,132 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2024-11-19 15:02:38,193 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-19 15:02:38,194 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-19 15:02:38,194 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-19 15:02:38,194 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-19 15:02:38,194 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-19 15:02:38,194 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-19 15:02:38,194 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-19 15:02:38,194 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-19 15:02:38,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:38,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 278 [2024-11-19 15:02:38,231 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:38,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:38,240 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:38,241 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:38,241 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-19 15:02:38,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:38,263 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 278 [2024-11-19 15:02:38,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:38,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:38,266 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:38,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:38,277 INFO L745 eck$LassoCheckResult]: Stem: 211#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 222#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 331#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 219#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 288#L304true assume !(1 == ~m_i~0);~m_st~0 := 2; 124#L304-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 27#L309-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 242#L314-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 139#L319-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L441true assume !(0 == ~M_E~0); 122#L441-2true assume !(0 == ~T1_E~0); 258#L446-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 96#L451-1true assume !(0 == ~T3_E~0); 279#L456-1true assume !(0 == ~E_M~0); 234#L461-1true assume !(0 == ~E_1~0); 254#L466-1true assume !(0 == ~E_2~0); 303#L471-1true assume !(0 == ~E_3~0); 49#L476-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87#L220true assume 1 == ~m_pc~0; 268#L221true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 105#L231true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67#L543true assume !(0 != activate_threads_~tmp~1#1); 329#L543-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 207#L239true assume !(1 == ~t1_pc~0); 230#L239-2true is_transmit1_triggered_~__retres1~1#1 := 0; 275#L250true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 212#L551true assume !(0 != activate_threads_~tmp___0~0#1); 333#L551-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213#L258true assume 1 == ~t2_pc~0; 252#L259true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86#L269true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 335#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 228#L559true assume !(0 != activate_threads_~tmp___1~0#1); 131#L559-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173#L277true assume !(1 == ~t3_pc~0); 330#L277-2true is_transmit3_triggered_~__retres1~3#1 := 0; 38#L288true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64#L567true assume !(0 != activate_threads_~tmp___2~0#1); 93#L567-2true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 311#L489true assume !(1 == ~M_E~0); 231#L489-2true assume !(1 == ~T1_E~0); 151#L494-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 59#L499-1true assume !(1 == ~T3_E~0); 125#L504-1true assume !(1 == ~E_M~0); 267#L509-1true assume !(1 == ~E_1~0); 51#L514-1true assume !(1 == ~E_2~0); 181#L519-1true assume !(1 == ~E_3~0); 56#L524-1true assume { :end_inline_reset_delta_events } true; 37#L690-2true [2024-11-19 15:02:38,280 INFO L747 eck$LassoCheckResult]: Loop: 37#L690-2true assume !false; 52#L691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 192#L416-1true assume false; 114#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 154#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199#L441-3true assume 0 == ~M_E~0;~M_E~0 := 1; 9#L441-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 260#L446-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 195#L451-3true assume !(0 == ~T3_E~0); 35#L456-3true assume 0 == ~E_M~0;~E_M~0 := 1; 72#L461-3true assume 0 == ~E_1~0;~E_1~0 := 1; 156#L466-3true assume 0 == ~E_2~0;~E_2~0 := 1; 263#L471-3true assume 0 == ~E_3~0;~E_3~0 := 1; 65#L476-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106#L220-15true assume !(1 == ~m_pc~0); 162#L220-17true is_master_triggered_~__retres1~0#1 := 0; 210#L231-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107#is_master_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 224#L543-15true assume !(0 != activate_threads_~tmp~1#1); 132#L543-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123#L239-15true assume !(1 == ~t1_pc~0); 266#L239-17true is_transmit1_triggered_~__retres1~1#1 := 0; 286#L250-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28#L551-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 321#L551-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 320#L258-15true assume !(1 == ~t2_pc~0); 95#L258-17true is_transmit2_triggered_~__retres1~2#1 := 0; 283#L269-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 284#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 338#L559-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 237#L559-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 307#L277-15true assume !(1 == ~t3_pc~0); 14#L277-17true is_transmit3_triggered_~__retres1~3#1 := 0; 332#L288-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 274#L567-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33#L567-17true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29#L489-3true assume 1 == ~M_E~0;~M_E~0 := 2; 176#L489-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 225#L494-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 305#L499-3true assume !(1 == ~T3_E~0); 108#L504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 18#L509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 304#L514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 167#L519-3true assume 1 == ~E_3~0;~E_3~0 := 2; 42#L524-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 53#L332-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 57#L354-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 287#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 152#L709true assume !(0 == start_simulation_~tmp~3#1); 8#L709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 116#L332-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 55#L354-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 47#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 54#L664true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 157#L671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 178#stop_simulation_returnLabel#1true start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 85#L722true assume !(0 != start_simulation_~tmp___0~1#1); 37#L690-2true [2024-11-19 15:02:38,290 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:38,293 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2024-11-19 15:02:38,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:38,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054851693] [2024-11-19 15:02:38,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:38,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:38,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:38,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:38,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:38,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2054851693] [2024-11-19 15:02:38,544 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2054851693] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:38,545 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:38,545 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:38,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952574866] [2024-11-19 15:02:38,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:38,553 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:38,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:38,554 INFO L85 PathProgramCache]: Analyzing trace with hash 1950122617, now seen corresponding path program 1 times [2024-11-19 15:02:38,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:38,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342349127] [2024-11-19 15:02:38,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:38,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:38,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:38,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:38,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:38,631 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [342349127] [2024-11-19 15:02:38,631 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [342349127] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:38,631 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:38,631 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:02:38,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328490385] [2024-11-19 15:02:38,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:38,633 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:38,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:38,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:38,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:38,676 INFO L87 Difference]: Start difference. First operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:38,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:38,721 INFO L93 Difference]: Finished difference Result 333 states and 495 transitions. [2024-11-19 15:02:38,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 333 states and 495 transitions. [2024-11-19 15:02:38,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-19 15:02:38,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 333 states to 327 states and 489 transitions. [2024-11-19 15:02:38,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2024-11-19 15:02:38,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2024-11-19 15:02:38,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 489 transitions. [2024-11-19 15:02:38,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:38,744 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 489 transitions. [2024-11-19 15:02:38,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 489 transitions. [2024-11-19 15:02:38,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2024-11-19 15:02:38,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.4954128440366972) internal successors, (489), 326 states have internal predecessors, (489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:38,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 489 transitions. [2024-11-19 15:02:38,785 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 489 transitions. [2024-11-19 15:02:38,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:38,789 INFO L425 stractBuchiCegarLoop]: Abstraction has 327 states and 489 transitions. [2024-11-19 15:02:38,791 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-19 15:02:38,791 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 489 transitions. [2024-11-19 15:02:38,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-19 15:02:38,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:38,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:38,797 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:38,798 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:38,798 INFO L745 eck$LassoCheckResult]: Stem: 956#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 957#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 969#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 967#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 968#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 887#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 737#L309-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 738#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 906#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 745#L441 assume !(0 == ~M_E~0); 746#L441-2 assume !(0 == ~T1_E~0); 883#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 850#L451-1 assume !(0 == ~T3_E~0); 851#L456-1 assume !(0 == ~E_M~0); 973#L461-1 assume !(0 == ~E_1~0); 974#L466-1 assume !(0 == ~E_2~0); 984#L471-1 assume !(0 == ~E_3~0); 780#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 781#L220 assume 1 == ~m_pc~0; 840#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 813#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 864#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 808#L543 assume !(0 != activate_threads_~tmp~1#1); 809#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 955#L239 assume !(1 == ~t1_pc~0); 953#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 954#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 776#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 777#L551 assume !(0 != activate_threads_~tmp___0~0#1); 958#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 959#L258 assume 1 == ~t2_pc~0; 960#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 837#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 838#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 971#L559 assume !(0 != activate_threads_~tmp___1~0#1); 895#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 896#L277 assume !(1 == ~t3_pc~0); 934#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 756#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 712#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 713#L567 assume !(0 != activate_threads_~tmp___2~0#1); 804#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 845#L489 assume !(1 == ~M_E~0); 972#L489-2 assume !(1 == ~T1_E~0); 917#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 795#L499-1 assume !(1 == ~T3_E~0); 796#L504-1 assume !(1 == ~E_M~0); 888#L509-1 assume !(1 == ~E_1~0); 782#L514-1 assume !(1 == ~E_2~0); 783#L519-1 assume !(1 == ~E_3~0); 789#L524-1 assume { :end_inline_reset_delta_events } true; 754#L690-2 [2024-11-19 15:02:38,798 INFO L747 eck$LassoCheckResult]: Loop: 754#L690-2 assume !false; 755#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 784#L416-1 assume !false; 818#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 819#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 763#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 714#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 715#L369 assume !(0 != eval_~tmp~0#1); 874#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 875#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 919#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 695#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 696#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 944#L451-3 assume !(0 == ~T3_E~0); 750#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 751#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 817#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 921#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 806#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 807#L220-15 assume 1 == ~m_pc~0; 701#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 702#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 865#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 866#L543-15 assume !(0 != activate_threads_~tmp~1#1); 894#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 884#L239-15 assume 1 == ~t1_pc~0; 885#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 987#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 839#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 735#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 736#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1005#L258-15 assume 1 == ~t2_pc~0; 918#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 847#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 995#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 996#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 975#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 976#L277-15 assume 1 == ~t3_pc~0; 816#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 708#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 980#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 981#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 747#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 739#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 740#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 937#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 970#L499-3 assume !(1 == ~T3_E~0); 863#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 716#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 717#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 928#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 764#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 765#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 786#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 790#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 916#L709 assume !(0 == start_simulation_~tmp~3#1); 691#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 692#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 788#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 770#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 787#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 920#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 836#L722 assume !(0 != start_simulation_~tmp___0~1#1); 754#L690-2 [2024-11-19 15:02:38,800 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:38,802 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2024-11-19 15:02:38,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:38,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853596706] [2024-11-19 15:02:38,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:38,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:38,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:38,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:38,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:38,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853596706] [2024-11-19 15:02:38,889 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [853596706] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:38,889 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:38,890 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:38,890 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436604501] [2024-11-19 15:02:38,890 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:38,891 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:38,892 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:38,893 INFO L85 PathProgramCache]: Analyzing trace with hash 67370114, now seen corresponding path program 1 times [2024-11-19 15:02:38,894 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:38,894 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882072355] [2024-11-19 15:02:38,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:38,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:38,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:39,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:39,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:39,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882072355] [2024-11-19 15:02:39,024 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882072355] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:39,024 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:39,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:39,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [470601598] [2024-11-19 15:02:39,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:39,025 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:39,025 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:39,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:39,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:39,026 INFO L87 Difference]: Start difference. First operand 327 states and 489 transitions. cyclomatic complexity: 163 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:39,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:39,049 INFO L93 Difference]: Finished difference Result 327 states and 488 transitions. [2024-11-19 15:02:39,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 488 transitions. [2024-11-19 15:02:39,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-19 15:02:39,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 327 states and 488 transitions. [2024-11-19 15:02:39,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2024-11-19 15:02:39,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2024-11-19 15:02:39,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 488 transitions. [2024-11-19 15:02:39,063 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:39,063 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 488 transitions. [2024-11-19 15:02:39,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 488 transitions. [2024-11-19 15:02:39,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2024-11-19 15:02:39,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.492354740061162) internal successors, (488), 326 states have internal predecessors, (488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:39,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 488 transitions. [2024-11-19 15:02:39,079 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 488 transitions. [2024-11-19 15:02:39,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:39,081 INFO L425 stractBuchiCegarLoop]: Abstraction has 327 states and 488 transitions. [2024-11-19 15:02:39,082 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-19 15:02:39,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 488 transitions. [2024-11-19 15:02:39,083 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-19 15:02:39,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:39,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:39,085 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:39,085 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:39,086 INFO L745 eck$LassoCheckResult]: Stem: 1619#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1632#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1630#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1631#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 1551#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1400#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1401#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1569#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1408#L441 assume !(0 == ~M_E~0); 1409#L441-2 assume !(0 == ~T1_E~0); 1546#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1511#L451-1 assume !(0 == ~T3_E~0); 1512#L456-1 assume !(0 == ~E_M~0); 1636#L461-1 assume !(0 == ~E_1~0); 1637#L466-1 assume !(0 == ~E_2~0); 1647#L471-1 assume !(0 == ~E_3~0); 1441#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1442#L220 assume 1 == ~m_pc~0; 1502#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1476#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1526#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1471#L543 assume !(0 != activate_threads_~tmp~1#1); 1472#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1618#L239 assume !(1 == ~t1_pc~0); 1616#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1617#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1439#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1440#L551 assume !(0 != activate_threads_~tmp___0~0#1); 1621#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1622#L258 assume 1 == ~t2_pc~0; 1623#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1500#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1501#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1634#L559 assume !(0 != activate_threads_~tmp___1~0#1); 1557#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1558#L277 assume !(1 == ~t3_pc~0); 1596#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1419#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1375#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1376#L567 assume !(0 != activate_threads_~tmp___2~0#1); 1467#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1508#L489 assume !(1 == ~M_E~0); 1635#L489-2 assume !(1 == ~T1_E~0); 1579#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L499-1 assume !(1 == ~T3_E~0); 1457#L504-1 assume !(1 == ~E_M~0); 1550#L509-1 assume !(1 == ~E_1~0); 1445#L514-1 assume !(1 == ~E_2~0); 1446#L519-1 assume !(1 == ~E_3~0); 1452#L524-1 assume { :end_inline_reset_delta_events } true; 1417#L690-2 [2024-11-19 15:02:39,086 INFO L747 eck$LassoCheckResult]: Loop: 1417#L690-2 assume !false; 1418#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1447#L416-1 assume !false; 1481#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1482#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1426#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1377#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1378#L369 assume !(0 != eval_~tmp~0#1); 1536#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1537#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1581#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1358#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1359#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1607#L451-3 assume !(0 == ~T3_E~0); 1413#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1414#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1480#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1583#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1469#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1470#L220-15 assume 1 == ~m_pc~0; 1364#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1365#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1527#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1528#L543-15 assume !(0 != activate_threads_~tmp~1#1); 1559#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1547#L239-15 assume 1 == ~t1_pc~0; 1548#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1650#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1506#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1398#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1399#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1668#L258-15 assume !(1 == ~t2_pc~0); 1509#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 1510#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1658#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1659#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1638#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1639#L277-15 assume 1 == ~t3_pc~0; 1479#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1371#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1643#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1644#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1410#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1402#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1403#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1600#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1633#L499-3 assume !(1 == ~T3_E~0); 1529#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1379#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1380#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1591#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1427#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1428#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1449#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1453#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1580#L709 assume !(0 == start_simulation_~tmp~3#1); 1356#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1357#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1451#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1437#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1438#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1450#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1584#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1499#L722 assume !(0 != start_simulation_~tmp___0~1#1); 1417#L690-2 [2024-11-19 15:02:39,087 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:39,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2024-11-19 15:02:39,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:39,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494145348] [2024-11-19 15:02:39,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:39,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:39,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:39,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:39,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:39,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [494145348] [2024-11-19 15:02:39,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [494145348] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:39,136 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:39,136 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:39,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43332919] [2024-11-19 15:02:39,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:39,138 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:39,138 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:39,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1509187645, now seen corresponding path program 1 times [2024-11-19 15:02:39,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:39,140 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665711251] [2024-11-19 15:02:39,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:39,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:39,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:39,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:39,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:39,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665711251] [2024-11-19 15:02:39,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665711251] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:39,210 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:39,212 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:39,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [665227675] [2024-11-19 15:02:39,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:39,213 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:39,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:39,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:39,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:39,214 INFO L87 Difference]: Start difference. First operand 327 states and 488 transitions. cyclomatic complexity: 162 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:39,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:39,224 INFO L93 Difference]: Finished difference Result 327 states and 487 transitions. [2024-11-19 15:02:39,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 487 transitions. [2024-11-19 15:02:39,226 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-19 15:02:39,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 327 states and 487 transitions. [2024-11-19 15:02:39,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2024-11-19 15:02:39,229 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2024-11-19 15:02:39,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 487 transitions. [2024-11-19 15:02:39,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:39,230 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 487 transitions. [2024-11-19 15:02:39,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 487 transitions. [2024-11-19 15:02:39,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2024-11-19 15:02:39,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.489296636085627) internal successors, (487), 326 states have internal predecessors, (487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:39,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 487 transitions. [2024-11-19 15:02:39,239 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 487 transitions. [2024-11-19 15:02:39,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:39,240 INFO L425 stractBuchiCegarLoop]: Abstraction has 327 states and 487 transitions. [2024-11-19 15:02:39,240 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-19 15:02:39,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 487 transitions. [2024-11-19 15:02:39,242 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-19 15:02:39,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:39,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:39,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:39,243 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:39,243 INFO L745 eck$LassoCheckResult]: Stem: 2282#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2295#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2293#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2294#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 2213#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2061#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2062#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2232#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2071#L441 assume !(0 == ~M_E~0); 2072#L441-2 assume !(0 == ~T1_E~0); 2209#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2174#L451-1 assume !(0 == ~T3_E~0); 2175#L456-1 assume !(0 == ~E_M~0); 2299#L461-1 assume !(0 == ~E_1~0); 2300#L466-1 assume !(0 == ~E_2~0); 2310#L471-1 assume !(0 == ~E_3~0); 2104#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2105#L220 assume 1 == ~m_pc~0; 2165#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2139#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2189#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2134#L543 assume !(0 != activate_threads_~tmp~1#1); 2135#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2281#L239 assume !(1 == ~t1_pc~0); 2279#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2280#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2103#L551 assume !(0 != activate_threads_~tmp___0~0#1); 2284#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2285#L258 assume 1 == ~t2_pc~0; 2286#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2163#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2164#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2297#L559 assume !(0 != activate_threads_~tmp___1~0#1); 2220#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2221#L277 assume !(1 == ~t3_pc~0); 2259#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2082#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2038#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2039#L567 assume !(0 != activate_threads_~tmp___2~0#1); 2130#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2171#L489 assume !(1 == ~M_E~0); 2298#L489-2 assume !(1 == ~T1_E~0); 2242#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2119#L499-1 assume !(1 == ~T3_E~0); 2120#L504-1 assume !(1 == ~E_M~0); 2214#L509-1 assume !(1 == ~E_1~0); 2108#L514-1 assume !(1 == ~E_2~0); 2109#L519-1 assume !(1 == ~E_3~0); 2115#L524-1 assume { :end_inline_reset_delta_events } true; 2080#L690-2 [2024-11-19 15:02:39,244 INFO L747 eck$LassoCheckResult]: Loop: 2080#L690-2 assume !false; 2081#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2110#L416-1 assume !false; 2144#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2145#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2089#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2040#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2041#L369 assume !(0 != eval_~tmp~0#1); 2199#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2200#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2244#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2021#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2022#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2270#L451-3 assume !(0 == ~T3_E~0); 2076#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2077#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2143#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2246#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2132#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2133#L220-15 assume 1 == ~m_pc~0; 2027#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2028#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2190#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2191#L543-15 assume !(0 != activate_threads_~tmp~1#1); 2222#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2210#L239-15 assume 1 == ~t1_pc~0; 2211#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2313#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2169#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2063#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2064#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2331#L258-15 assume 1 == ~t2_pc~0; 2245#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2173#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2321#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2322#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2301#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2302#L277-15 assume !(1 == ~t3_pc~0); 2033#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2034#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2306#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2307#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2073#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2065#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2066#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2263#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2296#L499-3 assume !(1 == ~T3_E~0); 2192#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2042#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2043#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2254#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2090#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2091#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2112#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2116#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2243#L709 assume !(0 == start_simulation_~tmp~3#1); 2019#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2020#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2114#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2100#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2101#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2113#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2247#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2162#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2080#L690-2 [2024-11-19 15:02:39,244 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:39,244 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2024-11-19 15:02:39,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:39,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857863361] [2024-11-19 15:02:39,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:39,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:39,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:39,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:39,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:39,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857863361] [2024-11-19 15:02:39,336 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857863361] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:39,336 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:39,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:39,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342551929] [2024-11-19 15:02:39,337 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:39,337 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:39,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:39,337 INFO L85 PathProgramCache]: Analyzing trace with hash -1605147517, now seen corresponding path program 1 times [2024-11-19 15:02:39,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:39,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106833026] [2024-11-19 15:02:39,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:39,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:39,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:39,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:39,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:39,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106833026] [2024-11-19 15:02:39,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106833026] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:39,429 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:39,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:39,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1594714568] [2024-11-19 15:02:39,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:39,430 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:39,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:39,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:02:39,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:02:39,431 INFO L87 Difference]: Start difference. First operand 327 states and 487 transitions. cyclomatic complexity: 161 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:39,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:39,532 INFO L93 Difference]: Finished difference Result 569 states and 842 transitions. [2024-11-19 15:02:39,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 569 states and 842 transitions. [2024-11-19 15:02:39,536 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2024-11-19 15:02:39,539 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 569 states to 569 states and 842 transitions. [2024-11-19 15:02:39,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 569 [2024-11-19 15:02:39,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 569 [2024-11-19 15:02:39,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 569 states and 842 transitions. [2024-11-19 15:02:39,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:39,541 INFO L218 hiAutomatonCegarLoop]: Abstraction has 569 states and 842 transitions. [2024-11-19 15:02:39,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 569 states and 842 transitions. [2024-11-19 15:02:39,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 569 to 569. [2024-11-19 15:02:39,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 569 states, 569 states have (on average 1.4797891036906854) internal successors, (842), 568 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:39,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 842 transitions. [2024-11-19 15:02:39,561 INFO L240 hiAutomatonCegarLoop]: Abstraction has 569 states and 842 transitions. [2024-11-19 15:02:39,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:02:39,562 INFO L425 stractBuchiCegarLoop]: Abstraction has 569 states and 842 transitions. [2024-11-19 15:02:39,564 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-19 15:02:39,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 569 states and 842 transitions. [2024-11-19 15:02:39,566 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2024-11-19 15:02:39,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:39,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:39,567 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:39,568 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:39,568 INFO L745 eck$LassoCheckResult]: Stem: 3218#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3234#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3231#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3232#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 3128#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2969#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2970#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3148#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2980#L441 assume !(0 == ~M_E~0); 2981#L441-2 assume !(0 == ~T1_E~0); 3124#L446-1 assume !(0 == ~T2_E~0); 3086#L451-1 assume !(0 == ~T3_E~0); 3087#L456-1 assume !(0 == ~E_M~0); 3241#L461-1 assume !(0 == ~E_1~0); 3242#L466-1 assume !(0 == ~E_2~0); 3255#L471-1 assume !(0 == ~E_3~0); 3013#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3014#L220 assume 1 == ~m_pc~0; 3076#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3049#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3101#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3044#L543 assume !(0 != activate_threads_~tmp~1#1); 3045#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3216#L239 assume !(1 == ~t1_pc~0); 3214#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3215#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3011#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3012#L551 assume !(0 != activate_threads_~tmp___0~0#1); 3220#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3221#L258 assume 1 == ~t2_pc~0; 3222#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3074#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3075#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3237#L559 assume !(0 != activate_threads_~tmp___1~0#1); 3136#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3137#L277 assume !(1 == ~t3_pc~0); 3180#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2991#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2946#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2947#L567 assume !(0 != activate_threads_~tmp___2~0#1); 3040#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3083#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 3278#L489-2 assume !(1 == ~T1_E~0); 3364#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3160#L499-1 assume !(1 == ~T3_E~0); 3333#L504-1 assume !(1 == ~E_M~0); 3332#L509-1 assume !(1 == ~E_1~0); 3330#L514-1 assume !(1 == ~E_2~0); 3329#L519-1 assume !(1 == ~E_3~0); 3025#L524-1 assume { :end_inline_reset_delta_events } true; 2989#L690-2 [2024-11-19 15:02:39,568 INFO L747 eck$LassoCheckResult]: Loop: 2989#L690-2 assume !false; 2990#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3019#L416-1 assume !false; 3054#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3055#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3249#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3250#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3226#L369 assume !(0 != eval_~tmp~0#1); 3228#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3162#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3163#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3282#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3456#L446-3 assume !(0 == ~T2_E~0); 3455#L451-3 assume !(0 == ~T3_E~0); 3454#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3453#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3452#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3451#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3450#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3449#L220-15 assume 1 == ~m_pc~0; 3447#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3446#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3445#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3444#L543-15 assume !(0 != activate_threads_~tmp~1#1); 3443#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3442#L239-15 assume 1 == ~t1_pc~0; 3440#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3439#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3438#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3437#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3436#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3435#L258-15 assume 1 == ~t2_pc~0; 3433#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3432#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3431#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3430#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3429#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3428#L277-15 assume 1 == ~t3_pc~0; 3426#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3425#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3424#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3423#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3422#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3421#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2974#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3420#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3235#L499-3 assume !(1 == ~T3_E~0); 3419#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3418#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3417#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3416#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2999#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3000#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3411#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3410#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3409#L709 assume !(0 == start_simulation_~tmp~3#1); 3188#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3115#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3024#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3009#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3010#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3023#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3331#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3073#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2989#L690-2 [2024-11-19 15:02:39,568 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:39,569 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2024-11-19 15:02:39,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:39,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557569512] [2024-11-19 15:02:39,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:39,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:39,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:39,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:39,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:39,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557569512] [2024-11-19 15:02:39,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557569512] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:39,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:39,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:02:39,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2036847730] [2024-11-19 15:02:39,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:39,628 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:39,628 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:39,628 INFO L85 PathProgramCache]: Analyzing trace with hash 1605710144, now seen corresponding path program 1 times [2024-11-19 15:02:39,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:39,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393775509] [2024-11-19 15:02:39,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:39,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:39,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:39,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:39,691 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:39,691 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393775509] [2024-11-19 15:02:39,691 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1393775509] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:39,691 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:39,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:39,692 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2122963029] [2024-11-19 15:02:39,692 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:39,692 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:39,692 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:39,693 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:39,693 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:39,693 INFO L87 Difference]: Start difference. First operand 569 states and 842 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:39,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:39,748 INFO L93 Difference]: Finished difference Result 1049 states and 1527 transitions. [2024-11-19 15:02:39,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1049 states and 1527 transitions. [2024-11-19 15:02:39,754 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 983 [2024-11-19 15:02:39,759 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1049 states to 1049 states and 1527 transitions. [2024-11-19 15:02:39,759 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1049 [2024-11-19 15:02:39,760 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1049 [2024-11-19 15:02:39,761 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1049 states and 1527 transitions. [2024-11-19 15:02:39,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:39,762 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1049 states and 1527 transitions. [2024-11-19 15:02:39,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1049 states and 1527 transitions. [2024-11-19 15:02:39,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1049 to 995. [2024-11-19 15:02:39,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 995 states, 995 states have (on average 1.4603015075376884) internal successors, (1453), 994 states have internal predecessors, (1453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:39,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 995 states to 995 states and 1453 transitions. [2024-11-19 15:02:39,788 INFO L240 hiAutomatonCegarLoop]: Abstraction has 995 states and 1453 transitions. [2024-11-19 15:02:39,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:39,789 INFO L425 stractBuchiCegarLoop]: Abstraction has 995 states and 1453 transitions. [2024-11-19 15:02:39,789 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-19 15:02:39,790 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 995 states and 1453 transitions. [2024-11-19 15:02:39,794 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 929 [2024-11-19 15:02:39,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:39,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:39,795 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:39,795 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:39,795 INFO L745 eck$LassoCheckResult]: Stem: 4866#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4867#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4884#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4879#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4880#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 4766#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4599#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4600#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4785#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4608#L441 assume !(0 == ~M_E~0); 4609#L441-2 assume !(0 == ~T1_E~0); 4762#L446-1 assume !(0 == ~T2_E~0); 4719#L451-1 assume !(0 == ~T3_E~0); 4720#L456-1 assume !(0 == ~E_M~0); 4891#L461-1 assume !(0 == ~E_1~0); 4892#L466-1 assume !(0 == ~E_2~0); 4916#L471-1 assume !(0 == ~E_3~0); 4643#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4644#L220 assume !(1 == ~m_pc~0); 4678#L220-2 is_master_triggered_~__retres1~0#1 := 0; 4679#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4739#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4674#L543 assume !(0 != activate_threads_~tmp~1#1); 4675#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4862#L239 assume !(1 == ~t1_pc~0); 4860#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4861#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4639#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4640#L551 assume !(0 != activate_threads_~tmp___0~0#1); 4868#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4869#L258 assume 1 == ~t2_pc~0; 4870#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4706#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4707#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4888#L559 assume !(0 != activate_threads_~tmp___1~0#1); 4774#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4775#L277 assume !(1 == ~t3_pc~0); 4829#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4619#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4573#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4574#L567 assume !(0 != activate_threads_~tmp___2~0#1); 4669#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4714#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 4889#L489-2 assume !(1 == ~T1_E~0); 4890#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4660#L499-1 assume !(1 == ~T3_E~0); 4661#L504-1 assume !(1 == ~E_M~0); 4767#L509-1 assume !(1 == ~E_1~0); 4647#L514-1 assume !(1 == ~E_2~0); 4648#L519-1 assume !(1 == ~E_3~0); 4653#L524-1 assume { :end_inline_reset_delta_events } true; 4654#L690-2 [2024-11-19 15:02:39,796 INFO L747 eck$LassoCheckResult]: Loop: 4654#L690-2 assume !false; 4645#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4646#L416-1 assume !false; 4684#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4685#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4904#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4575#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4576#L369 assume !(0 != eval_~tmp~0#1); 5403#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5401#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5398#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5399#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5504#L446-3 assume !(0 == ~T2_E~0); 5503#L451-3 assume !(0 == ~T3_E~0); 5502#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5501#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5500#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5499#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5498#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5497#L220-15 assume !(1 == ~m_pc~0); 5496#L220-17 is_master_triggered_~__retres1~0#1 := 0; 5495#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5494#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5493#L543-15 assume !(0 != activate_threads_~tmp~1#1); 5492#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5491#L239-15 assume 1 == ~t1_pc~0; 5489#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5488#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5487#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5486#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5485#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5484#L258-15 assume 1 == ~t2_pc~0; 5482#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5481#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5480#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5479#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5478#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5477#L277-15 assume 1 == ~t3_pc~0; 5475#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5474#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5473#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5472#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5471#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5470#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5222#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5469#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5219#L499-3 assume !(1 == ~T3_E~0); 5468#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5467#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5466#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5465#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5464#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5463#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5459#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5458#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5457#L709 assume !(0 == start_simulation_~tmp~3#1); 4835#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4752#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4754#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5452#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5450#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5448#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5446#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4705#L722 assume !(0 != start_simulation_~tmp___0~1#1); 4654#L690-2 [2024-11-19 15:02:39,796 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:39,796 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2024-11-19 15:02:39,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:39,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1986230416] [2024-11-19 15:02:39,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:39,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:39,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:39,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:39,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:39,830 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1986230416] [2024-11-19 15:02:39,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1986230416] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:39,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:39,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:02:39,831 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [835177180] [2024-11-19 15:02:39,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:39,831 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:39,831 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:39,832 INFO L85 PathProgramCache]: Analyzing trace with hash 732232449, now seen corresponding path program 1 times [2024-11-19 15:02:39,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:39,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177956499] [2024-11-19 15:02:39,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:39,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:39,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:39,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:39,917 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:39,917 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177956499] [2024-11-19 15:02:39,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177956499] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:39,918 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:39,918 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:39,918 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1936470467] [2024-11-19 15:02:39,918 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:39,918 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:39,919 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:39,919 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:39,919 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:39,919 INFO L87 Difference]: Start difference. First operand 995 states and 1453 transitions. cyclomatic complexity: 462 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:39,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:39,976 INFO L93 Difference]: Finished difference Result 1789 states and 2591 transitions. [2024-11-19 15:02:39,976 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1789 states and 2591 transitions. [2024-11-19 15:02:39,987 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1712 [2024-11-19 15:02:39,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1789 states to 1789 states and 2591 transitions. [2024-11-19 15:02:39,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1789 [2024-11-19 15:02:39,999 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1789 [2024-11-19 15:02:39,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1789 states and 2591 transitions. [2024-11-19 15:02:40,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:40,003 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1789 states and 2591 transitions. [2024-11-19 15:02:40,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1789 states and 2591 transitions. [2024-11-19 15:02:40,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1789 to 1781. [2024-11-19 15:02:40,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1781 states, 1781 states have (on average 1.450308815272319) internal successors, (2583), 1780 states have internal predecessors, (2583), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:40,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1781 states to 1781 states and 2583 transitions. [2024-11-19 15:02:40,042 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1781 states and 2583 transitions. [2024-11-19 15:02:40,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:40,043 INFO L425 stractBuchiCegarLoop]: Abstraction has 1781 states and 2583 transitions. [2024-11-19 15:02:40,043 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-19 15:02:40,043 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1781 states and 2583 transitions. [2024-11-19 15:02:40,054 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1704 [2024-11-19 15:02:40,054 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:40,054 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:40,056 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:40,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:40,057 INFO L745 eck$LassoCheckResult]: Stem: 7639#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7640#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7652#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7650#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7651#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 7553#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7388#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7389#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7574#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7398#L441 assume !(0 == ~M_E~0); 7399#L441-2 assume !(0 == ~T1_E~0); 7549#L446-1 assume !(0 == ~T2_E~0); 7507#L451-1 assume !(0 == ~T3_E~0); 7508#L456-1 assume !(0 == ~E_M~0); 7658#L461-1 assume !(0 == ~E_1~0); 7659#L466-1 assume !(0 == ~E_2~0); 7676#L471-1 assume !(0 == ~E_3~0); 7431#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7432#L220 assume !(1 == ~m_pc~0); 7467#L220-2 is_master_triggered_~__retres1~0#1 := 0; 7468#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7523#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7463#L543 assume !(0 != activate_threads_~tmp~1#1); 7464#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7638#L239 assume !(1 == ~t1_pc~0); 7636#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7637#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7429#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7430#L551 assume !(0 != activate_threads_~tmp___0~0#1); 7641#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7642#L258 assume !(1 == ~t2_pc~0); 7643#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7496#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7497#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7655#L559 assume !(0 != activate_threads_~tmp___1~0#1); 7562#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7563#L277 assume !(1 == ~t3_pc~0); 7607#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7409#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7366#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7367#L567 assume !(0 != activate_threads_~tmp___2~0#1); 7459#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7504#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 7656#L489-2 assume !(1 == ~T1_E~0); 7657#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7586#L499-1 assume !(1 == ~T3_E~0); 8539#L504-1 assume !(1 == ~E_M~0); 8537#L509-1 assume !(1 == ~E_1~0); 8536#L514-1 assume !(1 == ~E_2~0); 7617#L519-1 assume !(1 == ~E_3~0); 7442#L524-1 assume { :end_inline_reset_delta_events } true; 7443#L690-2 [2024-11-19 15:02:40,059 INFO L747 eck$LassoCheckResult]: Loop: 7443#L690-2 assume !false; 8077#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8072#L416-1 assume !false; 8070#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8064#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8060#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8058#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8054#L369 assume !(0 != eval_~tmp~0#1); 8052#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8050#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8047#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8043#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8038#L446-3 assume !(0 == ~T2_E~0); 8034#L451-3 assume !(0 == ~T3_E~0); 8029#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8025#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8022#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8018#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8012#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8008#L220-15 assume !(1 == ~m_pc~0); 8005#L220-17 is_master_triggered_~__retres1~0#1 := 0; 8002#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7999#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7996#L543-15 assume !(0 != activate_threads_~tmp~1#1); 7993#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7991#L239-15 assume 1 == ~t1_pc~0; 7918#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7916#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7914#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7911#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7909#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7907#L258-15 assume !(1 == ~t2_pc~0); 7905#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 7903#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7901#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7899#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7896#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7897#L277-15 assume 1 == ~t3_pc~0; 7889#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7887#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7885#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7882#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7880#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7878#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7876#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7874#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7872#L499-3 assume !(1 == ~T3_E~0); 7870#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7868#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7866#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7864#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7862#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7861#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7858#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8328#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 8325#L709 assume !(0 == start_simulation_~tmp~3#1); 8322#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8142#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8137#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8135#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 8134#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8131#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8129#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 8127#L722 assume !(0 != start_simulation_~tmp___0~1#1); 7443#L690-2 [2024-11-19 15:02:40,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:40,060 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2024-11-19 15:02:40,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:40,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345270696] [2024-11-19 15:02:40,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:40,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:40,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:40,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:40,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:40,112 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345270696] [2024-11-19 15:02:40,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345270696] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:40,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:40,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:02:40,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220824732] [2024-11-19 15:02:40,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:40,113 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:40,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:40,114 INFO L85 PathProgramCache]: Analyzing trace with hash -844325310, now seen corresponding path program 1 times [2024-11-19 15:02:40,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:40,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1475427011] [2024-11-19 15:02:40,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:40,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:40,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:40,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:40,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:40,163 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1475427011] [2024-11-19 15:02:40,163 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1475427011] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:40,163 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:40,163 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:40,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2010972355] [2024-11-19 15:02:40,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:40,164 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:40,164 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:40,164 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:40,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:40,165 INFO L87 Difference]: Start difference. First operand 1781 states and 2583 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:40,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:40,202 INFO L93 Difference]: Finished difference Result 2597 states and 3764 transitions. [2024-11-19 15:02:40,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2597 states and 3764 transitions. [2024-11-19 15:02:40,216 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2514 [2024-11-19 15:02:40,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2597 states to 2597 states and 3764 transitions. [2024-11-19 15:02:40,229 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2597 [2024-11-19 15:02:40,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2597 [2024-11-19 15:02:40,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2597 states and 3764 transitions. [2024-11-19 15:02:40,235 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:40,235 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2597 states and 3764 transitions. [2024-11-19 15:02:40,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2597 states and 3764 transitions. [2024-11-19 15:02:40,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2597 to 1805. [2024-11-19 15:02:40,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.453185595567867) internal successors, (2623), 1804 states have internal predecessors, (2623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:40,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2623 transitions. [2024-11-19 15:02:40,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2623 transitions. [2024-11-19 15:02:40,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:40,268 INFO L425 stractBuchiCegarLoop]: Abstraction has 1805 states and 2623 transitions. [2024-11-19 15:02:40,268 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-19 15:02:40,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2623 transitions. [2024-11-19 15:02:40,276 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1736 [2024-11-19 15:02:40,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:40,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:40,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:40,277 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:40,278 INFO L745 eck$LassoCheckResult]: Stem: 12017#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 12018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12031#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12029#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12030#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 11934#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11775#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11776#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11954#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11785#L441 assume !(0 == ~M_E~0); 11786#L441-2 assume !(0 == ~T1_E~0); 11930#L446-1 assume !(0 == ~T2_E~0); 11890#L451-1 assume !(0 == ~T3_E~0); 11891#L456-1 assume !(0 == ~E_M~0); 12035#L461-1 assume !(0 == ~E_1~0); 12036#L466-1 assume !(0 == ~E_2~0); 12052#L471-1 assume !(0 == ~E_3~0); 11818#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11819#L220 assume !(1 == ~m_pc~0); 11853#L220-2 is_master_triggered_~__retres1~0#1 := 0; 11854#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11906#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11849#L543 assume !(0 != activate_threads_~tmp~1#1); 11850#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12016#L239 assume !(1 == ~t1_pc~0); 12014#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12015#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11816#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11817#L551 assume !(0 != activate_threads_~tmp___0~0#1); 12019#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12020#L258 assume !(1 == ~t2_pc~0); 12021#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11879#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11880#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12033#L559 assume !(0 != activate_threads_~tmp___1~0#1); 11942#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11943#L277 assume !(1 == ~t3_pc~0); 11991#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11796#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11753#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11754#L567 assume !(0 != activate_threads_~tmp___2~0#1); 11845#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11887#L489 assume !(1 == ~M_E~0); 12034#L489-2 assume !(1 == ~T1_E~0); 11968#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11834#L499-1 assume !(1 == ~T3_E~0); 11835#L504-1 assume !(1 == ~E_M~0); 11935#L509-1 assume !(1 == ~E_1~0); 11822#L514-1 assume !(1 == ~E_2~0); 11823#L519-1 assume !(1 == ~E_3~0); 11829#L524-1 assume { :end_inline_reset_delta_events } true; 11830#L690-2 [2024-11-19 15:02:40,278 INFO L747 eck$LassoCheckResult]: Loop: 11830#L690-2 assume !false; 13411#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13406#L416-1 assume !false; 13392#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13388#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13384#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13382#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13380#L369 assume !(0 != eval_~tmp~0#1); 11919#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11920#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11973#L441-3 assume !(0 == ~M_E~0); 11736#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11737#L446-3 assume !(0 == ~T2_E~0); 12005#L451-3 assume !(0 == ~T3_E~0); 11790#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11791#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11858#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11977#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11847#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11848#L220-15 assume !(1 == ~m_pc~0); 11907#L220-17 is_master_triggered_~__retres1~0#1 := 0; 13524#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13523#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13521#L543-15 assume !(0 != activate_threads_~tmp~1#1); 13520#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13519#L239-15 assume 1 == ~t1_pc~0; 13517#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13516#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13515#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13514#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13513#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13512#L258-15 assume !(1 == ~t2_pc~0); 13490#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 12067#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12068#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12069#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12038#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12039#L277-15 assume 1 == ~t3_pc~0; 11857#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11749#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12048#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12049#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11787#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11779#L489-3 assume !(1 == ~M_E~0); 11780#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11996#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12032#L499-3 assume !(1 == ~T3_E~0); 11910#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11757#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11758#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11986#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11804#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11805#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11826#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11831#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 11969#L709 assume !(0 == start_simulation_~tmp~3#1); 11970#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13431#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13427#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13425#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 13423#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13421#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13419#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 13417#L722 assume !(0 != start_simulation_~tmp___0~1#1); 11830#L690-2 [2024-11-19 15:02:40,278 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:40,279 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2024-11-19 15:02:40,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:40,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294449618] [2024-11-19 15:02:40,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:40,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:40,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:40,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:40,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:40,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294449618] [2024-11-19 15:02:40,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294449618] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:40,322 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:40,322 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:40,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [367433370] [2024-11-19 15:02:40,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:40,323 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:40,323 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:40,324 INFO L85 PathProgramCache]: Analyzing trace with hash 454395522, now seen corresponding path program 1 times [2024-11-19 15:02:40,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:40,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087401298] [2024-11-19 15:02:40,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:40,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:40,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:40,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:40,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:40,379 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1087401298] [2024-11-19 15:02:40,379 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1087401298] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:40,379 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:40,382 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:40,382 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1667298438] [2024-11-19 15:02:40,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:40,383 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:40,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:40,383 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:02:40,383 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:02:40,383 INFO L87 Difference]: Start difference. First operand 1805 states and 2623 transitions. cyclomatic complexity: 822 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:40,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:40,435 INFO L93 Difference]: Finished difference Result 2591 states and 3732 transitions. [2024-11-19 15:02:40,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2591 states and 3732 transitions. [2024-11-19 15:02:40,447 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2514 [2024-11-19 15:02:40,460 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2591 states to 2591 states and 3732 transitions. [2024-11-19 15:02:40,460 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2591 [2024-11-19 15:02:40,463 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2591 [2024-11-19 15:02:40,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2591 states and 3732 transitions. [2024-11-19 15:02:40,467 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:40,467 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2591 states and 3732 transitions. [2024-11-19 15:02:40,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2591 states and 3732 transitions. [2024-11-19 15:02:40,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2591 to 1805. [2024-11-19 15:02:40,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.4437673130193907) internal successors, (2606), 1804 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:40,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2606 transitions. [2024-11-19 15:02:40,501 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2606 transitions. [2024-11-19 15:02:40,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:02:40,502 INFO L425 stractBuchiCegarLoop]: Abstraction has 1805 states and 2606 transitions. [2024-11-19 15:02:40,502 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-19 15:02:40,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2606 transitions. [2024-11-19 15:02:40,510 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1736 [2024-11-19 15:02:40,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:40,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:40,512 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:40,512 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:40,512 INFO L745 eck$LassoCheckResult]: Stem: 16425#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 16426#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16438#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16436#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16437#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 16341#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16183#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16184#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16362#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16193#L441 assume !(0 == ~M_E~0); 16194#L441-2 assume !(0 == ~T1_E~0); 16337#L446-1 assume !(0 == ~T2_E~0); 16299#L451-1 assume !(0 == ~T3_E~0); 16300#L456-1 assume !(0 == ~E_M~0); 16443#L461-1 assume !(0 == ~E_1~0); 16444#L466-1 assume !(0 == ~E_2~0); 16458#L471-1 assume !(0 == ~E_3~0); 16226#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16227#L220 assume !(1 == ~m_pc~0); 16260#L220-2 is_master_triggered_~__retres1~0#1 := 0; 16261#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16315#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16256#L543 assume !(0 != activate_threads_~tmp~1#1); 16257#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16424#L239 assume !(1 == ~t1_pc~0); 16422#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16423#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16224#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16225#L551 assume !(0 != activate_threads_~tmp___0~0#1); 16427#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16428#L258 assume !(1 == ~t2_pc~0); 16429#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16288#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16289#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16440#L559 assume !(0 != activate_threads_~tmp___1~0#1); 16349#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16350#L277 assume !(1 == ~t3_pc~0); 16398#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16204#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16161#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16162#L567 assume !(0 != activate_threads_~tmp___2~0#1); 16252#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16296#L489 assume !(1 == ~M_E~0); 16441#L489-2 assume !(1 == ~T1_E~0); 16375#L494-1 assume !(1 == ~T2_E~0); 16241#L499-1 assume !(1 == ~T3_E~0); 16242#L504-1 assume !(1 == ~E_M~0); 16342#L509-1 assume !(1 == ~E_1~0); 16230#L514-1 assume !(1 == ~E_2~0); 16231#L519-1 assume !(1 == ~E_3~0); 16237#L524-1 assume { :end_inline_reset_delta_events } true; 16202#L690-2 [2024-11-19 15:02:40,512 INFO L747 eck$LassoCheckResult]: Loop: 16202#L690-2 assume !false; 16203#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16232#L416-1 assume !false; 16266#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16267#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16211#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16163#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16164#L369 assume !(0 != eval_~tmp~0#1); 16433#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17923#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17921#L441-3 assume !(0 == ~M_E~0); 17920#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17919#L446-3 assume !(0 == ~T2_E~0); 16412#L451-3 assume !(0 == ~T3_E~0); 16198#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16199#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16265#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16383#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16254#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16255#L220-15 assume !(1 == ~m_pc~0); 16316#L220-17 is_master_triggered_~__retres1~0#1 := 0; 16389#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16317#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16318#L543-15 assume !(0 != activate_threads_~tmp~1#1); 16351#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16338#L239-15 assume 1 == ~t1_pc~0; 16339#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16463#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16294#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16185#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16186#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16489#L258-15 assume !(1 == ~t2_pc~0); 16297#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 16298#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16473#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16474#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16445#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16446#L277-15 assume 1 == ~t3_pc~0; 16264#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16157#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16454#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16455#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16195#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16187#L489-3 assume !(1 == ~M_E~0); 16188#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16403#L494-3 assume !(1 == ~T2_E~0); 16439#L499-3 assume !(1 == ~T3_E~0); 16319#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16165#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16166#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16392#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16212#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16213#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16234#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16238#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 16376#L709 assume !(0 == start_simulation_~tmp~3#1); 16142#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16143#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16236#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16222#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 16223#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16235#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16384#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 16287#L722 assume !(0 != start_simulation_~tmp___0~1#1); 16202#L690-2 [2024-11-19 15:02:40,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:40,513 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2024-11-19 15:02:40,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:40,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078817246] [2024-11-19 15:02:40,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:40,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:40,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:40,523 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:40,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:40,557 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:40,558 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:40,558 INFO L85 PathProgramCache]: Analyzing trace with hash -1234548220, now seen corresponding path program 1 times [2024-11-19 15:02:40,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:40,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857755598] [2024-11-19 15:02:40,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:40,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:40,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:40,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:40,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:40,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857755598] [2024-11-19 15:02:40,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857755598] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:40,603 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:40,603 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:40,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605877236] [2024-11-19 15:02:40,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:40,603 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:40,604 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:40,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:02:40,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:02:40,604 INFO L87 Difference]: Start difference. First operand 1805 states and 2606 transitions. cyclomatic complexity: 805 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:40,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:40,664 INFO L93 Difference]: Finished difference Result 1861 states and 2662 transitions. [2024-11-19 15:02:40,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1861 states and 2662 transitions. [2024-11-19 15:02:40,673 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1792 [2024-11-19 15:02:40,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1861 states to 1861 states and 2662 transitions. [2024-11-19 15:02:40,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1861 [2024-11-19 15:02:40,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1861 [2024-11-19 15:02:40,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1861 states and 2662 transitions. [2024-11-19 15:02:40,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:40,684 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1861 states and 2662 transitions. [2024-11-19 15:02:40,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1861 states and 2662 transitions. [2024-11-19 15:02:40,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1861 to 1829. [2024-11-19 15:02:40,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1829 states, 1829 states have (on average 1.437944231820667) internal successors, (2630), 1828 states have internal predecessors, (2630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:40,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1829 states to 1829 states and 2630 transitions. [2024-11-19 15:02:40,711 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1829 states and 2630 transitions. [2024-11-19 15:02:40,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:02:40,712 INFO L425 stractBuchiCegarLoop]: Abstraction has 1829 states and 2630 transitions. [2024-11-19 15:02:40,712 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-19 15:02:40,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1829 states and 2630 transitions. [2024-11-19 15:02:40,718 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1760 [2024-11-19 15:02:40,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:40,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:40,719 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:40,719 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:40,719 INFO L745 eck$LassoCheckResult]: Stem: 20104#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 20105#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20117#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20115#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20116#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 20024#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19857#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19858#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20044#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19867#L441 assume !(0 == ~M_E~0); 19868#L441-2 assume !(0 == ~T1_E~0); 20020#L446-1 assume !(0 == ~T2_E~0); 19980#L451-1 assume !(0 == ~T3_E~0); 19981#L456-1 assume !(0 == ~E_M~0); 20123#L461-1 assume !(0 == ~E_1~0); 20124#L466-1 assume !(0 == ~E_2~0); 20137#L471-1 assume !(0 == ~E_3~0); 19901#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19902#L220 assume !(1 == ~m_pc~0); 19936#L220-2 is_master_triggered_~__retres1~0#1 := 0; 19937#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19996#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19932#L543 assume !(0 != activate_threads_~tmp~1#1); 19933#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20103#L239 assume !(1 == ~t1_pc~0); 20101#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20102#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19899#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19900#L551 assume !(0 != activate_threads_~tmp___0~0#1); 20106#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20107#L258 assume !(1 == ~t2_pc~0); 20108#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19965#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19966#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20119#L559 assume !(0 != activate_threads_~tmp___1~0#1); 20032#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20033#L277 assume !(1 == ~t3_pc~0); 20079#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19878#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19835#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19836#L567 assume !(0 != activate_threads_~tmp___2~0#1); 19928#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19977#L489 assume !(1 == ~M_E~0); 20120#L489-2 assume !(1 == ~T1_E~0); 20056#L494-1 assume !(1 == ~T2_E~0); 19917#L499-1 assume !(1 == ~T3_E~0); 19918#L504-1 assume !(1 == ~E_M~0); 20025#L509-1 assume !(1 == ~E_1~0); 19905#L514-1 assume !(1 == ~E_2~0); 19906#L519-1 assume !(1 == ~E_3~0); 19912#L524-1 assume { :end_inline_reset_delta_events } true; 19913#L690-2 [2024-11-19 15:02:40,720 INFO L747 eck$LassoCheckResult]: Loop: 19913#L690-2 assume !false; 20908#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20902#L416-1 assume !false; 20900#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20895#L332 assume !(0 == ~m_st~0); 20896#L336 assume !(0 == ~t1_st~0); 20892#L340 assume !(0 == ~t2_st~0); 20893#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 20894#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21276#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 21274#L369 assume !(0 != eval_~tmp~0#1); 21272#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21270#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21268#L441-3 assume !(0 == ~M_E~0); 21266#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21264#L446-3 assume !(0 == ~T2_E~0); 21262#L451-3 assume !(0 == ~T3_E~0); 21260#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21258#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21255#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21253#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21251#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21249#L220-15 assume !(1 == ~m_pc~0); 21247#L220-17 is_master_triggered_~__retres1~0#1 := 0; 21246#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21245#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21244#L543-15 assume !(0 != activate_threads_~tmp~1#1); 21243#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21242#L239-15 assume 1 == ~t1_pc~0; 21240#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21239#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21237#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21236#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21233#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21231#L258-15 assume !(1 == ~t2_pc~0); 21229#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 21227#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21225#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21223#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21221#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21219#L277-15 assume 1 == ~t3_pc~0; 21216#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21214#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21212#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21210#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21207#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21205#L489-3 assume !(1 == ~M_E~0); 21201#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21199#L494-3 assume !(1 == ~T2_E~0); 21197#L499-3 assume !(1 == ~T3_E~0); 21194#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21192#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21190#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21188#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21186#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21184#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21179#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21177#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 21176#L709 assume !(0 == start_simulation_~tmp~3#1); 21174#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21173#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21169#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20916#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 20915#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20912#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20911#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 20910#L722 assume !(0 != start_simulation_~tmp___0~1#1); 19913#L690-2 [2024-11-19 15:02:40,720 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:40,720 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2024-11-19 15:02:40,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:40,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1072347784] [2024-11-19 15:02:40,721 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:02:40,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:40,729 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:02:40,729 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:02:40,729 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:40,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:40,743 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:40,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:40,743 INFO L85 PathProgramCache]: Analyzing trace with hash 435870986, now seen corresponding path program 1 times [2024-11-19 15:02:40,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:40,744 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405470031] [2024-11-19 15:02:40,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:40,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:40,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:40,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:40,768 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:40,768 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405470031] [2024-11-19 15:02:40,769 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405470031] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:40,769 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:40,769 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:40,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254316606] [2024-11-19 15:02:40,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:40,769 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:40,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:40,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:40,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:40,770 INFO L87 Difference]: Start difference. First operand 1829 states and 2630 transitions. cyclomatic complexity: 805 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:40,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:40,823 INFO L93 Difference]: Finished difference Result 3277 states and 4630 transitions. [2024-11-19 15:02:40,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3277 states and 4630 transitions. [2024-11-19 15:02:40,850 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3200 [2024-11-19 15:02:40,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3277 states to 3277 states and 4630 transitions. [2024-11-19 15:02:40,863 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3277 [2024-11-19 15:02:40,865 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3277 [2024-11-19 15:02:40,865 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3277 states and 4630 transitions. [2024-11-19 15:02:40,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:40,868 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3277 states and 4630 transitions. [2024-11-19 15:02:40,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3277 states and 4630 transitions. [2024-11-19 15:02:40,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3277 to 3187. [2024-11-19 15:02:40,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3187 states, 3187 states have (on average 1.4144963915908377) internal successors, (4508), 3186 states have internal predecessors, (4508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:40,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3187 states to 3187 states and 4508 transitions. [2024-11-19 15:02:40,916 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3187 states and 4508 transitions. [2024-11-19 15:02:40,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:40,918 INFO L425 stractBuchiCegarLoop]: Abstraction has 3187 states and 4508 transitions. [2024-11-19 15:02:40,918 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-19 15:02:40,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3187 states and 4508 transitions. [2024-11-19 15:02:40,928 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3110 [2024-11-19 15:02:40,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:40,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:40,930 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:40,930 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:40,930 INFO L745 eck$LassoCheckResult]: Stem: 25222#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 25223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 25234#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25232#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25233#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 25134#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24972#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24973#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25154#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24980#L441 assume !(0 == ~M_E~0); 24981#L441-2 assume !(0 == ~T1_E~0); 25130#L446-1 assume !(0 == ~T2_E~0); 25090#L451-1 assume !(0 == ~T3_E~0); 25091#L456-1 assume !(0 == ~E_M~0); 25242#L461-1 assume !(0 == ~E_1~0); 25243#L466-1 assume !(0 == ~E_2~0); 25257#L471-1 assume !(0 == ~E_3~0); 25018#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25019#L220 assume !(1 == ~m_pc~0); 25051#L220-2 is_master_triggered_~__retres1~0#1 := 0; 25052#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25110#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 25047#L543 assume !(0 != activate_threads_~tmp~1#1); 25048#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25218#L239 assume !(1 == ~t1_pc~0); 25216#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25217#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25014#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25015#L551 assume !(0 != activate_threads_~tmp___0~0#1); 25224#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25225#L258 assume !(1 == ~t2_pc~0); 25226#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25078#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25079#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25239#L559 assume !(0 != activate_threads_~tmp___1~0#1); 25143#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25144#L277 assume !(1 == ~t3_pc~0); 25192#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 24992#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24947#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24948#L567 assume !(0 != activate_threads_~tmp___2~0#1); 25043#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25087#L489 assume !(1 == ~M_E~0); 25241#L489-2 assume !(1 == ~T1_E~0); 25171#L494-1 assume !(1 == ~T2_E~0); 25032#L499-1 assume !(1 == ~T3_E~0); 25033#L504-1 assume !(1 == ~E_M~0); 25135#L509-1 assume !(1 == ~E_1~0); 25020#L514-1 assume !(1 == ~E_2~0); 25021#L519-1 assume !(1 == ~E_3~0); 25026#L524-1 assume { :end_inline_reset_delta_events } true; 25027#L690-2 [2024-11-19 15:02:40,930 INFO L747 eck$LassoCheckResult]: Loop: 25027#L690-2 assume !false; 27245#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27241#L416-1 assume !false; 27240#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 27238#L332 assume !(0 == ~m_st~0); 27239#L336 assume !(0 == ~t1_st~0); 27422#L340 assume !(0 == ~t2_st~0); 27424#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 27419#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27392#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 27393#L369 assume !(0 != eval_~tmp~0#1); 27712#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27710#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27709#L441-3 assume !(0 == ~M_E~0); 27707#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27704#L446-3 assume !(0 == ~T2_E~0); 27702#L451-3 assume !(0 == ~T3_E~0); 27700#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27697#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27695#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27693#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27691#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27689#L220-15 assume !(1 == ~m_pc~0); 27687#L220-17 is_master_triggered_~__retres1~0#1 := 0; 25221#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25106#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 25107#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27607#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27603#L239-15 assume !(1 == ~t1_pc~0); 27600#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 27597#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27595#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27593#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27591#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27589#L258-15 assume !(1 == ~t2_pc~0); 27588#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 27587#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27585#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27582#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27583#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27726#L277-15 assume 1 == ~t3_pc~0; 27724#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27723#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27722#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27721#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27720#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27719#L489-3 assume !(1 == ~M_E~0); 26942#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27718#L494-3 assume !(1 == ~T2_E~0); 27717#L499-3 assume !(1 == ~T3_E~0); 27716#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27715#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27206#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27201#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27202#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 27692#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 27690#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27688#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 25169#L709 assume !(0 == start_simulation_~tmp~3#1); 25170#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 27279#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 27276#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27273#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 27268#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27265#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27260#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 27256#L722 assume !(0 != start_simulation_~tmp___0~1#1); 25027#L690-2 [2024-11-19 15:02:40,931 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:40,931 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2024-11-19 15:02:40,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:40,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1419019807] [2024-11-19 15:02:40,932 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 15:02:40,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:40,943 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 15:02:40,943 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:02:40,943 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:40,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:40,955 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:40,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:40,955 INFO L85 PathProgramCache]: Analyzing trace with hash -944704119, now seen corresponding path program 1 times [2024-11-19 15:02:40,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:40,956 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016303347] [2024-11-19 15:02:40,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:40,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:40,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:41,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:41,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:41,024 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1016303347] [2024-11-19 15:02:41,024 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1016303347] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:41,024 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:41,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:02:41,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396697214] [2024-11-19 15:02:41,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:41,025 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:41,025 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:41,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:02:41,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:02:41,025 INFO L87 Difference]: Start difference. First operand 3187 states and 4508 transitions. cyclomatic complexity: 1325 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:41,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:41,163 INFO L93 Difference]: Finished difference Result 2808 states and 3912 transitions. [2024-11-19 15:02:41,164 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2808 states and 3912 transitions. [2024-11-19 15:02:41,174 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2735 [2024-11-19 15:02:41,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2808 states to 2808 states and 3912 transitions. [2024-11-19 15:02:41,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2808 [2024-11-19 15:02:41,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2808 [2024-11-19 15:02:41,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2808 states and 3912 transitions. [2024-11-19 15:02:41,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:41,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2808 states and 3912 transitions. [2024-11-19 15:02:41,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2808 states and 3912 transitions. [2024-11-19 15:02:41,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2808 to 2808. [2024-11-19 15:02:41,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2808 states, 2808 states have (on average 1.393162393162393) internal successors, (3912), 2807 states have internal predecessors, (3912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:41,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2808 states to 2808 states and 3912 transitions. [2024-11-19 15:02:41,234 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2808 states and 3912 transitions. [2024-11-19 15:02:41,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:02:41,235 INFO L425 stractBuchiCegarLoop]: Abstraction has 2808 states and 3912 transitions. [2024-11-19 15:02:41,235 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-19 15:02:41,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2808 states and 3912 transitions. [2024-11-19 15:02:41,242 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2735 [2024-11-19 15:02:41,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:41,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:41,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:41,243 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:41,243 INFO L745 eck$LassoCheckResult]: Stem: 31226#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 31227#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 31239#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31237#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31238#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 31138#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30974#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30975#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31159#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30982#L441 assume !(0 == ~M_E~0); 30983#L441-2 assume !(0 == ~T1_E~0); 31134#L446-1 assume !(0 == ~T2_E~0); 31097#L451-1 assume !(0 == ~T3_E~0); 31098#L456-1 assume !(0 == ~E_M~0); 31244#L461-1 assume !(0 == ~E_1~0); 31245#L466-1 assume !(0 == ~E_2~0); 31260#L471-1 assume !(0 == ~E_3~0); 31018#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31019#L220 assume !(1 == ~m_pc~0); 31053#L220-2 is_master_triggered_~__retres1~0#1 := 0; 31054#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31115#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31051#L543 assume !(0 != activate_threads_~tmp~1#1); 31052#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31225#L239 assume !(1 == ~t1_pc~0); 31223#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31224#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31014#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31015#L551 assume !(0 != activate_threads_~tmp___0~0#1); 31228#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31229#L258 assume !(1 == ~t2_pc~0); 31230#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31082#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31083#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31242#L559 assume !(0 != activate_threads_~tmp___1~0#1); 31147#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31148#L277 assume !(1 == ~t3_pc~0); 31198#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30993#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30952#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30953#L567 assume !(0 != activate_threads_~tmp___2~0#1); 31044#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31092#L489 assume !(1 == ~M_E~0); 31243#L489-2 assume !(1 == ~T1_E~0); 31173#L494-1 assume !(1 == ~T2_E~0); 31035#L499-1 assume !(1 == ~T3_E~0); 31036#L504-1 assume !(1 == ~E_M~0); 31139#L509-1 assume !(1 == ~E_1~0); 31022#L514-1 assume !(1 == ~E_2~0); 31023#L519-1 assume !(1 == ~E_3~0); 31027#L524-1 assume { :end_inline_reset_delta_events } true; 31028#L690-2 assume !false; 31509#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31505#L416-1 [2024-11-19 15:02:41,243 INFO L747 eck$LassoCheckResult]: Loop: 31505#L416-1 assume !false; 31502#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 31499#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 31497#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 31495#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 31493#L369 assume 0 != eval_~tmp~0#1; 31488#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 31485#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 31483#L377-2 havoc eval_~tmp_ndt_1~0#1; 31479#L374-1 assume !(0 == ~t1_st~0); 31476#L388-1 assume !(0 == ~t2_st~0); 31477#L402-1 assume !(0 == ~t3_st~0); 31505#L416-1 [2024-11-19 15:02:41,244 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:41,244 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2024-11-19 15:02:41,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:41,244 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129744875] [2024-11-19 15:02:41,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:41,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:41,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:41,252 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:41,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:41,262 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:41,262 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:41,263 INFO L85 PathProgramCache]: Analyzing trace with hash -583220711, now seen corresponding path program 1 times [2024-11-19 15:02:41,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:41,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117895121] [2024-11-19 15:02:41,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:41,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:41,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:41,266 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:41,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:41,268 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:41,268 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:41,269 INFO L85 PathProgramCache]: Analyzing trace with hash 979003743, now seen corresponding path program 1 times [2024-11-19 15:02:41,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:41,269 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1181931117] [2024-11-19 15:02:41,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:41,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:41,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:41,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:41,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:41,327 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1181931117] [2024-11-19 15:02:41,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1181931117] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:41,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:41,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:41,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [745401552] [2024-11-19 15:02:41,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:41,405 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:41,406 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:41,406 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:41,406 INFO L87 Difference]: Start difference. First operand 2808 states and 3912 transitions. cyclomatic complexity: 1110 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:41,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:41,507 INFO L93 Difference]: Finished difference Result 5040 states and 6945 transitions. [2024-11-19 15:02:41,507 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5040 states and 6945 transitions. [2024-11-19 15:02:41,526 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4900 [2024-11-19 15:02:41,549 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5040 states to 5040 states and 6945 transitions. [2024-11-19 15:02:41,549 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5040 [2024-11-19 15:02:41,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5040 [2024-11-19 15:02:41,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5040 states and 6945 transitions. [2024-11-19 15:02:41,560 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:41,560 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5040 states and 6945 transitions. [2024-11-19 15:02:41,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5040 states and 6945 transitions. [2024-11-19 15:02:41,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5040 to 4795. [2024-11-19 15:02:41,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4795 states, 4795 states have (on average 1.3826903023983317) internal successors, (6630), 4794 states have internal predecessors, (6630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:41,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4795 states to 4795 states and 6630 transitions. [2024-11-19 15:02:41,637 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4795 states and 6630 transitions. [2024-11-19 15:02:41,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:41,638 INFO L425 stractBuchiCegarLoop]: Abstraction has 4795 states and 6630 transitions. [2024-11-19 15:02:41,638 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-19 15:02:41,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4795 states and 6630 transitions. [2024-11-19 15:02:41,653 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4655 [2024-11-19 15:02:41,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:41,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:41,654 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:41,654 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:41,654 INFO L745 eck$LassoCheckResult]: Stem: 39108#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 39109#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 39122#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39119#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39120#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 39001#L304-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 39002#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39141#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39142#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38840#L441 assume !(0 == ~M_E~0); 38841#L441-2 assume !(0 == ~T1_E~0); 39153#L446-1 assume !(0 == ~T2_E~0); 39154#L451-1 assume !(0 == ~T3_E~0); 39173#L456-1 assume !(0 == ~E_M~0); 39174#L461-1 assume !(0 == ~E_1~0); 39149#L466-1 assume !(0 == ~E_2~0); 39150#L471-1 assume !(0 == ~E_3~0); 38875#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38876#L220 assume !(1 == ~m_pc~0); 38911#L220-2 is_master_triggered_~__retres1~0#1 := 0; 38912#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39084#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 39085#L543 assume !(0 != activate_threads_~tmp~1#1); 39207#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39208#L239 assume !(1 == ~t1_pc~0); 39103#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39104#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38873#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38874#L551 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39111#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39112#L258 assume !(1 == ~t2_pc~0); 39113#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38940#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38941#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39126#L559 assume !(0 != activate_threads_~tmp___1~0#1); 39127#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39063#L277 assume !(1 == ~t3_pc~0); 39064#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38851#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38852#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38902#L567 assume !(0 != activate_threads_~tmp___2~0#1); 38903#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39194#L489 assume !(1 == ~M_E~0); 39195#L489-2 assume !(1 == ~T1_E~0); 39042#L494-1 assume !(1 == ~T2_E~0); 39043#L499-1 assume !(1 == ~T3_E~0); 39003#L504-1 assume !(1 == ~E_M~0); 39004#L509-1 assume !(1 == ~E_1~0); 38879#L514-1 assume !(1 == ~E_2~0); 38880#L519-1 assume !(1 == ~E_3~0); 38885#L524-1 assume { :end_inline_reset_delta_events } true; 38886#L690-2 assume !false; 40179#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40174#L416-1 [2024-11-19 15:02:41,654 INFO L747 eck$LassoCheckResult]: Loop: 40174#L416-1 assume !false; 40172#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 40170#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 40162#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 40163#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40148#L369 assume 0 != eval_~tmp~0#1; 40149#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 40217#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 40211#L377-2 havoc eval_~tmp_ndt_1~0#1; 40207#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 40048#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 40192#L391-2 havoc eval_~tmp_ndt_2~0#1; 40184#L388-1 assume !(0 == ~t2_st~0); 40177#L402-1 assume !(0 == ~t3_st~0); 40174#L416-1 [2024-11-19 15:02:41,654 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:41,654 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2024-11-19 15:02:41,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:41,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627918585] [2024-11-19 15:02:41,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:41,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:41,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:41,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:41,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:41,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627918585] [2024-11-19 15:02:41,676 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627918585] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:41,676 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:41,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:41,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [4133816] [2024-11-19 15:02:41,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:41,676 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:41,677 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:41,677 INFO L85 PathProgramCache]: Analyzing trace with hash 2039297175, now seen corresponding path program 1 times [2024-11-19 15:02:41,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:41,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872881565] [2024-11-19 15:02:41,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:41,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:41,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:41,680 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:41,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:41,684 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:41,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:41,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:41,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:41,739 INFO L87 Difference]: Start difference. First operand 4795 states and 6630 transitions. cyclomatic complexity: 1841 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:41,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:41,760 INFO L93 Difference]: Finished difference Result 4746 states and 6561 transitions. [2024-11-19 15:02:41,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4746 states and 6561 transitions. [2024-11-19 15:02:41,776 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4655 [2024-11-19 15:02:41,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4746 states to 4746 states and 6561 transitions. [2024-11-19 15:02:41,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4746 [2024-11-19 15:02:41,801 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4746 [2024-11-19 15:02:41,801 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4746 states and 6561 transitions. [2024-11-19 15:02:41,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:41,809 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4746 states and 6561 transitions. [2024-11-19 15:02:41,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4746 states and 6561 transitions. [2024-11-19 15:02:41,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4746 to 4746. [2024-11-19 15:02:41,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4746 states, 4746 states have (on average 1.3824273072060682) internal successors, (6561), 4745 states have internal predecessors, (6561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:41,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4746 states to 4746 states and 6561 transitions. [2024-11-19 15:02:41,949 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4746 states and 6561 transitions. [2024-11-19 15:02:41,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:41,950 INFO L425 stractBuchiCegarLoop]: Abstraction has 4746 states and 6561 transitions. [2024-11-19 15:02:41,950 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-19 15:02:41,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4746 states and 6561 transitions. [2024-11-19 15:02:41,968 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4655 [2024-11-19 15:02:41,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:41,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:41,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:41,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:41,970 INFO L745 eck$LassoCheckResult]: Stem: 48628#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 48629#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 48640#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48638#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48639#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 48544#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48375#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48376#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48566#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48386#L441 assume !(0 == ~M_E~0); 48387#L441-2 assume !(0 == ~T1_E~0); 48540#L446-1 assume !(0 == ~T2_E~0); 48498#L451-1 assume !(0 == ~T3_E~0); 48499#L456-1 assume !(0 == ~E_M~0); 48645#L461-1 assume !(0 == ~E_1~0); 48646#L466-1 assume !(0 == ~E_2~0); 48661#L471-1 assume !(0 == ~E_3~0); 48420#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48421#L220 assume !(1 == ~m_pc~0); 48455#L220-2 is_master_triggered_~__retres1~0#1 := 0; 48456#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48515#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 48451#L543 assume !(0 != activate_threads_~tmp~1#1); 48452#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48627#L239 assume !(1 == ~t1_pc~0); 48625#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48626#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48418#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 48419#L551 assume !(0 != activate_threads_~tmp___0~0#1); 48630#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48631#L258 assume !(1 == ~t2_pc~0); 48632#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48485#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48486#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 48643#L559 assume !(0 != activate_threads_~tmp___1~0#1); 48552#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48553#L277 assume !(1 == ~t3_pc~0); 48604#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48397#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48353#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48354#L567 assume !(0 != activate_threads_~tmp___2~0#1); 48447#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48495#L489 assume !(1 == ~M_E~0); 48644#L489-2 assume !(1 == ~T1_E~0); 48581#L494-1 assume !(1 == ~T2_E~0); 48436#L499-1 assume !(1 == ~T3_E~0); 48437#L504-1 assume !(1 == ~E_M~0); 48545#L509-1 assume !(1 == ~E_1~0); 48424#L514-1 assume !(1 == ~E_2~0); 48425#L519-1 assume !(1 == ~E_3~0); 48430#L524-1 assume { :end_inline_reset_delta_events } true; 48431#L690-2 assume !false; 49044#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49037#L416-1 [2024-11-19 15:02:41,970 INFO L747 eck$LassoCheckResult]: Loop: 49037#L416-1 assume !false; 49033#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 49028#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 49024#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 49021#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49020#L369 assume 0 != eval_~tmp~0#1; 49018#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 49015#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 48996#L377-2 havoc eval_~tmp_ndt_1~0#1; 48990#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 48926#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 48979#L391-2 havoc eval_~tmp_ndt_2~0#1; 48919#L388-1 assume !(0 == ~t2_st~0); 48920#L402-1 assume !(0 == ~t3_st~0); 49037#L416-1 [2024-11-19 15:02:41,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:41,971 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2024-11-19 15:02:41,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:41,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199952834] [2024-11-19 15:02:41,971 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:02:41,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:41,980 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:02:41,980 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:02:41,980 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:41,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:41,992 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:41,992 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:41,993 INFO L85 PathProgramCache]: Analyzing trace with hash 2039297175, now seen corresponding path program 2 times [2024-11-19 15:02:41,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:41,993 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981592181] [2024-11-19 15:02:41,993 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:02:41,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:41,997 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:02:41,997 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:02:41,997 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:41,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:42,000 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:42,001 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:42,001 INFO L85 PathProgramCache]: Analyzing trace with hash 98443869, now seen corresponding path program 1 times [2024-11-19 15:02:42,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:42,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529042966] [2024-11-19 15:02:42,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:42,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:42,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:42,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:42,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:42,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [529042966] [2024-11-19 15:02:42,031 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [529042966] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:42,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:42,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:42,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79036239] [2024-11-19 15:02:42,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:42,084 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:42,084 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:42,085 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:42,085 INFO L87 Difference]: Start difference. First operand 4746 states and 6561 transitions. cyclomatic complexity: 1821 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:42,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:42,137 INFO L93 Difference]: Finished difference Result 5349 states and 7350 transitions. [2024-11-19 15:02:42,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5349 states and 7350 transitions. [2024-11-19 15:02:42,158 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5266 [2024-11-19 15:02:42,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5349 states to 5349 states and 7350 transitions. [2024-11-19 15:02:42,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5349 [2024-11-19 15:02:42,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5349 [2024-11-19 15:02:42,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5349 states and 7350 transitions. [2024-11-19 15:02:42,197 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:42,197 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5349 states and 7350 transitions. [2024-11-19 15:02:42,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5349 states and 7350 transitions. [2024-11-19 15:02:42,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5349 to 5195. [2024-11-19 15:02:42,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5195 states, 5195 states have (on average 1.3770933589990375) internal successors, (7154), 5194 states have internal predecessors, (7154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:42,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5195 states to 5195 states and 7154 transitions. [2024-11-19 15:02:42,277 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5195 states and 7154 transitions. [2024-11-19 15:02:42,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:42,278 INFO L425 stractBuchiCegarLoop]: Abstraction has 5195 states and 7154 transitions. [2024-11-19 15:02:42,278 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-19 15:02:42,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5195 states and 7154 transitions. [2024-11-19 15:02:42,297 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5112 [2024-11-19 15:02:42,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:42,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:42,298 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:42,298 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:42,298 INFO L745 eck$LassoCheckResult]: Stem: 58744#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 58745#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 58759#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58754#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58755#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 58647#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58481#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58482#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58668#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58489#L441 assume !(0 == ~M_E~0); 58490#L441-2 assume !(0 == ~T1_E~0); 58643#L446-1 assume !(0 == ~T2_E~0); 58603#L451-1 assume !(0 == ~T3_E~0); 58604#L456-1 assume !(0 == ~E_M~0); 58764#L461-1 assume !(0 == ~E_1~0); 58765#L466-1 assume !(0 == ~E_2~0); 58782#L471-1 assume !(0 == ~E_3~0); 58525#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58526#L220 assume !(1 == ~m_pc~0); 58560#L220-2 is_master_triggered_~__retres1~0#1 := 0; 58561#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58623#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 58558#L543 assume !(0 != activate_threads_~tmp~1#1); 58559#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58743#L239 assume !(1 == ~t1_pc~0); 58741#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58742#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58521#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 58522#L551 assume !(0 != activate_threads_~tmp___0~0#1); 58746#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58747#L258 assume !(1 == ~t2_pc~0); 58748#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 58592#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58593#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 58762#L559 assume !(0 != activate_threads_~tmp___1~0#1); 58656#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58657#L277 assume !(1 == ~t3_pc~0); 58710#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58500#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58456#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 58457#L567 assume !(0 != activate_threads_~tmp___2~0#1); 58552#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58600#L489 assume !(1 == ~M_E~0); 58763#L489-2 assume !(1 == ~T1_E~0); 58684#L494-1 assume !(1 == ~T2_E~0); 58541#L499-1 assume !(1 == ~T3_E~0); 58542#L504-1 assume !(1 == ~E_M~0); 58648#L509-1 assume !(1 == ~E_1~0); 58527#L514-1 assume !(1 == ~E_2~0); 58528#L519-1 assume !(1 == ~E_3~0); 58535#L524-1 assume { :end_inline_reset_delta_events } true; 58536#L690-2 assume !false; 61660#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61656#L416-1 [2024-11-19 15:02:42,298 INFO L747 eck$LassoCheckResult]: Loop: 61656#L416-1 assume !false; 61655#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 61602#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 61599#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 61600#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 63013#L369 assume 0 != eval_~tmp~0#1; 63011#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 63010#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 63006#L377-2 havoc eval_~tmp_ndt_1~0#1; 61671#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 61668#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 61667#L391-2 havoc eval_~tmp_ndt_2~0#1; 61664#L388-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 61663#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 61662#L405-2 havoc eval_~tmp_ndt_3~0#1; 61658#L402-1 assume !(0 == ~t3_st~0); 61656#L416-1 [2024-11-19 15:02:42,299 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:42,299 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2024-11-19 15:02:42,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:42,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647335341] [2024-11-19 15:02:42,299 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 15:02:42,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:42,309 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 15:02:42,309 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:02:42,309 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:42,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:42,320 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:42,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:42,321 INFO L85 PathProgramCache]: Analyzing trace with hash 1255454681, now seen corresponding path program 1 times [2024-11-19 15:02:42,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:42,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [276662241] [2024-11-19 15:02:42,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:42,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:42,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:42,325 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:42,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:42,328 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:42,328 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:42,328 INFO L85 PathProgramCache]: Analyzing trace with hash 111234079, now seen corresponding path program 1 times [2024-11-19 15:02:42,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:42,328 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145503878] [2024-11-19 15:02:42,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:42,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:42,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:42,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:42,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:42,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145503878] [2024-11-19 15:02:42,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1145503878] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:42,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:42,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:02:42,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [145176976] [2024-11-19 15:02:42,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:42,454 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:42,454 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:42,454 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:42,455 INFO L87 Difference]: Start difference. First operand 5195 states and 7154 transitions. cyclomatic complexity: 1965 Second operand has 3 states, 2 states have (on average 34.5) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:42,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:42,526 INFO L93 Difference]: Finished difference Result 8757 states and 11970 transitions. [2024-11-19 15:02:42,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8757 states and 11970 transitions. [2024-11-19 15:02:42,568 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8646 [2024-11-19 15:02:42,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8757 states to 8757 states and 11970 transitions. [2024-11-19 15:02:42,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8757 [2024-11-19 15:02:42,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8757 [2024-11-19 15:02:42,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8757 states and 11970 transitions. [2024-11-19 15:02:42,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:42,611 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8757 states and 11970 transitions. [2024-11-19 15:02:42,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8757 states and 11970 transitions. [2024-11-19 15:02:42,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8757 to 8613. [2024-11-19 15:02:42,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8613 states, 8613 states have (on average 1.3730407523510972) internal successors, (11826), 8612 states have internal predecessors, (11826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:42,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8613 states to 8613 states and 11826 transitions. [2024-11-19 15:02:42,733 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8613 states and 11826 transitions. [2024-11-19 15:02:42,733 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:42,734 INFO L425 stractBuchiCegarLoop]: Abstraction has 8613 states and 11826 transitions. [2024-11-19 15:02:42,734 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-19 15:02:42,734 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8613 states and 11826 transitions. [2024-11-19 15:02:42,761 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8502 [2024-11-19 15:02:42,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:42,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:42,762 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:42,762 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:42,762 INFO L745 eck$LassoCheckResult]: Stem: 72703#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 72704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 72718#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 72714#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 72715#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 72606#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 72442#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 72443#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 72627#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 72450#L441 assume !(0 == ~M_E~0); 72451#L441-2 assume !(0 == ~T1_E~0); 72602#L446-1 assume !(0 == ~T2_E~0); 72562#L451-1 assume !(0 == ~T3_E~0); 72563#L456-1 assume !(0 == ~E_M~0); 72722#L461-1 assume !(0 == ~E_1~0); 72723#L466-1 assume !(0 == ~E_2~0); 72743#L471-1 assume !(0 == ~E_3~0); 72485#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72486#L220 assume !(1 == ~m_pc~0); 72520#L220-2 is_master_triggered_~__retres1~0#1 := 0; 72521#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72581#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 72518#L543 assume !(0 != activate_threads_~tmp~1#1); 72519#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72702#L239 assume !(1 == ~t1_pc~0); 72700#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 72701#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72481#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 72482#L551 assume !(0 != activate_threads_~tmp___0~0#1); 72705#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72706#L258 assume !(1 == ~t2_pc~0); 72707#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 72549#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72550#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 72720#L559 assume !(0 != activate_threads_~tmp___1~0#1); 72615#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72616#L277 assume !(1 == ~t3_pc~0); 72668#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 72461#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72418#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 72419#L567 assume !(0 != activate_threads_~tmp___2~0#1); 72512#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72557#L489 assume !(1 == ~M_E~0); 72721#L489-2 assume !(1 == ~T1_E~0); 72645#L494-1 assume !(1 == ~T2_E~0); 72503#L499-1 assume !(1 == ~T3_E~0); 72504#L504-1 assume !(1 == ~E_M~0); 72607#L509-1 assume !(1 == ~E_1~0); 72488#L514-1 assume !(1 == ~E_2~0); 72489#L519-1 assume !(1 == ~E_3~0); 72495#L524-1 assume { :end_inline_reset_delta_events } true; 72496#L690-2 assume !false; 77980#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77978#L416-1 [2024-11-19 15:02:42,762 INFO L747 eck$LassoCheckResult]: Loop: 77978#L416-1 assume !false; 77976#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 77230#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 77227#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 77225#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77223#L369 assume 0 != eval_~tmp~0#1; 77220#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 77217#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 77215#L377-2 havoc eval_~tmp_ndt_1~0#1; 74842#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 74840#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 74839#L391-2 havoc eval_~tmp_ndt_2~0#1; 74837#L388-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 74834#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 74832#L405-2 havoc eval_~tmp_ndt_3~0#1; 74830#L402-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 74628#L419 assume !(0 != eval_~tmp_ndt_4~0#1); 74828#L419-2 havoc eval_~tmp_ndt_4~0#1; 77978#L416-1 [2024-11-19 15:02:42,763 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:42,763 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2024-11-19 15:02:42,763 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:42,763 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694920275] [2024-11-19 15:02:42,763 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 15:02:42,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:42,771 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 15:02:42,771 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:02:42,771 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:42,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:42,810 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:42,810 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:42,810 INFO L85 PathProgramCache]: Analyzing trace with hash -393961001, now seen corresponding path program 1 times [2024-11-19 15:02:42,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:42,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321064840] [2024-11-19 15:02:42,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:42,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:42,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:42,814 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:42,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:42,816 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:42,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:42,817 INFO L85 PathProgramCache]: Analyzing trace with hash -478331747, now seen corresponding path program 1 times [2024-11-19 15:02:42,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:42,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251259103] [2024-11-19 15:02:42,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:42,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:42,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:42,824 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:42,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:42,836 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:02:43,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:43,758 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:02:43,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:02:43,904 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.11 03:02:43 BoogieIcfgContainer [2024-11-19 15:02:43,904 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-19 15:02:43,904 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-19 15:02:43,904 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-19 15:02:43,904 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-19 15:02:43,905 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:02:38" (3/4) ... [2024-11-19 15:02:43,907 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-19 15:02:43,973 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-19 15:02:43,974 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-19 15:02:43,974 INFO L158 Benchmark]: Toolchain (without parser) took 7369.35ms. Allocated memory was 155.2MB in the beginning and 234.9MB in the end (delta: 79.7MB). Free memory was 87.4MB in the beginning and 119.8MB in the end (delta: -32.5MB). Peak memory consumption was 48.3MB. Max. memory is 16.1GB. [2024-11-19 15:02:43,974 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 104.9MB. Free memory is still 67.0MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-19 15:02:43,975 INFO L158 Benchmark]: CACSL2BoogieTranslator took 430.81ms. Allocated memory is still 155.2MB. Free memory was 87.2MB in the beginning and 123.7MB in the end (delta: -36.5MB). Peak memory consumption was 15.3MB. Max. memory is 16.1GB. [2024-11-19 15:02:43,975 INFO L158 Benchmark]: Boogie Procedure Inliner took 68.63ms. Allocated memory is still 155.2MB. Free memory was 123.7MB in the beginning and 120.2MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-19 15:02:43,975 INFO L158 Benchmark]: Boogie Preprocessor took 66.48ms. Allocated memory is still 155.2MB. Free memory was 120.2MB in the beginning and 115.4MB in the end (delta: 4.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-19 15:02:43,975 INFO L158 Benchmark]: RCFGBuilder took 942.12ms. Allocated memory is still 155.2MB. Free memory was 115.4MB in the beginning and 68.3MB in the end (delta: 47.0MB). Peak memory consumption was 48.2MB. Max. memory is 16.1GB. [2024-11-19 15:02:43,976 INFO L158 Benchmark]: BuchiAutomizer took 5782.21ms. Allocated memory was 155.2MB in the beginning and 234.9MB in the end (delta: 79.7MB). Free memory was 67.7MB in the beginning and 128.2MB in the end (delta: -60.5MB). Peak memory consumption was 20.4MB. Max. memory is 16.1GB. [2024-11-19 15:02:43,976 INFO L158 Benchmark]: Witness Printer took 69.36ms. Allocated memory is still 234.9MB. Free memory was 128.2MB in the beginning and 119.8MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-19 15:02:43,977 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 104.9MB. Free memory is still 67.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 430.81ms. Allocated memory is still 155.2MB. Free memory was 87.2MB in the beginning and 123.7MB in the end (delta: -36.5MB). Peak memory consumption was 15.3MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 68.63ms. Allocated memory is still 155.2MB. Free memory was 123.7MB in the beginning and 120.2MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 66.48ms. Allocated memory is still 155.2MB. Free memory was 120.2MB in the beginning and 115.4MB in the end (delta: 4.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 942.12ms. Allocated memory is still 155.2MB. Free memory was 115.4MB in the beginning and 68.3MB in the end (delta: 47.0MB). Peak memory consumption was 48.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 5782.21ms. Allocated memory was 155.2MB in the beginning and 234.9MB in the end (delta: 79.7MB). Free memory was 67.7MB in the beginning and 128.2MB in the end (delta: -60.5MB). Peak memory consumption was 20.4MB. Max. memory is 16.1GB. * Witness Printer took 69.36ms. Allocated memory is still 234.9MB. Free memory was 128.2MB in the beginning and 119.8MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (15 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 8613 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.6s and 16 iterations. TraceHistogramMax:1. Analysis of lassos took 3.1s. Construction of modules took 0.4s. Büchi inclusion checks took 1.7s. Highest rank in rank-based complementation 0. Minimization of det autom 15. Minimization of nondet autom 0. Automata minimization 0.7s AutomataMinimizationTime, 15 MinimizatonAttempts, 2305 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 6472 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 6472 mSDsluCounter, 14011 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 6243 mSDsCounter, 130 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 339 IncrementalHoareTripleChecker+Invalid, 469 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 130 mSolverCounterUnsat, 7768 mSDtfsCounter, 339 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 364]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE !(\read(tmp_ndt_1)) [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE !(\read(tmp_ndt_2)) [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE !(\read(tmp_ndt_3)) [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 364]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE !(\read(tmp_ndt_1)) [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE !(\read(tmp_ndt_2)) [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE !(\read(tmp_ndt_3)) [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-19 15:02:44,009 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)