./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.07.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3061b6dc Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.07.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-assert-order-craig-3061b6d-m [2024-11-19 15:02:53,584 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-19 15:02:53,637 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-19 15:02:53,642 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-19 15:02:53,643 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-19 15:02:53,668 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-19 15:02:53,669 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-19 15:02:53,669 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-19 15:02:53,670 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-19 15:02:53,672 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-19 15:02:53,673 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-19 15:02:53,673 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-19 15:02:53,673 INFO L153 SettingsManager]: * Use SBE=true [2024-11-19 15:02:53,674 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-19 15:02:53,674 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-19 15:02:53,674 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-19 15:02:53,674 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-19 15:02:53,674 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-19 15:02:53,674 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-19 15:02:53,675 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-19 15:02:53,675 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-19 15:02:53,676 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-19 15:02:53,676 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-19 15:02:53,676 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-19 15:02:53,677 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-19 15:02:53,677 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-19 15:02:53,677 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-19 15:02:53,677 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-19 15:02:53,677 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-19 15:02:53,678 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-19 15:02:53,678 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-19 15:02:53,678 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-19 15:02:53,678 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-19 15:02:53,678 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-19 15:02:53,678 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-19 15:02:53,678 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-19 15:02:53,679 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-19 15:02:53,679 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-19 15:02:53,679 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-19 15:02:53,679 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b [2024-11-19 15:02:53,866 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-19 15:02:53,887 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-19 15:02:53,889 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-19 15:02:53,890 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-19 15:02:53,890 INFO L274 PluginConnector]: CDTParser initialized [2024-11-19 15:02:53,891 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2024-11-19 15:02:55,251 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-19 15:02:55,437 INFO L384 CDTParser]: Found 1 translation units. [2024-11-19 15:02:55,437 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2024-11-19 15:02:55,452 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2f50920fe/79657e215c914ad6bd68ac3d8ebd91af/FLAG54d74f080 [2024-11-19 15:02:55,463 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2f50920fe/79657e215c914ad6bd68ac3d8ebd91af [2024-11-19 15:02:55,465 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-19 15:02:55,466 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-19 15:02:55,468 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-19 15:02:55,468 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-19 15:02:55,473 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-19 15:02:55,473 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:55,474 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2aed4a6f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55, skipping insertion in model container [2024-11-19 15:02:55,474 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:55,514 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-19 15:02:55,791 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 15:02:55,806 INFO L200 MainTranslator]: Completed pre-run [2024-11-19 15:02:55,871 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 15:02:55,887 INFO L204 MainTranslator]: Completed translation [2024-11-19 15:02:55,888 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55 WrapperNode [2024-11-19 15:02:55,888 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-19 15:02:55,889 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-19 15:02:55,889 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-19 15:02:55,889 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-19 15:02:55,894 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:55,903 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:55,953 INFO L138 Inliner]: procedures = 42, calls = 54, calls flagged for inlining = 49, calls inlined = 137, statements flattened = 2020 [2024-11-19 15:02:55,957 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-19 15:02:55,958 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-19 15:02:55,958 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-19 15:02:55,958 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-19 15:02:55,975 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:55,978 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:55,988 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:56,023 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-19 15:02:56,027 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:56,027 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:56,055 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:56,076 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:56,084 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:56,097 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:56,111 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-19 15:02:56,113 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-19 15:02:56,113 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-19 15:02:56,113 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-19 15:02:56,114 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (1/1) ... [2024-11-19 15:02:56,124 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:02:56,132 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:02:56,149 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:02:56,152 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-19 15:02:56,188 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-19 15:02:56,188 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-19 15:02:56,188 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-19 15:02:56,188 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-19 15:02:56,285 INFO L238 CfgBuilder]: Building ICFG [2024-11-19 15:02:56,287 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-19 15:02:57,452 INFO L? ?]: Removed 396 outVars from TransFormulas that were not future-live. [2024-11-19 15:02:57,452 INFO L287 CfgBuilder]: Performing block encoding [2024-11-19 15:02:57,489 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-19 15:02:57,489 INFO L316 CfgBuilder]: Removed 10 assume(true) statements. [2024-11-19 15:02:57,490 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:02:57 BoogieIcfgContainer [2024-11-19 15:02:57,490 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-19 15:02:57,491 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-19 15:02:57,491 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-19 15:02:57,494 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-19 15:02:57,495 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:02:57,495 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 03:02:55" (1/3) ... [2024-11-19 15:02:57,497 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1e9296b8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 03:02:57, skipping insertion in model container [2024-11-19 15:02:57,497 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:02:57,497 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:02:55" (2/3) ... [2024-11-19 15:02:57,497 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1e9296b8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 03:02:57, skipping insertion in model container [2024-11-19 15:02:57,497 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:02:57,497 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:02:57" (3/3) ... [2024-11-19 15:02:57,498 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-2.c [2024-11-19 15:02:57,548 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-19 15:02:57,548 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-19 15:02:57,549 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-19 15:02:57,549 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-19 15:02:57,549 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-19 15:02:57,549 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-19 15:02:57,549 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-19 15:02:57,549 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-19 15:02:57,555 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:57,592 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2024-11-19 15:02:57,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:57,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:57,602 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:57,602 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:57,602 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-19 15:02:57,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:57,625 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2024-11-19 15:02:57,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:57,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:57,630 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:57,631 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:57,638 INFO L745 eck$LassoCheckResult]: Stem: 127#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 784#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 622#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 782#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 807#L548true assume !(1 == ~m_i~0);~m_st~0 := 2; 213#L548-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 401#L553-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 295#L558-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 760#L563-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 153#L568-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 41#L573-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 791#L578-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 130#L583-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 505#L781true assume !(0 == ~M_E~0); 822#L781-2true assume !(0 == ~T1_E~0); 846#L786-1true assume !(0 == ~T2_E~0); 21#L791-1true assume !(0 == ~T3_E~0); 385#L796-1true assume !(0 == ~T4_E~0); 355#L801-1true assume !(0 == ~T5_E~0); 387#L806-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 766#L811-1true assume !(0 == ~T7_E~0); 134#L816-1true assume !(0 == ~E_M~0); 626#L821-1true assume !(0 == ~E_1~0); 37#L826-1true assume !(0 == ~E_2~0); 353#L831-1true assume !(0 == ~E_3~0); 210#L836-1true assume !(0 == ~E_4~0); 507#L841-1true assume !(0 == ~E_5~0); 107#L846-1true assume 0 == ~E_6~0;~E_6~0 := 1; 799#L851-1true assume !(0 == ~E_7~0); 119#L856-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 651#L388true assume !(1 == ~m_pc~0); 116#L388-2true is_master_triggered_~__retres1~0#1 := 0; 478#L399true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 545#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44#L967true assume !(0 != activate_threads_~tmp~1#1); 767#L967-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11#L407true assume 1 == ~t1_pc~0; 414#L408true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13#L418true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 618#L975true assume !(0 != activate_threads_~tmp___0~0#1); 644#L975-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 184#L426true assume !(1 == ~t2_pc~0); 662#L426-2true is_transmit2_triggered_~__retres1~2#1 := 0; 753#L437true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 745#L983true assume !(0 != activate_threads_~tmp___1~0#1); 847#L983-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 241#L445true assume 1 == ~t3_pc~0; 838#L446true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 517#L456true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 441#L991true assume !(0 != activate_threads_~tmp___2~0#1); 512#L991-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 415#L464true assume !(1 == ~t4_pc~0); 121#L464-2true is_transmit4_triggered_~__retres1~4#1 := 0; 52#L475true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 845#L999true assume !(0 != activate_threads_~tmp___3~0#1); 227#L999-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 410#L483true assume 1 == ~t5_pc~0; 737#L484true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 593#L494true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 548#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 701#L1007true assume !(0 != activate_threads_~tmp___4~0#1); 175#L1007-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 461#L502true assume 1 == ~t6_pc~0; 383#L503true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73#L513true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 322#L1015true assume !(0 != activate_threads_~tmp___5~0#1); 560#L1015-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 711#L521true assume !(1 == ~t7_pc~0); 666#L521-2true is_transmit7_triggered_~__retres1~7#1 := 0; 42#L532true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 800#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 607#L1023true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 569#L1023-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 469#L869true assume !(1 == ~M_E~0); 223#L869-2true assume !(1 == ~T1_E~0); 738#L874-1true assume !(1 == ~T2_E~0); 686#L879-1true assume !(1 == ~T3_E~0); 272#L884-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 5#L889-1true assume !(1 == ~T5_E~0); 139#L894-1true assume !(1 == ~T6_E~0); 836#L899-1true assume !(1 == ~T7_E~0); 431#L904-1true assume !(1 == ~E_M~0); 239#L909-1true assume !(1 == ~E_1~0); 371#L914-1true assume !(1 == ~E_2~0); 394#L919-1true assume !(1 == ~E_3~0); 183#L924-1true assume 1 == ~E_4~0;~E_4~0 := 2; 90#L929-1true assume !(1 == ~E_5~0); 705#L934-1true assume !(1 == ~E_6~0); 225#L939-1true assume !(1 == ~E_7~0); 559#L944-1true assume { :end_inline_reset_delta_events } true; 555#L1190-2true [2024-11-19 15:02:57,640 INFO L747 eck$LassoCheckResult]: Loop: 555#L1190-2true assume !false; 135#L1191true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 136#L756-1true assume false; 491#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 302#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 398#L781-3true assume 0 == ~M_E~0;~M_E~0 := 1; 59#L781-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 253#L786-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 308#L791-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 34#L796-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 632#L801-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 176#L806-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 303#L811-3true assume !(0 == ~T7_E~0); 497#L816-3true assume 0 == ~E_M~0;~E_M~0 := 1; 663#L821-3true assume 0 == ~E_1~0;~E_1~0 := 1; 777#L826-3true assume 0 == ~E_2~0;~E_2~0 := 1; 437#L831-3true assume 0 == ~E_3~0;~E_3~0 := 1; 679#L836-3true assume 0 == ~E_4~0;~E_4~0 := 1; 112#L841-3true assume 0 == ~E_5~0;~E_5~0 := 1; 606#L846-3true assume 0 == ~E_6~0;~E_6~0 := 1; 321#L851-3true assume !(0 == ~E_7~0); 55#L856-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 759#L388-27true assume 1 == ~m_pc~0; 608#L389-9true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 773#L399-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 458#is_master_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 709#L967-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155#L967-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 459#L407-27true assume 1 == ~t1_pc~0; 442#L408-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 540#L418-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 482#L975-27true assume !(0 != activate_threads_~tmp___0~0#1); 337#L975-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108#L426-27true assume !(1 == ~t2_pc~0); 851#L426-29true is_transmit2_triggered_~__retres1~2#1 := 0; 113#L437-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 438#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 707#L983-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 602#L983-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 298#L445-27true assume 1 == ~t3_pc~0; 278#L446-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32#L456-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 854#L991-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 376#L991-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171#L464-27true assume 1 == ~t4_pc~0; 483#L465-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65#L475-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 251#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304#L999-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 104#L999-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 796#L483-27true assume !(1 == ~t5_pc~0); 587#L483-29true is_transmit5_triggered_~__retres1~5#1 := 0; 56#L494-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 563#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 552#L1007-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 824#L1007-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 717#L502-27true assume !(1 == ~t6_pc~0); 317#L502-29true is_transmit6_triggered_~__retres1~6#1 := 0; 706#L513-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 690#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 464#L1015-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 750#L1015-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6#L521-27true assume 1 == ~t7_pc~0; 193#L522-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 785#L532-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 162#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30#L1023-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 328#L1023-29true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 678#L869-3true assume 1 == ~M_E~0;~M_E~0 := 2; 462#L869-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 252#L874-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 291#L879-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 320#L884-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 284#L889-3true assume !(1 == ~T5_E~0); 85#L894-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 425#L899-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 97#L904-3true assume 1 == ~E_M~0;~E_M~0 := 2; 269#L909-3true assume 1 == ~E_1~0;~E_1~0 := 2; 74#L914-3true assume 1 == ~E_2~0;~E_2~0 := 2; 94#L919-3true assume 1 == ~E_3~0;~E_3~0 := 2; 619#L924-3true assume 1 == ~E_4~0;~E_4~0 := 2; 448#L929-3true assume !(1 == ~E_5~0); 374#L934-3true assume 1 == ~E_6~0;~E_6~0 := 2; 565#L939-3true assume 1 == ~E_7~0;~E_7~0 := 2; 100#L944-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 601#L596-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 674#L638-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 169#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 790#L1209true assume !(0 == start_simulation_~tmp~3#1); 314#L1209-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 301#L596-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 544#L638-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 609#L1164true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 25#L1171true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 315#stop_simulation_returnLabel#1true start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 128#L1222true assume !(0 != start_simulation_~tmp___0~1#1); 555#L1190-2true [2024-11-19 15:02:57,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:57,646 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2024-11-19 15:02:57,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:57,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628470942] [2024-11-19 15:02:57,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:57,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:57,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:57,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:57,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:57,962 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628470942] [2024-11-19 15:02:57,962 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1628470942] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:57,963 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:57,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:57,964 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [933771357] [2024-11-19 15:02:57,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:57,968 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:57,969 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:57,970 INFO L85 PathProgramCache]: Analyzing trace with hash -41697262, now seen corresponding path program 1 times [2024-11-19 15:02:57,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:57,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013831124] [2024-11-19 15:02:57,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:57,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:57,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:58,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:58,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:58,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013831124] [2024-11-19 15:02:58,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1013831124] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:58,034 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:58,034 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:02:58,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721946491] [2024-11-19 15:02:58,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:58,036 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:58,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:58,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:58,087 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:58,094 INFO L87 Difference]: Start difference. First operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:58,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:58,165 INFO L93 Difference]: Finished difference Result 849 states and 1263 transitions. [2024-11-19 15:02:58,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 849 states and 1263 transitions. [2024-11-19 15:02:58,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:58,186 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 849 states to 843 states and 1257 transitions. [2024-11-19 15:02:58,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-19 15:02:58,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-19 15:02:58,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1257 transitions. [2024-11-19 15:02:58,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:58,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1257 transitions. [2024-11-19 15:02:58,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1257 transitions. [2024-11-19 15:02:58,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-19 15:02:58,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.491103202846975) internal successors, (1257), 842 states have internal predecessors, (1257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:58,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1257 transitions. [2024-11-19 15:02:58,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1257 transitions. [2024-11-19 15:02:58,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:58,275 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1257 transitions. [2024-11-19 15:02:58,276 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-19 15:02:58,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1257 transitions. [2024-11-19 15:02:58,280 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:58,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:58,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:58,283 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:58,283 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:58,284 INFO L745 eck$LassoCheckResult]: Stem: 1961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2509#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2510#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2549#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2104#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2105#L553-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2227#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2228#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2005#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1796#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1797#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1966#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1967#L781 assume !(0 == ~M_E~0); 2444#L781-2 assume !(0 == ~T1_E~0); 2552#L786-1 assume !(0 == ~T2_E~0); 1756#L791-1 assume !(0 == ~T3_E~0); 1757#L796-1 assume !(0 == ~T4_E~0); 2296#L801-1 assume !(0 == ~T5_E~0); 2297#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2327#L811-1 assume !(0 == ~T7_E~0); 1973#L816-1 assume !(0 == ~E_M~0); 1974#L821-1 assume !(0 == ~E_1~0); 1787#L826-1 assume !(0 == ~E_2~0); 1788#L831-1 assume !(0 == ~E_3~0); 2099#L836-1 assume !(0 == ~E_4~0); 2100#L841-1 assume !(0 == ~E_5~0); 1924#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1925#L851-1 assume !(0 == ~E_7~0); 1948#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1949#L388 assume !(1 == ~m_pc~0); 1942#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1943#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2422#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1802#L967 assume !(0 != activate_threads_~tmp~1#1); 1803#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1732#L407 assume 1 == ~t1_pc~0; 1733#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1737#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1738#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1773#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2507#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2059#L426 assume !(1 == ~t2_pc~0); 2060#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2524#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2081#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2082#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2545#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2145#L445 assume 1 == ~t3_pc~0; 2146#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2450#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1730#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1731#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2386#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2354#L464 assume !(1 == ~t4_pc~0); 1952#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1822#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1823#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1834#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2124#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2125#L483 assume 1 == ~t5_pc~0; 2350#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2490#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2463#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2464#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2042#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2043#L502 assume 1 == ~t6_pc~0; 2324#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1862#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1863#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2067#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2264#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2473#L521 assume !(1 == ~t7_pc~0); 2504#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1798#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1799#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2498#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2477#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2413#L869 assume !(1 == ~M_E~0); 2118#L869-2 assume !(1 == ~T1_E~0); 2119#L874-1 assume !(1 == ~T2_E~0); 2532#L879-1 assume !(1 == ~T3_E~0); 2193#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1718#L889-1 assume !(1 == ~T5_E~0); 1719#L894-1 assume !(1 == ~T6_E~0); 1981#L899-1 assume !(1 == ~T7_E~0); 2375#L904-1 assume !(1 == ~E_M~0); 2142#L909-1 assume !(1 == ~E_1~0); 2143#L914-1 assume !(1 == ~E_2~0); 2312#L919-1 assume !(1 == ~E_3~0); 2058#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1895#L929-1 assume !(1 == ~E_5~0); 1896#L934-1 assume !(1 == ~E_6~0); 2120#L939-1 assume !(1 == ~E_7~0); 2121#L944-1 assume { :end_inline_reset_delta_events } true; 1964#L1190-2 [2024-11-19 15:02:58,284 INFO L747 eck$LassoCheckResult]: Loop: 1964#L1190-2 assume !false; 1975#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1976#L756-1 assume !false; 1977#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2550#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1815#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2106#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2107#L653 assume !(0 != eval_~tmp~0#1); 2158#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2237#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2238#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1835#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1836#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2164#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1781#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1782#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2044#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2045#L811-3 assume !(0 == ~T7_E~0); 2239#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2436#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2525#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2379#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2380#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1935#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1936#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2263#L851-3 assume !(0 == ~E_7~0); 1829#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1830#L388-27 assume 1 == ~m_pc~0; 2499#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2500#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2403#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2404#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2008#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2009#L407-27 assume 1 == ~t1_pc~0; 2387#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2388#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2306#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2307#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 2280#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1926#L426-27 assume 1 == ~t2_pc~0; 1927#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1940#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1941#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2381#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2496#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2231#L445-27 assume 1 == ~t3_pc~0; 2205#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1778#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1779#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2232#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2317#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2034#L464-27 assume !(1 == ~t4_pc~0); 1776#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1777#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1848#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2161#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1919#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1920#L483-27 assume 1 == ~t5_pc~0; 2455#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1831#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1832#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2468#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2469#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2536#L502-27 assume !(1 == ~t6_pc~0); 2257#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2258#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2533#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2409#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2410#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1720#L521-27 assume 1 == ~t7_pc~0; 1721#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2072#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2020#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1774#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1775#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2270#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2406#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2162#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2163#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2223#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2216#L889-3 assume !(1 == ~T5_E~0); 1885#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1886#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1906#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1907#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1864#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1865#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1901#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2393#L929-3 assume !(1 == ~E_5~0); 2314#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2315#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1911#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1912#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1740#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2031#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2032#L1209 assume !(0 == start_simulation_~tmp~3#1); 2253#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2236#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1879#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1770#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1765#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1766#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1963#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1964#L1190-2 [2024-11-19 15:02:58,285 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:58,285 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2024-11-19 15:02:58,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:58,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074708450] [2024-11-19 15:02:58,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:58,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:58,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:58,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:58,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:58,379 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074708450] [2024-11-19 15:02:58,379 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2074708450] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:58,379 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:58,380 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:58,380 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1505516411] [2024-11-19 15:02:58,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:58,380 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:58,381 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:58,381 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 1 times [2024-11-19 15:02:58,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:58,381 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793313109] [2024-11-19 15:02:58,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:58,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:58,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:58,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:58,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:58,497 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793313109] [2024-11-19 15:02:58,497 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1793313109] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:58,497 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:58,497 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:58,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048846043] [2024-11-19 15:02:58,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:58,498 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:58,498 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:58,498 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:58,499 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:58,499 INFO L87 Difference]: Start difference. First operand 843 states and 1257 transitions. cyclomatic complexity: 415 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:58,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:58,517 INFO L93 Difference]: Finished difference Result 843 states and 1256 transitions. [2024-11-19 15:02:58,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1256 transitions. [2024-11-19 15:02:58,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:58,525 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1256 transitions. [2024-11-19 15:02:58,525 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-19 15:02:58,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-19 15:02:58,527 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1256 transitions. [2024-11-19 15:02:58,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:58,530 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1256 transitions. [2024-11-19 15:02:58,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1256 transitions. [2024-11-19 15:02:58,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-19 15:02:58,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4899169632265719) internal successors, (1256), 842 states have internal predecessors, (1256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:58,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1256 transitions. [2024-11-19 15:02:58,546 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1256 transitions. [2024-11-19 15:02:58,546 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:58,547 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1256 transitions. [2024-11-19 15:02:58,547 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-19 15:02:58,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1256 transitions. [2024-11-19 15:02:58,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:58,550 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:58,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:58,553 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:58,553 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:58,555 INFO L745 eck$LassoCheckResult]: Stem: 3654#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4202#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4203#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4242#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 3797#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3798#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3920#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3921#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3698#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3489#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3490#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3659#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3660#L781 assume !(0 == ~M_E~0); 4137#L781-2 assume !(0 == ~T1_E~0); 4245#L786-1 assume !(0 == ~T2_E~0); 3449#L791-1 assume !(0 == ~T3_E~0); 3450#L796-1 assume !(0 == ~T4_E~0); 3989#L801-1 assume !(0 == ~T5_E~0); 3990#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4020#L811-1 assume !(0 == ~T7_E~0); 3666#L816-1 assume !(0 == ~E_M~0); 3667#L821-1 assume !(0 == ~E_1~0); 3480#L826-1 assume !(0 == ~E_2~0); 3481#L831-1 assume !(0 == ~E_3~0); 3792#L836-1 assume !(0 == ~E_4~0); 3793#L841-1 assume !(0 == ~E_5~0); 3617#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3618#L851-1 assume !(0 == ~E_7~0); 3641#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3642#L388 assume !(1 == ~m_pc~0); 3635#L388-2 is_master_triggered_~__retres1~0#1 := 0; 3636#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4115#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3495#L967 assume !(0 != activate_threads_~tmp~1#1); 3496#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3425#L407 assume 1 == ~t1_pc~0; 3426#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3430#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3431#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3466#L975 assume !(0 != activate_threads_~tmp___0~0#1); 4200#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3752#L426 assume !(1 == ~t2_pc~0); 3753#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4217#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3774#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3775#L983 assume !(0 != activate_threads_~tmp___1~0#1); 4238#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3838#L445 assume 1 == ~t3_pc~0; 3839#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4143#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3424#L991 assume !(0 != activate_threads_~tmp___2~0#1); 4079#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4047#L464 assume !(1 == ~t4_pc~0); 3645#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3515#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3516#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3527#L999 assume !(0 != activate_threads_~tmp___3~0#1); 3817#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3818#L483 assume 1 == ~t5_pc~0; 4043#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4183#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4156#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4157#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 3735#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3736#L502 assume 1 == ~t6_pc~0; 4017#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3555#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3556#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3760#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 3957#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4166#L521 assume !(1 == ~t7_pc~0); 4197#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3491#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3492#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4191#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4170#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4106#L869 assume !(1 == ~M_E~0); 3811#L869-2 assume !(1 == ~T1_E~0); 3812#L874-1 assume !(1 == ~T2_E~0); 4225#L879-1 assume !(1 == ~T3_E~0); 3886#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3411#L889-1 assume !(1 == ~T5_E~0); 3412#L894-1 assume !(1 == ~T6_E~0); 3674#L899-1 assume !(1 == ~T7_E~0); 4068#L904-1 assume !(1 == ~E_M~0); 3835#L909-1 assume !(1 == ~E_1~0); 3836#L914-1 assume !(1 == ~E_2~0); 4005#L919-1 assume !(1 == ~E_3~0); 3751#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3588#L929-1 assume !(1 == ~E_5~0); 3589#L934-1 assume !(1 == ~E_6~0); 3813#L939-1 assume !(1 == ~E_7~0); 3814#L944-1 assume { :end_inline_reset_delta_events } true; 3657#L1190-2 [2024-11-19 15:02:58,555 INFO L747 eck$LassoCheckResult]: Loop: 3657#L1190-2 assume !false; 3668#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3669#L756-1 assume !false; 3670#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4243#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3508#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3799#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3800#L653 assume !(0 != eval_~tmp~0#1); 3851#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3930#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3931#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3528#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3529#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3857#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3474#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3475#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3737#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3738#L811-3 assume !(0 == ~T7_E~0); 3932#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4129#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4218#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4072#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4073#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3628#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3629#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3956#L851-3 assume !(0 == ~E_7~0); 3522#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3523#L388-27 assume 1 == ~m_pc~0; 4192#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4193#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4096#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4097#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3701#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3702#L407-27 assume 1 == ~t1_pc~0; 4080#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4081#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3999#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4000#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 3973#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3619#L426-27 assume 1 == ~t2_pc~0; 3620#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3633#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3634#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4074#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4189#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3924#L445-27 assume 1 == ~t3_pc~0; 3898#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3471#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3472#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3925#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4010#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3727#L464-27 assume 1 == ~t4_pc~0; 3728#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3470#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3541#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3854#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3612#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3613#L483-27 assume 1 == ~t5_pc~0; 4148#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3524#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3525#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4161#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4162#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4229#L502-27 assume 1 == ~t6_pc~0; 4230#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3951#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4226#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4102#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4103#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3413#L521-27 assume 1 == ~t7_pc~0; 3414#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3765#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3713#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3467#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3468#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3963#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4099#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3855#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3856#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3916#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3909#L889-3 assume !(1 == ~T5_E~0); 3578#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3579#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3599#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3600#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3557#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3558#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3594#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4086#L929-3 assume !(1 == ~E_5~0); 4007#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4008#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3604#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3605#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3433#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3724#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3725#L1209 assume !(0 == start_simulation_~tmp~3#1); 3946#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3929#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3572#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3462#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3463#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3458#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3459#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 3656#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 3657#L1190-2 [2024-11-19 15:02:58,556 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:58,556 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2024-11-19 15:02:58,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:58,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999632473] [2024-11-19 15:02:58,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:58,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:58,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:58,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:58,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:58,637 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1999632473] [2024-11-19 15:02:58,637 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1999632473] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:58,637 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:58,637 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:58,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1568245061] [2024-11-19 15:02:58,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:58,638 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:58,638 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:58,638 INFO L85 PathProgramCache]: Analyzing trace with hash -2135531812, now seen corresponding path program 1 times [2024-11-19 15:02:58,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:58,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861914399] [2024-11-19 15:02:58,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:58,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:58,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:58,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:58,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:58,709 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861914399] [2024-11-19 15:02:58,709 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [861914399] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:58,709 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:58,709 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:58,709 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090057521] [2024-11-19 15:02:58,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:58,709 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:58,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:58,710 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:58,710 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:58,710 INFO L87 Difference]: Start difference. First operand 843 states and 1256 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:58,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:58,724 INFO L93 Difference]: Finished difference Result 843 states and 1255 transitions. [2024-11-19 15:02:58,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1255 transitions. [2024-11-19 15:02:58,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:58,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1255 transitions. [2024-11-19 15:02:58,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-19 15:02:58,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-19 15:02:58,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1255 transitions. [2024-11-19 15:02:58,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:58,733 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1255 transitions. [2024-11-19 15:02:58,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1255 transitions. [2024-11-19 15:02:58,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-19 15:02:58,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4887307236061684) internal successors, (1255), 842 states have internal predecessors, (1255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:58,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1255 transitions. [2024-11-19 15:02:58,744 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1255 transitions. [2024-11-19 15:02:58,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:58,746 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1255 transitions. [2024-11-19 15:02:58,746 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-19 15:02:58,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1255 transitions. [2024-11-19 15:02:58,750 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:58,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:58,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:58,752 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:58,753 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:58,753 INFO L745 eck$LassoCheckResult]: Stem: 5347#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5895#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5896#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5935#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 5490#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5491#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5613#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5614#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5391#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5182#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5183#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5352#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5353#L781 assume !(0 == ~M_E~0); 5830#L781-2 assume !(0 == ~T1_E~0); 5938#L786-1 assume !(0 == ~T2_E~0); 5142#L791-1 assume !(0 == ~T3_E~0); 5143#L796-1 assume !(0 == ~T4_E~0); 5682#L801-1 assume !(0 == ~T5_E~0); 5683#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5713#L811-1 assume !(0 == ~T7_E~0); 5359#L816-1 assume !(0 == ~E_M~0); 5360#L821-1 assume !(0 == ~E_1~0); 5173#L826-1 assume !(0 == ~E_2~0); 5174#L831-1 assume !(0 == ~E_3~0); 5485#L836-1 assume !(0 == ~E_4~0); 5486#L841-1 assume !(0 == ~E_5~0); 5310#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5311#L851-1 assume !(0 == ~E_7~0); 5334#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5335#L388 assume !(1 == ~m_pc~0); 5328#L388-2 is_master_triggered_~__retres1~0#1 := 0; 5329#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5808#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5188#L967 assume !(0 != activate_threads_~tmp~1#1); 5189#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5118#L407 assume 1 == ~t1_pc~0; 5119#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5123#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5159#L975 assume !(0 != activate_threads_~tmp___0~0#1); 5893#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5445#L426 assume !(1 == ~t2_pc~0); 5446#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5910#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5467#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5468#L983 assume !(0 != activate_threads_~tmp___1~0#1); 5931#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5531#L445 assume 1 == ~t3_pc~0; 5532#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5836#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5117#L991 assume !(0 != activate_threads_~tmp___2~0#1); 5772#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5740#L464 assume !(1 == ~t4_pc~0); 5338#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5208#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5209#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5220#L999 assume !(0 != activate_threads_~tmp___3~0#1); 5510#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5511#L483 assume 1 == ~t5_pc~0; 5736#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5876#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5849#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5850#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 5428#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5429#L502 assume 1 == ~t6_pc~0; 5710#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5248#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5249#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5453#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 5650#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5859#L521 assume !(1 == ~t7_pc~0); 5890#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5184#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5185#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5884#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5863#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5799#L869 assume !(1 == ~M_E~0); 5504#L869-2 assume !(1 == ~T1_E~0); 5505#L874-1 assume !(1 == ~T2_E~0); 5918#L879-1 assume !(1 == ~T3_E~0); 5579#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5104#L889-1 assume !(1 == ~T5_E~0); 5105#L894-1 assume !(1 == ~T6_E~0); 5367#L899-1 assume !(1 == ~T7_E~0); 5761#L904-1 assume !(1 == ~E_M~0); 5528#L909-1 assume !(1 == ~E_1~0); 5529#L914-1 assume !(1 == ~E_2~0); 5698#L919-1 assume !(1 == ~E_3~0); 5444#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5281#L929-1 assume !(1 == ~E_5~0); 5282#L934-1 assume !(1 == ~E_6~0); 5506#L939-1 assume !(1 == ~E_7~0); 5507#L944-1 assume { :end_inline_reset_delta_events } true; 5350#L1190-2 [2024-11-19 15:02:58,753 INFO L747 eck$LassoCheckResult]: Loop: 5350#L1190-2 assume !false; 5361#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5362#L756-1 assume !false; 5363#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5936#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5201#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5492#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5493#L653 assume !(0 != eval_~tmp~0#1); 5544#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5624#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5221#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5222#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5550#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5167#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5168#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5430#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5431#L811-3 assume !(0 == ~T7_E~0); 5625#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5822#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5911#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5765#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5766#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5321#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5322#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5649#L851-3 assume !(0 == ~E_7~0); 5215#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5216#L388-27 assume 1 == ~m_pc~0; 5885#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5886#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5789#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5790#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5394#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5395#L407-27 assume 1 == ~t1_pc~0; 5773#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5774#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5692#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5693#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 5666#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5312#L426-27 assume 1 == ~t2_pc~0; 5313#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5326#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5327#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5767#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5882#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5617#L445-27 assume 1 == ~t3_pc~0; 5591#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5164#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5165#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5618#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5703#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5420#L464-27 assume !(1 == ~t4_pc~0); 5162#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5163#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5234#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5547#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5305#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5306#L483-27 assume 1 == ~t5_pc~0; 5841#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5217#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5218#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5854#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5855#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5922#L502-27 assume 1 == ~t6_pc~0; 5923#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5644#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5919#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5795#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5796#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5106#L521-27 assume 1 == ~t7_pc~0; 5107#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5458#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5406#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5160#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5161#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5656#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5792#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5548#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5549#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5609#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5602#L889-3 assume !(1 == ~T5_E~0); 5271#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5272#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5292#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5293#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5250#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5251#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5287#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5779#L929-3 assume !(1 == ~E_5~0); 5700#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5701#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5297#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5298#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5126#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5417#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5418#L1209 assume !(0 == start_simulation_~tmp~3#1); 5639#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5622#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5265#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5155#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5156#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5151#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5152#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 5349#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 5350#L1190-2 [2024-11-19 15:02:58,754 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:58,754 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2024-11-19 15:02:58,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:58,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [772014707] [2024-11-19 15:02:58,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:58,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:58,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:58,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:58,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:58,816 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [772014707] [2024-11-19 15:02:58,816 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [772014707] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:58,816 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:58,817 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:58,817 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912252114] [2024-11-19 15:02:58,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:58,817 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:58,818 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:58,818 INFO L85 PathProgramCache]: Analyzing trace with hash 1885656989, now seen corresponding path program 1 times [2024-11-19 15:02:58,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:58,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369205406] [2024-11-19 15:02:58,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:58,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:58,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:58,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:58,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:58,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369205406] [2024-11-19 15:02:58,870 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1369205406] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:58,870 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:58,870 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:58,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369686873] [2024-11-19 15:02:58,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:58,871 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:58,871 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:58,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:58,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:58,871 INFO L87 Difference]: Start difference. First operand 843 states and 1255 transitions. cyclomatic complexity: 413 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:58,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:58,883 INFO L93 Difference]: Finished difference Result 843 states and 1254 transitions. [2024-11-19 15:02:58,883 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1254 transitions. [2024-11-19 15:02:58,886 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:58,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1254 transitions. [2024-11-19 15:02:58,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-19 15:02:58,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-19 15:02:58,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1254 transitions. [2024-11-19 15:02:58,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:58,891 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1254 transitions. [2024-11-19 15:02:58,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1254 transitions. [2024-11-19 15:02:58,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-19 15:02:58,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4875444839857652) internal successors, (1254), 842 states have internal predecessors, (1254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:58,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1254 transitions. [2024-11-19 15:02:58,905 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1254 transitions. [2024-11-19 15:02:58,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:58,907 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1254 transitions. [2024-11-19 15:02:58,907 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-19 15:02:58,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1254 transitions. [2024-11-19 15:02:58,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:58,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:58,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:58,912 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:58,912 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:58,913 INFO L745 eck$LassoCheckResult]: Stem: 7040#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7041#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7588#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7589#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7628#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 7183#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7184#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7306#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7307#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7084#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6875#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6876#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7048#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7049#L781 assume !(0 == ~M_E~0); 7523#L781-2 assume !(0 == ~T1_E~0); 7631#L786-1 assume !(0 == ~T2_E~0); 6838#L791-1 assume !(0 == ~T3_E~0); 6839#L796-1 assume !(0 == ~T4_E~0); 7375#L801-1 assume !(0 == ~T5_E~0); 7376#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7406#L811-1 assume !(0 == ~T7_E~0); 7052#L816-1 assume !(0 == ~E_M~0); 7053#L821-1 assume !(0 == ~E_1~0); 6866#L826-1 assume !(0 == ~E_2~0); 6867#L831-1 assume !(0 == ~E_3~0); 7178#L836-1 assume !(0 == ~E_4~0); 7179#L841-1 assume !(0 == ~E_5~0); 7003#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 7004#L851-1 assume !(0 == ~E_7~0); 7027#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7028#L388 assume !(1 == ~m_pc~0); 7021#L388-2 is_master_triggered_~__retres1~0#1 := 0; 7022#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7501#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6881#L967 assume !(0 != activate_threads_~tmp~1#1); 6882#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6811#L407 assume 1 == ~t1_pc~0; 6812#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6819#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6820#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6854#L975 assume !(0 != activate_threads_~tmp___0~0#1); 7586#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7138#L426 assume !(1 == ~t2_pc~0); 7139#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7603#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7160#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7161#L983 assume !(0 != activate_threads_~tmp___1~0#1); 7624#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7224#L445 assume 1 == ~t3_pc~0; 7225#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7529#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6809#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6810#L991 assume !(0 != activate_threads_~tmp___2~0#1); 7465#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7433#L464 assume !(1 == ~t4_pc~0); 7031#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6901#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6902#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6913#L999 assume !(0 != activate_threads_~tmp___3~0#1); 7203#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7204#L483 assume 1 == ~t5_pc~0; 7429#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7569#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7543#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 7123#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7124#L502 assume 1 == ~t6_pc~0; 7404#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6941#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6942#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7148#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 7343#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7552#L521 assume !(1 == ~t7_pc~0); 7583#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6877#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6878#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7577#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7556#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7494#L869 assume !(1 == ~M_E~0); 7197#L869-2 assume !(1 == ~T1_E~0); 7198#L874-1 assume !(1 == ~T2_E~0); 7611#L879-1 assume !(1 == ~T3_E~0); 7272#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6797#L889-1 assume !(1 == ~T5_E~0); 6798#L894-1 assume !(1 == ~T6_E~0); 7063#L899-1 assume !(1 == ~T7_E~0); 7455#L904-1 assume !(1 == ~E_M~0); 7221#L909-1 assume !(1 == ~E_1~0); 7222#L914-1 assume !(1 == ~E_2~0); 7392#L919-1 assume !(1 == ~E_3~0); 7137#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6974#L929-1 assume !(1 == ~E_5~0); 6975#L934-1 assume !(1 == ~E_6~0); 7201#L939-1 assume !(1 == ~E_7~0); 7202#L944-1 assume { :end_inline_reset_delta_events } true; 7043#L1190-2 [2024-11-19 15:02:58,913 INFO L747 eck$LassoCheckResult]: Loop: 7043#L1190-2 assume !false; 7054#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7055#L756-1 assume !false; 7056#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7629#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6896#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7186#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7187#L653 assume !(0 != eval_~tmp~0#1); 7240#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7317#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7318#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6914#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6915#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7243#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6860#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6861#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7121#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7122#L811-3 assume !(0 == ~T7_E~0); 7316#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7515#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7604#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7458#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7459#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7014#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7015#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7342#L851-3 assume !(0 == ~E_7~0); 6908#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6909#L388-27 assume 1 == ~m_pc~0; 7578#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7579#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7482#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7483#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7087#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7088#L407-27 assume 1 == ~t1_pc~0; 7466#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7467#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7385#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7386#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 7359#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7005#L426-27 assume 1 == ~t2_pc~0; 7006#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7019#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7020#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7460#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7575#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7310#L445-27 assume 1 == ~t3_pc~0; 7282#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6857#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6858#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7311#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7395#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7113#L464-27 assume !(1 == ~t4_pc~0); 6855#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 6856#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6927#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7238#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6998#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6999#L483-27 assume 1 == ~t5_pc~0; 7534#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6910#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6911#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7547#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7548#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7615#L502-27 assume 1 == ~t6_pc~0; 7616#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7337#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7612#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7488#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7489#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6799#L521-27 assume 1 == ~t7_pc~0; 6800#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7151#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7099#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6852#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6853#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7349#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7485#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7241#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7242#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7302#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7295#L889-3 assume !(1 == ~T5_E~0); 6964#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6965#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6985#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6986#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6943#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6944#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6980#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7472#L929-3 assume !(1 == ~E_5~0); 7393#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7394#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6990#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6991#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6817#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7110#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7111#L1209 assume !(0 == start_simulation_~tmp~3#1); 7332#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7315#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6958#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6848#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 6849#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 6844#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6845#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 7042#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 7043#L1190-2 [2024-11-19 15:02:58,913 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:58,913 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2024-11-19 15:02:58,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:58,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [794588780] [2024-11-19 15:02:58,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:58,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:58,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:58,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:58,982 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:58,982 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [794588780] [2024-11-19 15:02:58,982 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [794588780] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:58,982 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:58,982 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:58,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824285704] [2024-11-19 15:02:58,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:58,983 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:58,983 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:58,983 INFO L85 PathProgramCache]: Analyzing trace with hash 1885656989, now seen corresponding path program 2 times [2024-11-19 15:02:58,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:58,983 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087302498] [2024-11-19 15:02:58,983 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:02:58,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:59,000 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:02:59,000 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:02:59,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:59,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:59,057 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1087302498] [2024-11-19 15:02:59,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1087302498] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:59,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:59,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:59,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [331311075] [2024-11-19 15:02:59,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:59,058 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:59,058 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:59,058 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:59,058 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:59,058 INFO L87 Difference]: Start difference. First operand 843 states and 1254 transitions. cyclomatic complexity: 412 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:59,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:59,083 INFO L93 Difference]: Finished difference Result 843 states and 1253 transitions. [2024-11-19 15:02:59,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1253 transitions. [2024-11-19 15:02:59,094 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:59,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1253 transitions. [2024-11-19 15:02:59,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-19 15:02:59,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-19 15:02:59,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1253 transitions. [2024-11-19 15:02:59,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:59,099 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1253 transitions. [2024-11-19 15:02:59,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1253 transitions. [2024-11-19 15:02:59,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-19 15:02:59,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4863582443653618) internal successors, (1253), 842 states have internal predecessors, (1253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:59,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1253 transitions. [2024-11-19 15:02:59,123 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1253 transitions. [2024-11-19 15:02:59,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:59,124 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1253 transitions. [2024-11-19 15:02:59,124 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-19 15:02:59,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1253 transitions. [2024-11-19 15:02:59,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:59,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:59,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:59,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:59,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:59,131 INFO L745 eck$LassoCheckResult]: Stem: 8733#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9281#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9282#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9321#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 8876#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8877#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8999#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9000#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8777#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8568#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8569#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8741#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8742#L781 assume !(0 == ~M_E~0); 9216#L781-2 assume !(0 == ~T1_E~0); 9324#L786-1 assume !(0 == ~T2_E~0); 8528#L791-1 assume !(0 == ~T3_E~0); 8529#L796-1 assume !(0 == ~T4_E~0); 9068#L801-1 assume !(0 == ~T5_E~0); 9069#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9099#L811-1 assume !(0 == ~T7_E~0); 8745#L816-1 assume !(0 == ~E_M~0); 8746#L821-1 assume !(0 == ~E_1~0); 8559#L826-1 assume !(0 == ~E_2~0); 8560#L831-1 assume !(0 == ~E_3~0); 8871#L836-1 assume !(0 == ~E_4~0); 8872#L841-1 assume !(0 == ~E_5~0); 8696#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8697#L851-1 assume !(0 == ~E_7~0); 8720#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8721#L388 assume !(1 == ~m_pc~0); 8714#L388-2 is_master_triggered_~__retres1~0#1 := 0; 8715#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9194#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8574#L967 assume !(0 != activate_threads_~tmp~1#1); 8575#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8504#L407 assume 1 == ~t1_pc~0; 8505#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8512#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8513#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8547#L975 assume !(0 != activate_threads_~tmp___0~0#1); 9279#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8831#L426 assume !(1 == ~t2_pc~0); 8832#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9296#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8853#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8854#L983 assume !(0 != activate_threads_~tmp___1~0#1); 9317#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8917#L445 assume 1 == ~t3_pc~0; 8918#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9222#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8502#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8503#L991 assume !(0 != activate_threads_~tmp___2~0#1); 9158#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9126#L464 assume !(1 == ~t4_pc~0); 8724#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8594#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8595#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8606#L999 assume !(0 != activate_threads_~tmp___3~0#1); 8896#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8897#L483 assume 1 == ~t5_pc~0; 9122#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9262#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9235#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9236#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 8814#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8815#L502 assume 1 == ~t6_pc~0; 9097#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8634#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8635#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8839#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 9036#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9245#L521 assume !(1 == ~t7_pc~0); 9276#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8570#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8571#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9270#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9249#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9185#L869 assume !(1 == ~M_E~0); 8890#L869-2 assume !(1 == ~T1_E~0); 8891#L874-1 assume !(1 == ~T2_E~0); 9304#L879-1 assume !(1 == ~T3_E~0); 8965#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8490#L889-1 assume !(1 == ~T5_E~0); 8491#L894-1 assume !(1 == ~T6_E~0); 8753#L899-1 assume !(1 == ~T7_E~0); 9148#L904-1 assume !(1 == ~E_M~0); 8914#L909-1 assume !(1 == ~E_1~0); 8915#L914-1 assume !(1 == ~E_2~0); 9084#L919-1 assume !(1 == ~E_3~0); 8830#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8667#L929-1 assume !(1 == ~E_5~0); 8668#L934-1 assume !(1 == ~E_6~0); 8892#L939-1 assume !(1 == ~E_7~0); 8893#L944-1 assume { :end_inline_reset_delta_events } true; 8736#L1190-2 [2024-11-19 15:02:59,131 INFO L747 eck$LassoCheckResult]: Loop: 8736#L1190-2 assume !false; 8747#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8748#L756-1 assume !false; 8749#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9322#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8589#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8878#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8879#L653 assume !(0 != eval_~tmp~0#1); 8931#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9009#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9010#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8607#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8608#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8936#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8553#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8554#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8816#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8817#L811-3 assume !(0 == ~T7_E~0); 9011#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9208#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9297#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9151#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9152#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8707#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8708#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9035#L851-3 assume !(0 == ~E_7~0); 8601#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8602#L388-27 assume 1 == ~m_pc~0; 9271#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9272#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9175#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9176#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8780#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8781#L407-27 assume 1 == ~t1_pc~0; 9159#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9160#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9078#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9079#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 9052#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8698#L426-27 assume 1 == ~t2_pc~0; 8699#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8712#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8713#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9153#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9268#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9003#L445-27 assume 1 == ~t3_pc~0; 8977#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8550#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8551#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9004#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9088#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8806#L464-27 assume !(1 == ~t4_pc~0); 8548#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 8549#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8618#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8929#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8691#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8692#L483-27 assume 1 == ~t5_pc~0; 9227#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8603#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8604#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9240#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9241#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9308#L502-27 assume !(1 == ~t6_pc~0); 9029#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 9030#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9305#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9181#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9182#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8492#L521-27 assume 1 == ~t7_pc~0; 8493#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8844#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8792#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8545#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8546#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9040#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9178#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8934#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8935#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8995#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8988#L889-3 assume !(1 == ~T5_E~0); 8657#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8658#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8678#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8679#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8636#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8637#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8673#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9165#L929-3 assume !(1 == ~E_5~0); 9086#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9087#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8683#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8684#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8510#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8804#L1209 assume !(0 == start_simulation_~tmp~3#1); 9025#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9008#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8651#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8541#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8542#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 8537#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8538#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8735#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 8736#L1190-2 [2024-11-19 15:02:59,132 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:59,132 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2024-11-19 15:02:59,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:59,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740592937] [2024-11-19 15:02:59,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:59,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:59,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:59,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:59,184 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:59,184 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740592937] [2024-11-19 15:02:59,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740592937] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:59,184 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:59,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:59,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [367293825] [2024-11-19 15:02:59,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:59,184 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:59,185 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:59,185 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 2 times [2024-11-19 15:02:59,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:59,185 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1496120764] [2024-11-19 15:02:59,185 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:02:59,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:59,205 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:02:59,206 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:02:59,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:59,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:59,262 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1496120764] [2024-11-19 15:02:59,262 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1496120764] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:59,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:59,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:59,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1774952270] [2024-11-19 15:02:59,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:59,263 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:59,263 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:59,263 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:59,263 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:59,264 INFO L87 Difference]: Start difference. First operand 843 states and 1253 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:59,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:59,276 INFO L93 Difference]: Finished difference Result 843 states and 1252 transitions. [2024-11-19 15:02:59,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1252 transitions. [2024-11-19 15:02:59,280 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:59,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1252 transitions. [2024-11-19 15:02:59,283 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-19 15:02:59,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-19 15:02:59,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1252 transitions. [2024-11-19 15:02:59,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:59,284 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1252 transitions. [2024-11-19 15:02:59,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1252 transitions. [2024-11-19 15:02:59,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-19 15:02:59,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4851720047449586) internal successors, (1252), 842 states have internal predecessors, (1252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:59,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1252 transitions. [2024-11-19 15:02:59,294 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1252 transitions. [2024-11-19 15:02:59,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:59,295 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1252 transitions. [2024-11-19 15:02:59,295 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-19 15:02:59,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1252 transitions. [2024-11-19 15:02:59,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:59,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:59,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:59,299 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:59,300 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:59,300 INFO L745 eck$LassoCheckResult]: Stem: 10426#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10427#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11014#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 10569#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10570#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10692#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10693#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10470#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10261#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10262#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10431#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10432#L781 assume !(0 == ~M_E~0); 10909#L781-2 assume !(0 == ~T1_E~0); 11017#L786-1 assume !(0 == ~T2_E~0); 10221#L791-1 assume !(0 == ~T3_E~0); 10222#L796-1 assume !(0 == ~T4_E~0); 10761#L801-1 assume !(0 == ~T5_E~0); 10762#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10792#L811-1 assume !(0 == ~T7_E~0); 10438#L816-1 assume !(0 == ~E_M~0); 10439#L821-1 assume !(0 == ~E_1~0); 10252#L826-1 assume !(0 == ~E_2~0); 10253#L831-1 assume !(0 == ~E_3~0); 10564#L836-1 assume !(0 == ~E_4~0); 10565#L841-1 assume !(0 == ~E_5~0); 10389#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10390#L851-1 assume !(0 == ~E_7~0); 10413#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10414#L388 assume !(1 == ~m_pc~0); 10407#L388-2 is_master_triggered_~__retres1~0#1 := 0; 10408#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10887#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10267#L967 assume !(0 != activate_threads_~tmp~1#1); 10268#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10197#L407 assume 1 == ~t1_pc~0; 10198#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10202#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10238#L975 assume !(0 != activate_threads_~tmp___0~0#1); 10972#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10524#L426 assume !(1 == ~t2_pc~0); 10525#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10989#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10546#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10547#L983 assume !(0 != activate_threads_~tmp___1~0#1); 11010#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10610#L445 assume 1 == ~t3_pc~0; 10611#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10915#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10195#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10196#L991 assume !(0 != activate_threads_~tmp___2~0#1); 10851#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10819#L464 assume !(1 == ~t4_pc~0); 10417#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10287#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10288#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10299#L999 assume !(0 != activate_threads_~tmp___3~0#1); 10589#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10590#L483 assume 1 == ~t5_pc~0; 10815#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10955#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10929#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 10507#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10508#L502 assume 1 == ~t6_pc~0; 10789#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10327#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10328#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10532#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 10729#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10938#L521 assume !(1 == ~t7_pc~0); 10969#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10263#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10264#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10963#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10942#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10878#L869 assume !(1 == ~M_E~0); 10583#L869-2 assume !(1 == ~T1_E~0); 10584#L874-1 assume !(1 == ~T2_E~0); 10997#L879-1 assume !(1 == ~T3_E~0); 10658#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10183#L889-1 assume !(1 == ~T5_E~0); 10184#L894-1 assume !(1 == ~T6_E~0); 10446#L899-1 assume !(1 == ~T7_E~0); 10840#L904-1 assume !(1 == ~E_M~0); 10607#L909-1 assume !(1 == ~E_1~0); 10608#L914-1 assume !(1 == ~E_2~0); 10777#L919-1 assume !(1 == ~E_3~0); 10523#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10360#L929-1 assume !(1 == ~E_5~0); 10361#L934-1 assume !(1 == ~E_6~0); 10585#L939-1 assume !(1 == ~E_7~0); 10586#L944-1 assume { :end_inline_reset_delta_events } true; 10429#L1190-2 [2024-11-19 15:02:59,300 INFO L747 eck$LassoCheckResult]: Loop: 10429#L1190-2 assume !false; 10440#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10441#L756-1 assume !false; 10442#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11015#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10280#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10571#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10572#L653 assume !(0 != eval_~tmp~0#1); 10623#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10703#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10300#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10301#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10629#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10246#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10247#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10509#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10510#L811-3 assume !(0 == ~T7_E~0); 10704#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10901#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10990#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10844#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10845#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10400#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10401#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10728#L851-3 assume !(0 == ~E_7~0); 10294#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10295#L388-27 assume 1 == ~m_pc~0; 10964#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10965#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10868#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10869#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10473#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10474#L407-27 assume 1 == ~t1_pc~0; 10852#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10853#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10771#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10772#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 10745#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10391#L426-27 assume 1 == ~t2_pc~0; 10392#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10405#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10406#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10846#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10961#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10696#L445-27 assume 1 == ~t3_pc~0; 10670#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10243#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10244#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10697#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10782#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10499#L464-27 assume !(1 == ~t4_pc~0); 10241#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 10242#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10313#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10626#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10384#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10385#L483-27 assume 1 == ~t5_pc~0; 10920#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10296#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10297#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10933#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10934#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11001#L502-27 assume !(1 == ~t6_pc~0); 10722#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 10723#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10998#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10874#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10875#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10185#L521-27 assume 1 == ~t7_pc~0; 10186#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10537#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10485#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10239#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10240#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10735#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10871#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10627#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10628#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10688#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10681#L889-3 assume !(1 == ~T5_E~0); 10350#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10351#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10371#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10372#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10329#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10330#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10366#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10858#L929-3 assume !(1 == ~E_5~0); 10779#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10780#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10376#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10377#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10205#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10496#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10497#L1209 assume !(0 == start_simulation_~tmp~3#1); 10718#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10701#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10344#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10234#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10235#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 10230#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10231#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10428#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 10429#L1190-2 [2024-11-19 15:02:59,301 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:59,301 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2024-11-19 15:02:59,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:59,301 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977745632] [2024-11-19 15:02:59,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:59,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:59,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:59,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:59,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:59,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977745632] [2024-11-19 15:02:59,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [977745632] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:59,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:59,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:59,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795892743] [2024-11-19 15:02:59,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:59,336 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:59,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:59,337 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 3 times [2024-11-19 15:02:59,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:59,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056655429] [2024-11-19 15:02:59,337 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 15:02:59,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:59,353 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 15:02:59,353 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:02:59,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:59,380 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:59,380 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056655429] [2024-11-19 15:02:59,380 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1056655429] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:59,380 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:59,380 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:59,380 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [826226611] [2024-11-19 15:02:59,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:59,381 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:59,381 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:59,381 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:02:59,381 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:02:59,381 INFO L87 Difference]: Start difference. First operand 843 states and 1252 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:59,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:59,394 INFO L93 Difference]: Finished difference Result 843 states and 1251 transitions. [2024-11-19 15:02:59,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1251 transitions. [2024-11-19 15:02:59,399 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:59,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1251 transitions. [2024-11-19 15:02:59,402 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-19 15:02:59,402 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-19 15:02:59,402 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1251 transitions. [2024-11-19 15:02:59,403 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:59,403 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1251 transitions. [2024-11-19 15:02:59,404 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1251 transitions. [2024-11-19 15:02:59,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-19 15:02:59,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4839857651245552) internal successors, (1251), 842 states have internal predecessors, (1251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:59,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1251 transitions. [2024-11-19 15:02:59,413 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1251 transitions. [2024-11-19 15:02:59,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:02:59,415 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1251 transitions. [2024-11-19 15:02:59,415 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-19 15:02:59,415 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1251 transitions. [2024-11-19 15:02:59,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-19 15:02:59,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:59,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:59,419 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:59,419 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:59,420 INFO L745 eck$LassoCheckResult]: Stem: 12119#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12120#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12667#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12668#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12707#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 12262#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12263#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12385#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12386#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12163#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11954#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11955#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12124#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12125#L781 assume !(0 == ~M_E~0); 12602#L781-2 assume !(0 == ~T1_E~0); 12710#L786-1 assume !(0 == ~T2_E~0); 11914#L791-1 assume !(0 == ~T3_E~0); 11915#L796-1 assume !(0 == ~T4_E~0); 12454#L801-1 assume !(0 == ~T5_E~0); 12455#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12485#L811-1 assume !(0 == ~T7_E~0); 12131#L816-1 assume !(0 == ~E_M~0); 12132#L821-1 assume !(0 == ~E_1~0); 11945#L826-1 assume !(0 == ~E_2~0); 11946#L831-1 assume !(0 == ~E_3~0); 12257#L836-1 assume !(0 == ~E_4~0); 12258#L841-1 assume !(0 == ~E_5~0); 12082#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 12083#L851-1 assume !(0 == ~E_7~0); 12106#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12107#L388 assume !(1 == ~m_pc~0); 12100#L388-2 is_master_triggered_~__retres1~0#1 := 0; 12101#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12580#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11960#L967 assume !(0 != activate_threads_~tmp~1#1); 11961#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11890#L407 assume 1 == ~t1_pc~0; 11891#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11895#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11896#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11931#L975 assume !(0 != activate_threads_~tmp___0~0#1); 12665#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12217#L426 assume !(1 == ~t2_pc~0); 12218#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12682#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12239#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12240#L983 assume !(0 != activate_threads_~tmp___1~0#1); 12703#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12303#L445 assume 1 == ~t3_pc~0; 12304#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12608#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11888#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11889#L991 assume !(0 != activate_threads_~tmp___2~0#1); 12544#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12512#L464 assume !(1 == ~t4_pc~0); 12110#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11980#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11981#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11992#L999 assume !(0 != activate_threads_~tmp___3~0#1); 12282#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12283#L483 assume 1 == ~t5_pc~0; 12508#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12648#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12621#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12622#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 12200#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12201#L502 assume 1 == ~t6_pc~0; 12482#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12020#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12021#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12225#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 12422#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12631#L521 assume !(1 == ~t7_pc~0); 12662#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11956#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11957#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12656#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12635#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12571#L869 assume !(1 == ~M_E~0); 12276#L869-2 assume !(1 == ~T1_E~0); 12277#L874-1 assume !(1 == ~T2_E~0); 12690#L879-1 assume !(1 == ~T3_E~0); 12351#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11876#L889-1 assume !(1 == ~T5_E~0); 11877#L894-1 assume !(1 == ~T6_E~0); 12139#L899-1 assume !(1 == ~T7_E~0); 12533#L904-1 assume !(1 == ~E_M~0); 12300#L909-1 assume !(1 == ~E_1~0); 12301#L914-1 assume !(1 == ~E_2~0); 12470#L919-1 assume !(1 == ~E_3~0); 12216#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12053#L929-1 assume !(1 == ~E_5~0); 12054#L934-1 assume !(1 == ~E_6~0); 12278#L939-1 assume !(1 == ~E_7~0); 12279#L944-1 assume { :end_inline_reset_delta_events } true; 12122#L1190-2 [2024-11-19 15:02:59,420 INFO L747 eck$LassoCheckResult]: Loop: 12122#L1190-2 assume !false; 12133#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12134#L756-1 assume !false; 12135#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12708#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11973#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12264#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12265#L653 assume !(0 != eval_~tmp~0#1); 12316#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12395#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12396#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11993#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11994#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12322#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11939#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11940#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12202#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12203#L811-3 assume !(0 == ~T7_E~0); 12397#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12594#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12683#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12537#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12538#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12093#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12094#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12421#L851-3 assume !(0 == ~E_7~0); 11987#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11988#L388-27 assume 1 == ~m_pc~0; 12657#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12658#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12561#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12562#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12166#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12167#L407-27 assume 1 == ~t1_pc~0; 12545#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12546#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12464#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12465#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 12438#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12084#L426-27 assume 1 == ~t2_pc~0; 12085#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12098#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12099#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12539#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12654#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12389#L445-27 assume 1 == ~t3_pc~0; 12363#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11936#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11937#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12390#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12475#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12192#L464-27 assume 1 == ~t4_pc~0; 12193#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11935#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12006#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12319#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12077#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12078#L483-27 assume 1 == ~t5_pc~0; 12613#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11989#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11990#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12626#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12627#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12694#L502-27 assume 1 == ~t6_pc~0; 12695#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12416#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12691#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12567#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12568#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11878#L521-27 assume 1 == ~t7_pc~0; 11879#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12230#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12178#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11932#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11933#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12428#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12564#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12320#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12321#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12381#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12374#L889-3 assume !(1 == ~T5_E~0); 12043#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12044#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12064#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12065#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12022#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12023#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12059#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12551#L929-3 assume !(1 == ~E_5~0); 12472#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12473#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12069#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12070#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11898#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12189#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 12190#L1209 assume !(0 == start_simulation_~tmp~3#1); 12411#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12394#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 12037#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11927#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11928#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11923#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11924#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12121#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 12122#L1190-2 [2024-11-19 15:02:59,421 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:59,421 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2024-11-19 15:02:59,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:59,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930720432] [2024-11-19 15:02:59,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:59,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:59,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:59,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:59,478 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:59,478 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930720432] [2024-11-19 15:02:59,479 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930720432] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:59,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:59,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:59,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556885404] [2024-11-19 15:02:59,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:59,481 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:59,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:59,482 INFO L85 PathProgramCache]: Analyzing trace with hash -2135531812, now seen corresponding path program 2 times [2024-11-19 15:02:59,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:59,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721560325] [2024-11-19 15:02:59,483 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:02:59,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:59,509 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:02:59,510 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:02:59,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:59,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:59,538 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [721560325] [2024-11-19 15:02:59,538 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [721560325] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:59,540 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:59,540 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:59,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102104614] [2024-11-19 15:02:59,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:59,541 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:59,541 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:59,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:02:59,541 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:02:59,541 INFO L87 Difference]: Start difference. First operand 843 states and 1251 transitions. cyclomatic complexity: 409 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:59,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:59,640 INFO L93 Difference]: Finished difference Result 1525 states and 2254 transitions. [2024-11-19 15:02:59,640 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1525 states and 2254 transitions. [2024-11-19 15:02:59,646 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1406 [2024-11-19 15:02:59,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1525 states to 1525 states and 2254 transitions. [2024-11-19 15:02:59,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1525 [2024-11-19 15:02:59,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1525 [2024-11-19 15:02:59,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1525 states and 2254 transitions. [2024-11-19 15:02:59,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:59,653 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2024-11-19 15:02:59,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1525 states and 2254 transitions. [2024-11-19 15:02:59,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1525 to 1525. [2024-11-19 15:02:59,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1525 states, 1525 states have (on average 1.4780327868852459) internal successors, (2254), 1524 states have internal predecessors, (2254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:59,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1525 states to 1525 states and 2254 transitions. [2024-11-19 15:02:59,677 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2024-11-19 15:02:59,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:02:59,679 INFO L425 stractBuchiCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2024-11-19 15:02:59,679 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-19 15:02:59,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1525 states and 2254 transitions. [2024-11-19 15:02:59,684 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1406 [2024-11-19 15:02:59,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:59,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:59,685 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:59,685 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:59,686 INFO L745 eck$LassoCheckResult]: Stem: 14498#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15072#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15073#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15121#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 14642#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14643#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14769#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14770#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14542#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14332#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14333#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14503#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14504#L781 assume !(0 == ~M_E~0); 15005#L781-2 assume !(0 == ~T1_E~0); 15127#L786-1 assume !(0 == ~T2_E~0); 14292#L791-1 assume !(0 == ~T3_E~0); 14293#L796-1 assume !(0 == ~T4_E~0); 14843#L801-1 assume !(0 == ~T5_E~0); 14844#L806-1 assume !(0 == ~T6_E~0); 14876#L811-1 assume !(0 == ~T7_E~0); 14510#L816-1 assume !(0 == ~E_M~0); 14511#L821-1 assume !(0 == ~E_1~0); 14323#L826-1 assume !(0 == ~E_2~0); 14324#L831-1 assume !(0 == ~E_3~0); 14637#L836-1 assume !(0 == ~E_4~0); 14638#L841-1 assume !(0 == ~E_5~0); 14460#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14461#L851-1 assume !(0 == ~E_7~0); 14484#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14485#L388 assume !(1 == ~m_pc~0); 14478#L388-2 is_master_triggered_~__retres1~0#1 := 0; 14479#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14981#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14338#L967 assume !(0 != activate_threads_~tmp~1#1); 14339#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14268#L407 assume 1 == ~t1_pc~0; 14269#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14273#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14274#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14309#L975 assume !(0 != activate_threads_~tmp___0~0#1); 15070#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14596#L426 assume !(1 == ~t2_pc~0); 14597#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15089#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14619#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14620#L983 assume !(0 != activate_threads_~tmp___1~0#1); 15116#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14684#L445 assume 1 == ~t3_pc~0; 14685#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15011#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14267#L991 assume !(0 != activate_threads_~tmp___2~0#1); 14942#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14908#L464 assume !(1 == ~t4_pc~0); 14488#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14358#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14359#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14370#L999 assume !(0 != activate_threads_~tmp___3~0#1); 14662#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14663#L483 assume 1 == ~t5_pc~0; 14904#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15053#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15024#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15025#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 14579#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14580#L502 assume 1 == ~t6_pc~0; 14873#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14398#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14399#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14605#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 14809#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15036#L521 assume !(1 == ~t7_pc~0); 15067#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14334#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14335#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15061#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15040#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14970#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 14656#L869-2 assume !(1 == ~T1_E~0); 14657#L874-1 assume !(1 == ~T2_E~0); 15101#L879-1 assume !(1 == ~T3_E~0); 14734#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14254#L889-1 assume !(1 == ~T5_E~0); 14255#L894-1 assume !(1 == ~T6_E~0); 14518#L899-1 assume !(1 == ~T7_E~0); 14930#L904-1 assume !(1 == ~E_M~0); 14681#L909-1 assume !(1 == ~E_1~0); 14682#L914-1 assume !(1 == ~E_2~0); 14860#L919-1 assume !(1 == ~E_3~0); 14595#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14431#L929-1 assume !(1 == ~E_5~0); 14432#L934-1 assume !(1 == ~E_6~0); 15105#L939-1 assume !(1 == ~E_7~0); 15035#L944-1 assume { :end_inline_reset_delta_events } true; 14501#L1190-2 [2024-11-19 15:02:59,686 INFO L747 eck$LassoCheckResult]: Loop: 14501#L1190-2 assume !false; 15139#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15138#L756-1 assume !false; 15137#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15136#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14899#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14900#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14696#L653 assume !(0 != eval_~tmp~0#1); 14698#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14780#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14781#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14371#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14372#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14704#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14317#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14318#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14581#L806-3 assume !(0 == ~T6_E~0); 14582#L811-3 assume !(0 == ~T7_E~0); 14782#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14997#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15090#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14935#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14936#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14471#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14472#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14808#L851-3 assume !(0 == ~E_7~0); 14365#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14366#L388-27 assume 1 == ~m_pc~0; 15062#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15063#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14959#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14960#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14545#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14546#L407-27 assume !(1 == ~t1_pc~0); 14945#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 14944#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14854#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14855#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 14826#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14462#L426-27 assume !(1 == ~t2_pc~0); 14464#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 14476#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14477#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14937#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15059#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14774#L445-27 assume 1 == ~t3_pc~0; 14746#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14314#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14315#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14775#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14866#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14571#L464-27 assume !(1 == ~t4_pc~0); 14312#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 14313#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14384#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14701#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14455#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14456#L483-27 assume 1 == ~t5_pc~0; 15016#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14367#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14368#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15029#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15030#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15107#L502-27 assume !(1 == ~t6_pc~0); 14802#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 14803#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15102#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14965#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14966#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14256#L521-27 assume 1 == ~t7_pc~0; 14257#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14610#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14557#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14310#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14311#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14816#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14962#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14702#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14703#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14764#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14757#L889-3 assume !(1 == ~T5_E~0); 14421#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14422#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14442#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14443#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14400#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14401#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14437#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14949#L929-3 assume !(1 == ~E_5~0); 14863#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14864#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14447#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14448#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14276#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15211#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15209#L1209 assume !(0 == start_simulation_~tmp~3#1); 14796#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14797#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15146#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15145#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15144#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 15143#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15142#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14500#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 14501#L1190-2 [2024-11-19 15:02:59,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:59,687 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2024-11-19 15:02:59,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:59,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368827135] [2024-11-19 15:02:59,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:59,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:59,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:59,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:59,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:59,730 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368827135] [2024-11-19 15:02:59,730 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368827135] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:59,730 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:59,730 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:59,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [390036825] [2024-11-19 15:02:59,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:59,731 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:02:59,731 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:59,731 INFO L85 PathProgramCache]: Analyzing trace with hash -1171889826, now seen corresponding path program 1 times [2024-11-19 15:02:59,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:59,731 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968146181] [2024-11-19 15:02:59,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:59,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:59,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:02:59,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:02:59,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:02:59,766 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1968146181] [2024-11-19 15:02:59,766 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1968146181] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:02:59,766 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:02:59,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:02:59,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096259370] [2024-11-19 15:02:59,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:02:59,767 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:02:59,767 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:02:59,767 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:02:59,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:02:59,768 INFO L87 Difference]: Start difference. First operand 1525 states and 2254 transitions. cyclomatic complexity: 731 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:59,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:02:59,900 INFO L93 Difference]: Finished difference Result 2755 states and 4059 transitions. [2024-11-19 15:02:59,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2755 states and 4059 transitions. [2024-11-19 15:02:59,913 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2622 [2024-11-19 15:02:59,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2755 states to 2755 states and 4059 transitions. [2024-11-19 15:02:59,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2755 [2024-11-19 15:02:59,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2755 [2024-11-19 15:02:59,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2755 states and 4059 transitions. [2024-11-19 15:02:59,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:02:59,928 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2755 states and 4059 transitions. [2024-11-19 15:02:59,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2755 states and 4059 transitions. [2024-11-19 15:02:59,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2755 to 2753. [2024-11-19 15:02:59,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2753 states, 2753 states have (on average 1.473665092626226) internal successors, (4057), 2752 states have internal predecessors, (4057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:02:59,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2753 states to 2753 states and 4057 transitions. [2024-11-19 15:02:59,966 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2753 states and 4057 transitions. [2024-11-19 15:02:59,966 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:02:59,967 INFO L425 stractBuchiCegarLoop]: Abstraction has 2753 states and 4057 transitions. [2024-11-19 15:02:59,967 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-19 15:02:59,967 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2753 states and 4057 transitions. [2024-11-19 15:02:59,975 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2622 [2024-11-19 15:02:59,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:02:59,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:02:59,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:59,976 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:02:59,977 INFO L745 eck$LassoCheckResult]: Stem: 18788#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19365#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19366#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19415#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 18933#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18934#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19061#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19062#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18833#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18622#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18623#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18796#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18797#L781 assume !(0 == ~M_E~0); 19290#L781-2 assume !(0 == ~T1_E~0); 19420#L786-1 assume !(0 == ~T2_E~0); 18585#L791-1 assume !(0 == ~T3_E~0); 18586#L796-1 assume !(0 == ~T4_E~0); 19135#L801-1 assume !(0 == ~T5_E~0); 19136#L806-1 assume !(0 == ~T6_E~0); 19167#L811-1 assume !(0 == ~T7_E~0); 18800#L816-1 assume !(0 == ~E_M~0); 18801#L821-1 assume !(0 == ~E_1~0); 18613#L826-1 assume !(0 == ~E_2~0); 18614#L831-1 assume !(0 == ~E_3~0); 18928#L836-1 assume !(0 == ~E_4~0); 18929#L841-1 assume !(0 == ~E_5~0); 18751#L846-1 assume !(0 == ~E_6~0); 18752#L851-1 assume !(0 == ~E_7~0); 18775#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18776#L388 assume !(1 == ~m_pc~0); 18769#L388-2 is_master_triggered_~__retres1~0#1 := 0; 18770#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19265#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18628#L967 assume !(0 != activate_threads_~tmp~1#1); 18629#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18558#L407 assume 1 == ~t1_pc~0; 18559#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18566#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18567#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18601#L975 assume !(0 != activate_threads_~tmp___0~0#1); 19363#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18888#L426 assume !(1 == ~t2_pc~0); 18889#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19385#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18910#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18911#L983 assume !(0 != activate_threads_~tmp___1~0#1); 19410#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18977#L445 assume 1 == ~t3_pc~0; 18978#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19300#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18557#L991 assume !(0 != activate_threads_~tmp___2~0#1); 19228#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19195#L464 assume !(1 == ~t4_pc~0); 18779#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18648#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18649#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18660#L999 assume !(0 != activate_threads_~tmp___3~0#1); 18955#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18956#L483 assume 1 == ~t5_pc~0; 19191#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19345#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19315#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19316#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 18871#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18872#L502 assume 1 == ~t6_pc~0; 19165#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18688#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18689#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18898#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 19102#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19325#L521 assume !(1 == ~t7_pc~0); 19360#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18624#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18625#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19354#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19332#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19257#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 19258#L869-2 assume !(1 == ~T1_E~0); 19591#L874-1 assume !(1 == ~T2_E~0); 19590#L879-1 assume !(1 == ~T3_E~0); 19589#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19588#L889-1 assume !(1 == ~T5_E~0); 19587#L894-1 assume !(1 == ~T6_E~0); 19585#L899-1 assume !(1 == ~T7_E~0); 19583#L904-1 assume !(1 == ~E_M~0); 19582#L909-1 assume !(1 == ~E_1~0); 19581#L914-1 assume !(1 == ~E_2~0); 19580#L919-1 assume !(1 == ~E_3~0); 19543#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19541#L929-1 assume !(1 == ~E_5~0); 19540#L934-1 assume !(1 == ~E_6~0); 19537#L939-1 assume !(1 == ~E_7~0); 19450#L944-1 assume { :end_inline_reset_delta_events } true; 19444#L1190-2 [2024-11-19 15:02:59,977 INFO L747 eck$LassoCheckResult]: Loop: 19444#L1190-2 assume !false; 19440#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19439#L756-1 assume !false; 19438#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19437#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19429#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19428#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19426#L653 assume !(0 != eval_~tmp~0#1); 19425#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19424#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19422#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19423#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19997#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19996#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19995#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19994#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19993#L806-3 assume !(0 == ~T6_E~0); 19941#L811-3 assume !(0 == ~T7_E~0); 19939#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19937#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19935#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19934#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19932#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19930#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19928#L846-3 assume !(0 == ~E_6~0); 19927#L851-3 assume !(0 == ~E_7~0); 19926#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19925#L388-27 assume !(1 == ~m_pc~0); 19922#L388-29 is_master_triggered_~__retres1~0#1 := 0; 19920#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19918#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19916#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19915#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19913#L407-27 assume 1 == ~t1_pc~0; 19910#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19908#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19905#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19862#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 19859#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19857#L426-27 assume 1 == ~t2_pc~0; 19854#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19851#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19849#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19847#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19845#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19843#L445-27 assume !(1 == ~t3_pc~0); 19815#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 19813#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19770#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19768#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19766#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19764#L464-27 assume 1 == ~t4_pc~0; 19760#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19758#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19756#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19754#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19752#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19750#L483-27 assume !(1 == ~t5_pc~0); 19723#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 19721#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19719#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19717#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19715#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19714#L502-27 assume 1 == ~t6_pc~0; 19712#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19711#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19664#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19663#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19636#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19633#L521-27 assume !(1 == ~t7_pc~0); 19630#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 19628#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19626#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19607#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19593#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19550#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19390#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19546#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19544#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19529#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19526#L889-3 assume !(1 == ~T5_E~0); 19524#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18712#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19518#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19515#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19511#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19508#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19505#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19502#L929-3 assume !(1 == ~E_5~0); 19499#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19495#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19492#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19486#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19480#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19476#L1209 assume !(0 == start_simulation_~tmp~3#1); 19103#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19469#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19463#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 19459#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 19455#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19453#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 19451#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 19444#L1190-2 [2024-11-19 15:02:59,977 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:02:59,977 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2024-11-19 15:02:59,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:02:59,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744344672] [2024-11-19 15:02:59,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:02:59,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:02:59,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:00,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:00,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:00,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744344672] [2024-11-19 15:03:00,031 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744344672] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:00,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:00,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:03:00,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969968275] [2024-11-19 15:03:00,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:00,032 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:00,032 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:00,032 INFO L85 PathProgramCache]: Analyzing trace with hash 601568924, now seen corresponding path program 1 times [2024-11-19 15:03:00,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:00,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171584993] [2024-11-19 15:03:00,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:00,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:00,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:00,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:00,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:00,060 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171584993] [2024-11-19 15:03:00,060 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1171584993] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:00,061 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:00,061 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:00,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1993867525] [2024-11-19 15:03:00,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:00,061 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:00,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:00,062 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:00,062 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:00,062 INFO L87 Difference]: Start difference. First operand 2753 states and 4057 transitions. cyclomatic complexity: 1308 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:00,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:00,134 INFO L93 Difference]: Finished difference Result 5107 states and 7472 transitions. [2024-11-19 15:03:00,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5107 states and 7472 transitions. [2024-11-19 15:03:00,154 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4969 [2024-11-19 15:03:00,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5107 states to 5107 states and 7472 transitions. [2024-11-19 15:03:00,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5107 [2024-11-19 15:03:00,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5107 [2024-11-19 15:03:00,207 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5107 states and 7472 transitions. [2024-11-19 15:03:00,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:00,212 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5107 states and 7472 transitions. [2024-11-19 15:03:00,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5107 states and 7472 transitions. [2024-11-19 15:03:00,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5107 to 5099. [2024-11-19 15:03:00,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5099 states, 5099 states have (on average 1.4638164345950186) internal successors, (7464), 5098 states have internal predecessors, (7464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:00,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5099 states to 5099 states and 7464 transitions. [2024-11-19 15:03:00,288 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5099 states and 7464 transitions. [2024-11-19 15:03:00,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:00,289 INFO L425 stractBuchiCegarLoop]: Abstraction has 5099 states and 7464 transitions. [2024-11-19 15:03:00,289 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-19 15:03:00,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5099 states and 7464 transitions. [2024-11-19 15:03:00,302 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4961 [2024-11-19 15:03:00,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:00,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:00,303 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:00,304 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:00,304 INFO L745 eck$LassoCheckResult]: Stem: 26658#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 26659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 27304#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27305#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27400#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 26808#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26809#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26945#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26946#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26705#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26488#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26489#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26666#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26667#L781 assume !(0 == ~M_E~0); 27209#L781-2 assume !(0 == ~T1_E~0); 27416#L786-1 assume !(0 == ~T2_E~0); 26448#L791-1 assume !(0 == ~T3_E~0); 26449#L796-1 assume !(0 == ~T4_E~0); 27023#L801-1 assume !(0 == ~T5_E~0); 27024#L806-1 assume !(0 == ~T6_E~0); 27061#L811-1 assume !(0 == ~T7_E~0); 26671#L816-1 assume !(0 == ~E_M~0); 26672#L821-1 assume !(0 == ~E_1~0); 26479#L826-1 assume !(0 == ~E_2~0); 26480#L831-1 assume !(0 == ~E_3~0); 26803#L836-1 assume !(0 == ~E_4~0); 26804#L841-1 assume !(0 == ~E_5~0); 26620#L846-1 assume !(0 == ~E_6~0); 26621#L851-1 assume !(0 == ~E_7~0); 26644#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26645#L388 assume !(1 == ~m_pc~0); 26638#L388-2 is_master_triggered_~__retres1~0#1 := 0; 26639#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27177#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26494#L967 assume !(0 != activate_threads_~tmp~1#1); 26495#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26425#L407 assume !(1 == ~t1_pc~0); 26426#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26432#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26433#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26467#L975 assume !(0 != activate_threads_~tmp___0~0#1); 27302#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26763#L426 assume !(1 == ~t2_pc~0); 26764#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27333#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26785#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26786#L983 assume !(0 != activate_threads_~tmp___1~0#1); 27384#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26855#L445 assume 1 == ~t3_pc~0; 26856#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27218#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26424#L991 assume !(0 != activate_threads_~tmp___2~0#1); 27131#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27092#L464 assume !(1 == ~t4_pc~0); 26648#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26514#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26515#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26526#L999 assume !(0 != activate_threads_~tmp___3~0#1); 26833#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26834#L483 assume 1 == ~t5_pc~0; 27087#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27282#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27240#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27241#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 26744#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26745#L502 assume 1 == ~t6_pc~0; 27059#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26554#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26555#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26771#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 26982#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27254#L521 assume !(1 == ~t7_pc~0); 27299#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26490#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26491#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27293#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27262#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27165#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 27166#L869-2 assume !(1 == ~T1_E~0); 28230#L874-1 assume !(1 == ~T2_E~0); 27348#L879-1 assume !(1 == ~T3_E~0); 27349#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28193#L889-1 assume !(1 == ~T5_E~0); 28191#L894-1 assume !(1 == ~T6_E~0); 28190#L899-1 assume !(1 == ~T7_E~0); 28160#L904-1 assume !(1 == ~E_M~0); 28139#L909-1 assume !(1 == ~E_1~0); 28137#L914-1 assume !(1 == ~E_2~0); 28135#L919-1 assume !(1 == ~E_3~0); 28134#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 26589#L929-1 assume !(1 == ~E_5~0); 26590#L934-1 assume !(1 == ~E_6~0); 28111#L939-1 assume !(1 == ~E_7~0); 28103#L944-1 assume { :end_inline_reset_delta_events } true; 28097#L1190-2 [2024-11-19 15:03:00,304 INFO L747 eck$LassoCheckResult]: Loop: 28097#L1190-2 assume !false; 28093#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28092#L756-1 assume !false; 28091#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28090#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28082#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28081#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28079#L653 assume !(0 != eval_~tmp~0#1); 28078#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28077#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28074#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28075#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29633#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29632#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29631#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29630#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29629#L806-3 assume !(0 == ~T6_E~0); 29628#L811-3 assume !(0 == ~T7_E~0); 29627#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29625#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29623#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29621#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29619#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29617#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29615#L846-3 assume !(0 == ~E_6~0); 29613#L851-3 assume !(0 == ~E_7~0); 29611#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29609#L388-27 assume !(1 == ~m_pc~0); 29605#L388-29 is_master_triggered_~__retres1~0#1 := 0; 29603#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29601#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29599#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29597#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29595#L407-27 assume !(1 == ~t1_pc~0); 29593#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 29591#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29589#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29586#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 29584#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29582#L426-27 assume 1 == ~t2_pc~0; 29579#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29577#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29575#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29573#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29571#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29569#L445-27 assume !(1 == ~t3_pc~0); 29566#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 29564#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29562#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29559#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29557#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29555#L464-27 assume 1 == ~t4_pc~0; 29552#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29550#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29548#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29545#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29543#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29541#L483-27 assume !(1 == ~t5_pc~0); 29538#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 29536#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29534#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29531#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29529#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29527#L502-27 assume 1 == ~t6_pc~0; 29524#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29522#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29520#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29517#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29515#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29513#L521-27 assume !(1 == ~t7_pc~0); 27954#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 27951#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27948#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27945#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27943#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27939#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27936#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27933#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27929#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27930#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28364#L889-3 assume !(1 == ~T5_E~0); 28346#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28269#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28267#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28266#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28265#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28263#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28261#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28259#L929-3 assume !(1 == ~E_5~0); 28229#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28226#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28196#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28172#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28167#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28166#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 28165#L1209 assume !(0 == start_simulation_~tmp~3#1); 27788#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28148#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28140#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28138#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 28125#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 28121#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28112#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 28104#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 28097#L1190-2 [2024-11-19 15:03:00,305 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:00,305 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2024-11-19 15:03:00,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:00,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435111151] [2024-11-19 15:03:00,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:00,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:00,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:00,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:00,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:00,342 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [435111151] [2024-11-19 15:03:00,342 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [435111151] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:00,343 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:00,343 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:03:00,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1663075864] [2024-11-19 15:03:00,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:00,343 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:00,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:00,344 INFO L85 PathProgramCache]: Analyzing trace with hash -1353752291, now seen corresponding path program 1 times [2024-11-19 15:03:00,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:00,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858633800] [2024-11-19 15:03:00,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:00,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:00,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:00,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:00,381 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:00,381 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858633800] [2024-11-19 15:03:00,381 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [858633800] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:00,381 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:00,381 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:00,382 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1534829974] [2024-11-19 15:03:00,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:00,382 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:00,382 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:00,382 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:00,382 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:00,382 INFO L87 Difference]: Start difference. First operand 5099 states and 7464 transitions. cyclomatic complexity: 2373 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:00,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:00,483 INFO L93 Difference]: Finished difference Result 9533 states and 13868 transitions. [2024-11-19 15:03:00,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9533 states and 13868 transitions. [2024-11-19 15:03:00,520 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9380 [2024-11-19 15:03:00,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9533 states to 9533 states and 13868 transitions. [2024-11-19 15:03:00,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9533 [2024-11-19 15:03:00,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9533 [2024-11-19 15:03:00,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9533 states and 13868 transitions. [2024-11-19 15:03:00,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:00,574 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9533 states and 13868 transitions. [2024-11-19 15:03:00,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9533 states and 13868 transitions. [2024-11-19 15:03:00,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9533 to 9517. [2024-11-19 15:03:00,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9517 states, 9517 states have (on average 1.4555006829883366) internal successors, (13852), 9516 states have internal predecessors, (13852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:00,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9517 states to 9517 states and 13852 transitions. [2024-11-19 15:03:00,970 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9517 states and 13852 transitions. [2024-11-19 15:03:00,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:00,973 INFO L425 stractBuchiCegarLoop]: Abstraction has 9517 states and 13852 transitions. [2024-11-19 15:03:00,973 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-19 15:03:00,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9517 states and 13852 transitions. [2024-11-19 15:03:01,004 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9364 [2024-11-19 15:03:01,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:01,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:01,005 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:01,005 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:01,006 INFO L745 eck$LassoCheckResult]: Stem: 41298#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 41299#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 41920#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41921#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42009#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 41448#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41449#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41580#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41581#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41344#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41126#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41127#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41306#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41307#L781 assume !(0 == ~M_E~0); 41839#L781-2 assume !(0 == ~T1_E~0); 42025#L786-1 assume !(0 == ~T2_E~0); 41089#L791-1 assume !(0 == ~T3_E~0); 41090#L796-1 assume !(0 == ~T4_E~0); 41660#L801-1 assume !(0 == ~T5_E~0); 41661#L806-1 assume !(0 == ~T6_E~0); 41697#L811-1 assume !(0 == ~T7_E~0); 41311#L816-1 assume !(0 == ~E_M~0); 41312#L821-1 assume !(0 == ~E_1~0); 41117#L826-1 assume !(0 == ~E_2~0); 41118#L831-1 assume !(0 == ~E_3~0); 41443#L836-1 assume !(0 == ~E_4~0); 41444#L841-1 assume !(0 == ~E_5~0); 41261#L846-1 assume !(0 == ~E_6~0); 41262#L851-1 assume !(0 == ~E_7~0); 41285#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41286#L388 assume !(1 == ~m_pc~0); 41279#L388-2 is_master_triggered_~__retres1~0#1 := 0; 41280#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41811#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41132#L967 assume !(0 != activate_threads_~tmp~1#1); 41133#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41064#L407 assume !(1 == ~t1_pc~0); 41065#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41071#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41072#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41105#L975 assume !(0 != activate_threads_~tmp___0~0#1); 41918#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41401#L426 assume !(1 == ~t2_pc~0); 41402#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41948#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41424#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41425#L983 assume !(0 != activate_threads_~tmp___1~0#1); 41993#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41491#L445 assume !(1 == ~t3_pc~0); 41492#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41847#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41062#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41063#L991 assume !(0 != activate_threads_~tmp___2~0#1); 41768#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41732#L464 assume !(1 == ~t4_pc~0); 41289#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41152#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41153#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41168#L999 assume !(0 != activate_threads_~tmp___3~0#1); 41469#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41470#L483 assume 1 == ~t5_pc~0; 41728#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41895#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41863#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41864#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 41385#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41386#L502 assume 1 == ~t6_pc~0; 41695#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41194#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41195#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41411#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 41620#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41877#L521 assume !(1 == ~t7_pc~0); 41912#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41128#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41129#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41906#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41882#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41802#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 41803#L869-2 assume !(1 == ~T1_E~0); 43992#L874-1 assume !(1 == ~T2_E~0); 43991#L879-1 assume !(1 == ~T3_E~0); 43990#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43989#L889-1 assume !(1 == ~T5_E~0); 43988#L894-1 assume !(1 == ~T6_E~0); 43987#L899-1 assume !(1 == ~T7_E~0); 43986#L904-1 assume !(1 == ~E_M~0); 43985#L909-1 assume !(1 == ~E_1~0); 43984#L914-1 assume !(1 == ~E_2~0); 41708#L919-1 assume !(1 == ~E_3~0); 41709#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43799#L929-1 assume !(1 == ~E_5~0); 43798#L934-1 assume !(1 == ~E_6~0); 43795#L939-1 assume !(1 == ~E_7~0); 43794#L944-1 assume { :end_inline_reset_delta_events } true; 43793#L1190-2 [2024-11-19 15:03:01,006 INFO L747 eck$LassoCheckResult]: Loop: 43793#L1190-2 assume !false; 43767#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43737#L756-1 assume !false; 43735#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43707#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43672#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43670#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43644#L653 assume !(0 != eval_~tmp~0#1); 43645#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46454#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46452#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46450#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46448#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46446#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46444#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46442#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46440#L806-3 assume !(0 == ~T6_E~0); 46438#L811-3 assume !(0 == ~T7_E~0); 46436#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46434#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46432#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46430#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46428#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46426#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46424#L846-3 assume !(0 == ~E_6~0); 46422#L851-3 assume !(0 == ~E_7~0); 46420#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46418#L388-27 assume !(1 == ~m_pc~0); 46414#L388-29 is_master_triggered_~__retres1~0#1 := 0; 46412#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46410#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46408#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46406#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46404#L407-27 assume !(1 == ~t1_pc~0); 46402#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 46400#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46398#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46396#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 46394#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46392#L426-27 assume 1 == ~t2_pc~0; 46388#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46386#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46384#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46382#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46380#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46378#L445-27 assume !(1 == ~t3_pc~0); 46376#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 46374#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46372#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46370#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46368#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46366#L464-27 assume 1 == ~t4_pc~0; 46362#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46360#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46358#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46356#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46354#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46352#L483-27 assume !(1 == ~t5_pc~0); 46348#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 46346#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46344#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46341#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46338#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46335#L502-27 assume 1 == ~t6_pc~0; 46330#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46327#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46325#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46322#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46319#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46315#L521-27 assume !(1 == ~t7_pc~0); 46308#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 46305#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46302#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46196#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46195#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46148#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44800#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46143#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46141#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46138#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46136#L889-3 assume !(1 == ~T5_E~0); 46134#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44786#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46131#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46129#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46127#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46125#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46123#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46057#L929-3 assume !(1 == ~E_5~0); 46058#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46053#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46054#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 42170#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 42166#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 42155#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 42156#L1209 assume !(0 == start_simulation_~tmp~3#1); 43171#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43172#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43160#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43161#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 43156#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 43157#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43146#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 43147#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 43793#L1190-2 [2024-11-19 15:03:01,007 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:01,007 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2024-11-19 15:03:01,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:01,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239376876] [2024-11-19 15:03:01,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:01,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:01,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:01,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:01,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:01,154 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239376876] [2024-11-19 15:03:01,154 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [239376876] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:01,154 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:01,154 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:03:01,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473859048] [2024-11-19 15:03:01,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:01,155 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:01,155 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:01,155 INFO L85 PathProgramCache]: Analyzing trace with hash -1353752291, now seen corresponding path program 2 times [2024-11-19 15:03:01,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:01,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143062774] [2024-11-19 15:03:01,156 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:03:01,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:01,169 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:03:01,170 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:03:01,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:01,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:01,192 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143062774] [2024-11-19 15:03:01,192 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143062774] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:01,192 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:01,193 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:01,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379321093] [2024-11-19 15:03:01,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:01,193 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:01,193 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:01,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:01,194 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:01,194 INFO L87 Difference]: Start difference. First operand 9517 states and 13852 transitions. cyclomatic complexity: 4351 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:01,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:01,316 INFO L93 Difference]: Finished difference Result 18316 states and 26485 transitions. [2024-11-19 15:03:01,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18316 states and 26485 transitions. [2024-11-19 15:03:01,402 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18108 [2024-11-19 15:03:01,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18316 states to 18316 states and 26485 transitions. [2024-11-19 15:03:01,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18316 [2024-11-19 15:03:01,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18316 [2024-11-19 15:03:01,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18316 states and 26485 transitions. [2024-11-19 15:03:01,502 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:01,502 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18316 states and 26485 transitions. [2024-11-19 15:03:01,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18316 states and 26485 transitions. [2024-11-19 15:03:02,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18316 to 18284. [2024-11-19 15:03:02,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18284 states, 18284 states have (on average 1.4467840735068913) internal successors, (26453), 18283 states have internal predecessors, (26453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:02,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18284 states to 18284 states and 26453 transitions. [2024-11-19 15:03:02,186 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18284 states and 26453 transitions. [2024-11-19 15:03:02,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:02,191 INFO L425 stractBuchiCegarLoop]: Abstraction has 18284 states and 26453 transitions. [2024-11-19 15:03:02,191 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-19 15:03:02,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18284 states and 26453 transitions. [2024-11-19 15:03:02,286 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18076 [2024-11-19 15:03:02,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:02,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:02,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:02,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:02,288 INFO L745 eck$LassoCheckResult]: Stem: 69133#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 69134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 69745#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69746#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69824#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 69280#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69281#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69413#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69414#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69180#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68965#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68966#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69141#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69142#L781 assume !(0 == ~M_E~0); 69660#L781-2 assume !(0 == ~T1_E~0); 69843#L786-1 assume !(0 == ~T2_E~0); 68926#L791-1 assume !(0 == ~T3_E~0); 68927#L796-1 assume !(0 == ~T4_E~0); 69491#L801-1 assume !(0 == ~T5_E~0); 69492#L806-1 assume !(0 == ~T6_E~0); 69527#L811-1 assume !(0 == ~T7_E~0); 69146#L816-1 assume !(0 == ~E_M~0); 69147#L821-1 assume !(0 == ~E_1~0); 68957#L826-1 assume !(0 == ~E_2~0); 68958#L831-1 assume !(0 == ~E_3~0); 69275#L836-1 assume !(0 == ~E_4~0); 69276#L841-1 assume !(0 == ~E_5~0); 69095#L846-1 assume !(0 == ~E_6~0); 69096#L851-1 assume !(0 == ~E_7~0); 69119#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69120#L388 assume !(1 == ~m_pc~0); 69113#L388-2 is_master_triggered_~__retres1~0#1 := 0; 69114#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69633#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68971#L967 assume !(0 != activate_threads_~tmp~1#1); 68972#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68904#L407 assume !(1 == ~t1_pc~0); 68905#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68911#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68912#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68945#L975 assume !(0 != activate_threads_~tmp___0~0#1); 69742#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69234#L426 assume !(1 == ~t2_pc~0); 69235#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69770#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69256#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 69257#L983 assume !(0 != activate_threads_~tmp___1~0#1); 69814#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69325#L445 assume !(1 == ~t3_pc~0); 69326#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69667#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68902#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68903#L991 assume !(0 != activate_threads_~tmp___2~0#1); 69591#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69557#L464 assume !(1 == ~t4_pc~0); 69123#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68991#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68992#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69003#L999 assume !(0 != activate_threads_~tmp___3~0#1); 69303#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69304#L483 assume !(1 == ~t5_pc~0); 69554#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69724#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69687#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69688#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 69217#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69218#L502 assume 1 == ~t6_pc~0; 69525#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69031#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69032#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69242#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 69454#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69699#L521 assume !(1 == ~t7_pc~0); 69738#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68967#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68968#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69732#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 69706#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69622#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 69297#L869-2 assume !(1 == ~T1_E~0); 69298#L874-1 assume !(1 == ~T2_E~0); 69809#L879-1 assume !(1 == ~T3_E~0); 69375#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69376#L889-1 assume !(1 == ~T5_E~0); 69154#L894-1 assume !(1 == ~T6_E~0); 69155#L899-1 assume !(1 == ~T7_E~0); 69581#L904-1 assume !(1 == ~E_M~0); 69322#L909-1 assume !(1 == ~E_1~0); 69323#L914-1 assume !(1 == ~E_2~0); 69510#L919-1 assume !(1 == ~E_3~0); 69536#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69065#L929-1 assume !(1 == ~E_5~0); 69066#L934-1 assume !(1 == ~E_6~0); 73409#L939-1 assume !(1 == ~E_7~0); 73399#L944-1 assume { :end_inline_reset_delta_events } true; 73392#L1190-2 [2024-11-19 15:03:02,288 INFO L747 eck$LassoCheckResult]: Loop: 73392#L1190-2 assume !false; 73387#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 73385#L756-1 assume !false; 73383#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 73381#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73373#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 73370#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 73368#L653 assume !(0 != eval_~tmp~0#1); 73369#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 73982#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 73979#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 73976#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 73973#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 73970#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 73967#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 73964#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 73961#L806-3 assume !(0 == ~T6_E~0); 73958#L811-3 assume !(0 == ~T7_E~0); 73955#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 73952#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 73949#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 73946#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 73943#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 73940#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 73937#L846-3 assume !(0 == ~E_6~0); 73934#L851-3 assume !(0 == ~E_7~0); 73931#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73928#L388-27 assume !(1 == ~m_pc~0); 73923#L388-29 is_master_triggered_~__retres1~0#1 := 0; 73919#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73916#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 73913#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 73910#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73907#L407-27 assume !(1 == ~t1_pc~0); 73904#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 73901#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73898#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 73895#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 73892#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73889#L426-27 assume !(1 == ~t2_pc~0); 73885#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 73880#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73877#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 73874#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 73871#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73868#L445-27 assume !(1 == ~t3_pc~0); 73865#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 73862#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73859#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 73855#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 73851#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73847#L464-27 assume 1 == ~t4_pc~0; 73841#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73836#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73832#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73828#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 73823#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73819#L483-27 assume !(1 == ~t5_pc~0); 73815#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 73811#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73807#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73803#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 73799#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73795#L502-27 assume 1 == ~t6_pc~0; 73789#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73784#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73780#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73776#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 73771#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73766#L521-27 assume 1 == ~t7_pc~0; 73759#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 73752#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 73747#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73742#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 73736#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73731#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 69775#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73720#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73710#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73704#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73698#L889-3 assume !(1 == ~T5_E~0); 73693#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69055#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 73680#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 73675#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 73670#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 73665#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 73660#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73655#L929-3 assume !(1 == ~E_5~0); 73650#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 73644#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 73642#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 73590#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73582#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 73579#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 73575#L1209 assume !(0 == start_simulation_~tmp~3#1); 73573#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 73457#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73443#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 73433#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 73428#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 73419#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73410#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 73400#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 73392#L1190-2 [2024-11-19 15:03:02,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:02,289 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2024-11-19 15:03:02,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:02,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510809825] [2024-11-19 15:03:02,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:02,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:02,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:02,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:02,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:02,411 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510809825] [2024-11-19 15:03:02,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [510809825] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:02,412 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:02,412 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:03:02,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935539383] [2024-11-19 15:03:02,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:02,413 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:02,413 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:02,414 INFO L85 PathProgramCache]: Analyzing trace with hash -2027558563, now seen corresponding path program 1 times [2024-11-19 15:03:02,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:02,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312096917] [2024-11-19 15:03:02,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:02,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:02,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:02,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:02,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:02,448 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312096917] [2024-11-19 15:03:02,448 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312096917] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:02,448 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:02,448 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:02,448 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070186470] [2024-11-19 15:03:02,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:02,449 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:02,449 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:02,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:02,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:02,450 INFO L87 Difference]: Start difference. First operand 18284 states and 26453 transitions. cyclomatic complexity: 8201 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:02,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:02,619 INFO L93 Difference]: Finished difference Result 34391 states and 49534 transitions. [2024-11-19 15:03:02,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34391 states and 49534 transitions. [2024-11-19 15:03:02,882 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 34040 [2024-11-19 15:03:03,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34391 states to 34391 states and 49534 transitions. [2024-11-19 15:03:03,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34391 [2024-11-19 15:03:03,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34391 [2024-11-19 15:03:03,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34391 states and 49534 transitions. [2024-11-19 15:03:03,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:03,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34391 states and 49534 transitions. [2024-11-19 15:03:03,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34391 states and 49534 transitions. [2024-11-19 15:03:03,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34391 to 34327. [2024-11-19 15:03:03,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34327 states, 34327 states have (on average 1.4411396276983133) internal successors, (49470), 34326 states have internal predecessors, (49470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:03,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34327 states to 34327 states and 49470 transitions. [2024-11-19 15:03:03,484 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34327 states and 49470 transitions. [2024-11-19 15:03:03,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:03,485 INFO L425 stractBuchiCegarLoop]: Abstraction has 34327 states and 49470 transitions. [2024-11-19 15:03:03,485 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-19 15:03:03,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34327 states and 49470 transitions. [2024-11-19 15:03:03,793 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 33976 [2024-11-19 15:03:03,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:03,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:03,795 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:03,798 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:03,798 INFO L745 eck$LassoCheckResult]: Stem: 121814#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 121815#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 122417#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122418#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 122502#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 121960#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121961#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122090#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122091#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 121861#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 121647#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 121648#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 121819#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 121820#L781 assume !(0 == ~M_E~0); 122333#L781-2 assume !(0 == ~T1_E~0); 122511#L786-1 assume !(0 == ~T2_E~0); 121608#L791-1 assume !(0 == ~T3_E~0); 121609#L796-1 assume !(0 == ~T4_E~0); 122164#L801-1 assume !(0 == ~T5_E~0); 122165#L806-1 assume !(0 == ~T6_E~0); 122197#L811-1 assume !(0 == ~T7_E~0); 121827#L816-1 assume !(0 == ~E_M~0); 121828#L821-1 assume !(0 == ~E_1~0); 121639#L826-1 assume !(0 == ~E_2~0); 121640#L831-1 assume !(0 == ~E_3~0); 121955#L836-1 assume !(0 == ~E_4~0); 121956#L841-1 assume !(0 == ~E_5~0); 121777#L846-1 assume !(0 == ~E_6~0); 121778#L851-1 assume !(0 == ~E_7~0); 121800#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121801#L388 assume !(1 == ~m_pc~0); 121794#L388-2 is_master_triggered_~__retres1~0#1 := 0; 121795#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122307#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 121653#L967 assume !(0 != activate_threads_~tmp~1#1); 121654#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121586#L407 assume !(1 == ~t1_pc~0); 121587#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 121590#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121591#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 121625#L975 assume !(0 != activate_threads_~tmp___0~0#1); 122414#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121916#L426 assume !(1 == ~t2_pc~0); 121917#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 122445#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121938#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 121939#L983 assume !(0 != activate_threads_~tmp___1~0#1); 122492#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122001#L445 assume !(1 == ~t3_pc~0); 122002#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 122342#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 121584#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 121585#L991 assume !(0 != activate_threads_~tmp___2~0#1); 122266#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122230#L464 assume !(1 == ~t4_pc~0); 121804#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 121673#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121674#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121685#L999 assume !(0 != activate_threads_~tmp___3~0#1); 121981#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121982#L483 assume !(1 == ~t5_pc~0); 122227#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 122392#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 122361#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122362#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 121898#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121899#L502 assume !(1 == ~t6_pc~0); 121755#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 121713#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121714#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 121924#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 122128#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122373#L521 assume !(1 == ~t7_pc~0); 122409#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 121649#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 121650#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 122403#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 122378#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122297#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 122298#L869-2 assume !(1 == ~T1_E~0); 122487#L874-1 assume !(1 == ~T2_E~0); 122457#L879-1 assume !(1 == ~T3_E~0); 122458#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123702#L889-1 assume !(1 == ~T5_E~0); 123700#L894-1 assume !(1 == ~T6_E~0); 123698#L899-1 assume !(1 == ~T7_E~0); 123697#L904-1 assume !(1 == ~E_M~0); 123696#L909-1 assume !(1 == ~E_1~0); 123695#L914-1 assume !(1 == ~E_2~0); 122206#L919-1 assume !(1 == ~E_3~0); 121915#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 121747#L929-1 assume !(1 == ~E_5~0); 121748#L934-1 assume !(1 == ~E_6~0); 123590#L939-1 assume !(1 == ~E_7~0); 123585#L944-1 assume { :end_inline_reset_delta_events } true; 123576#L1190-2 [2024-11-19 15:03:03,799 INFO L747 eck$LassoCheckResult]: Loop: 123576#L1190-2 assume !false; 123545#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 123543#L756-1 assume !false; 123489#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 123487#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 123479#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 123469#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 123459#L653 assume !(0 != eval_~tmp~0#1); 123460#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 124177#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 124176#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 124175#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 124174#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 124173#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 124172#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 124171#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 124170#L806-3 assume !(0 == ~T6_E~0); 124169#L811-3 assume !(0 == ~T7_E~0); 124167#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 124166#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 124165#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 124164#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 124163#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 124162#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 124153#L846-3 assume !(0 == ~E_6~0); 124151#L851-3 assume !(0 == ~E_7~0); 124149#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124147#L388-27 assume !(1 == ~m_pc~0); 124109#L388-29 is_master_triggered_~__retres1~0#1 := 0; 124107#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124105#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 124103#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 124101#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124099#L407-27 assume !(1 == ~t1_pc~0); 124097#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 124095#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 124093#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 124091#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 124089#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124087#L426-27 assume 1 == ~t2_pc~0; 124083#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 124081#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124079#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124077#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 124075#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124073#L445-27 assume !(1 == ~t3_pc~0); 124071#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 124069#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124067#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124065#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 124063#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124061#L464-27 assume 1 == ~t4_pc~0; 124057#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 124055#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124053#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 124051#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124049#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124047#L483-27 assume !(1 == ~t5_pc~0); 124045#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 124043#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124041#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 124039#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 124037#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124035#L502-27 assume !(1 == ~t6_pc~0); 124033#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 124031#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124029#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 124027#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 124025#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124023#L521-27 assume !(1 == ~t7_pc~0); 124019#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 124017#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 124015#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124013#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 124011#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124009#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 124005#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 124003#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 124001#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123999#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123997#L889-3 assume !(1 == ~T5_E~0); 123993#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 123989#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 123987#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 123985#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 123983#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 123981#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 123979#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 123977#L929-3 assume !(1 == ~E_5~0); 123976#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 123973#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 123972#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 123968#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 123963#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 123954#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 123951#L1209 assume !(0 == start_simulation_~tmp~3#1); 123949#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 123852#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 123822#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 123802#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 123795#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 123689#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123688#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 123586#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 123576#L1190-2 [2024-11-19 15:03:03,799 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:03,799 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2024-11-19 15:03:03,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:03,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728919387] [2024-11-19 15:03:03,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:03,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:03,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:03,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:03,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:03,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [728919387] [2024-11-19 15:03:03,849 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [728919387] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:03,850 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:03,850 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:03:03,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [212001696] [2024-11-19 15:03:03,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:03,851 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:03,851 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:03,852 INFO L85 PathProgramCache]: Analyzing trace with hash -1838927010, now seen corresponding path program 1 times [2024-11-19 15:03:03,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:03,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171349955] [2024-11-19 15:03:03,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:03,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:03,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:03,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:03,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:03,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171349955] [2024-11-19 15:03:03,887 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [171349955] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:03,887 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:03,887 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:03,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665860260] [2024-11-19 15:03:03,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:03,888 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:03,888 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:03,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:03:03,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:03:03,889 INFO L87 Difference]: Start difference. First operand 34327 states and 49470 transitions. cyclomatic complexity: 15207 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:04,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:04,233 INFO L93 Difference]: Finished difference Result 35674 states and 50817 transitions. [2024-11-19 15:03:04,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35674 states and 50817 transitions. [2024-11-19 15:03:04,377 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35320 [2024-11-19 15:03:04,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35674 states to 35674 states and 50817 transitions. [2024-11-19 15:03:04,634 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35674 [2024-11-19 15:03:04,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35674 [2024-11-19 15:03:04,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35674 states and 50817 transitions. [2024-11-19 15:03:04,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:04,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35674 states and 50817 transitions. [2024-11-19 15:03:04,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35674 states and 50817 transitions. [2024-11-19 15:03:04,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35674 to 35674. [2024-11-19 15:03:05,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35674 states, 35674 states have (on average 1.4244828166171442) internal successors, (50817), 35673 states have internal predecessors, (50817), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:05,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35674 states to 35674 states and 50817 transitions. [2024-11-19 15:03:05,070 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35674 states and 50817 transitions. [2024-11-19 15:03:05,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:03:05,071 INFO L425 stractBuchiCegarLoop]: Abstraction has 35674 states and 50817 transitions. [2024-11-19 15:03:05,071 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-19 15:03:05,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35674 states and 50817 transitions. [2024-11-19 15:03:05,156 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35320 [2024-11-19 15:03:05,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:05,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:05,157 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:05,158 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:05,158 INFO L745 eck$LassoCheckResult]: Stem: 191828#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 191829#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 192470#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 192471#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 192552#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 191977#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 191978#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 192110#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 192111#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 191874#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 191658#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 191659#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 191833#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 191834#L781 assume !(0 == ~M_E~0); 192376#L781-2 assume !(0 == ~T1_E~0); 192566#L786-1 assume !(0 == ~T2_E~0); 191618#L791-1 assume !(0 == ~T3_E~0); 191619#L796-1 assume !(0 == ~T4_E~0); 192193#L801-1 assume !(0 == ~T5_E~0); 192194#L806-1 assume !(0 == ~T6_E~0); 192232#L811-1 assume !(0 == ~T7_E~0); 191841#L816-1 assume !(0 == ~E_M~0); 191842#L821-1 assume !(0 == ~E_1~0); 191649#L826-1 assume !(0 == ~E_2~0); 191650#L831-1 assume !(0 == ~E_3~0); 191972#L836-1 assume !(0 == ~E_4~0); 191973#L841-1 assume !(0 == ~E_5~0); 191790#L846-1 assume !(0 == ~E_6~0); 191791#L851-1 assume !(0 == ~E_7~0); 191814#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 191815#L388 assume !(1 == ~m_pc~0); 191808#L388-2 is_master_triggered_~__retres1~0#1 := 0; 191809#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 192347#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 191664#L967 assume !(0 != activate_threads_~tmp~1#1); 191665#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 191596#L407 assume !(1 == ~t1_pc~0); 191597#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 191600#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 191601#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 191635#L975 assume !(0 != activate_threads_~tmp___0~0#1); 192467#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191930#L426 assume !(1 == ~t2_pc~0); 191931#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 192495#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 191953#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 191954#L983 assume !(0 != activate_threads_~tmp___1~0#1); 192538#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192020#L445 assume !(1 == ~t3_pc~0); 192021#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 192385#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 191594#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 191595#L991 assume !(0 != activate_threads_~tmp___2~0#1); 192300#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192260#L464 assume !(1 == ~t4_pc~0); 191818#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 191684#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 191685#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 191696#L999 assume !(0 != activate_threads_~tmp___3~0#1); 191998#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 191999#L483 assume !(1 == ~t5_pc~0); 192257#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 192447#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 192406#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 192407#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 191913#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 191914#L502 assume !(1 == ~t6_pc~0); 191766#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 191724#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 191725#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 191938#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 192151#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 192420#L521 assume !(1 == ~t7_pc~0); 192463#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 191660#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 191661#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 192455#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 192430#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 192336#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 191992#L869-2 assume !(1 == ~T1_E~0); 191993#L874-1 assume !(1 == ~T2_E~0); 192511#L879-1 assume !(1 == ~T3_E~0); 192073#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 191582#L889-1 assume !(1 == ~T5_E~0); 191583#L894-1 assume !(1 == ~T6_E~0); 191849#L899-1 assume !(1 == ~T7_E~0); 192287#L904-1 assume !(1 == ~E_M~0); 192017#L909-1 assume !(1 == ~E_1~0); 192018#L914-1 assume !(1 == ~E_2~0); 192215#L919-1 assume !(1 == ~E_3~0); 191929#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 191759#L929-1 assume !(1 == ~E_5~0); 191760#L934-1 assume !(1 == ~E_6~0); 192518#L939-1 assume !(1 == ~E_7~0); 194520#L944-1 assume { :end_inline_reset_delta_events } true; 194512#L1190-2 [2024-11-19 15:03:05,158 INFO L747 eck$LassoCheckResult]: Loop: 194512#L1190-2 assume !false; 194506#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 194502#L756-1 assume !false; 194499#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 194435#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 194332#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 194318#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 194310#L653 assume !(0 != eval_~tmp~0#1); 194311#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 198922#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 198921#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 198915#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 198913#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 198911#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 198909#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 198906#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 198904#L806-3 assume !(0 == ~T6_E~0); 198902#L811-3 assume !(0 == ~T7_E~0); 198900#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 198898#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 198896#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 198894#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 198892#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 198890#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 198888#L846-3 assume !(0 == ~E_6~0); 198886#L851-3 assume !(0 == ~E_7~0); 198884#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 198881#L388-27 assume 1 == ~m_pc~0; 198879#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 198876#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 198874#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 198872#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 198870#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 198867#L407-27 assume !(1 == ~t1_pc~0); 198865#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 198863#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 198861#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 198859#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 198857#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 198856#L426-27 assume !(1 == ~t2_pc~0); 198853#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 198850#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198848#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 198846#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 198844#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 198842#L445-27 assume !(1 == ~t3_pc~0); 198840#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 198838#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 198836#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198834#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 193081#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 193079#L464-27 assume 1 == ~t4_pc~0; 193076#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 193073#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 193074#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 198530#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 198526#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 198522#L483-27 assume !(1 == ~t5_pc~0); 198517#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 198515#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 198513#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 198504#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 198502#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 198500#L502-27 assume !(1 == ~t6_pc~0); 198497#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 198495#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198493#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 198491#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 198489#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 198487#L521-27 assume !(1 == ~t7_pc~0); 198485#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 198799#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 198797#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 198442#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 198439#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198437#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 193018#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 198433#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 198431#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 198429#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 198427#L889-3 assume !(1 == ~T5_E~0); 198259#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 193006#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 198256#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 198254#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 198251#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 198249#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 198247#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 198242#L929-3 assume !(1 == ~E_5~0); 194892#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 194888#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 194885#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 194566#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 194560#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 194558#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 194556#L1209 assume !(0 == start_simulation_~tmp~3#1); 194553#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 194540#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 194534#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 194531#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 194529#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 194525#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 194523#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 194521#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 194512#L1190-2 [2024-11-19 15:03:05,159 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:05,159 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2024-11-19 15:03:05,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:05,159 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25956151] [2024-11-19 15:03:05,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:05,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:05,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:05,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:05,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:05,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25956151] [2024-11-19 15:03:05,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [25956151] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:05,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:05,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:03:05,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [510425368] [2024-11-19 15:03:05,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:05,198 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:05,198 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:05,198 INFO L85 PathProgramCache]: Analyzing trace with hash 1082629472, now seen corresponding path program 1 times [2024-11-19 15:03:05,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:05,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790157158] [2024-11-19 15:03:05,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:05,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:05,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:05,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:05,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:05,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1790157158] [2024-11-19 15:03:05,409 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1790157158] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:05,409 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:05,409 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:05,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1960830003] [2024-11-19 15:03:05,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:05,413 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:05,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:05,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:05,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:05,414 INFO L87 Difference]: Start difference. First operand 35674 states and 50817 transitions. cyclomatic complexity: 15207 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:05,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:05,745 INFO L93 Difference]: Finished difference Result 44740 states and 63748 transitions. [2024-11-19 15:03:05,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44740 states and 63748 transitions. [2024-11-19 15:03:05,991 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 44344 [2024-11-19 15:03:06,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44740 states to 44740 states and 63748 transitions. [2024-11-19 15:03:06,125 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44740 [2024-11-19 15:03:06,155 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44740 [2024-11-19 15:03:06,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44740 states and 63748 transitions. [2024-11-19 15:03:06,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:06,192 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44740 states and 63748 transitions. [2024-11-19 15:03:06,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44740 states and 63748 transitions. [2024-11-19 15:03:06,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44740 to 19206. [2024-11-19 15:03:06,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.4305425387899615) internal successors, (27475), 19205 states have internal predecessors, (27475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:06,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27475 transitions. [2024-11-19 15:03:06,686 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27475 transitions. [2024-11-19 15:03:06,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:06,687 INFO L425 stractBuchiCegarLoop]: Abstraction has 19206 states and 27475 transitions. [2024-11-19 15:03:06,687 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-19 15:03:06,687 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27475 transitions. [2024-11-19 15:03:06,732 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2024-11-19 15:03:06,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:06,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:06,733 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:06,733 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:06,733 INFO L745 eck$LassoCheckResult]: Stem: 272247#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 272248#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 272842#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 272843#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 272915#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 272395#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 272396#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 272523#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 272524#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 272293#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 272080#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 272081#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 272255#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 272256#L781 assume !(0 == ~M_E~0); 272766#L781-2 assume !(0 == ~T1_E~0); 272928#L786-1 assume !(0 == ~T2_E~0); 272043#L791-1 assume !(0 == ~T3_E~0); 272044#L796-1 assume !(0 == ~T4_E~0); 272597#L801-1 assume !(0 == ~T5_E~0); 272598#L806-1 assume !(0 == ~T6_E~0); 272630#L811-1 assume !(0 == ~T7_E~0); 272259#L816-1 assume !(0 == ~E_M~0); 272260#L821-1 assume !(0 == ~E_1~0); 272071#L826-1 assume !(0 == ~E_2~0); 272072#L831-1 assume !(0 == ~E_3~0); 272390#L836-1 assume !(0 == ~E_4~0); 272391#L841-1 assume !(0 == ~E_5~0); 272210#L846-1 assume !(0 == ~E_6~0); 272211#L851-1 assume !(0 == ~E_7~0); 272234#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272235#L388 assume !(1 == ~m_pc~0); 272228#L388-2 is_master_triggered_~__retres1~0#1 := 0; 272229#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 272739#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 272086#L967 assume !(0 != activate_threads_~tmp~1#1); 272087#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 272017#L407 assume !(1 == ~t1_pc~0); 272018#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 272024#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 272025#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 272059#L975 assume !(0 != activate_threads_~tmp___0~0#1); 272839#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 272349#L426 assume !(1 == ~t2_pc~0); 272350#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 272867#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 272371#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 272372#L983 assume !(0 != activate_threads_~tmp___1~0#1); 272907#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 272436#L445 assume !(1 == ~t3_pc~0); 272437#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 272773#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 272015#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 272016#L991 assume !(0 != activate_threads_~tmp___2~0#1); 272695#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272659#L464 assume !(1 == ~t4_pc~0); 272240#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 272106#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 272107#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 272120#L999 assume !(0 != activate_threads_~tmp___3~0#1); 272416#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 272417#L483 assume !(1 == ~t5_pc~0); 272656#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 272821#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 272787#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 272788#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 272334#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 272335#L502 assume !(1 == ~t6_pc~0); 272186#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 272146#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 272147#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 272359#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 272561#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 272799#L521 assume !(1 == ~t7_pc~0); 272836#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 272871#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 272932#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 272830#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 272804#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 272730#L869 assume !(1 == ~M_E~0); 272410#L869-2 assume !(1 == ~T1_E~0); 272411#L874-1 assume !(1 == ~T2_E~0); 272884#L879-1 assume !(1 == ~T3_E~0); 272486#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 272003#L889-1 assume !(1 == ~T5_E~0); 272004#L894-1 assume !(1 == ~T6_E~0); 272270#L899-1 assume !(1 == ~T7_E~0); 272684#L904-1 assume !(1 == ~E_M~0); 272433#L909-1 assume !(1 == ~E_1~0); 272434#L914-1 assume !(1 == ~E_2~0); 272616#L919-1 assume !(1 == ~E_3~0); 272348#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 272179#L929-1 assume !(1 == ~E_5~0); 272180#L934-1 assume !(1 == ~E_6~0); 272414#L939-1 assume !(1 == ~E_7~0); 272415#L944-1 assume { :end_inline_reset_delta_events } true; 272798#L1190-2 [2024-11-19 15:03:06,734 INFO L747 eck$LassoCheckResult]: Loop: 272798#L1190-2 assume !false; 278617#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 278612#L756-1 assume !false; 278610#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 278608#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 278592#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 278590#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 278587#L653 assume !(0 != eval_~tmp~0#1); 278584#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 278580#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 278576#L781-3 assume !(0 == ~M_E~0); 278572#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 278568#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 278564#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 278561#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 278558#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 278557#L806-3 assume !(0 == ~T6_E~0); 278556#L811-3 assume !(0 == ~T7_E~0); 278493#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 278491#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 278489#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 278488#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 278485#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 278484#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 278483#L846-3 assume !(0 == ~E_6~0); 278481#L851-3 assume !(0 == ~E_7~0); 278480#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 278479#L388-27 assume !(1 == ~m_pc~0); 278477#L388-29 is_master_triggered_~__retres1~0#1 := 0; 278476#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 278475#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 278474#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 278473#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 278472#L407-27 assume !(1 == ~t1_pc~0); 278471#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 278470#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 278469#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 278468#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 278467#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278466#L426-27 assume 1 == ~t2_pc~0; 278464#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 278462#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 278461#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 278460#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 278459#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 278458#L445-27 assume !(1 == ~t3_pc~0); 278457#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 278456#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 278454#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 278453#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 278452#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278451#L464-27 assume 1 == ~t4_pc~0; 278449#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 278448#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 278447#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 278445#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 278442#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 278440#L483-27 assume !(1 == ~t5_pc~0); 278438#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 278436#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 278434#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 278432#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 278430#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 278428#L502-27 assume !(1 == ~t6_pc~0); 278426#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 278424#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 278422#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278420#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 278417#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 278415#L521-27 assume 1 == ~t7_pc~0; 278413#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 278414#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 278455#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 278404#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 278401#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 278399#L869-3 assume !(1 == ~M_E~0); 276159#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 278396#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 278394#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 278392#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 278389#L889-3 assume !(1 == ~T5_E~0); 278387#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 278385#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 278383#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 278381#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 278379#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 278377#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 278375#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 278373#L929-3 assume !(1 == ~E_5~0); 278371#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 278369#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 278367#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 278061#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 278044#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 278038#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 273240#L1209 assume !(0 == start_simulation_~tmp~3#1); 273241#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 278861#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 278855#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 278853#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 278851#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 278848#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 278846#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 278844#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 272798#L1190-2 [2024-11-19 15:03:06,734 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:06,734 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2024-11-19 15:03:06,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:06,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881929280] [2024-11-19 15:03:06,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:06,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:06,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:06,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:06,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:06,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881929280] [2024-11-19 15:03:06,778 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881929280] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:06,778 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:06,778 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:06,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1358672347] [2024-11-19 15:03:06,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:06,778 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:06,778 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:06,779 INFO L85 PathProgramCache]: Analyzing trace with hash 1171819677, now seen corresponding path program 1 times [2024-11-19 15:03:06,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:06,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068862934] [2024-11-19 15:03:06,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:06,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:06,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:06,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:06,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:06,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1068862934] [2024-11-19 15:03:06,807 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1068862934] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:06,807 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:06,807 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:06,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319261506] [2024-11-19 15:03:06,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:06,807 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:06,808 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:06,808 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:03:06,808 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:03:06,808 INFO L87 Difference]: Start difference. First operand 19206 states and 27475 transitions. cyclomatic complexity: 8285 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:06,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:06,916 INFO L93 Difference]: Finished difference Result 30482 states and 43470 transitions. [2024-11-19 15:03:06,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30482 states and 43470 transitions. [2024-11-19 15:03:07,171 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 30128 [2024-11-19 15:03:07,233 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30482 states to 30482 states and 43470 transitions. [2024-11-19 15:03:07,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30482 [2024-11-19 15:03:07,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30482 [2024-11-19 15:03:07,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30482 states and 43470 transitions. [2024-11-19 15:03:07,267 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:07,267 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30482 states and 43470 transitions. [2024-11-19 15:03:07,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30482 states and 43470 transitions. [2024-11-19 15:03:07,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30482 to 21646. [2024-11-19 15:03:07,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21646 states, 21646 states have (on average 1.4298715698050448) internal successors, (30951), 21645 states have internal predecessors, (30951), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:07,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21646 states to 21646 states and 30951 transitions. [2024-11-19 15:03:07,462 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30951 transitions. [2024-11-19 15:03:07,462 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:03:07,463 INFO L425 stractBuchiCegarLoop]: Abstraction has 21646 states and 30951 transitions. [2024-11-19 15:03:07,463 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-19 15:03:07,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21646 states and 30951 transitions. [2024-11-19 15:03:07,513 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2024-11-19 15:03:07,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:07,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:07,515 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:07,515 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:07,515 INFO L745 eck$LassoCheckResult]: Stem: 321943#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 321944#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 322548#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 322549#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 322651#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 322089#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 322090#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 322217#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 322218#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 321988#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 321777#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 321778#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 321948#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 321949#L781 assume !(0 == ~M_E~0); 322463#L781-2 assume !(0 == ~T1_E~0); 322670#L786-1 assume !(0 == ~T2_E~0); 321737#L791-1 assume !(0 == ~T3_E~0); 321738#L796-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 322295#L801-1 assume !(0 == ~T5_E~0); 322296#L806-1 assume !(0 == ~T6_E~0); 322640#L811-1 assume !(0 == ~T7_E~0); 322641#L816-1 assume !(0 == ~E_M~0); 322551#L821-1 assume !(0 == ~E_1~0); 322552#L826-1 assume !(0 == ~E_2~0); 322293#L831-1 assume !(0 == ~E_3~0); 322294#L836-1 assume !(0 == ~E_4~0); 322698#L841-1 assume !(0 == ~E_5~0); 321906#L846-1 assume !(0 == ~E_6~0); 321907#L851-1 assume !(0 == ~E_7~0); 322697#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 322572#L388 assume !(1 == ~m_pc~0); 322573#L388-2 is_master_triggered_~__retres1~0#1 := 0; 322696#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 322486#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 322487#L967 assume !(0 != activate_threads_~tmp~1#1); 322642#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 322643#L407 assume !(1 == ~t1_pc~0); 322650#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 321719#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 321720#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 321754#L975 assume !(0 != activate_threads_~tmp___0~0#1); 322568#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 322569#L426 assume !(1 == ~t2_pc~0); 322580#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 322581#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 322066#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 322067#L983 assume !(0 != activate_threads_~tmp___1~0#1); 322693#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 322692#L445 assume !(1 == ~t3_pc~0); 322671#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 322473#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 322474#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 322690#L991 assume !(0 != activate_threads_~tmp___2~0#1); 322689#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 322360#L464 assume !(1 == ~t4_pc~0); 321933#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 321934#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 322686#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 322685#L999 assume !(0 != activate_threads_~tmp___3~0#1); 322684#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 322356#L483 assume !(1 == ~t5_pc~0); 322357#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 322523#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 322524#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 322600#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 322601#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 322683#L502 assume !(1 == ~t6_pc~0); 321883#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 321884#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 322051#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 322052#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 322502#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 322503#L521 assume !(1 == ~t7_pc~0); 322541#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 321779#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 321780#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 322675#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 322507#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 322429#L869 assume !(1 == ~M_E~0); 322104#L869-2 assume !(1 == ~T1_E~0); 322105#L874-1 assume !(1 == ~T2_E~0); 322596#L879-1 assume !(1 == ~T3_E~0); 322597#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 321701#L889-1 assume !(1 == ~T5_E~0); 321702#L894-1 assume !(1 == ~T6_E~0); 321963#L899-1 assume !(1 == ~T7_E~0); 322382#L904-1 assume !(1 == ~E_M~0); 322129#L909-1 assume !(1 == ~E_1~0); 322130#L914-1 assume !(1 == ~E_2~0); 322314#L919-1 assume !(1 == ~E_3~0); 322042#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 321876#L929-1 assume !(1 == ~E_5~0); 321877#L934-1 assume !(1 == ~E_6~0); 322106#L939-1 assume !(1 == ~E_7~0); 322107#L944-1 assume { :end_inline_reset_delta_events } true; 322501#L1190-2 [2024-11-19 15:03:07,515 INFO L747 eck$LassoCheckResult]: Loop: 322501#L1190-2 assume !false; 336372#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 336370#L756-1 assume !false; 336367#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 336365#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 336356#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 336355#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 336351#L653 assume !(0 != eval_~tmp~0#1); 336352#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 342590#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 342585#L781-3 assume !(0 == ~M_E~0); 342579#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 342574#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 342568#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 342562#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 342561#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 342560#L806-3 assume !(0 == ~T6_E~0); 342559#L811-3 assume !(0 == ~T7_E~0); 342558#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 342557#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 342556#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 342555#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 342554#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 342553#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 342552#L846-3 assume !(0 == ~E_6~0); 342551#L851-3 assume !(0 == ~E_7~0); 342550#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 342549#L388-27 assume 1 == ~m_pc~0; 342548#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 342546#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 342545#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 342544#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 342543#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 342542#L407-27 assume !(1 == ~t1_pc~0); 342541#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 342540#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 342539#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 342538#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 342537#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 342536#L426-27 assume !(1 == ~t2_pc~0); 342535#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 342533#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 342532#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 342531#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 342530#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 342529#L445-27 assume !(1 == ~t3_pc~0); 342528#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 342527#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 342526#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 342525#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 342524#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 342523#L464-27 assume 1 == ~t4_pc~0; 342521#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 342520#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 342519#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 342518#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 342517#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 342516#L483-27 assume !(1 == ~t5_pc~0); 342515#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 342514#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 342513#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 342512#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 342511#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 342510#L502-27 assume !(1 == ~t6_pc~0); 342509#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 342508#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 342507#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 342506#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 342505#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 342504#L521-27 assume !(1 == ~t7_pc~0); 342503#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 342501#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 342499#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 342497#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 342495#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 342494#L869-3 assume !(1 == ~M_E~0); 329222#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 342493#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 342492#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 342490#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 342485#L889-3 assume !(1 == ~T5_E~0); 342481#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 342476#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 342471#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 342467#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 342385#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 342384#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 342371#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 342370#L929-3 assume !(1 == ~E_5~0); 342369#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 342368#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 342367#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 342363#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 342350#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 342348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 329116#L1209 assume !(0 == start_simulation_~tmp~3#1); 329117#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 336510#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 336504#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 336501#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 336500#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 336499#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 336498#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 336497#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 322501#L1190-2 [2024-11-19 15:03:07,516 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:07,516 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2024-11-19 15:03:07,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:07,516 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758350631] [2024-11-19 15:03:07,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:07,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:07,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:07,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:07,666 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:07,666 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758350631] [2024-11-19 15:03:07,666 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1758350631] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:07,666 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:07,666 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:07,666 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526162473] [2024-11-19 15:03:07,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:07,667 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:07,667 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:07,667 INFO L85 PathProgramCache]: Analyzing trace with hash 849857952, now seen corresponding path program 1 times [2024-11-19 15:03:07,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:07,667 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1015197282] [2024-11-19 15:03:07,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:07,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:07,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:07,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:07,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:07,694 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1015197282] [2024-11-19 15:03:07,694 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1015197282] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:07,694 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:07,694 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:07,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639728309] [2024-11-19 15:03:07,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:07,695 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:07,695 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:07,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:03:07,695 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:03:07,695 INFO L87 Difference]: Start difference. First operand 21646 states and 30951 transitions. cyclomatic complexity: 9321 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:07,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:07,792 INFO L93 Difference]: Finished difference Result 28030 states and 39857 transitions. [2024-11-19 15:03:07,792 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28030 states and 39857 transitions. [2024-11-19 15:03:07,885 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27760 [2024-11-19 15:03:07,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28030 states to 28030 states and 39857 transitions. [2024-11-19 15:03:07,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28030 [2024-11-19 15:03:07,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28030 [2024-11-19 15:03:07,956 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28030 states and 39857 transitions. [2024-11-19 15:03:07,972 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:07,973 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28030 states and 39857 transitions. [2024-11-19 15:03:07,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28030 states and 39857 transitions. [2024-11-19 15:03:08,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28030 to 19206. [2024-11-19 15:03:08,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.42543996667708) internal successors, (27377), 19205 states have internal predecessors, (27377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:08,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27377 transitions. [2024-11-19 15:03:08,332 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27377 transitions. [2024-11-19 15:03:08,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:03:08,332 INFO L425 stractBuchiCegarLoop]: Abstraction has 19206 states and 27377 transitions. [2024-11-19 15:03:08,332 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-19 15:03:08,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27377 transitions. [2024-11-19 15:03:08,380 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2024-11-19 15:03:08,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:08,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:08,382 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:08,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:08,382 INFO L745 eck$LassoCheckResult]: Stem: 371631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 371632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 372252#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 372253#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 372329#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 371778#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 371779#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 371908#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 371909#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 371678#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 371463#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 371464#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 371636#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 371637#L781 assume !(0 == ~M_E~0); 372158#L781-2 assume !(0 == ~T1_E~0); 372347#L786-1 assume !(0 == ~T2_E~0); 371423#L791-1 assume !(0 == ~T3_E~0); 371424#L796-1 assume !(0 == ~T4_E~0); 371986#L801-1 assume !(0 == ~T5_E~0); 371987#L806-1 assume !(0 == ~T6_E~0); 372021#L811-1 assume !(0 == ~T7_E~0); 371643#L816-1 assume !(0 == ~E_M~0); 371644#L821-1 assume !(0 == ~E_1~0); 371454#L826-1 assume !(0 == ~E_2~0); 371455#L831-1 assume !(0 == ~E_3~0); 371773#L836-1 assume !(0 == ~E_4~0); 371774#L841-1 assume !(0 == ~E_5~0); 371594#L846-1 assume !(0 == ~E_6~0); 371595#L851-1 assume !(0 == ~E_7~0); 371618#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371619#L388 assume !(1 == ~m_pc~0); 371612#L388-2 is_master_triggered_~__retres1~0#1 := 0; 371613#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 372132#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 371469#L967 assume !(0 != activate_threads_~tmp~1#1); 371470#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 371401#L407 assume !(1 == ~t1_pc~0); 371402#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 371405#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 371406#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 371440#L975 assume !(0 != activate_threads_~tmp___0~0#1); 372250#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 371734#L426 assume !(1 == ~t2_pc~0); 371735#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 372274#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 371756#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 371757#L983 assume !(0 != activate_threads_~tmp___1~0#1); 372316#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 371823#L445 assume !(1 == ~t3_pc~0); 371824#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 372165#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 371399#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 371400#L991 assume !(0 != activate_threads_~tmp___2~0#1); 372086#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372049#L464 assume !(1 == ~t4_pc~0); 371622#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 371489#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 371490#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 371501#L999 assume !(0 != activate_threads_~tmp___3~0#1); 371801#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 371802#L483 assume !(1 == ~t5_pc~0); 372046#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 372227#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 372191#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 372192#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 371718#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 371719#L502 assume !(1 == ~t6_pc~0); 371569#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 371529#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 371530#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 371742#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 371948#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 372204#L521 assume !(1 == ~t7_pc~0); 372246#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 371465#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 371466#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 372239#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 372210#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 372121#L869 assume !(1 == ~M_E~0); 371795#L869-2 assume !(1 == ~T1_E~0); 371796#L874-1 assume !(1 == ~T2_E~0); 372287#L879-1 assume !(1 == ~T3_E~0); 371873#L884-1 assume !(1 == ~T4_E~0); 371387#L889-1 assume !(1 == ~T5_E~0); 371388#L894-1 assume !(1 == ~T6_E~0); 371651#L899-1 assume !(1 == ~T7_E~0); 372072#L904-1 assume !(1 == ~E_M~0); 371820#L909-1 assume !(1 == ~E_1~0); 371821#L914-1 assume !(1 == ~E_2~0); 372007#L919-1 assume !(1 == ~E_3~0); 371733#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 371562#L929-1 assume !(1 == ~E_5~0); 371563#L934-1 assume !(1 == ~E_6~0); 371797#L939-1 assume !(1 == ~E_7~0); 371798#L944-1 assume { :end_inline_reset_delta_events } true; 372203#L1190-2 [2024-11-19 15:03:08,383 INFO L747 eck$LassoCheckResult]: Loop: 372203#L1190-2 assume !false; 384809#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 384807#L756-1 assume !false; 384805#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 384803#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 384793#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 384791#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 384788#L653 assume !(0 != eval_~tmp~0#1); 384789#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 390368#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 390364#L781-3 assume !(0 == ~M_E~0); 390360#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 390356#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 390351#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 390346#L796-3 assume !(0 == ~T4_E~0); 390342#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 390338#L806-3 assume !(0 == ~T6_E~0); 390334#L811-3 assume !(0 == ~T7_E~0); 390330#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 390326#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 390321#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 390317#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 390313#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 390309#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 390304#L846-3 assume !(0 == ~E_6~0); 390301#L851-3 assume !(0 == ~E_7~0); 390299#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 390297#L388-27 assume 1 == ~m_pc~0; 390295#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 390292#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 390290#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 390288#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 390286#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 390284#L407-27 assume !(1 == ~t1_pc~0); 390282#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 390280#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 390278#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 390272#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 390267#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 390263#L426-27 assume !(1 == ~t2_pc~0); 390259#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 390254#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 390250#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 390246#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 390242#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 390238#L445-27 assume !(1 == ~t3_pc~0); 390234#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 390229#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 390226#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 390224#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 390222#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 390220#L464-27 assume 1 == ~t4_pc~0; 390217#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 390215#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 390213#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 390211#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 390209#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 390207#L483-27 assume !(1 == ~t5_pc~0); 390205#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 390203#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 390198#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 390194#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 390189#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 390185#L502-27 assume !(1 == ~t6_pc~0); 390181#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 390177#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 390169#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 390163#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 390160#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 390158#L521-27 assume 1 == ~t7_pc~0; 390156#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 390157#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 390167#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 390148#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 390143#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 390138#L869-3 assume !(1 == ~M_E~0); 379251#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 390130#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 390126#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 390123#L884-3 assume !(1 == ~T4_E~0); 390118#L889-3 assume !(1 == ~T5_E~0); 390113#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 390108#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 390102#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 390099#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 390096#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 390094#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 390093#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 390092#L929-3 assume !(1 == ~E_5~0); 390090#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 390088#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 390086#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 389908#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 389903#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 389553#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 379370#L1209 assume !(0 == start_simulation_~tmp~3#1); 379371#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 384895#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 384889#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 384887#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 384885#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 384883#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 384881#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 384879#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 372203#L1190-2 [2024-11-19 15:03:08,383 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:08,383 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2024-11-19 15:03:08,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:08,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735361507] [2024-11-19 15:03:08,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:08,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:08,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:08,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:08,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:08,433 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735361507] [2024-11-19 15:03:08,433 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1735361507] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:08,433 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:08,433 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:08,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1570051733] [2024-11-19 15:03:08,434 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:08,434 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:08,434 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:08,434 INFO L85 PathProgramCache]: Analyzing trace with hash 1114420829, now seen corresponding path program 1 times [2024-11-19 15:03:08,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:08,435 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454467793] [2024-11-19 15:03:08,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:08,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:08,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:08,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:08,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:08,469 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454467793] [2024-11-19 15:03:08,469 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [454467793] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:08,469 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:08,469 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:08,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416301230] [2024-11-19 15:03:08,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:08,470 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:08,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:08,471 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:03:08,471 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:03:08,471 INFO L87 Difference]: Start difference. First operand 19206 states and 27377 transitions. cyclomatic complexity: 8187 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:08,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:08,629 INFO L93 Difference]: Finished difference Result 30510 states and 43007 transitions. [2024-11-19 15:03:08,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30510 states and 43007 transitions. [2024-11-19 15:03:08,752 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 30116 [2024-11-19 15:03:08,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30510 states to 30510 states and 43007 transitions. [2024-11-19 15:03:08,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30510 [2024-11-19 15:03:08,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30510 [2024-11-19 15:03:08,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30510 states and 43007 transitions. [2024-11-19 15:03:08,894 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:08,894 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30510 states and 43007 transitions. [2024-11-19 15:03:08,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30510 states and 43007 transitions. [2024-11-19 15:03:09,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30510 to 21646. [2024-11-19 15:03:09,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21646 states, 21646 states have (on average 1.4149496442760787) internal successors, (30628), 21645 states have internal predecessors, (30628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:09,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21646 states to 21646 states and 30628 transitions. [2024-11-19 15:03:09,151 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30628 transitions. [2024-11-19 15:03:09,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:03:09,152 INFO L425 stractBuchiCegarLoop]: Abstraction has 21646 states and 30628 transitions. [2024-11-19 15:03:09,152 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-19 15:03:09,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21646 states and 30628 transitions. [2024-11-19 15:03:09,213 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2024-11-19 15:03:09,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:09,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:09,215 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:09,216 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:09,216 INFO L745 eck$LassoCheckResult]: Stem: 421355#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 421356#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 421985#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 421986#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 422085#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 421506#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 421507#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 421638#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 421639#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 421402#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 421190#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 421191#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 421363#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 421364#L781 assume !(0 == ~M_E~0); 421889#L781-2 assume !(0 == ~T1_E~0); 422096#L786-1 assume !(0 == ~T2_E~0); 421153#L791-1 assume !(0 == ~T3_E~0); 421154#L796-1 assume !(0 == ~T4_E~0); 421719#L801-1 assume !(0 == ~T5_E~0); 421720#L806-1 assume !(0 == ~T6_E~0); 421752#L811-1 assume !(0 == ~T7_E~0); 421367#L816-1 assume !(0 == ~E_M~0); 421368#L821-1 assume !(0 == ~E_1~0); 421181#L826-1 assume !(0 == ~E_2~0); 421182#L831-1 assume !(0 == ~E_3~0); 421500#L836-1 assume 0 == ~E_4~0;~E_4~0 := 1; 421501#L841-1 assume !(0 == ~E_5~0); 421318#L846-1 assume !(0 == ~E_6~0); 421319#L851-1 assume !(0 == ~E_7~0); 422152#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 422008#L388 assume !(1 == ~m_pc~0); 422009#L388-2 is_master_triggered_~__retres1~0#1 := 0; 422151#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 421917#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 421918#L967 assume !(0 != activate_threads_~tmp~1#1); 422076#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 422077#L407 assume !(1 == ~t1_pc~0); 422084#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 421134#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 421135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 421169#L975 assume !(0 != activate_threads_~tmp___0~0#1); 422003#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 422004#L426 assume !(1 == ~t2_pc~0); 422017#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 422018#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 421481#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 421482#L983 assume !(0 != activate_threads_~tmp___1~0#1); 422147#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 422146#L445 assume !(1 == ~t3_pc~0); 422145#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 422144#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 421125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 421126#L991 assume !(0 != activate_threads_~tmp___2~0#1); 421819#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 421895#L464 assume !(1 == ~t4_pc~0); 422140#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 422139#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 422138#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 422137#L999 assume !(0 != activate_threads_~tmp___3~0#1); 422136#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 422135#L483 assume !(1 == ~t5_pc~0); 422134#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 422133#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 422132#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 422131#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 422130#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 422129#L502 assume !(1 == ~t6_pc~0); 422128#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 422127#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 422126#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 422125#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 422124#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 422123#L521 assume !(1 == ~t7_pc~0); 422121#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 422119#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 422117#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 422115#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 422114#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 422113#L869 assume !(1 == ~M_E~0); 422112#L869-2 assume !(1 == ~T1_E~0); 422111#L874-1 assume !(1 == ~T2_E~0); 422110#L879-1 assume !(1 == ~T3_E~0); 422109#L884-1 assume !(1 == ~T4_E~0); 422108#L889-1 assume !(1 == ~T5_E~0); 422107#L894-1 assume !(1 == ~T6_E~0); 422106#L899-1 assume !(1 == ~T7_E~0); 422105#L904-1 assume !(1 == ~E_M~0); 422104#L909-1 assume !(1 == ~E_1~0); 422103#L914-1 assume !(1 == ~E_2~0); 422102#L919-1 assume !(1 == ~E_3~0); 422101#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 421289#L929-1 assume !(1 == ~E_5~0); 421290#L934-1 assume !(1 == ~E_6~0); 421528#L939-1 assume !(1 == ~E_7~0); 421529#L944-1 assume { :end_inline_reset_delta_events } true; 421936#L1190-2 [2024-11-19 15:03:09,216 INFO L747 eck$LassoCheckResult]: Loop: 421936#L1190-2 assume !false; 434492#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 434490#L756-1 assume !false; 434488#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 434486#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 434476#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 434466#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 434456#L653 assume !(0 != eval_~tmp~0#1); 434457#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 442268#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 442266#L781-3 assume !(0 == ~M_E~0); 442265#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 442263#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 442261#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 442259#L796-3 assume !(0 == ~T4_E~0); 442257#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 441948#L806-3 assume !(0 == ~T6_E~0); 441938#L811-3 assume !(0 == ~T7_E~0); 441933#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 441928#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 441921#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 441920#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 441918#L836-3 assume !(0 == ~E_4~0); 441919#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 442363#L846-3 assume !(0 == ~E_6~0); 442362#L851-3 assume !(0 == ~E_7~0); 442361#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 442360#L388-27 assume !(1 == ~m_pc~0); 442358#L388-29 is_master_triggered_~__retres1~0#1 := 0; 442357#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 442356#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 442355#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 442354#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 442352#L407-27 assume !(1 == ~t1_pc~0); 442350#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 442348#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 442346#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 442343#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 442341#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 442339#L426-27 assume 1 == ~t2_pc~0; 442336#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 442334#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 442332#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 442329#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 442327#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 442325#L445-27 assume !(1 == ~t3_pc~0); 442323#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 442321#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 442319#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 442316#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 442314#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 442312#L464-27 assume !(1 == ~t4_pc~0); 441885#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 442308#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 442306#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 442303#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 442301#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 442299#L483-27 assume !(1 == ~t5_pc~0); 442297#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 442295#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 442292#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 442291#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 442289#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 442287#L502-27 assume !(1 == ~t6_pc~0); 442285#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 442283#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 442282#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 442281#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 442279#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 442278#L521-27 assume !(1 == ~t7_pc~0); 442276#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 442274#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 442272#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 442271#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 442269#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 442267#L869-3 assume !(1 == ~M_E~0); 425629#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 442264#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 442262#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 442260#L884-3 assume !(1 == ~T4_E~0); 442258#L889-3 assume !(1 == ~T5_E~0); 441940#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 441936#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 441931#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 441927#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 441926#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 441925#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 441846#L924-3 assume !(1 == ~E_4~0); 441843#L929-3 assume !(1 == ~E_5~0); 441842#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 441841#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 441840#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 441824#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 441818#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 441816#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 425906#L1209 assume !(0 == start_simulation_~tmp~3#1); 425907#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 434633#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 434627#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 434625#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 434623#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 434620#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 434619#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 434618#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 421936#L1190-2 [2024-11-19 15:03:09,217 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:09,217 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2024-11-19 15:03:09,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:09,217 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902855361] [2024-11-19 15:03:09,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:09,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:09,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:09,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:09,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:09,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902855361] [2024-11-19 15:03:09,264 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902855361] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:09,264 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:09,265 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:09,265 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832577847] [2024-11-19 15:03:09,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:09,265 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:09,265 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:09,265 INFO L85 PathProgramCache]: Analyzing trace with hash 352144737, now seen corresponding path program 1 times [2024-11-19 15:03:09,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:09,266 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050060919] [2024-11-19 15:03:09,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:09,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:09,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:09,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:09,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:09,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050060919] [2024-11-19 15:03:09,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050060919] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:09,304 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:09,304 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:09,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1042420517] [2024-11-19 15:03:09,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:09,305 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:09,306 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:09,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:03:09,306 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:03:09,306 INFO L87 Difference]: Start difference. First operand 21646 states and 30628 transitions. cyclomatic complexity: 8998 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:09,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:09,596 INFO L93 Difference]: Finished difference Result 27562 states and 38762 transitions. [2024-11-19 15:03:09,596 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27562 states and 38762 transitions. [2024-11-19 15:03:09,676 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27284 [2024-11-19 15:03:09,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27562 states to 27562 states and 38762 transitions. [2024-11-19 15:03:09,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27562 [2024-11-19 15:03:09,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27562 [2024-11-19 15:03:09,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27562 states and 38762 transitions. [2024-11-19 15:03:09,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:09,757 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27562 states and 38762 transitions. [2024-11-19 15:03:09,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27562 states and 38762 transitions. [2024-11-19 15:03:09,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27562 to 19206. [2024-11-19 15:03:09,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.408622305529522) internal successors, (27054), 19205 states have internal predecessors, (27054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:09,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27054 transitions. [2024-11-19 15:03:09,914 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27054 transitions. [2024-11-19 15:03:09,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:03:09,915 INFO L425 stractBuchiCegarLoop]: Abstraction has 19206 states and 27054 transitions. [2024-11-19 15:03:09,915 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-19 15:03:09,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27054 transitions. [2024-11-19 15:03:09,949 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2024-11-19 15:03:09,949 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:09,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:09,950 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:09,950 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:09,951 INFO L745 eck$LassoCheckResult]: Stem: 470573#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 470574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 471194#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 471195#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 471290#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 470716#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 470717#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 470842#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 470843#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 470620#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 470408#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 470409#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 470579#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 470580#L781 assume !(0 == ~M_E~0); 471099#L781-2 assume !(0 == ~T1_E~0); 471305#L786-1 assume !(0 == ~T2_E~0); 470371#L791-1 assume !(0 == ~T3_E~0); 470372#L796-1 assume !(0 == ~T4_E~0); 470921#L801-1 assume !(0 == ~T5_E~0); 470922#L806-1 assume !(0 == ~T6_E~0); 470953#L811-1 assume !(0 == ~T7_E~0); 470585#L816-1 assume !(0 == ~E_M~0); 470586#L821-1 assume !(0 == ~E_1~0); 470399#L826-1 assume !(0 == ~E_2~0); 470400#L831-1 assume !(0 == ~E_3~0); 470711#L836-1 assume !(0 == ~E_4~0); 470712#L841-1 assume !(0 == ~E_5~0); 470536#L846-1 assume !(0 == ~E_6~0); 470537#L851-1 assume !(0 == ~E_7~0); 470560#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 470561#L388 assume !(1 == ~m_pc~0); 470554#L388-2 is_master_triggered_~__retres1~0#1 := 0; 470555#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 471069#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 470414#L967 assume !(0 != activate_threads_~tmp~1#1); 470415#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 470345#L407 assume !(1 == ~t1_pc~0); 470346#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 470352#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 470353#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 470387#L975 assume !(0 != activate_threads_~tmp___0~0#1); 471192#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 470672#L426 assume !(1 == ~t2_pc~0); 470673#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 471225#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 470694#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 470695#L983 assume !(0 != activate_threads_~tmp___1~0#1); 471282#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 470756#L445 assume !(1 == ~t3_pc~0); 470757#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 471106#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 470343#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 470344#L991 assume !(0 != activate_threads_~tmp___2~0#1); 471022#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 470984#L464 assume !(1 == ~t4_pc~0); 470566#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 470434#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 470435#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 470448#L999 assume !(0 != activate_threads_~tmp___3~0#1); 470736#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 470737#L483 assume !(1 == ~t5_pc~0); 470981#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 471166#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 471129#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 471130#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 470659#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 470660#L502 assume !(1 == ~t6_pc~0); 470514#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 470474#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 470475#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 470683#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 470881#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 471144#L521 assume !(1 == ~t7_pc~0); 471189#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 470410#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 470411#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 471180#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 471150#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 471059#L869 assume !(1 == ~M_E~0); 470730#L869-2 assume !(1 == ~T1_E~0); 470731#L874-1 assume !(1 == ~T2_E~0); 471245#L879-1 assume !(1 == ~T3_E~0); 470806#L884-1 assume !(1 == ~T4_E~0); 470331#L889-1 assume !(1 == ~T5_E~0); 470332#L894-1 assume !(1 == ~T6_E~0); 470596#L899-1 assume !(1 == ~T7_E~0); 471010#L904-1 assume !(1 == ~E_M~0); 470753#L909-1 assume !(1 == ~E_1~0); 470754#L914-1 assume !(1 == ~E_2~0); 470940#L919-1 assume !(1 == ~E_3~0); 470671#L924-1 assume !(1 == ~E_4~0); 470507#L929-1 assume !(1 == ~E_5~0); 470508#L934-1 assume !(1 == ~E_6~0); 470734#L939-1 assume !(1 == ~E_7~0); 470735#L944-1 assume { :end_inline_reset_delta_events } true; 471143#L1190-2 [2024-11-19 15:03:09,951 INFO L747 eck$LassoCheckResult]: Loop: 471143#L1190-2 assume !false; 477129#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 477127#L756-1 assume !false; 477125#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 477122#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 477113#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 477111#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 477108#L653 assume !(0 != eval_~tmp~0#1); 477106#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 477104#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 477102#L781-3 assume !(0 == ~M_E~0); 477100#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 477098#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 477096#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 477041#L796-3 assume !(0 == ~T4_E~0); 477036#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 477031#L806-3 assume !(0 == ~T6_E~0); 477025#L811-3 assume !(0 == ~T7_E~0); 477020#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 477015#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 477010#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 477004#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 476998#L836-3 assume !(0 == ~E_4~0); 476993#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 476988#L846-3 assume !(0 == ~E_6~0); 476982#L851-3 assume !(0 == ~E_7~0); 476977#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 476972#L388-27 assume 1 == ~m_pc~0; 476967#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 476961#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 476956#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 476950#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 476945#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 476939#L407-27 assume !(1 == ~t1_pc~0); 476933#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 476928#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 476923#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 476917#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 476911#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 476906#L426-27 assume !(1 == ~t2_pc~0); 476901#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 476895#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 476890#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 476885#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 476878#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 476872#L445-27 assume !(1 == ~t3_pc~0); 476867#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 476862#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 476856#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 476851#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 476845#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 476839#L464-27 assume !(1 == ~t4_pc~0); 476833#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 476828#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 476823#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 476817#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 476812#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 476807#L483-27 assume !(1 == ~t5_pc~0); 476801#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 476796#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 476791#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 476785#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 476780#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 476774#L502-27 assume !(1 == ~t6_pc~0); 476767#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 476760#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 476753#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 476746#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 476740#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 476735#L521-27 assume !(1 == ~t7_pc~0); 476730#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 476724#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 476718#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 476713#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 476707#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 476702#L869-3 assume !(1 == ~M_E~0); 476431#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 476693#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 476688#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 476683#L884-3 assume !(1 == ~T4_E~0); 476677#L889-3 assume !(1 == ~T5_E~0); 476671#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 476666#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 476661#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 476657#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 476578#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 476577#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 476576#L924-3 assume !(1 == ~E_4~0); 476575#L929-3 assume !(1 == ~E_5~0); 476574#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 476573#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 476572#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 476542#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 476534#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 476532#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 476486#L1209 assume !(0 == start_simulation_~tmp~3#1); 476487#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 477166#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 477153#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 477151#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 477149#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 477147#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 477145#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 477143#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 471143#L1190-2 [2024-11-19 15:03:09,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:09,951 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2024-11-19 15:03:09,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:09,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910955467] [2024-11-19 15:03:09,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:09,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:09,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:09,962 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:09,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:09,999 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:10,000 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:10,000 INFO L85 PathProgramCache]: Analyzing trace with hash -1722865951, now seen corresponding path program 1 times [2024-11-19 15:03:10,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:10,000 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414696878] [2024-11-19 15:03:10,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:10,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:10,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:10,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:10,026 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:10,027 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414696878] [2024-11-19 15:03:10,027 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [414696878] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:10,027 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:10,027 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:10,027 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850184002] [2024-11-19 15:03:10,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:10,027 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:10,027 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:10,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:10,028 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:10,028 INFO L87 Difference]: Start difference. First operand 19206 states and 27054 transitions. cyclomatic complexity: 7864 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:10,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:10,081 INFO L93 Difference]: Finished difference Result 21646 states and 30463 transitions. [2024-11-19 15:03:10,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21646 states and 30463 transitions. [2024-11-19 15:03:10,133 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2024-11-19 15:03:10,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21646 states to 21646 states and 30463 transitions. [2024-11-19 15:03:10,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21646 [2024-11-19 15:03:10,172 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21646 [2024-11-19 15:03:10,172 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21646 states and 30463 transitions. [2024-11-19 15:03:10,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:10,183 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30463 transitions. [2024-11-19 15:03:10,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21646 states and 30463 transitions. [2024-11-19 15:03:10,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21646 to 21646. [2024-11-19 15:03:10,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21646 states, 21646 states have (on average 1.4073269888201054) internal successors, (30463), 21645 states have internal predecessors, (30463), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:10,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21646 states to 21646 states and 30463 transitions. [2024-11-19 15:03:10,512 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30463 transitions. [2024-11-19 15:03:10,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:10,513 INFO L425 stractBuchiCegarLoop]: Abstraction has 21646 states and 30463 transitions. [2024-11-19 15:03:10,513 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-19 15:03:10,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21646 states and 30463 transitions. [2024-11-19 15:03:10,555 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2024-11-19 15:03:10,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:10,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:10,556 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:10,556 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:10,557 INFO L745 eck$LassoCheckResult]: Stem: 511431#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 511432#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 512046#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 512047#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 512137#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 511574#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 511575#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 511700#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 511701#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 511477#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 511265#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 511266#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 511438#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 511439#L781 assume !(0 == ~M_E~0); 511952#L781-2 assume !(0 == ~T1_E~0); 512154#L786-1 assume !(0 == ~T2_E~0); 511228#L791-1 assume !(0 == ~T3_E~0); 511229#L796-1 assume !(0 == ~T4_E~0); 511779#L801-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 511780#L806-1 assume !(0 == ~T6_E~0); 511815#L811-1 assume !(0 == ~T7_E~0); 511442#L816-1 assume !(0 == ~E_M~0); 511443#L821-1 assume !(0 == ~E_1~0); 511257#L826-1 assume !(0 == ~E_2~0); 511258#L831-1 assume !(0 == ~E_3~0); 512198#L836-1 assume !(0 == ~E_4~0); 512197#L841-1 assume !(0 == ~E_5~0); 512196#L846-1 assume !(0 == ~E_6~0); 512143#L851-1 assume !(0 == ~E_7~0); 511417#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 511418#L388 assume !(1 == ~m_pc~0); 511411#L388-2 is_master_triggered_~__retres1~0#1 := 0; 511412#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 511929#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 511271#L967 assume !(0 != activate_threads_~tmp~1#1); 511272#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 511203#L407 assume !(1 == ~t1_pc~0); 511204#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 512193#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 512192#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 512042#L975 assume !(0 != activate_threads_~tmp___0~0#1); 512043#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 511529#L426 assume !(1 == ~t2_pc~0); 511530#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 512121#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 511551#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 511552#L983 assume !(0 != activate_threads_~tmp___1~0#1); 512190#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 512189#L445 assume !(1 == ~t3_pc~0); 512188#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 512187#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 511201#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 511202#L991 assume !(0 != activate_threads_~tmp___2~0#1); 511884#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 511958#L464 assume !(1 == ~t4_pc~0); 512183#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 511291#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 511292#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 511305#L999 assume !(0 != activate_threads_~tmp___3~0#1); 511594#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 511595#L483 assume !(1 == ~t5_pc~0); 511842#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 512019#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 512020#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 512093#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 512094#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 512178#L502 assume !(1 == ~t6_pc~0); 511371#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 511372#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 512176#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 512175#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 512174#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 512173#L521 assume !(1 == ~t7_pc~0); 512078#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 512079#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 512177#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 512168#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 512167#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 512166#L869 assume !(1 == ~M_E~0); 512165#L869-2 assume !(1 == ~T1_E~0); 512164#L874-1 assume !(1 == ~T2_E~0); 512163#L879-1 assume !(1 == ~T3_E~0); 512162#L884-1 assume !(1 == ~T4_E~0); 511189#L889-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 511190#L894-1 assume !(1 == ~T6_E~0); 511453#L899-1 assume !(1 == ~T7_E~0); 511874#L904-1 assume !(1 == ~E_M~0); 511612#L909-1 assume !(1 == ~E_1~0); 511613#L914-1 assume !(1 == ~E_2~0); 511802#L919-1 assume !(1 == ~E_3~0); 511528#L924-1 assume !(1 == ~E_4~0); 511364#L929-1 assume !(1 == ~E_5~0); 511365#L934-1 assume !(1 == ~E_6~0); 511592#L939-1 assume !(1 == ~E_7~0); 511593#L944-1 assume { :end_inline_reset_delta_events } true; 511995#L1190-2 [2024-11-19 15:03:10,557 INFO L747 eck$LassoCheckResult]: Loop: 511995#L1190-2 assume !false; 515875#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 515873#L756-1 assume !false; 515871#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 515869#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 515860#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 515857#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 515854#L653 assume !(0 != eval_~tmp~0#1); 515855#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 516863#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 516862#L781-3 assume !(0 == ~M_E~0); 516861#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 516860#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 516859#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 516857#L796-3 assume !(0 == ~T4_E~0); 516853#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 516854#L806-3 assume !(0 == ~T6_E~0); 518423#L811-3 assume !(0 == ~T7_E~0); 518421#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 518419#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 518417#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 518415#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 518413#L836-3 assume !(0 == ~E_4~0); 518411#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 518409#L846-3 assume !(0 == ~E_6~0); 518407#L851-3 assume !(0 == ~E_7~0); 518405#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 518402#L388-27 assume 1 == ~m_pc~0; 518367#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 518364#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 518362#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 518360#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 518357#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 518353#L407-27 assume !(1 == ~t1_pc~0); 518351#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 518349#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 518347#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 518344#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 517692#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 517691#L426-27 assume !(1 == ~t2_pc~0); 517690#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 516571#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 516567#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 516565#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 516563#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 516562#L445-27 assume !(1 == ~t3_pc~0); 516559#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 516550#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 516548#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 516546#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 516544#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 516542#L464-27 assume !(1 == ~t4_pc~0); 516539#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 516537#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 516536#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 516533#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 516531#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 516529#L483-27 assume !(1 == ~t5_pc~0); 516527#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 516525#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 516523#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 516521#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 516519#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 516517#L502-27 assume !(1 == ~t6_pc~0); 516515#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 516513#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 516511#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 516508#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 516506#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 516504#L521-27 assume 1 == ~t7_pc~0; 516502#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 516503#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 516715#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 516493#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 516491#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 516489#L869-3 assume !(1 == ~M_E~0); 516132#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 516486#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 516483#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 516481#L884-3 assume !(1 == ~T4_E~0); 516479#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 516476#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 516474#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 516472#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 516470#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 516467#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 516465#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 516463#L924-3 assume !(1 == ~E_4~0); 516461#L929-3 assume !(1 == ~E_5~0); 516459#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 516457#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 516455#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 516442#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 516436#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 516433#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 516430#L1209 assume !(0 == start_simulation_~tmp~3#1); 516431#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 516555#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 516549#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 516547#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 516545#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 516543#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 516540#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 516538#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 511995#L1190-2 [2024-11-19 15:03:10,558 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:10,558 INFO L85 PathProgramCache]: Analyzing trace with hash 1343517957, now seen corresponding path program 1 times [2024-11-19 15:03:10,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:10,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288195223] [2024-11-19 15:03:10,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:10,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:10,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:10,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:10,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:10,589 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288195223] [2024-11-19 15:03:10,589 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288195223] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:10,590 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:10,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:10,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074758277] [2024-11-19 15:03:10,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:10,590 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:10,590 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:10,590 INFO L85 PathProgramCache]: Analyzing trace with hash 953065888, now seen corresponding path program 1 times [2024-11-19 15:03:10,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:10,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104182703] [2024-11-19 15:03:10,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:10,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:10,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:10,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:10,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:10,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1104182703] [2024-11-19 15:03:10,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1104182703] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:10,619 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:10,619 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:10,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [939383740] [2024-11-19 15:03:10,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:10,620 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:10,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:10,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:03:10,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:03:10,621 INFO L87 Difference]: Start difference. First operand 21646 states and 30463 transitions. cyclomatic complexity: 8833 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:10,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:10,715 INFO L93 Difference]: Finished difference Result 28041 states and 39369 transitions. [2024-11-19 15:03:10,715 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28041 states and 39369 transitions. [2024-11-19 15:03:10,801 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27760 [2024-11-19 15:03:10,849 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28041 states to 28041 states and 39369 transitions. [2024-11-19 15:03:10,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28041 [2024-11-19 15:03:10,861 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28041 [2024-11-19 15:03:10,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28041 states and 39369 transitions. [2024-11-19 15:03:10,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:10,879 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28041 states and 39369 transitions. [2024-11-19 15:03:10,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28041 states and 39369 transitions. [2024-11-19 15:03:11,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28041 to 19206. [2024-11-19 15:03:11,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.4069040924711027) internal successors, (27021), 19205 states have internal predecessors, (27021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:11,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27021 transitions. [2024-11-19 15:03:11,037 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27021 transitions. [2024-11-19 15:03:11,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:03:11,038 INFO L425 stractBuchiCegarLoop]: Abstraction has 19206 states and 27021 transitions. [2024-11-19 15:03:11,038 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-19 15:03:11,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27021 transitions. [2024-11-19 15:03:11,079 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2024-11-19 15:03:11,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:11,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:11,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:11,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:11,081 INFO L745 eck$LassoCheckResult]: Stem: 561126#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 561127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 561723#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 561724#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 561801#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 561270#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 561271#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 561401#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 561402#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 561172#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 560962#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 560963#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 561131#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 561132#L781 assume !(0 == ~M_E~0); 561639#L781-2 assume !(0 == ~T1_E~0); 561814#L786-1 assume !(0 == ~T2_E~0); 560923#L791-1 assume !(0 == ~T3_E~0); 560924#L796-1 assume !(0 == ~T4_E~0); 561476#L801-1 assume !(0 == ~T5_E~0); 561477#L806-1 assume !(0 == ~T6_E~0); 561508#L811-1 assume !(0 == ~T7_E~0); 561137#L816-1 assume !(0 == ~E_M~0); 561138#L821-1 assume !(0 == ~E_1~0); 560954#L826-1 assume !(0 == ~E_2~0); 560955#L831-1 assume !(0 == ~E_3~0); 561265#L836-1 assume !(0 == ~E_4~0); 561266#L841-1 assume !(0 == ~E_5~0); 561089#L846-1 assume !(0 == ~E_6~0); 561090#L851-1 assume !(0 == ~E_7~0); 561112#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 561113#L388 assume !(1 == ~m_pc~0); 561106#L388-2 is_master_triggered_~__retres1~0#1 := 0; 561107#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 561613#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 560968#L967 assume !(0 != activate_threads_~tmp~1#1); 560969#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 560900#L407 assume !(1 == ~t1_pc~0); 560901#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 560904#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 560905#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 560940#L975 assume !(0 != activate_threads_~tmp___0~0#1); 561720#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 561227#L426 assume !(1 == ~t2_pc~0); 561228#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 561744#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 561248#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 561249#L983 assume !(0 != activate_threads_~tmp___1~0#1); 561791#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 561313#L445 assume !(1 == ~t3_pc~0); 561314#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 561647#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 560898#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 560899#L991 assume !(0 != activate_threads_~tmp___2~0#1); 561571#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 561536#L464 assume !(1 == ~t4_pc~0); 561116#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 560988#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 560989#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 561000#L999 assume !(0 != activate_threads_~tmp___3~0#1); 561292#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 561293#L483 assume !(1 == ~t5_pc~0); 561533#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 561700#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 561665#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 561666#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 561210#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 561211#L502 assume !(1 == ~t6_pc~0); 561067#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 561027#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 561028#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 561235#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 561440#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 561676#L521 assume !(1 == ~t7_pc~0); 561717#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 561749#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 561821#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 561710#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 561682#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 561603#L869 assume !(1 == ~M_E~0); 561286#L869-2 assume !(1 == ~T1_E~0); 561287#L874-1 assume !(1 == ~T2_E~0); 561760#L879-1 assume !(1 == ~T3_E~0); 561364#L884-1 assume !(1 == ~T4_E~0); 560886#L889-1 assume !(1 == ~T5_E~0); 560887#L894-1 assume !(1 == ~T6_E~0); 561145#L899-1 assume !(1 == ~T7_E~0); 561558#L904-1 assume !(1 == ~E_M~0); 561310#L909-1 assume !(1 == ~E_1~0); 561311#L914-1 assume !(1 == ~E_2~0); 561494#L919-1 assume !(1 == ~E_3~0); 561226#L924-1 assume !(1 == ~E_4~0); 561060#L929-1 assume !(1 == ~E_5~0); 561061#L934-1 assume !(1 == ~E_6~0); 561288#L939-1 assume !(1 == ~E_7~0); 561289#L944-1 assume { :end_inline_reset_delta_events } true; 561675#L1190-2 [2024-11-19 15:03:11,081 INFO L747 eck$LassoCheckResult]: Loop: 561675#L1190-2 assume !false; 570970#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 570968#L756-1 assume !false; 570967#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 570403#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 567747#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 567744#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 567741#L653 assume !(0 != eval_~tmp~0#1); 567739#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 567737#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 567735#L781-3 assume !(0 == ~M_E~0); 567733#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 567730#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 567728#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 567726#L796-3 assume !(0 == ~T4_E~0); 567724#L801-3 assume !(0 == ~T5_E~0); 567722#L806-3 assume !(0 == ~T6_E~0); 567719#L811-3 assume !(0 == ~T7_E~0); 567717#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 567715#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 567713#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 567711#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 567709#L836-3 assume !(0 == ~E_4~0); 567707#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 567704#L846-3 assume !(0 == ~E_6~0); 567702#L851-3 assume !(0 == ~E_7~0); 567700#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 567698#L388-27 assume !(1 == ~m_pc~0); 567695#L388-29 is_master_triggered_~__retres1~0#1 := 0; 567693#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567691#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 567689#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 567687#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567685#L407-27 assume !(1 == ~t1_pc~0); 567683#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 567681#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567678#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567676#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 567674#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567673#L426-27 assume !(1 == ~t2_pc~0); 567672#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 567670#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567668#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 567667#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 567666#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567662#L445-27 assume !(1 == ~t3_pc~0); 567660#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 567658#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567656#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 567077#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 567068#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567066#L464-27 assume !(1 == ~t4_pc~0); 567063#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 567060#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567058#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 567056#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 567054#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 567052#L483-27 assume !(1 == ~t5_pc~0); 567050#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 567048#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 567046#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 567044#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 567042#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 567040#L502-27 assume !(1 == ~t6_pc~0); 567038#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 567036#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 567034#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 567032#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 567030#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 567028#L521-27 assume !(1 == ~t7_pc~0); 567024#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 567022#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 567020#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 567018#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 567014#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 567012#L869-3 assume !(1 == ~M_E~0); 564151#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 567009#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 567007#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 567005#L884-3 assume !(1 == ~T4_E~0); 567003#L889-3 assume !(1 == ~T5_E~0); 567001#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 566999#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 566997#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 566995#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 566993#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 566772#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 566757#L924-3 assume !(1 == ~E_4~0); 566750#L929-3 assume !(1 == ~E_5~0); 566742#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 566678#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 566674#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 566661#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 566652#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 566647#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 564254#L1209 assume !(0 == start_simulation_~tmp~3#1); 564255#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 571196#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 571190#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 571188#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 571186#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 571183#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 571181#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 571177#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 561675#L1190-2 [2024-11-19 15:03:11,081 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:11,082 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2024-11-19 15:03:11,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:11,082 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515952515] [2024-11-19 15:03:11,082 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:03:11,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:11,091 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:03:11,091 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:03:11,091 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:11,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:11,119 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:11,120 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:11,120 INFO L85 PathProgramCache]: Analyzing trace with hash -40946012, now seen corresponding path program 1 times [2024-11-19 15:03:11,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:11,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941141668] [2024-11-19 15:03:11,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:11,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:11,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:11,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:11,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:11,148 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1941141668] [2024-11-19 15:03:11,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1941141668] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:11,149 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:11,149 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:11,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [297147005] [2024-11-19 15:03:11,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:11,150 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:11,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:11,150 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:11,150 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:11,150 INFO L87 Difference]: Start difference. First operand 19206 states and 27021 transitions. cyclomatic complexity: 7831 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:11,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:11,445 INFO L93 Difference]: Finished difference Result 28778 states and 40307 transitions. [2024-11-19 15:03:11,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28778 states and 40307 transitions. [2024-11-19 15:03:11,543 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28452 [2024-11-19 15:03:11,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28778 states to 28778 states and 40307 transitions. [2024-11-19 15:03:11,600 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28778 [2024-11-19 15:03:11,616 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28778 [2024-11-19 15:03:11,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28778 states and 40307 transitions. [2024-11-19 15:03:11,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:11,635 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28778 states and 40307 transitions. [2024-11-19 15:03:11,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28778 states and 40307 transitions. [2024-11-19 15:03:11,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28778 to 28762. [2024-11-19 15:03:11,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28762 states, 28762 states have (on average 1.400841387942424) internal successors, (40291), 28761 states have internal predecessors, (40291), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:11,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28762 states to 28762 states and 40291 transitions. [2024-11-19 15:03:11,861 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28762 states and 40291 transitions. [2024-11-19 15:03:11,861 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:11,862 INFO L425 stractBuchiCegarLoop]: Abstraction has 28762 states and 40291 transitions. [2024-11-19 15:03:11,862 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-19 15:03:11,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28762 states and 40291 transitions. [2024-11-19 15:03:11,920 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28436 [2024-11-19 15:03:11,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:11,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:11,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:11,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:11,922 INFO L745 eck$LassoCheckResult]: Stem: 609120#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 609121#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 609744#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 609745#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 609836#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 609266#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 609267#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 609398#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 609399#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 609166#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 608953#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 608954#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 609127#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 609128#L781 assume !(0 == ~M_E~0); 609646#L781-2 assume !(0 == ~T1_E~0); 609847#L786-1 assume !(0 == ~T2_E~0); 608916#L791-1 assume !(0 == ~T3_E~0); 608917#L796-1 assume !(0 == ~T4_E~0); 609476#L801-1 assume !(0 == ~T5_E~0); 609477#L806-1 assume !(0 == ~T6_E~0); 609510#L811-1 assume !(0 == ~T7_E~0); 609131#L816-1 assume !(0 == ~E_M~0); 609132#L821-1 assume !(0 == ~E_1~0); 608944#L826-1 assume !(0 == ~E_2~0); 608945#L831-1 assume !(0 == ~E_3~0); 609261#L836-1 assume !(0 == ~E_4~0); 609262#L841-1 assume 0 == ~E_5~0;~E_5~0 := 1; 609084#L846-1 assume !(0 == ~E_6~0); 609085#L851-1 assume !(0 == ~E_7~0); 609886#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 609767#L388 assume !(1 == ~m_pc~0); 609768#L388-2 is_master_triggered_~__retres1~0#1 := 0; 609885#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 609676#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 609677#L967 assume !(0 != activate_threads_~tmp~1#1); 609830#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 609831#L407 assume !(1 == ~t1_pc~0); 609835#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 608897#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 608898#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 608932#L975 assume !(0 != activate_threads_~tmp___0~0#1); 609760#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 609761#L426 assume !(1 == ~t2_pc~0); 609775#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 609776#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 609882#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 609823#L983 assume !(0 != activate_threads_~tmp___1~0#1); 609824#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 609310#L445 assume !(1 == ~t3_pc~0); 609311#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 609879#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 608888#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 608889#L991 assume !(0 != activate_threads_~tmp___2~0#1); 609578#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 609540#L464 assume !(1 == ~t4_pc~0); 609113#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 609114#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 609873#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 609872#L999 assume !(0 != activate_threads_~tmp___3~0#1); 609871#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 609536#L483 assume !(1 == ~t5_pc~0); 609537#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 609715#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 609716#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 609797#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 609798#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 609870#L502 assume !(1 == ~t6_pc~0); 609060#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 609061#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 609231#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 609232#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 609694#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 609695#L521 assume !(1 == ~t7_pc~0); 609737#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 608955#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 608956#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 609729#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 609730#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 609868#L869 assume !(1 == ~M_E~0); 609867#L869-2 assume !(1 == ~T1_E~0); 609818#L874-1 assume !(1 == ~T2_E~0); 609819#L879-1 assume !(1 == ~T3_E~0); 609361#L884-1 assume !(1 == ~T4_E~0); 609362#L889-1 assume !(1 == ~T5_E~0); 609141#L894-1 assume !(1 == ~T6_E~0); 609142#L899-1 assume !(1 == ~T7_E~0); 609568#L904-1 assume !(1 == ~E_M~0); 609307#L909-1 assume !(1 == ~E_1~0); 609308#L914-1 assume !(1 == ~E_2~0); 609520#L919-1 assume !(1 == ~E_3~0); 609217#L924-1 assume !(1 == ~E_4~0); 609053#L929-1 assume 1 == ~E_5~0;~E_5~0 := 2; 609054#L934-1 assume !(1 == ~E_6~0); 609288#L939-1 assume !(1 == ~E_7~0); 609289#L944-1 assume { :end_inline_reset_delta_events } true; 609693#L1190-2 [2024-11-19 15:03:11,922 INFO L747 eck$LassoCheckResult]: Loop: 609693#L1190-2 assume !false; 614758#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 614755#L756-1 assume !false; 614753#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 614751#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 614743#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 614740#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 614738#L653 assume !(0 != eval_~tmp~0#1); 614739#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 615092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 615090#L781-3 assume !(0 == ~M_E~0); 615088#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 615086#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 615084#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 615082#L796-3 assume !(0 == ~T4_E~0); 615080#L801-3 assume !(0 == ~T5_E~0); 615078#L806-3 assume !(0 == ~T6_E~0); 615076#L811-3 assume !(0 == ~T7_E~0); 615072#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 615070#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 615068#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 615066#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 615063#L836-3 assume !(0 == ~E_4~0); 615060#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 615059#L846-3 assume !(0 == ~E_6~0); 615058#L851-3 assume !(0 == ~E_7~0); 615056#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 615055#L388-27 assume !(1 == ~m_pc~0); 615053#L388-29 is_master_triggered_~__retres1~0#1 := 0; 615052#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 615051#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 615050#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 615049#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 615048#L407-27 assume !(1 == ~t1_pc~0); 615047#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 615046#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 615044#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 615041#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 615039#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 615037#L426-27 assume !(1 == ~t2_pc~0); 615035#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 615032#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 615030#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 615028#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 615026#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 615024#L445-27 assume !(1 == ~t3_pc~0); 615022#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 615020#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 615018#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 615015#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 615013#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 615011#L464-27 assume !(1 == ~t4_pc~0); 615008#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 615006#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 615004#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 615002#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 615000#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 614998#L483-27 assume !(1 == ~t5_pc~0); 614996#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 614994#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 614991#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 614989#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 614987#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 614985#L502-27 assume !(1 == ~t6_pc~0); 614983#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 614981#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 614979#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 614977#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 614975#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 614973#L521-27 assume !(1 == ~t7_pc~0); 614969#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 614967#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 614965#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 614963#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 614960#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 614958#L869-3 assume !(1 == ~M_E~0); 614954#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 614952#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 614948#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 614946#L884-3 assume !(1 == ~T4_E~0); 614944#L889-3 assume !(1 == ~T5_E~0); 614942#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 614939#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 614937#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 614934#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 614932#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 614930#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 614928#L924-3 assume !(1 == ~E_4~0); 614926#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 614923#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 614921#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 614919#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 614909#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 614903#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 614901#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 614900#L1209 assume !(0 == start_simulation_~tmp~3#1); 614898#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 614894#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 614889#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 614888#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 614887#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 614886#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 614885#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 614884#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 609693#L1190-2 [2024-11-19 15:03:11,922 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:11,923 INFO L85 PathProgramCache]: Analyzing trace with hash 2121315589, now seen corresponding path program 1 times [2024-11-19 15:03:11,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:11,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [366121804] [2024-11-19 15:03:11,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:11,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:11,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:11,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:11,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:11,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [366121804] [2024-11-19 15:03:11,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [366121804] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:11,951 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:11,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:11,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539593833] [2024-11-19 15:03:11,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:11,951 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:11,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:11,951 INFO L85 PathProgramCache]: Analyzing trace with hash 980122342, now seen corresponding path program 1 times [2024-11-19 15:03:11,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:11,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347019739] [2024-11-19 15:03:11,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:11,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:11,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:11,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:11,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:11,996 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347019739] [2024-11-19 15:03:11,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347019739] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:11,997 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:11,997 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:03:11,997 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [45742828] [2024-11-19 15:03:11,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:11,997 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:11,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:11,997 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:03:11,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:03:11,998 INFO L87 Difference]: Start difference. First operand 28762 states and 40291 transitions. cyclomatic complexity: 11545 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:12,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:12,141 INFO L93 Difference]: Finished difference Result 39377 states and 55061 transitions. [2024-11-19 15:03:12,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39377 states and 55061 transitions. [2024-11-19 15:03:12,496 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 38304 [2024-11-19 15:03:12,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39377 states to 39377 states and 55061 transitions. [2024-11-19 15:03:12,580 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39377 [2024-11-19 15:03:12,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39377 [2024-11-19 15:03:12,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39377 states and 55061 transitions. [2024-11-19 15:03:12,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:12,629 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39377 states and 55061 transitions. [2024-11-19 15:03:12,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39377 states and 55061 transitions. [2024-11-19 15:03:12,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39377 to 27514. [2024-11-19 15:03:12,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27514 states, 27514 states have (on average 1.3997237769862616) internal successors, (38512), 27513 states have internal predecessors, (38512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:12,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27514 states to 27514 states and 38512 transitions. [2024-11-19 15:03:12,937 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27514 states and 38512 transitions. [2024-11-19 15:03:12,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:03:12,938 INFO L425 stractBuchiCegarLoop]: Abstraction has 27514 states and 38512 transitions. [2024-11-19 15:03:12,938 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-19 15:03:12,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27514 states and 38512 transitions. [2024-11-19 15:03:13,011 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27260 [2024-11-19 15:03:13,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:13,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:13,012 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:13,012 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:13,013 INFO L745 eck$LassoCheckResult]: Stem: 677268#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 677269#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 677878#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 677879#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 677961#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 677415#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 677416#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 677545#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 677546#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 677313#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 677103#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 677104#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 677275#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 677276#L781 assume !(0 == ~M_E~0); 677791#L781-2 assume !(0 == ~T1_E~0); 677982#L786-1 assume !(0 == ~T2_E~0); 677066#L791-1 assume !(0 == ~T3_E~0); 677067#L796-1 assume !(0 == ~T4_E~0); 677626#L801-1 assume !(0 == ~T5_E~0); 677627#L806-1 assume !(0 == ~T6_E~0); 677661#L811-1 assume !(0 == ~T7_E~0); 677279#L816-1 assume !(0 == ~E_M~0); 677280#L821-1 assume !(0 == ~E_1~0); 677095#L826-1 assume !(0 == ~E_2~0); 677096#L831-1 assume !(0 == ~E_3~0); 677410#L836-1 assume !(0 == ~E_4~0); 677411#L841-1 assume !(0 == ~E_5~0); 677232#L846-1 assume !(0 == ~E_6~0); 677233#L851-1 assume !(0 == ~E_7~0); 677255#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 677256#L388 assume !(1 == ~m_pc~0); 677249#L388-2 is_master_triggered_~__retres1~0#1 := 0; 677250#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 677767#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 677109#L967 assume !(0 != activate_threads_~tmp~1#1); 677110#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 677041#L407 assume !(1 == ~t1_pc~0); 677042#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 677048#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 677049#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 677082#L975 assume !(0 != activate_threads_~tmp___0~0#1); 677874#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 677367#L426 assume !(1 == ~t2_pc~0); 677368#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 677902#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 677390#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 677391#L983 assume !(0 != activate_threads_~tmp___1~0#1); 677947#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 677459#L445 assume !(1 == ~t3_pc~0); 677460#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 677800#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 677039#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 677040#L991 assume !(0 != activate_threads_~tmp___2~0#1); 677726#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 677691#L464 assume !(1 == ~t4_pc~0); 677261#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 677129#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 677130#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 677143#L999 assume !(0 != activate_threads_~tmp___3~0#1); 677438#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 677439#L483 assume !(1 == ~t5_pc~0); 677688#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 677853#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 677820#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 677821#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 677352#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 677353#L502 assume !(1 == ~t6_pc~0); 677210#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 677168#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 677169#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 677379#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 677586#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 677832#L521 assume !(1 == ~t7_pc~0); 677871#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 677105#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 677106#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 677864#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 677838#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 677757#L869 assume !(1 == ~M_E~0); 677432#L869-2 assume !(1 == ~T1_E~0); 677433#L874-1 assume !(1 == ~T2_E~0); 677912#L879-1 assume !(1 == ~T3_E~0); 677508#L884-1 assume !(1 == ~T4_E~0); 677027#L889-1 assume !(1 == ~T5_E~0); 677028#L894-1 assume !(1 == ~T6_E~0); 677290#L899-1 assume !(1 == ~T7_E~0); 677716#L904-1 assume !(1 == ~E_M~0); 677456#L909-1 assume !(1 == ~E_1~0); 677457#L914-1 assume !(1 == ~E_2~0); 677647#L919-1 assume !(1 == ~E_3~0); 677366#L924-1 assume !(1 == ~E_4~0); 677202#L929-1 assume !(1 == ~E_5~0); 677203#L934-1 assume !(1 == ~E_6~0); 677436#L939-1 assume !(1 == ~E_7~0); 677437#L944-1 assume { :end_inline_reset_delta_events } true; 677831#L1190-2 [2024-11-19 15:03:13,013 INFO L747 eck$LassoCheckResult]: Loop: 677831#L1190-2 assume !false; 689036#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 689035#L756-1 assume !false; 689033#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 688711#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 688693#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 688686#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 688682#L653 assume !(0 != eval_~tmp~0#1); 688683#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 691029#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 691027#L781-3 assume !(0 == ~M_E~0); 691025#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 691023#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 691021#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 691019#L796-3 assume !(0 == ~T4_E~0); 691017#L801-3 assume !(0 == ~T5_E~0); 691015#L806-3 assume !(0 == ~T6_E~0); 691013#L811-3 assume !(0 == ~T7_E~0); 691011#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 691009#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 691007#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 691005#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 691003#L836-3 assume !(0 == ~E_4~0); 691001#L841-3 assume !(0 == ~E_5~0); 690999#L846-3 assume !(0 == ~E_6~0); 690997#L851-3 assume !(0 == ~E_7~0); 690995#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 690993#L388-27 assume !(1 == ~m_pc~0); 690990#L388-29 is_master_triggered_~__retres1~0#1 := 0; 690987#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 690985#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 690983#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 690981#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 690979#L407-27 assume !(1 == ~t1_pc~0); 690977#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 690975#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 690973#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 690971#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 690969#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 690967#L426-27 assume 1 == ~t2_pc~0; 690964#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 690961#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 690959#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 690957#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 690955#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 690953#L445-27 assume !(1 == ~t3_pc~0); 690951#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 690948#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 690946#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 690944#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 690942#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 690940#L464-27 assume !(1 == ~t4_pc~0); 690936#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 690934#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 690932#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 690930#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 690928#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 690926#L483-27 assume !(1 == ~t5_pc~0); 690924#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 690922#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 690920#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 690917#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 690914#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 690911#L502-27 assume !(1 == ~t6_pc~0); 690908#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 690905#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 690902#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 690899#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 690896#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 690893#L521-27 assume !(1 == ~t7_pc~0); 690890#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 690885#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 690879#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 690873#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 690867#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 690863#L869-3 assume !(1 == ~M_E~0); 684300#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 690859#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 690857#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 690854#L884-3 assume !(1 == ~T4_E~0); 690851#L889-3 assume !(1 == ~T5_E~0); 690848#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 690845#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 690842#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 690839#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 690836#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 690833#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 690830#L924-3 assume !(1 == ~E_4~0); 690827#L929-3 assume !(1 == ~E_5~0); 690823#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 690821#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 690819#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 690814#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 690808#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 690807#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 677964#L1209 assume !(0 == start_simulation_~tmp~3#1); 677965#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 689081#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 689065#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 689055#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 689051#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 689049#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 689047#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 689046#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 677831#L1190-2 [2024-11-19 15:03:13,013 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:13,013 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 3 times [2024-11-19 15:03:13,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:13,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1755497835] [2024-11-19 15:03:13,014 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 15:03:13,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:13,023 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 15:03:13,023 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:03:13,023 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:13,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:13,041 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:13,041 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:13,041 INFO L85 PathProgramCache]: Analyzing trace with hash -1476426907, now seen corresponding path program 1 times [2024-11-19 15:03:13,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:13,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [408719501] [2024-11-19 15:03:13,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:13,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:13,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:13,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:13,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:13,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [408719501] [2024-11-19 15:03:13,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [408719501] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:13,083 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:13,083 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:03:13,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046163280] [2024-11-19 15:03:13,084 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:13,084 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:13,084 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:13,084 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:03:13,084 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:03:13,084 INFO L87 Difference]: Start difference. First operand 27514 states and 38512 transitions. cyclomatic complexity: 11014 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:13,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:13,210 INFO L93 Difference]: Finished difference Result 27786 states and 38784 transitions. [2024-11-19 15:03:13,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27786 states and 38784 transitions. [2024-11-19 15:03:13,316 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27532 [2024-11-19 15:03:13,385 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27786 states to 27786 states and 38784 transitions. [2024-11-19 15:03:13,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27786 [2024-11-19 15:03:13,406 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27786 [2024-11-19 15:03:13,406 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27786 states and 38784 transitions. [2024-11-19 15:03:13,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:13,430 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27786 states and 38784 transitions. [2024-11-19 15:03:13,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27786 states and 38784 transitions. [2024-11-19 15:03:13,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27786 to 27658. [2024-11-19 15:03:13,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27658 states, 27658 states have (on average 1.3976426350423024) internal successors, (38656), 27657 states have internal predecessors, (38656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:13,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27658 states to 27658 states and 38656 transitions. [2024-11-19 15:03:13,996 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27658 states and 38656 transitions. [2024-11-19 15:03:13,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:03:13,997 INFO L425 stractBuchiCegarLoop]: Abstraction has 27658 states and 38656 transitions. [2024-11-19 15:03:13,997 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-19 15:03:13,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27658 states and 38656 transitions. [2024-11-19 15:03:14,056 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27404 [2024-11-19 15:03:14,057 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:14,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:14,058 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:14,058 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:14,059 INFO L745 eck$LassoCheckResult]: Stem: 732576#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 732577#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 733222#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 733223#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 733316#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 732721#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 732722#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 732852#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 732853#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 732620#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 732412#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 732413#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 732581#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 732582#L781 assume !(0 == ~M_E~0); 733121#L781-2 assume !(0 == ~T1_E~0); 733339#L786-1 assume !(0 == ~T2_E~0); 732375#L791-1 assume !(0 == ~T3_E~0); 732376#L796-1 assume !(0 == ~T4_E~0); 732936#L801-1 assume !(0 == ~T5_E~0); 732937#L806-1 assume !(0 == ~T6_E~0); 732974#L811-1 assume !(0 == ~T7_E~0); 732587#L816-1 assume !(0 == ~E_M~0); 732588#L821-1 assume !(0 == ~E_1~0); 732403#L826-1 assume !(0 == ~E_2~0); 732404#L831-1 assume !(0 == ~E_3~0); 732716#L836-1 assume !(0 == ~E_4~0); 732717#L841-1 assume !(0 == ~E_5~0); 732540#L846-1 assume !(0 == ~E_6~0); 732541#L851-1 assume !(0 == ~E_7~0); 732563#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 732564#L388 assume !(1 == ~m_pc~0); 732557#L388-2 is_master_triggered_~__retres1~0#1 := 0; 732558#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 733091#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 732418#L967 assume !(0 != activate_threads_~tmp~1#1); 732419#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 732349#L407 assume !(1 == ~t1_pc~0); 732350#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 732356#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 732357#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 732391#L975 assume !(0 != activate_threads_~tmp___0~0#1); 733219#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 732677#L426 assume !(1 == ~t2_pc~0); 732678#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 733252#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 732698#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 732699#L983 assume !(0 != activate_threads_~tmp___1~0#1); 733304#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 732763#L445 assume !(1 == ~t3_pc~0); 732764#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 733133#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 732347#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 732348#L991 assume !(0 != activate_threads_~tmp___2~0#1); 733049#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 733007#L464 assume !(1 == ~t4_pc~0); 732570#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 732438#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 732439#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 732452#L999 assume !(0 != activate_threads_~tmp___3~0#1); 732743#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 732744#L483 assume !(1 == ~t5_pc~0); 733002#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 733193#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 733156#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 733157#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 732662#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 732663#L502 assume !(1 == ~t6_pc~0); 732518#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 732477#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 732478#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 732687#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 732895#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 733169#L521 assume !(1 == ~t7_pc~0); 733216#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 732414#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 732415#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 733207#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 733176#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 733082#L869 assume !(1 == ~M_E~0); 732737#L869-2 assume !(1 == ~T1_E~0); 732738#L874-1 assume !(1 == ~T2_E~0); 733271#L879-1 assume !(1 == ~T3_E~0); 732814#L884-1 assume !(1 == ~T4_E~0); 732335#L889-1 assume !(1 == ~T5_E~0); 732336#L894-1 assume !(1 == ~T6_E~0); 732597#L899-1 assume !(1 == ~T7_E~0); 733036#L904-1 assume !(1 == ~E_M~0); 732760#L909-1 assume !(1 == ~E_1~0); 732761#L914-1 assume !(1 == ~E_2~0); 732958#L919-1 assume !(1 == ~E_3~0); 732676#L924-1 assume !(1 == ~E_4~0); 732511#L929-1 assume !(1 == ~E_5~0); 732512#L934-1 assume !(1 == ~E_6~0); 732741#L939-1 assume !(1 == ~E_7~0); 732742#L944-1 assume { :end_inline_reset_delta_events } true; 733168#L1190-2 [2024-11-19 15:03:14,059 INFO L747 eck$LassoCheckResult]: Loop: 733168#L1190-2 assume !false; 744408#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 744407#L756-1 assume !false; 744406#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 744405#L596 assume !(0 == ~m_st~0); 744401#L600 assume !(0 == ~t1_st~0); 744402#L604 assume !(0 == ~t2_st~0); 744404#L608 assume !(0 == ~t3_st~0); 744399#L612 assume !(0 == ~t4_st~0); 744400#L616 assume !(0 == ~t5_st~0); 744403#L620 assume !(0 == ~t6_st~0); 744397#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 744398#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 742880#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 742881#L653 assume !(0 != eval_~tmp~0#1); 746462#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 746461#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 746460#L781-3 assume !(0 == ~M_E~0); 746459#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 746458#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 746457#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 746456#L796-3 assume !(0 == ~T4_E~0); 746455#L801-3 assume !(0 == ~T5_E~0); 746454#L806-3 assume !(0 == ~T6_E~0); 746453#L811-3 assume !(0 == ~T7_E~0); 746452#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 746451#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 746450#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 746449#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 746448#L836-3 assume !(0 == ~E_4~0); 746447#L841-3 assume !(0 == ~E_5~0); 746446#L846-3 assume !(0 == ~E_6~0); 746445#L851-3 assume !(0 == ~E_7~0); 746444#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 746443#L388-27 assume 1 == ~m_pc~0; 746442#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 746440#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 746439#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 746438#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 746437#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 746436#L407-27 assume !(1 == ~t1_pc~0); 746435#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 746434#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 746433#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 746432#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 746431#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 746430#L426-27 assume !(1 == ~t2_pc~0); 746429#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 746427#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 746426#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 746425#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 746424#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 746423#L445-27 assume !(1 == ~t3_pc~0); 746422#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 746421#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 746420#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 746419#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 746418#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 746417#L464-27 assume !(1 == ~t4_pc~0); 746415#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 746414#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 746413#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 746412#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 746411#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 746410#L483-27 assume !(1 == ~t5_pc~0); 746409#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 746408#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 746407#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 746406#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 746405#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 746404#L502-27 assume !(1 == ~t6_pc~0); 746403#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 746402#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 746401#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 746400#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 746399#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 746398#L521-27 assume !(1 == ~t7_pc~0); 746397#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 746395#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 746393#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 746391#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 746389#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 746388#L869-3 assume !(1 == ~M_E~0); 745528#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 746387#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 746386#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 746385#L884-3 assume !(1 == ~T4_E~0); 746384#L889-3 assume !(1 == ~T5_E~0); 746383#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 746382#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 746381#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 746380#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 746379#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 746378#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 746377#L924-3 assume !(1 == ~E_4~0); 746376#L929-3 assume !(1 == ~E_5~0); 746375#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 746374#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 746373#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 746369#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 746341#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 733598#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 733599#L1209 assume !(0 == start_simulation_~tmp~3#1); 745266#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 744866#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 744556#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 744423#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 744421#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 744417#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 744415#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 744413#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 733168#L1190-2 [2024-11-19 15:03:14,059 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:14,059 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 4 times [2024-11-19 15:03:14,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:14,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260965551] [2024-11-19 15:03:14,060 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 15:03:14,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:14,070 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 15:03:14,070 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:03:14,070 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:14,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:14,089 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:14,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:14,090 INFO L85 PathProgramCache]: Analyzing trace with hash -643556747, now seen corresponding path program 1 times [2024-11-19 15:03:14,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:14,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254622219] [2024-11-19 15:03:14,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:14,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:14,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:14,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:14,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:14,128 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254622219] [2024-11-19 15:03:14,128 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254622219] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:14,128 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:14,128 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:03:14,128 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909904533] [2024-11-19 15:03:14,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:14,129 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:14,129 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:14,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:03:14,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:03:14,130 INFO L87 Difference]: Start difference. First operand 27658 states and 38656 transitions. cyclomatic complexity: 11014 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:14,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:14,240 INFO L93 Difference]: Finished difference Result 27818 states and 38816 transitions. [2024-11-19 15:03:14,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27818 states and 38816 transitions. [2024-11-19 15:03:14,335 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27564 [2024-11-19 15:03:14,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27818 states to 27818 states and 38816 transitions. [2024-11-19 15:03:14,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27818 [2024-11-19 15:03:14,420 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27818 [2024-11-19 15:03:14,420 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27818 states and 38816 transitions. [2024-11-19 15:03:14,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:14,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27818 states and 38816 transitions. [2024-11-19 15:03:14,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27818 states and 38816 transitions. [2024-11-19 15:03:14,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27818 to 27754. [2024-11-19 15:03:14,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27754 states, 27754 states have (on average 1.3962672047272464) internal successors, (38752), 27753 states have internal predecessors, (38752), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:14,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27754 states to 27754 states and 38752 transitions. [2024-11-19 15:03:14,687 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27754 states and 38752 transitions. [2024-11-19 15:03:14,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:03:14,688 INFO L425 stractBuchiCegarLoop]: Abstraction has 27754 states and 38752 transitions. [2024-11-19 15:03:14,688 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-19 15:03:14,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27754 states and 38752 transitions. [2024-11-19 15:03:14,754 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27500 [2024-11-19 15:03:14,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:14,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:14,759 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:14,759 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:14,759 INFO L745 eck$LassoCheckResult]: Stem: 788064#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 788065#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 788736#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 788737#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 788856#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 788210#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 788211#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 788358#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 788359#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 788111#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 787894#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 787895#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 788070#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 788071#L781 assume !(0 == ~M_E~0); 788634#L781-2 assume !(0 == ~T1_E~0); 788884#L786-1 assume !(0 == ~T2_E~0); 787855#L791-1 assume !(0 == ~T3_E~0); 787856#L796-1 assume !(0 == ~T4_E~0); 788439#L801-1 assume !(0 == ~T5_E~0); 788440#L806-1 assume !(0 == ~T6_E~0); 788479#L811-1 assume !(0 == ~T7_E~0); 788076#L816-1 assume !(0 == ~E_M~0); 788077#L821-1 assume !(0 == ~E_1~0); 787886#L826-1 assume !(0 == ~E_2~0); 787887#L831-1 assume !(0 == ~E_3~0); 788205#L836-1 assume !(0 == ~E_4~0); 788206#L841-1 assume !(0 == ~E_5~0); 788027#L846-1 assume !(0 == ~E_6~0); 788028#L851-1 assume !(0 == ~E_7~0); 788050#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 788051#L388 assume !(1 == ~m_pc~0); 788044#L388-2 is_master_triggered_~__retres1~0#1 := 0; 788045#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 788605#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 787900#L967 assume !(0 != activate_threads_~tmp~1#1); 787901#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 787833#L407 assume !(1 == ~t1_pc~0); 787834#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 787840#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 787841#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 787872#L975 assume !(0 != activate_threads_~tmp___0~0#1); 788733#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 788165#L426 assume !(1 == ~t2_pc~0); 788166#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 788776#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 788187#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 788188#L983 assume !(0 != activate_threads_~tmp___1~0#1); 788839#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 788261#L445 assume !(1 == ~t3_pc~0); 788262#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 788643#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 787831#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 787832#L991 assume !(0 != activate_threads_~tmp___2~0#1); 788553#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 788512#L464 assume !(1 == ~t4_pc~0); 788054#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 787920#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 787921#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 787934#L999 assume !(0 != activate_threads_~tmp___3~0#1); 788236#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 788237#L483 assume !(1 == ~t5_pc~0); 788508#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 788706#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 788668#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 788669#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 788148#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 788149#L502 assume !(1 == ~t6_pc~0); 788004#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 787961#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 787962#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 788176#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 788399#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 788681#L521 assume !(1 == ~t7_pc~0); 788728#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 787896#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 787897#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 788721#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 788685#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 788594#L869 assume !(1 == ~M_E~0); 788228#L869-2 assume !(1 == ~T1_E~0); 788229#L874-1 assume !(1 == ~T2_E~0); 788797#L879-1 assume !(1 == ~T3_E~0); 788316#L884-1 assume !(1 == ~T4_E~0); 787819#L889-1 assume !(1 == ~T5_E~0); 787820#L894-1 assume !(1 == ~T6_E~0); 788087#L899-1 assume !(1 == ~T7_E~0); 788540#L904-1 assume !(1 == ~E_M~0); 788257#L909-1 assume !(1 == ~E_1~0); 788258#L914-1 assume !(1 == ~E_2~0); 788464#L919-1 assume !(1 == ~E_3~0); 788164#L924-1 assume !(1 == ~E_4~0); 787996#L929-1 assume !(1 == ~E_5~0); 787997#L934-1 assume !(1 == ~E_6~0); 788234#L939-1 assume !(1 == ~E_7~0); 788235#L944-1 assume { :end_inline_reset_delta_events } true; 788680#L1190-2 [2024-11-19 15:03:14,760 INFO L747 eck$LassoCheckResult]: Loop: 788680#L1190-2 assume !false; 801325#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 801320#L756-1 assume !false; 801316#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 801239#L596 assume !(0 == ~m_st~0); 801235#L600 assume !(0 == ~t1_st~0); 801236#L604 assume !(0 == ~t2_st~0); 801238#L608 assume !(0 == ~t3_st~0); 801233#L612 assume !(0 == ~t4_st~0); 801234#L616 assume !(0 == ~t5_st~0); 801237#L620 assume !(0 == ~t6_st~0); 801231#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 801232#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 799926#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 799927#L653 assume !(0 != eval_~tmp~0#1); 802038#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 802037#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 802036#L781-3 assume !(0 == ~M_E~0); 802035#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 802034#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 802033#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 802032#L796-3 assume !(0 == ~T4_E~0); 802031#L801-3 assume !(0 == ~T5_E~0); 802030#L806-3 assume !(0 == ~T6_E~0); 802029#L811-3 assume !(0 == ~T7_E~0); 802028#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 802027#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 802026#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 802025#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 802024#L836-3 assume !(0 == ~E_4~0); 802023#L841-3 assume !(0 == ~E_5~0); 802022#L846-3 assume !(0 == ~E_6~0); 802021#L851-3 assume !(0 == ~E_7~0); 802020#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 802019#L388-27 assume !(1 == ~m_pc~0); 802017#L388-29 is_master_triggered_~__retres1~0#1 := 0; 802016#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 802015#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 802014#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 802013#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 802012#L407-27 assume !(1 == ~t1_pc~0); 802011#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 802010#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 802009#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 802008#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 802007#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 802006#L426-27 assume 1 == ~t2_pc~0; 802004#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 802003#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 802002#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 802001#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 802000#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 801999#L445-27 assume !(1 == ~t3_pc~0); 801998#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 801997#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 801996#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 801995#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 801994#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 801993#L464-27 assume !(1 == ~t4_pc~0); 801991#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 801990#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 801989#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 801988#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 801987#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 801986#L483-27 assume !(1 == ~t5_pc~0); 801985#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 801984#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 801983#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 801982#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 801981#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 801980#L502-27 assume !(1 == ~t6_pc~0); 801979#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 801978#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 801977#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 801976#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 801975#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 801974#L521-27 assume 1 == ~t7_pc~0; 801972#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 801970#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 801968#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 801966#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 801965#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 801964#L869-3 assume !(1 == ~M_E~0); 800255#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 801963#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 801962#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 801961#L884-3 assume !(1 == ~T4_E~0); 801960#L889-3 assume !(1 == ~T5_E~0); 801959#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 801958#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 801957#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 801956#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 801955#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 801954#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 801953#L924-3 assume !(1 == ~E_4~0); 801952#L929-3 assume !(1 == ~E_5~0); 801951#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 801950#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 801949#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 801945#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 801746#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 789148#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 789144#L1209 assume !(0 == start_simulation_~tmp~3#1); 789145#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 801448#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 801409#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 801368#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 801360#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 801351#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 801342#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 801337#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 788680#L1190-2 [2024-11-19 15:03:14,764 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:14,765 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 5 times [2024-11-19 15:03:14,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:14,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [490168394] [2024-11-19 15:03:14,765 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 15:03:14,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:14,772 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:03:14,773 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:03:14,773 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:14,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:14,792 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:14,793 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:14,793 INFO L85 PathProgramCache]: Analyzing trace with hash -321654604, now seen corresponding path program 1 times [2024-11-19 15:03:14,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:14,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935719406] [2024-11-19 15:03:14,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:14,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:14,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:14,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:14,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:14,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935719406] [2024-11-19 15:03:14,849 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1935719406] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:14,849 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:14,850 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:03:14,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126088889] [2024-11-19 15:03:14,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:14,850 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:14,850 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:14,850 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:03:14,850 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:03:14,851 INFO L87 Difference]: Start difference. First operand 27754 states and 38752 transitions. cyclomatic complexity: 11014 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:15,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:15,248 INFO L93 Difference]: Finished difference Result 28789 states and 39787 transitions. [2024-11-19 15:03:15,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28789 states and 39787 transitions. [2024-11-19 15:03:15,330 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28532 [2024-11-19 15:03:15,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28789 states to 28789 states and 39787 transitions. [2024-11-19 15:03:15,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28789 [2024-11-19 15:03:15,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28789 [2024-11-19 15:03:15,395 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28789 states and 39787 transitions. [2024-11-19 15:03:15,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:15,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28789 states and 39787 transitions. [2024-11-19 15:03:15,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28789 states and 39787 transitions. [2024-11-19 15:03:15,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28789 to 28789. [2024-11-19 15:03:15,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28789 states, 28789 states have (on average 1.382020910764528) internal successors, (39787), 28788 states have internal predecessors, (39787), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:15,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28789 states to 28789 states and 39787 transitions. [2024-11-19 15:03:15,619 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28789 states and 39787 transitions. [2024-11-19 15:03:15,620 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:03:15,620 INFO L425 stractBuchiCegarLoop]: Abstraction has 28789 states and 39787 transitions. [2024-11-19 15:03:15,620 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-19 15:03:15,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28789 states and 39787 transitions. [2024-11-19 15:03:15,683 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28532 [2024-11-19 15:03:15,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:15,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:15,684 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:15,684 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:15,684 INFO L745 eck$LassoCheckResult]: Stem: 844610#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 844611#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 845245#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 845246#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 845339#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 844759#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 844760#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 844890#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 844891#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 844656#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 844446#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 844447#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 844615#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 844616#L781 assume !(0 == ~M_E~0); 845150#L781-2 assume !(0 == ~T1_E~0); 845356#L786-1 assume !(0 == ~T2_E~0); 844406#L791-1 assume !(0 == ~T3_E~0); 844407#L796-1 assume !(0 == ~T4_E~0); 844967#L801-1 assume !(0 == ~T5_E~0); 844968#L806-1 assume !(0 == ~T6_E~0); 845008#L811-1 assume !(0 == ~T7_E~0); 844621#L816-1 assume !(0 == ~E_M~0); 844622#L821-1 assume !(0 == ~E_1~0); 844437#L826-1 assume !(0 == ~E_2~0); 844438#L831-1 assume !(0 == ~E_3~0); 844754#L836-1 assume !(0 == ~E_4~0); 844755#L841-1 assume !(0 == ~E_5~0); 844574#L846-1 assume !(0 == ~E_6~0); 844575#L851-1 assume !(0 == ~E_7~0); 844598#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 844599#L388 assume !(1 == ~m_pc~0); 844592#L388-2 is_master_triggered_~__retres1~0#1 := 0; 844593#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 845179#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 844452#L967 assume !(0 != activate_threads_~tmp~1#1); 844453#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 844384#L407 assume !(1 == ~t1_pc~0); 844385#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 844388#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 844389#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 844423#L975 assume !(0 != activate_threads_~tmp___0~0#1); 845241#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 844711#L426 assume !(1 == ~t2_pc~0); 844712#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 845270#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 844735#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 844736#L983 assume !(0 != activate_threads_~tmp___1~0#1); 845320#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 844802#L445 assume !(1 == ~t3_pc~0); 844803#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 845160#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 844382#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 844383#L991 assume !(0 != activate_threads_~tmp___2~0#1); 845080#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 845040#L464 assume !(1 == ~t4_pc~0); 844602#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 844472#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 844473#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 844484#L999 assume !(0 != activate_threads_~tmp___3~0#1); 844782#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 844783#L483 assume !(1 == ~t5_pc~0); 845037#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 845219#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 845183#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 845184#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 844695#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 844696#L502 assume !(1 == ~t6_pc~0); 844552#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 844512#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 844513#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 844722#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 844932#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 845196#L521 assume !(1 == ~t7_pc~0); 845238#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 844448#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 844449#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 845231#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 845201#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 845113#L869 assume !(1 == ~M_E~0); 844776#L869-2 assume !(1 == ~T1_E~0); 844777#L874-1 assume !(1 == ~T2_E~0); 845289#L879-1 assume !(1 == ~T3_E~0); 844851#L884-1 assume !(1 == ~T4_E~0); 844370#L889-1 assume !(1 == ~T5_E~0); 844371#L894-1 assume !(1 == ~T6_E~0); 844630#L899-1 assume !(1 == ~T7_E~0); 845066#L904-1 assume !(1 == ~E_M~0); 844799#L909-1 assume !(1 == ~E_1~0); 844800#L914-1 assume !(1 == ~E_2~0); 844991#L919-1 assume !(1 == ~E_3~0); 844710#L924-1 assume !(1 == ~E_4~0); 844545#L929-1 assume !(1 == ~E_5~0); 844546#L934-1 assume !(1 == ~E_6~0); 844778#L939-1 assume !(1 == ~E_7~0); 844779#L944-1 assume { :end_inline_reset_delta_events } true; 845195#L1190-2 [2024-11-19 15:03:15,684 INFO L747 eck$LassoCheckResult]: Loop: 845195#L1190-2 assume !false; 857679#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 857676#L756-1 assume !false; 857674#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 856731#L596 assume !(0 == ~m_st~0); 856727#L600 assume !(0 == ~t1_st~0); 856728#L604 assume !(0 == ~t2_st~0); 856730#L608 assume !(0 == ~t3_st~0); 856725#L612 assume !(0 == ~t4_st~0); 856726#L616 assume !(0 == ~t5_st~0); 856729#L620 assume !(0 == ~t6_st~0); 856723#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 856724#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 858105#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 858103#L653 assume !(0 != eval_~tmp~0#1); 858101#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 858099#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 858096#L781-3 assume !(0 == ~M_E~0); 858094#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 858092#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 858090#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 858088#L796-3 assume !(0 == ~T4_E~0); 858086#L801-3 assume !(0 == ~T5_E~0); 858084#L806-3 assume !(0 == ~T6_E~0); 858082#L811-3 assume !(0 == ~T7_E~0); 858080#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 858078#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 858076#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 858074#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 858072#L836-3 assume !(0 == ~E_4~0); 858070#L841-3 assume !(0 == ~E_5~0); 858068#L846-3 assume !(0 == ~E_6~0); 858066#L851-3 assume !(0 == ~E_7~0); 858064#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 858062#L388-27 assume 1 == ~m_pc~0; 858060#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 858061#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 858117#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 858049#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 858046#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 858044#L407-27 assume !(1 == ~t1_pc~0); 858043#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 858042#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 858040#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 858039#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 858038#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 858037#L426-27 assume !(1 == ~t2_pc~0); 858036#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 858034#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 858033#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 858032#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 858030#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 858028#L445-27 assume !(1 == ~t3_pc~0); 858026#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 858024#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 858022#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 858019#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 858017#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 858015#L464-27 assume !(1 == ~t4_pc~0); 858012#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 858010#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 858008#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 858006#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 858004#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 858002#L483-27 assume !(1 == ~t5_pc~0); 858000#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 857998#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 857995#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 857993#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 857991#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 857989#L502-27 assume !(1 == ~t6_pc~0); 857987#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 857985#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 857983#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 857981#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 857979#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 857977#L521-27 assume !(1 == ~t7_pc~0); 857973#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 857971#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 857969#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 857967#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 857964#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 857962#L869-3 assume !(1 == ~M_E~0); 857958#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 857956#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 857952#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 857950#L884-3 assume !(1 == ~T4_E~0); 857948#L889-3 assume !(1 == ~T5_E~0); 857946#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 857943#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 857941#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 857938#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 857936#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 857934#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 857932#L924-3 assume !(1 == ~E_4~0); 857930#L929-3 assume !(1 == ~E_5~0); 857928#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 857926#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 857924#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 857914#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 857908#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 857906#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 857905#L1209 assume !(0 == start_simulation_~tmp~3#1); 857903#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 857733#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 857726#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 857724#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 857722#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 857707#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 857700#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 857691#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 845195#L1190-2 [2024-11-19 15:03:15,685 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:15,685 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 6 times [2024-11-19 15:03:15,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:15,685 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72939117] [2024-11-19 15:03:15,685 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 15:03:15,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:15,696 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2024-11-19 15:03:15,696 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:03:15,696 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:15,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:15,710 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:15,710 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:15,710 INFO L85 PathProgramCache]: Analyzing trace with hash -643616329, now seen corresponding path program 1 times [2024-11-19 15:03:15,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:15,711 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509971748] [2024-11-19 15:03:15,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:15,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:15,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:15,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:15,757 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:15,757 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [509971748] [2024-11-19 15:03:15,757 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [509971748] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:15,757 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:15,757 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:03:15,757 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644968472] [2024-11-19 15:03:15,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:15,757 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:15,758 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:15,758 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:03:15,758 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:03:15,758 INFO L87 Difference]: Start difference. First operand 28789 states and 39787 transitions. cyclomatic complexity: 11014 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:16,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:16,068 INFO L93 Difference]: Finished difference Result 29824 states and 40822 transitions. [2024-11-19 15:03:16,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29824 states and 40822 transitions. [2024-11-19 15:03:16,172 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29564 [2024-11-19 15:03:16,243 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29824 states to 29824 states and 40822 transitions. [2024-11-19 15:03:16,244 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29824 [2024-11-19 15:03:16,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29824 [2024-11-19 15:03:16,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29824 states and 40822 transitions. [2024-11-19 15:03:16,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:16,281 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29824 states and 40822 transitions. [2024-11-19 15:03:16,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29824 states and 40822 transitions. [2024-11-19 15:03:16,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29824 to 29824. [2024-11-19 15:03:16,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29824 states, 29824 states have (on average 1.3687634120171674) internal successors, (40822), 29823 states have internal predecessors, (40822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:16,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29824 states to 29824 states and 40822 transitions. [2024-11-19 15:03:16,645 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29824 states and 40822 transitions. [2024-11-19 15:03:16,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:03:16,645 INFO L425 stractBuchiCegarLoop]: Abstraction has 29824 states and 40822 transitions. [2024-11-19 15:03:16,645 INFO L332 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-19 15:03:16,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29824 states and 40822 transitions. [2024-11-19 15:03:16,718 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29564 [2024-11-19 15:03:16,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:16,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:16,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:16,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:16,722 INFO L745 eck$LassoCheckResult]: Stem: 903229#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 903230#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 903849#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 903850#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 903933#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 903374#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 903375#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 903508#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 903509#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 903276#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 903066#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 903067#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 903235#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 903236#L781 assume !(0 == ~M_E~0); 903760#L781-2 assume !(0 == ~T1_E~0); 903955#L786-1 assume !(0 == ~T2_E~0); 903027#L791-1 assume !(0 == ~T3_E~0); 903028#L796-1 assume !(0 == ~T4_E~0); 903586#L801-1 assume !(0 == ~T5_E~0); 903587#L806-1 assume !(0 == ~T6_E~0); 903624#L811-1 assume !(0 == ~T7_E~0); 903241#L816-1 assume !(0 == ~E_M~0); 903242#L821-1 assume !(0 == ~E_1~0); 903058#L826-1 assume !(0 == ~E_2~0); 903059#L831-1 assume !(0 == ~E_3~0); 903369#L836-1 assume !(0 == ~E_4~0); 903370#L841-1 assume !(0 == ~E_5~0); 903194#L846-1 assume !(0 == ~E_6~0); 903195#L851-1 assume !(0 == ~E_7~0); 903217#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 903218#L388 assume !(1 == ~m_pc~0); 903211#L388-2 is_master_triggered_~__retres1~0#1 := 0; 903212#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 903780#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 903072#L967 assume !(0 != activate_threads_~tmp~1#1); 903073#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 903005#L407 assume !(1 == ~t1_pc~0); 903006#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 903009#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 903010#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 903044#L975 assume !(0 != activate_threads_~tmp___0~0#1); 903844#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 903330#L426 assume !(1 == ~t2_pc~0); 903331#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 903874#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 903965#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 903917#L983 assume !(0 != activate_threads_~tmp___1~0#1); 903918#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 903420#L445 assume !(1 == ~t3_pc~0); 903421#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 903770#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 903003#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 903004#L991 assume !(0 != activate_threads_~tmp___2~0#1); 903689#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 903654#L464 assume !(1 == ~t4_pc~0); 903221#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 903092#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 903093#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 903104#L999 assume !(0 != activate_threads_~tmp___3~0#1); 903397#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 903398#L483 assume !(1 == ~t5_pc~0); 903650#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 903822#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 903785#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 903786#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 903313#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 903314#L502 assume !(1 == ~t6_pc~0); 903172#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 903131#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 903132#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 903338#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 903548#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 903797#L521 assume !(1 == ~t7_pc~0); 903841#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 903068#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 903069#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 903834#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 903806#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 903722#L869 assume !(1 == ~M_E~0); 903391#L869-2 assume !(1 == ~T1_E~0); 903392#L874-1 assume !(1 == ~T2_E~0); 903886#L879-1 assume !(1 == ~T3_E~0); 903471#L884-1 assume !(1 == ~T4_E~0); 902991#L889-1 assume !(1 == ~T5_E~0); 902992#L894-1 assume !(1 == ~T6_E~0); 903250#L899-1 assume !(1 == ~T7_E~0); 903676#L904-1 assume !(1 == ~E_M~0); 903417#L909-1 assume !(1 == ~E_1~0); 903418#L914-1 assume !(1 == ~E_2~0); 903608#L919-1 assume !(1 == ~E_3~0); 903329#L924-1 assume !(1 == ~E_4~0); 903165#L929-1 assume !(1 == ~E_5~0); 903166#L934-1 assume !(1 == ~E_6~0); 903393#L939-1 assume !(1 == ~E_7~0); 903394#L944-1 assume { :end_inline_reset_delta_events } true; 903796#L1190-2 [2024-11-19 15:03:16,722 INFO L747 eck$LassoCheckResult]: Loop: 903796#L1190-2 assume !false; 917727#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 917725#L756-1 assume !false; 917723#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 917720#L596 assume !(0 == ~m_st~0); 917718#L600 assume !(0 == ~t1_st~0); 917716#L604 assume !(0 == ~t2_st~0); 917714#L608 assume !(0 == ~t3_st~0); 917712#L612 assume !(0 == ~t4_st~0); 917709#L616 assume !(0 == ~t5_st~0); 917707#L620 assume !(0 == ~t6_st~0); 917704#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 917702#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 917700#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 917697#L653 assume !(0 != eval_~tmp~0#1); 917695#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 917693#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 917691#L781-3 assume !(0 == ~M_E~0); 917689#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 917687#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 917685#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 917683#L796-3 assume !(0 == ~T4_E~0); 917680#L801-3 assume !(0 == ~T5_E~0); 917678#L806-3 assume !(0 == ~T6_E~0); 917676#L811-3 assume !(0 == ~T7_E~0); 917674#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 917672#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 917668#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 917666#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 917664#L836-3 assume !(0 == ~E_4~0); 917662#L841-3 assume !(0 == ~E_5~0); 917659#L846-3 assume !(0 == ~E_6~0); 917657#L851-3 assume !(0 == ~E_7~0); 917654#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 917652#L388-27 assume 1 == ~m_pc~0; 917650#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 917651#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 917756#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 917641#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 917639#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 917637#L407-27 assume !(1 == ~t1_pc~0); 917635#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 917633#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 917560#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 917555#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 917549#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 917544#L426-27 assume 1 == ~t2_pc~0; 917538#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 917529#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 917516#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 917510#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 917504#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 917497#L445-27 assume !(1 == ~t3_pc~0); 917489#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 917482#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 917475#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 917467#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 917460#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 917453#L464-27 assume !(1 == ~t4_pc~0); 917444#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 917438#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 917433#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 917389#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 917386#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 917384#L483-27 assume !(1 == ~t5_pc~0); 917382#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 917380#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 917378#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 917376#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 917374#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 917372#L502-27 assume !(1 == ~t6_pc~0); 917369#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 917367#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 917365#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 917363#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 917361#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 917359#L521-27 assume !(1 == ~t7_pc~0); 917357#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 917405#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 917397#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 917343#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 917340#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 917338#L869-3 assume !(1 == ~M_E~0); 915482#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 917335#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 917333#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 917330#L884-3 assume !(1 == ~T4_E~0); 917328#L889-3 assume !(1 == ~T5_E~0); 917326#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 917311#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 917303#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 917292#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 917282#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 917269#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 917257#L924-3 assume !(1 == ~E_4~0); 917249#L929-3 assume !(1 == ~E_5~0); 917246#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 917243#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 917242#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 917237#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 916137#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 916134#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 916129#L1209 assume !(0 == start_simulation_~tmp~3#1); 916130#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 925648#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 925634#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 925719#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 925624#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 925620#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 925618#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 925614#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 903796#L1190-2 [2024-11-19 15:03:16,723 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:16,723 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 7 times [2024-11-19 15:03:16,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:16,724 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966961706] [2024-11-19 15:03:16,724 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 15:03:16,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:16,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:16,744 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:16,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:16,777 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:16,778 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:16,778 INFO L85 PathProgramCache]: Analyzing trace with hash -1021259146, now seen corresponding path program 1 times [2024-11-19 15:03:16,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:16,778 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036619552] [2024-11-19 15:03:16,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:16,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:16,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:16,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:16,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:16,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036619552] [2024-11-19 15:03:16,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036619552] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:16,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:16,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:03:16,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2003976467] [2024-11-19 15:03:16,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:16,898 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:16,898 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:16,898 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:03:16,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:03:16,899 INFO L87 Difference]: Start difference. First operand 29824 states and 40822 transitions. cyclomatic complexity: 11014 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:17,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:17,141 INFO L93 Difference]: Finished difference Result 30376 states and 41213 transitions. [2024-11-19 15:03:17,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30376 states and 41213 transitions. [2024-11-19 15:03:17,243 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30116 [2024-11-19 15:03:17,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30376 states to 30376 states and 41213 transitions. [2024-11-19 15:03:17,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30376 [2024-11-19 15:03:17,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30376 [2024-11-19 15:03:17,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30376 states and 41213 transitions. [2024-11-19 15:03:17,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:17,348 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30376 states and 41213 transitions. [2024-11-19 15:03:17,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30376 states and 41213 transitions. [2024-11-19 15:03:17,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30376 to 30376. [2024-11-19 15:03:17,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30376 states, 30376 states have (on average 1.356761917303134) internal successors, (41213), 30375 states have internal predecessors, (41213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:17,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30376 states to 30376 states and 41213 transitions. [2024-11-19 15:03:17,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30376 states and 41213 transitions. [2024-11-19 15:03:17,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:03:17,599 INFO L425 stractBuchiCegarLoop]: Abstraction has 30376 states and 41213 transitions. [2024-11-19 15:03:17,599 INFO L332 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-19 15:03:17,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30376 states and 41213 transitions. [2024-11-19 15:03:17,673 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30116 [2024-11-19 15:03:17,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:17,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:17,674 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:17,674 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:17,674 INFO L745 eck$LassoCheckResult]: Stem: 963440#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 963441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 964070#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 964071#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 964152#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 963583#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 963584#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 963715#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 963716#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 963486#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 963276#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 963277#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 963446#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 963447#L781 assume !(0 == ~M_E~0); 963974#L781-2 assume !(0 == ~T1_E~0); 964171#L786-1 assume !(0 == ~T2_E~0); 963236#L791-1 assume !(0 == ~T3_E~0); 963237#L796-1 assume !(0 == ~T4_E~0); 963797#L801-1 assume !(0 == ~T5_E~0); 963798#L806-1 assume !(0 == ~T6_E~0); 963835#L811-1 assume !(0 == ~T7_E~0); 963452#L816-1 assume !(0 == ~E_M~0); 963453#L821-1 assume !(0 == ~E_1~0); 963267#L826-1 assume !(0 == ~E_2~0); 963268#L831-1 assume !(0 == ~E_3~0); 963578#L836-1 assume !(0 == ~E_4~0); 963579#L841-1 assume !(0 == ~E_5~0); 963404#L846-1 assume !(0 == ~E_6~0); 963405#L851-1 assume !(0 == ~E_7~0); 963427#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 963428#L388 assume !(1 == ~m_pc~0); 963421#L388-2 is_master_triggered_~__retres1~0#1 := 0; 963422#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 964001#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 963282#L967 assume !(0 != activate_threads_~tmp~1#1); 963283#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 963213#L407 assume !(1 == ~t1_pc~0); 963214#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 963217#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 963218#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 963253#L975 assume !(0 != activate_threads_~tmp___0~0#1); 964066#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 963539#L426 assume !(1 == ~t2_pc~0); 963540#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 964095#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 964181#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 964137#L983 assume !(0 != activate_threads_~tmp___1~0#1); 964138#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 963628#L445 assume !(1 == ~t3_pc~0); 963629#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 963984#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 963211#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 963212#L991 assume !(0 != activate_threads_~tmp___2~0#1); 963902#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 963866#L464 assume !(1 == ~t4_pc~0); 963431#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 963302#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 963303#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 963314#L999 assume !(0 != activate_threads_~tmp___3~0#1); 963607#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 963608#L483 assume !(1 == ~t5_pc~0); 963863#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 964043#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 964006#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 964007#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 963523#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 963524#L502 assume !(1 == ~t6_pc~0); 963382#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 963341#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 963342#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 963547#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 963755#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 964021#L521 assume !(1 == ~t7_pc~0); 964062#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 963278#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 963279#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 964054#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 964027#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 963936#L869 assume !(1 == ~M_E~0); 963601#L869-2 assume !(1 == ~T1_E~0); 963602#L874-1 assume !(1 == ~T2_E~0); 964107#L879-1 assume !(1 == ~T3_E~0); 963678#L884-1 assume !(1 == ~T4_E~0); 963199#L889-1 assume !(1 == ~T5_E~0); 963200#L894-1 assume !(1 == ~T6_E~0); 963460#L899-1 assume !(1 == ~T7_E~0); 963888#L904-1 assume !(1 == ~E_M~0); 963625#L909-1 assume !(1 == ~E_1~0); 963626#L914-1 assume !(1 == ~E_2~0); 963820#L919-1 assume !(1 == ~E_3~0); 963538#L924-1 assume !(1 == ~E_4~0); 963375#L929-1 assume !(1 == ~E_5~0); 963376#L934-1 assume !(1 == ~E_6~0); 963603#L939-1 assume !(1 == ~E_7~0); 963604#L944-1 assume { :end_inline_reset_delta_events } true; 964020#L1190-2 [2024-11-19 15:03:17,674 INFO L747 eck$LassoCheckResult]: Loop: 964020#L1190-2 assume !false; 992738#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 992736#L756-1 assume !false; 964164#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 964155#L596 assume !(0 == ~m_st~0); 963349#L600 assume !(0 == ~t1_st~0); 963350#L604 assume !(0 == ~t2_st~0); 963294#L608 assume !(0 == ~t3_st~0); 963296#L612 assume !(0 == ~t4_st~0); 963572#L616 assume !(0 == ~t5_st~0); 963864#L620 assume !(0 == ~t6_st~0); 963799#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 963800#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 993149#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 993147#L653 assume !(0 != eval_~tmp~0#1); 993145#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 993143#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 993141#L781-3 assume !(0 == ~M_E~0); 993139#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 993138#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 993137#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 993136#L796-3 assume !(0 == ~T4_E~0); 993135#L801-3 assume !(0 == ~T5_E~0); 993133#L806-3 assume !(0 == ~T6_E~0); 993132#L811-3 assume !(0 == ~T7_E~0); 993129#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 993127#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 993125#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 993123#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 993121#L836-3 assume !(0 == ~E_4~0); 993119#L841-3 assume !(0 == ~E_5~0); 993117#L846-3 assume !(0 == ~E_6~0); 993115#L851-3 assume !(0 == ~E_7~0); 993113#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 993111#L388-27 assume 1 == ~m_pc~0; 993109#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 993110#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 993213#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 993100#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 993098#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 993096#L407-27 assume !(1 == ~t1_pc~0); 993094#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 993092#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 993090#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 993088#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 993087#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 993086#L426-27 assume 1 == ~t2_pc~0; 993085#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 993083#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 993081#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 993078#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 993076#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 993074#L445-27 assume !(1 == ~t3_pc~0); 993072#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 993070#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 993068#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 993066#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 993064#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 993062#L464-27 assume !(1 == ~t4_pc~0); 993059#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 993057#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 993055#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 993053#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 993049#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 993047#L483-27 assume !(1 == ~t5_pc~0); 993045#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 993043#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 993040#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 993038#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 993036#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 993035#L502-27 assume !(1 == ~t6_pc~0); 993033#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 993031#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 993029#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 993027#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 993025#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 993023#L521-27 assume 1 == ~t7_pc~0; 993021#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 993019#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 993017#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 993010#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 993008#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 993006#L869-3 assume !(1 == ~M_E~0); 991852#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 993002#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 993000#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 992998#L884-3 assume !(1 == ~T4_E~0); 992996#L889-3 assume !(1 == ~T5_E~0); 992994#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 992992#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 992990#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 992988#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 992984#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 992982#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 992980#L924-3 assume !(1 == ~E_4~0); 992978#L929-3 assume !(1 == ~E_5~0); 992975#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 992973#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 992971#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 964050#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 963220#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 963512#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 963513#L1209 assume !(0 == start_simulation_~tmp~3#1); 991556#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 992874#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 992869#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 992868#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 992864#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 992861#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 992859#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 992857#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 964020#L1190-2 [2024-11-19 15:03:17,675 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:17,675 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 8 times [2024-11-19 15:03:17,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:17,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780675480] [2024-11-19 15:03:17,675 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:03:17,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:17,682 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:03:17,682 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:03:17,683 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:17,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:17,697 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:17,698 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:17,698 INFO L85 PathProgramCache]: Analyzing trace with hash -1387522699, now seen corresponding path program 1 times [2024-11-19 15:03:17,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:17,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801391676] [2024-11-19 15:03:17,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:17,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:17,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:17,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:17,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:17,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801391676] [2024-11-19 15:03:17,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801391676] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:17,909 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:17,909 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:03:17,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275237381] [2024-11-19 15:03:17,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:17,909 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:17,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:17,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:03:17,910 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:03:17,910 INFO L87 Difference]: Start difference. First operand 30376 states and 41213 transitions. cyclomatic complexity: 10853 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:18,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:18,112 INFO L93 Difference]: Finished difference Result 30448 states and 40964 transitions. [2024-11-19 15:03:18,112 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30448 states and 40964 transitions. [2024-11-19 15:03:18,225 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30188 [2024-11-19 15:03:18,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30448 states to 30448 states and 40964 transitions. [2024-11-19 15:03:18,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30448 [2024-11-19 15:03:18,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30448 [2024-11-19 15:03:18,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30448 states and 40964 transitions. [2024-11-19 15:03:18,339 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:18,339 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30448 states and 40964 transitions. [2024-11-19 15:03:18,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30448 states and 40964 transitions. [2024-11-19 15:03:18,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30448 to 30448. [2024-11-19 15:03:18,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30448 states, 30448 states have (on average 1.3453757225433527) internal successors, (40964), 30447 states have internal predecessors, (40964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:18,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30448 states to 30448 states and 40964 transitions. [2024-11-19 15:03:18,673 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30448 states and 40964 transitions. [2024-11-19 15:03:18,674 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:03:18,674 INFO L425 stractBuchiCegarLoop]: Abstraction has 30448 states and 40964 transitions. [2024-11-19 15:03:18,674 INFO L332 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-19 15:03:18,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30448 states and 40964 transitions. [2024-11-19 15:03:18,763 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30188 [2024-11-19 15:03:18,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:18,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:18,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:18,765 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:18,765 INFO L745 eck$LassoCheckResult]: Stem: 1024272#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1024273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1024898#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1024899#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1024991#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1024419#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1024420#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1024551#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1024552#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1024317#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1024108#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1024109#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1024277#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1024278#L781 assume !(0 == ~M_E~0); 1024804#L781-2 assume !(0 == ~T1_E~0); 1025013#L786-1 assume !(0 == ~T2_E~0); 1024068#L791-1 assume !(0 == ~T3_E~0); 1024069#L796-1 assume !(0 == ~T4_E~0); 1024625#L801-1 assume !(0 == ~T5_E~0); 1024626#L806-1 assume !(0 == ~T6_E~0); 1024662#L811-1 assume !(0 == ~T7_E~0); 1024283#L816-1 assume !(0 == ~E_M~0); 1024284#L821-1 assume !(0 == ~E_1~0); 1024099#L826-1 assume !(0 == ~E_2~0); 1024100#L831-1 assume !(0 == ~E_3~0); 1024414#L836-1 assume !(0 == ~E_4~0); 1024415#L841-1 assume !(0 == ~E_5~0); 1024236#L846-1 assume !(0 == ~E_6~0); 1024237#L851-1 assume !(0 == ~E_7~0); 1024259#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1024260#L388 assume !(1 == ~m_pc~0); 1024253#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1024254#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1024829#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1024114#L967 assume !(0 != activate_threads_~tmp~1#1); 1024115#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1024045#L407 assume !(1 == ~t1_pc~0); 1024046#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1024049#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1024050#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1024085#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1024894#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1024371#L426 assume !(1 == ~t2_pc~0); 1024372#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1024927#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1025027#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1024975#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1024976#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1024462#L445 assume !(1 == ~t3_pc~0); 1024463#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1024813#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1024043#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1024044#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1024735#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1024697#L464 assume !(1 == ~t4_pc~0); 1024263#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1024134#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1024135#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1024146#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1024442#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1024443#L483 assume !(1 == ~t5_pc~0); 1024694#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1024871#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1024833#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1024834#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1024354#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1024355#L502 assume !(1 == ~t6_pc~0); 1024214#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1024173#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1024174#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1024381#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1024589#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1024845#L521 assume !(1 == ~t7_pc~0); 1024890#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1024110#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1024111#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1024882#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1024851#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1024765#L869 assume !(1 == ~M_E~0); 1024436#L869-2 assume !(1 == ~T1_E~0); 1024437#L874-1 assume !(1 == ~T2_E~0); 1024940#L879-1 assume !(1 == ~T3_E~0); 1024513#L884-1 assume !(1 == ~T4_E~0); 1024031#L889-1 assume !(1 == ~T5_E~0); 1024032#L894-1 assume !(1 == ~T6_E~0); 1024291#L899-1 assume !(1 == ~T7_E~0); 1024719#L904-1 assume !(1 == ~E_M~0); 1024459#L909-1 assume !(1 == ~E_1~0); 1024460#L914-1 assume !(1 == ~E_2~0); 1024645#L919-1 assume !(1 == ~E_3~0); 1024370#L924-1 assume !(1 == ~E_4~0); 1024206#L929-1 assume !(1 == ~E_5~0); 1024207#L934-1 assume !(1 == ~E_6~0); 1024438#L939-1 assume !(1 == ~E_7~0); 1024439#L944-1 assume { :end_inline_reset_delta_events } true; 1024844#L1190-2 [2024-11-19 15:03:18,766 INFO L747 eck$LassoCheckResult]: Loop: 1024844#L1190-2 assume !false; 1030776#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1030774#L756-1 assume !false; 1030772#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1030770#L596 assume !(0 == ~m_st~0); 1030766#L600 assume !(0 == ~t1_st~0); 1030767#L604 assume !(0 == ~t2_st~0); 1030769#L608 assume !(0 == ~t3_st~0); 1030764#L612 assume !(0 == ~t4_st~0); 1030765#L616 assume !(0 == ~t5_st~0); 1030768#L620 assume !(0 == ~t6_st~0); 1030762#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1030763#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1030754#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1030755#L653 assume !(0 != eval_~tmp~0#1); 1031759#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1031755#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1031749#L781-3 assume !(0 == ~M_E~0); 1031744#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1031739#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1031734#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1031729#L796-3 assume !(0 == ~T4_E~0); 1031725#L801-3 assume !(0 == ~T5_E~0); 1031720#L806-3 assume !(0 == ~T6_E~0); 1031715#L811-3 assume !(0 == ~T7_E~0); 1031710#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1031704#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1031699#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1031695#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1031690#L836-3 assume !(0 == ~E_4~0); 1031685#L841-3 assume !(0 == ~E_5~0); 1031680#L846-3 assume !(0 == ~E_6~0); 1031675#L851-3 assume !(0 == ~E_7~0); 1031671#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1031667#L388-27 assume !(1 == ~m_pc~0); 1031662#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1031636#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1031628#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1031619#L967-27 assume !(0 != activate_threads_~tmp~1#1); 1031609#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1031603#L407-27 assume !(1 == ~t1_pc~0); 1031597#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1031591#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1031584#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1031577#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1031570#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1031564#L426-27 assume !(1 == ~t2_pc~0); 1031558#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1031551#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1031542#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1031534#L983-27 assume !(0 != activate_threads_~tmp___1~0#1); 1031526#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1031520#L445-27 assume !(1 == ~t3_pc~0); 1031515#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1031509#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1031503#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1031496#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1031490#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1031485#L464-27 assume !(1 == ~t4_pc~0); 1031478#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1031472#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1031467#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1031461#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 1031456#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1031451#L483-27 assume !(1 == ~t5_pc~0); 1031447#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1031443#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1031437#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1031430#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1031423#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1031416#L502-27 assume !(1 == ~t6_pc~0); 1031408#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1031403#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1031058#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1031055#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1031053#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1031051#L521-27 assume 1 == ~t7_pc~0; 1031049#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1031050#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1031062#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1031038#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1031036#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1031034#L869-3 assume !(1 == ~M_E~0); 1031029#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1031027#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1031026#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1031025#L884-3 assume !(1 == ~T4_E~0); 1031024#L889-3 assume !(1 == ~T5_E~0); 1031022#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1031021#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1031020#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1031016#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1031014#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1031012#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1031010#L924-3 assume !(1 == ~E_4~0); 1031007#L929-3 assume !(1 == ~E_5~0); 1031005#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1031003#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1031002#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1030859#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1030850#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1030845#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1030839#L1209 assume !(0 == start_simulation_~tmp~3#1); 1030834#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1030820#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1030811#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1030805#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1030800#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1030794#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1030790#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1030786#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1024844#L1190-2 [2024-11-19 15:03:18,766 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:18,766 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 9 times [2024-11-19 15:03:18,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:18,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349873488] [2024-11-19 15:03:18,767 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 15:03:18,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:18,776 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 15:03:18,777 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:03:18,777 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:18,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:18,805 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:18,806 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:18,806 INFO L85 PathProgramCache]: Analyzing trace with hash 1477787005, now seen corresponding path program 1 times [2024-11-19 15:03:18,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:18,806 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664284334] [2024-11-19 15:03:18,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:18,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:18,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:18,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:18,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:18,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664284334] [2024-11-19 15:03:18,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664284334] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:18,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:18,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:18,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280548816] [2024-11-19 15:03:18,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:18,837 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:18,837 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:18,838 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:18,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:18,838 INFO L87 Difference]: Start difference. First operand 30448 states and 40964 transitions. cyclomatic complexity: 10532 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:19,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:19,005 INFO L93 Difference]: Finished difference Result 57412 states and 76304 transitions. [2024-11-19 15:03:19,005 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57412 states and 76304 transitions. [2024-11-19 15:03:19,246 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 57000 [2024-11-19 15:03:19,622 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57412 states to 57412 states and 76304 transitions. [2024-11-19 15:03:19,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57412 [2024-11-19 15:03:19,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57412 [2024-11-19 15:03:19,647 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57412 states and 76304 transitions. [2024-11-19 15:03:19,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:19,663 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57412 states and 76304 transitions. [2024-11-19 15:03:19,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57412 states and 76304 transitions. [2024-11-19 15:03:19,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57412 to 54692. [2024-11-19 15:03:19,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54692 states, 54692 states have (on average 1.332699480728443) internal successors, (72888), 54691 states have internal predecessors, (72888), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:20,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54692 states to 54692 states and 72888 transitions. [2024-11-19 15:03:20,078 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54692 states and 72888 transitions. [2024-11-19 15:03:20,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:20,080 INFO L425 stractBuchiCegarLoop]: Abstraction has 54692 states and 72888 transitions. [2024-11-19 15:03:20,080 INFO L332 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2024-11-19 15:03:20,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54692 states and 72888 transitions. [2024-11-19 15:03:20,214 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54280 [2024-11-19 15:03:20,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:20,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:20,215 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:20,215 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:20,215 INFO L745 eck$LassoCheckResult]: Stem: 1112139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1112140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1112806#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1112807#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1112897#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1112288#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1112289#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1112425#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1112426#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1112185#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1111973#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1111974#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1112144#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1112145#L781 assume !(0 == ~M_E~0); 1112695#L781-2 assume !(0 == ~T1_E~0); 1112916#L786-1 assume !(0 == ~T2_E~0); 1111934#L791-1 assume !(0 == ~T3_E~0); 1111935#L796-1 assume !(0 == ~T4_E~0); 1112504#L801-1 assume !(0 == ~T5_E~0); 1112505#L806-1 assume !(0 == ~T6_E~0); 1112548#L811-1 assume !(0 == ~T7_E~0); 1112150#L816-1 assume !(0 == ~E_M~0); 1112151#L821-1 assume !(0 == ~E_1~0); 1111965#L826-1 assume !(0 == ~E_2~0); 1111966#L831-1 assume !(0 == ~E_3~0); 1112283#L836-1 assume !(0 == ~E_4~0); 1112284#L841-1 assume !(0 == ~E_5~0); 1112103#L846-1 assume !(0 == ~E_6~0); 1112104#L851-1 assume !(0 == ~E_7~0); 1112126#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1112127#L388 assume !(1 == ~m_pc~0); 1112120#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1112121#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1112724#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1111979#L967 assume !(0 != activate_threads_~tmp~1#1); 1111980#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1111911#L407 assume !(1 == ~t1_pc~0); 1111912#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1111915#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1111916#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1111951#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1112802#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1112239#L426 assume !(1 == ~t2_pc~0); 1112240#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1112835#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1112924#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1112882#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1112883#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1112333#L445 assume !(1 == ~t3_pc~0); 1112334#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1112703#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1111909#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1111910#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1112618#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1112579#L464 assume !(1 == ~t4_pc~0); 1112130#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1111999#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1112000#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1112011#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1112311#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1112312#L483 assume !(1 == ~t5_pc~0); 1112576#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1112776#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1112729#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1112730#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1112224#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1112225#L502 assume !(1 == ~t6_pc~0); 1112081#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1112038#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1112039#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1112250#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1112465#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1112746#L521 assume !(1 == ~t7_pc~0); 1112799#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1111975#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1111976#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1112790#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1112755#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1112652#L869 assume !(1 == ~M_E~0); 1112305#L869-2 assume !(1 == ~T1_E~0); 1112306#L874-1 assume !(1 == ~T2_E~0); 1112849#L879-1 assume !(1 == ~T3_E~0); 1112387#L884-1 assume !(1 == ~T4_E~0); 1111897#L889-1 assume !(1 == ~T5_E~0); 1111898#L894-1 assume !(1 == ~T6_E~0); 1112159#L899-1 assume !(1 == ~T7_E~0); 1112605#L904-1 assume !(1 == ~E_M~0); 1112330#L909-1 assume !(1 == ~E_1~0); 1112331#L914-1 assume !(1 == ~E_2~0); 1112528#L919-1 assume !(1 == ~E_3~0); 1112238#L924-1 assume !(1 == ~E_4~0); 1112072#L929-1 assume !(1 == ~E_5~0); 1112073#L934-1 assume !(1 == ~E_6~0); 1112307#L939-1 assume !(1 == ~E_7~0); 1112308#L944-1 assume { :end_inline_reset_delta_events } true; 1112745#L1190-2 [2024-11-19 15:03:20,216 INFO L747 eck$LassoCheckResult]: Loop: 1112745#L1190-2 assume !false; 1121329#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1121327#L756-1 assume !false; 1121325#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1121322#L596 assume !(0 == ~m_st~0); 1121323#L600 assume !(0 == ~t1_st~0); 1121791#L604 assume !(0 == ~t2_st~0); 1121789#L608 assume !(0 == ~t3_st~0); 1121787#L612 assume !(0 == ~t4_st~0); 1121785#L616 assume !(0 == ~t5_st~0); 1121783#L620 assume !(0 == ~t6_st~0); 1121780#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1121778#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1121776#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1121774#L653 assume !(0 != eval_~tmp~0#1); 1121772#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1121770#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1121768#L781-3 assume !(0 == ~M_E~0); 1121766#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1121764#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1121761#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1121759#L796-3 assume !(0 == ~T4_E~0); 1121757#L801-3 assume !(0 == ~T5_E~0); 1121754#L806-3 assume !(0 == ~T6_E~0); 1121753#L811-3 assume !(0 == ~T7_E~0); 1121749#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1121747#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1121745#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1121743#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1121738#L836-3 assume !(0 == ~E_4~0); 1121736#L841-3 assume !(0 == ~E_5~0); 1121734#L846-3 assume !(0 == ~E_6~0); 1121732#L851-3 assume !(0 == ~E_7~0); 1121730#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1121728#L388-27 assume 1 == ~m_pc~0; 1121725#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1121723#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1121719#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1121716#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1121714#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1121712#L407-27 assume !(1 == ~t1_pc~0); 1121709#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1121707#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1121705#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1121703#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1121701#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1121699#L426-27 assume 1 == ~t2_pc~0; 1121697#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1121698#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1122112#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1121687#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1121685#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1121683#L445-27 assume !(1 == ~t3_pc~0); 1121681#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1121679#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1121677#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1121675#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1121673#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1121671#L464-27 assume !(1 == ~t4_pc~0); 1121668#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1121666#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1121664#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1121662#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 1121660#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1121658#L483-27 assume !(1 == ~t5_pc~0); 1121656#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1121654#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1121650#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1121648#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1121646#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1121644#L502-27 assume !(1 == ~t6_pc~0); 1121641#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1121639#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1121636#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1121634#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1121632#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1121630#L521-27 assume !(1 == ~t7_pc~0); 1121626#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1121624#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1121622#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1121620#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1121617#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1121615#L869-3 assume !(1 == ~M_E~0); 1121611#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1121609#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1121607#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1121605#L884-3 assume !(1 == ~T4_E~0); 1121603#L889-3 assume !(1 == ~T5_E~0); 1121601#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1121600#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1121599#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1121597#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1121595#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1121593#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1121592#L924-3 assume !(1 == ~E_4~0); 1121590#L929-3 assume !(1 == ~E_5~0); 1121588#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1121586#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1121584#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1121581#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1121579#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1121578#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1121573#L1209 assume !(0 == start_simulation_~tmp~3#1); 1121570#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1121567#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1121565#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1121562#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1121560#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1121558#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1121556#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1121554#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1112745#L1190-2 [2024-11-19 15:03:20,216 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:20,216 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 10 times [2024-11-19 15:03:20,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:20,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679488433] [2024-11-19 15:03:20,217 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 15:03:20,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:20,226 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 15:03:20,226 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:03:20,227 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:20,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:20,240 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:20,240 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:20,240 INFO L85 PathProgramCache]: Analyzing trace with hash 350007546, now seen corresponding path program 1 times [2024-11-19 15:03:20,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:20,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714494165] [2024-11-19 15:03:20,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:20,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:20,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:20,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:20,292 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:20,292 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1714494165] [2024-11-19 15:03:20,292 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1714494165] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:20,292 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:20,292 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:03:20,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451993620] [2024-11-19 15:03:20,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:20,293 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:20,293 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:20,293 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:03:20,293 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:03:20,293 INFO L87 Difference]: Start difference. First operand 54692 states and 72888 transitions. cyclomatic complexity: 18212 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:20,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:20,565 INFO L93 Difference]: Finished difference Result 55364 states and 73143 transitions. [2024-11-19 15:03:20,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55364 states and 73143 transitions. [2024-11-19 15:03:21,099 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54952 [2024-11-19 15:03:21,213 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55364 states to 55364 states and 73143 transitions. [2024-11-19 15:03:21,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55364 [2024-11-19 15:03:21,256 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55364 [2024-11-19 15:03:21,257 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55364 states and 73143 transitions. [2024-11-19 15:03:21,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:21,281 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55364 states and 73143 transitions. [2024-11-19 15:03:21,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55364 states and 73143 transitions. [2024-11-19 15:03:21,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55364 to 55364. [2024-11-19 15:03:21,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55364 states, 55364 states have (on average 1.3211292536666426) internal successors, (73143), 55363 states have internal predecessors, (73143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:21,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55364 states to 55364 states and 73143 transitions. [2024-11-19 15:03:21,769 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55364 states and 73143 transitions. [2024-11-19 15:03:21,770 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:03:21,770 INFO L425 stractBuchiCegarLoop]: Abstraction has 55364 states and 73143 transitions. [2024-11-19 15:03:21,770 INFO L332 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2024-11-19 15:03:21,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55364 states and 73143 transitions. [2024-11-19 15:03:21,910 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54952 [2024-11-19 15:03:21,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:21,910 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:21,911 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:21,911 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:21,911 INFO L745 eck$LassoCheckResult]: Stem: 1222204#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1222205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1222872#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1222873#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1222975#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1222353#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1222354#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1222488#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1222489#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1222252#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1222038#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1222039#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1222211#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1222212#L781 assume !(0 == ~M_E~0); 1222761#L781-2 assume !(0 == ~T1_E~0); 1222997#L786-1 assume !(0 == ~T2_E~0); 1222001#L791-1 assume !(0 == ~T3_E~0); 1222002#L796-1 assume !(0 == ~T4_E~0); 1222573#L801-1 assume !(0 == ~T5_E~0); 1222574#L806-1 assume !(0 == ~T6_E~0); 1222609#L811-1 assume !(0 == ~T7_E~0); 1222215#L816-1 assume !(0 == ~E_M~0); 1222216#L821-1 assume !(0 == ~E_1~0); 1222029#L826-1 assume !(0 == ~E_2~0); 1222030#L831-1 assume !(0 == ~E_3~0); 1222348#L836-1 assume !(0 == ~E_4~0); 1222349#L841-1 assume !(0 == ~E_5~0); 1222167#L846-1 assume !(0 == ~E_6~0); 1222168#L851-1 assume !(0 == ~E_7~0); 1222191#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1222192#L388 assume !(1 == ~m_pc~0); 1222185#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1222186#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1222794#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1222044#L967 assume !(0 != activate_threads_~tmp~1#1); 1222045#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1221975#L407 assume !(1 == ~t1_pc~0); 1221976#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1221982#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1221983#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1222017#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1222867#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1222308#L426 assume !(1 == ~t2_pc~0); 1222309#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1222903#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1223006#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1222955#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1222956#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1222400#L445 assume !(1 == ~t3_pc~0); 1222401#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1222772#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1221973#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1221974#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1222681#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1222643#L464 assume !(1 == ~t4_pc~0); 1222197#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1222064#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1222065#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1222078#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1222378#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1222379#L483 assume !(1 == ~t5_pc~0); 1222640#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1222841#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1222799#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1222800#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1222294#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1222295#L502 assume !(1 == ~t6_pc~0); 1222145#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1222103#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1222104#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1222318#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1222530#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1222813#L521 assume !(1 == ~t7_pc~0); 1222860#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1222040#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1222041#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1222853#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1222819#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1222715#L869 assume !(1 == ~M_E~0); 1222372#L869-2 assume !(1 == ~T1_E~0); 1222373#L874-1 assume !(1 == ~T2_E~0); 1222923#L879-1 assume !(1 == ~T3_E~0); 1222449#L884-1 assume !(1 == ~T4_E~0); 1221961#L889-1 assume !(1 == ~T5_E~0); 1221962#L894-1 assume !(1 == ~T6_E~0); 1222227#L899-1 assume !(1 == ~T7_E~0); 1222669#L904-1 assume !(1 == ~E_M~0); 1222397#L909-1 assume !(1 == ~E_1~0); 1222398#L914-1 assume !(1 == ~E_2~0); 1222594#L919-1 assume !(1 == ~E_3~0); 1222307#L924-1 assume !(1 == ~E_4~0); 1222136#L929-1 assume !(1 == ~E_5~0); 1222137#L934-1 assume !(1 == ~E_6~0); 1222376#L939-1 assume !(1 == ~E_7~0); 1222377#L944-1 assume { :end_inline_reset_delta_events } true; 1222812#L1190-2 [2024-11-19 15:03:21,912 INFO L747 eck$LassoCheckResult]: Loop: 1222812#L1190-2 assume !false; 1232011#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1232009#L756-1 assume !false; 1232007#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1232004#L596 assume !(0 == ~m_st~0); 1232005#L600 assume !(0 == ~t1_st~0); 1232575#L604 assume !(0 == ~t2_st~0); 1232573#L608 assume !(0 == ~t3_st~0); 1232571#L612 assume !(0 == ~t4_st~0); 1232568#L616 assume !(0 == ~t5_st~0); 1232566#L620 assume !(0 == ~t6_st~0); 1232563#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1232561#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1232559#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1232557#L653 assume !(0 != eval_~tmp~0#1); 1232555#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1232553#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1232550#L781-3 assume !(0 == ~M_E~0); 1232548#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1232546#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1232544#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1232542#L796-3 assume !(0 == ~T4_E~0); 1232540#L801-3 assume !(0 == ~T5_E~0); 1232538#L806-3 assume !(0 == ~T6_E~0); 1232536#L811-3 assume !(0 == ~T7_E~0); 1232534#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1232532#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1232530#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1232528#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1232526#L836-3 assume !(0 == ~E_4~0); 1232524#L841-3 assume !(0 == ~E_5~0); 1232522#L846-3 assume !(0 == ~E_6~0); 1232520#L851-3 assume !(0 == ~E_7~0); 1232518#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1232516#L388-27 assume 1 == ~m_pc~0; 1232511#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1232509#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1232507#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1232504#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1232501#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1232499#L407-27 assume !(1 == ~t1_pc~0); 1232498#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1232497#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1232495#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1232494#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1232493#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1232492#L426-27 assume !(1 == ~t2_pc~0); 1232490#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1232488#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1232486#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1232485#L983-27 assume !(0 != activate_threads_~tmp___1~0#1); 1232483#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1232481#L445-27 assume !(1 == ~t3_pc~0); 1232480#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1232479#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1232478#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1232476#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1232474#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1232472#L464-27 assume !(1 == ~t4_pc~0); 1232470#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1232468#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1232466#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1232464#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 1232462#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1232460#L483-27 assume !(1 == ~t5_pc~0); 1232458#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1232457#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1232453#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1232451#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1232449#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1232447#L502-27 assume !(1 == ~t6_pc~0); 1232444#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1232442#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1232440#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1232438#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1232436#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1232434#L521-27 assume 1 == ~t7_pc~0; 1232432#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1232433#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1232496#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1232422#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1232420#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1232418#L869-3 assume !(1 == ~M_E~0); 1232414#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1232412#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1232410#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1232408#L884-3 assume !(1 == ~T4_E~0); 1232406#L889-3 assume !(1 == ~T5_E~0); 1232404#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1232402#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1232400#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1232398#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1232396#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1232394#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1232392#L924-3 assume !(1 == ~E_4~0); 1232390#L929-3 assume !(1 == ~E_5~0); 1232388#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1232384#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1232382#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1232379#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1232377#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1232374#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1232371#L1209 assume !(0 == start_simulation_~tmp~3#1); 1232368#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1232366#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1232364#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1232362#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1232361#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1232358#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1232354#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1232351#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1222812#L1190-2 [2024-11-19 15:03:21,912 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:21,912 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 11 times [2024-11-19 15:03:21,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:21,913 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145695250] [2024-11-19 15:03:21,913 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 15:03:21,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:21,919 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:03:21,920 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:03:21,920 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:21,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:21,934 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:21,935 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:21,935 INFO L85 PathProgramCache]: Analyzing trace with hash 38782780, now seen corresponding path program 1 times [2024-11-19 15:03:21,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:21,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875039205] [2024-11-19 15:03:21,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:21,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:21,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:21,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:21,976 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:21,976 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1875039205] [2024-11-19 15:03:21,976 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1875039205] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:21,976 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:21,976 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:03:21,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726361245] [2024-11-19 15:03:21,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:21,977 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:21,977 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:21,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:03:21,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:03:21,977 INFO L87 Difference]: Start difference. First operand 55364 states and 73143 transitions. cyclomatic complexity: 17795 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:22,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:22,600 INFO L93 Difference]: Finished difference Result 56420 states and 73894 transitions. [2024-11-19 15:03:22,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56420 states and 73894 transitions. [2024-11-19 15:03:22,828 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 56008 [2024-11-19 15:03:22,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56420 states to 56420 states and 73894 transitions. [2024-11-19 15:03:22,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56420 [2024-11-19 15:03:22,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56420 [2024-11-19 15:03:22,998 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56420 states and 73894 transitions. [2024-11-19 15:03:23,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:23,028 INFO L218 hiAutomatonCegarLoop]: Abstraction has 56420 states and 73894 transitions. [2024-11-19 15:03:23,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56420 states and 73894 transitions. [2024-11-19 15:03:23,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56420 to 56420. [2024-11-19 15:03:23,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56420 states, 56420 states have (on average 1.309712867777384) internal successors, (73894), 56419 states have internal predecessors, (73894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:23,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56420 states to 56420 states and 73894 transitions. [2024-11-19 15:03:23,496 INFO L240 hiAutomatonCegarLoop]: Abstraction has 56420 states and 73894 transitions. [2024-11-19 15:03:23,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:03:23,500 INFO L425 stractBuchiCegarLoop]: Abstraction has 56420 states and 73894 transitions. [2024-11-19 15:03:23,501 INFO L332 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2024-11-19 15:03:23,501 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56420 states and 73894 transitions. [2024-11-19 15:03:23,636 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 56008 [2024-11-19 15:03:23,637 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:23,637 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:23,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:23,638 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:23,641 INFO L745 eck$LassoCheckResult]: Stem: 1333995#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1333996#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1334646#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1334647#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1334740#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1334143#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1334144#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1334277#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1334278#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1334041#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1333829#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1333830#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1334001#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1334002#L781 assume !(0 == ~M_E~0); 1334541#L781-2 assume !(0 == ~T1_E~0); 1334769#L786-1 assume !(0 == ~T2_E~0); 1333792#L791-1 assume !(0 == ~T3_E~0); 1333793#L796-1 assume !(0 == ~T4_E~0); 1334361#L801-1 assume !(0 == ~T5_E~0); 1334362#L806-1 assume !(0 == ~T6_E~0); 1334398#L811-1 assume !(0 == ~T7_E~0); 1334007#L816-1 assume !(0 == ~E_M~0); 1334008#L821-1 assume !(0 == ~E_1~0); 1333820#L826-1 assume !(0 == ~E_2~0); 1333821#L831-1 assume !(0 == ~E_3~0); 1334138#L836-1 assume !(0 == ~E_4~0); 1334139#L841-1 assume !(0 == ~E_5~0); 1333959#L846-1 assume !(0 == ~E_6~0); 1333960#L851-1 assume !(0 == ~E_7~0); 1333983#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1333984#L388 assume !(1 == ~m_pc~0); 1333977#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1333978#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1334568#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1333835#L967 assume !(0 != activate_threads_~tmp~1#1); 1333836#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1333767#L407 assume !(1 == ~t1_pc~0); 1333768#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1333774#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1333775#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1333808#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1334641#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1334096#L426 assume !(1 == ~t2_pc~0); 1334097#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1334673#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1334778#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1334720#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1334721#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1334187#L445 assume !(1 == ~t3_pc~0); 1334188#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1334551#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1333765#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1333766#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1334467#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1334428#L464 assume !(1 == ~t4_pc~0); 1333989#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1333855#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1333856#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1333869#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1334167#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1334168#L483 assume !(1 == ~t5_pc~0); 1334425#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1334618#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1334573#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1334574#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1334081#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1334082#L502 assume !(1 == ~t6_pc~0); 1333936#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1333894#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1333895#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1334107#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1334320#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1334589#L521 assume !(1 == ~t7_pc~0); 1334638#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1333831#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1333832#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1334631#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1334597#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1334504#L869 assume !(1 == ~M_E~0); 1334161#L869-2 assume !(1 == ~T1_E~0); 1334162#L874-1 assume !(1 == ~T2_E~0); 1334689#L879-1 assume !(1 == ~T3_E~0); 1334239#L884-1 assume !(1 == ~T4_E~0); 1333753#L889-1 assume !(1 == ~T5_E~0); 1333754#L894-1 assume !(1 == ~T6_E~0); 1334017#L899-1 assume !(1 == ~T7_E~0); 1334455#L904-1 assume !(1 == ~E_M~0); 1334184#L909-1 assume !(1 == ~E_1~0); 1334185#L914-1 assume !(1 == ~E_2~0); 1334384#L919-1 assume !(1 == ~E_3~0); 1334095#L924-1 assume !(1 == ~E_4~0); 1333928#L929-1 assume !(1 == ~E_5~0); 1333929#L934-1 assume !(1 == ~E_6~0); 1334165#L939-1 assume !(1 == ~E_7~0); 1334166#L944-1 assume { :end_inline_reset_delta_events } true; 1334588#L1190-2 [2024-11-19 15:03:23,641 INFO L747 eck$LassoCheckResult]: Loop: 1334588#L1190-2 assume !false; 1348619#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1348620#L756-1 assume !false; 1348611#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1348612#L596 assume !(0 == ~m_st~0); 1344702#L600 assume !(0 == ~t1_st~0); 1344689#L604 assume !(0 == ~t2_st~0); 1344683#L608 assume !(0 == ~t3_st~0); 1344678#L612 assume !(0 == ~t4_st~0); 1344673#L616 assume !(0 == ~t5_st~0); 1344669#L620 assume !(0 == ~t6_st~0); 1344664#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1344650#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1344644#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1344637#L653 assume !(0 != eval_~tmp~0#1); 1344631#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1344627#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1344624#L781-3 assume !(0 == ~M_E~0); 1344620#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1344616#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1344613#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1344611#L796-3 assume !(0 == ~T4_E~0); 1344608#L801-3 assume !(0 == ~T5_E~0); 1344605#L806-3 assume !(0 == ~T6_E~0); 1344603#L811-3 assume !(0 == ~T7_E~0); 1344600#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1344597#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1344594#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1344591#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1344588#L836-3 assume !(0 == ~E_4~0); 1344584#L841-3 assume !(0 == ~E_5~0); 1344581#L846-3 assume !(0 == ~E_6~0); 1344578#L851-3 assume !(0 == ~E_7~0); 1344575#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1344571#L388-27 assume 1 == ~m_pc~0; 1344566#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1344562#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1344558#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1344554#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1344551#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1344549#L407-27 assume !(1 == ~t1_pc~0); 1344546#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1344543#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1344540#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1344535#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1344530#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1344526#L426-27 assume 1 == ~t2_pc~0; 1344521#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1344517#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1344512#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1344508#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1344505#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1344501#L445-27 assume !(1 == ~t3_pc~0); 1344498#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1344494#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1344492#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1344490#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1344486#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1344482#L464-27 assume !(1 == ~t4_pc~0); 1344477#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1344473#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1344467#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1344464#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 1344461#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1344458#L483-27 assume !(1 == ~t5_pc~0); 1344455#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1344451#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1344447#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1344442#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1344436#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1344431#L502-27 assume !(1 == ~t6_pc~0); 1344425#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1344420#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1344415#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1344410#L1015-27 assume !(0 != activate_threads_~tmp___5~0#1); 1344406#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1344402#L521-27 assume 1 == ~t7_pc~0; 1344397#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1344393#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1344389#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1344385#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1344380#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1344375#L869-3 assume !(1 == ~M_E~0); 1344285#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1344366#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1344359#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1344355#L884-3 assume !(1 == ~T4_E~0); 1344351#L889-3 assume !(1 == ~T5_E~0); 1344347#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1344343#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1344339#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1344335#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1344331#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1344327#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1344322#L924-3 assume !(1 == ~E_4~0); 1344317#L929-3 assume !(1 == ~E_5~0); 1344311#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1344305#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1344300#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1344294#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1344289#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1344283#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1344277#L1209 assume !(0 == start_simulation_~tmp~3#1); 1344278#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1353056#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1353054#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1353051#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1353049#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1353045#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1353043#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1353041#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1334588#L1190-2 [2024-11-19 15:03:23,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:23,642 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 12 times [2024-11-19 15:03:23,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:23,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514338143] [2024-11-19 15:03:23,642 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 15:03:23,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:23,649 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2024-11-19 15:03:23,649 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:03:23,649 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:23,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:23,663 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:23,664 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:23,664 INFO L85 PathProgramCache]: Analyzing trace with hash -1640903173, now seen corresponding path program 1 times [2024-11-19 15:03:23,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:23,664 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122279827] [2024-11-19 15:03:23,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:23,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:23,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:23,674 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:23,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:23,689 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:23,689 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:23,689 INFO L85 PathProgramCache]: Analyzing trace with hash 313368759, now seen corresponding path program 1 times [2024-11-19 15:03:23,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:23,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600851545] [2024-11-19 15:03:23,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:23,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:23,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:23,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:23,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:23,722 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600851545] [2024-11-19 15:03:23,722 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600851545] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:23,722 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:23,722 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:23,722 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1185158501] [2024-11-19 15:03:23,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:25,263 INFO L204 LassoAnalysis]: Preferences: [2024-11-19 15:03:25,263 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-19 15:03:25,263 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-19 15:03:25,263 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-19 15:03:25,263 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-19 15:03:25,264 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:25,264 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-19 15:03:25,264 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-19 15:03:25,264 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.07.cil-2.c_Iteration33_Loop [2024-11-19 15:03:25,264 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-19 15:03:25,264 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-19 15:03:25,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,296 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,298 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,299 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,302 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,305 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,309 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,311 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,314 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,315 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,318 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,323 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,325 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,327 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,329 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,337 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,343 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,345 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,347 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,353 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,355 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,356 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,364 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,365 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,373 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,385 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,392 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,395 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,404 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,411 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,413 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,421 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,423 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,424 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,430 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,432 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,433 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,439 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,441 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,444 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,446 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,451 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,453 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,461 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,463 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,468 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,470 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,481 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,483 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,484 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,486 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,493 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,501 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,503 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,509 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,514 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,523 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,525 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,532 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,534 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,536 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,542 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,545 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,547 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,554 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,561 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,562 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,564 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,566 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,567 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,569 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,571 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,572 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,574 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,580 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,582 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,583 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,585 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,590 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,592 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,596 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,599 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,601 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,605 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,608 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,610 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,614 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,617 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,619 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:25,620 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,075 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-19 15:03:26,075 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-19 15:03:26,077 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,077 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,080 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,088 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-19 15:03:26,090 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,090 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,108 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,108 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,120 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-19 15:03:26,121 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,121 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,123 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,124 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-19 15:03:26,125 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,125 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,137 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,138 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,148 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-19 15:03:26,149 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,149 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,150 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,151 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-19 15:03:26,155 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,155 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,167 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,168 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,179 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-19 15:03:26,180 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,180 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,182 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,185 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-19 15:03:26,185 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,186 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,204 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,204 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,216 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-19 15:03:26,216 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,216 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,217 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,218 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-19 15:03:26,220 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,220 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,232 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,232 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,243 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-19 15:03:26,244 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,244 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,246 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,250 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-19 15:03:26,251 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,251 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,264 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,265 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,278 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,279 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,279 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,280 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,281 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-19 15:03:26,282 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,282 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,295 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,295 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,306 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-19 15:03:26,307 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,307 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,309 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,309 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-19 15:03:26,311 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,311 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,323 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,324 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,340 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-19 15:03:26,341 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,341 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,342 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,343 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-19 15:03:26,345 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,345 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,373 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,374 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_8~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_8~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,404 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-19 15:03:26,404 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,405 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,406 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,407 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-19 15:03:26,409 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,409 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,422 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,422 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,433 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,434 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,434 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,436 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,437 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-19 15:03:26,437 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,437 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,450 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,450 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,461 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,462 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,462 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,463 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,464 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-19 15:03:26,466 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,466 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,482 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,482 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t7_pc~0=1} Honda state: {~t7_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,498 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,498 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,498 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,501 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,502 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-19 15:03:26,503 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,503 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,520 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,520 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret23#1=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret23#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,535 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,536 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,536 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,537 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,538 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-19 15:03:26,539 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,539 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,563 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,563 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,577 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-11-19 15:03:26,578 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,578 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,579 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,581 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-19 15:03:26,582 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,582 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,603 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,603 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~T5_E~0=-1} Honda state: {~T5_E~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,614 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,614 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,615 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,618 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,619 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-19 15:03:26,620 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,620 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,632 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,632 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit6_triggered_~__retres1~6#1=0} Honda state: {ULTIMATE.start_is_transmit6_triggered_~__retres1~6#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,643 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-19 15:03:26,643 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,644 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,645 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,646 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-19 15:03:26,647 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,647 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,665 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,666 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-1} Honda state: {~t1_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,678 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,678 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,678 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,680 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,683 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-19 15:03:26,683 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,683 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,696 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,697 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,708 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,708 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,709 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,710 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,711 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-19 15:03:26,712 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,712 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,731 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,732 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t5_st~0=4} Honda state: {~t5_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,742 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,742 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,743 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,744 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,747 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-19 15:03:26,748 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,748 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,771 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,771 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit7_triggered_~__retres1~7#1=0} Honda state: {ULTIMATE.start_is_transmit7_triggered_~__retres1~7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,790 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-19 15:03:26,790 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,790 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,793 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,794 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-19 15:03:26,795 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,795 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,808 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-19 15:03:26,809 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-19 15:03:26,819 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,820 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,820 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,821 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,822 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-19 15:03:26,823 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-19 15:03:26,823 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,844 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,845 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,845 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:26,846 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:26,847 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-19 15:03:26,847 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-19 15:03:26,848 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-19 15:03:26,860 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-19 15:03:26,871 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:26,871 INFO L204 LassoAnalysis]: Preferences: [2024-11-19 15:03:26,872 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-19 15:03:26,872 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-19 15:03:26,872 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-19 15:03:26,872 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-19 15:03:26,872 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:26,872 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-19 15:03:26,872 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-19 15:03:26,872 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.07.cil-2.c_Iteration33_Loop [2024-11-19 15:03:26,872 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-19 15:03:26,872 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-19 15:03:26,880 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,893 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,896 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,901 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,906 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,911 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,915 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,920 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,928 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,931 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,934 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,936 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,938 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,940 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,942 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,944 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,951 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,955 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,959 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,961 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,963 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,964 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,968 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,974 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,978 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,979 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,981 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,983 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,984 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,987 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,990 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,993 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:26,998 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,000 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,001 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,003 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,005 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,006 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,008 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,012 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,014 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,017 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,021 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,023 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,025 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,029 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,030 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,032 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,034 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,036 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,037 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,039 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,040 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,042 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,043 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,045 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,047 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,048 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,050 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,051 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,053 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,054 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,056 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,057 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,059 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,063 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,065 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,066 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,068 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,070 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,071 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,075 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,077 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,081 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,083 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,087 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,088 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,092 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,096 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,098 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-19 15:03:27,551 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-19 15:03:27,555 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-19 15:03:27,556 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,557 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,563 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,564 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-19 15:03:27,569 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,586 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,586 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,587 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,587 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,587 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,588 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,588 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,596 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,618 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-11-19 15:03:27,619 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,619 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,621 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,622 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-19 15:03:27,623 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,634 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,634 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,634 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,634 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,634 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,635 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,635 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,636 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,646 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:27,647 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,647 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,648 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,650 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-19 15:03:27,650 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,660 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,661 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,661 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,661 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,661 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,661 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,662 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,663 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,674 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2024-11-19 15:03:27,674 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,674 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,676 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,676 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-11-19 15:03:27,678 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,688 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,689 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,689 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,689 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-19 15:03:27,689 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,690 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-19 15:03:27,690 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,691 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,702 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:27,702 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,702 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,703 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,704 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-11-19 15:03:27,705 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,715 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,715 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,715 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,715 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,715 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,716 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,716 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,717 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,728 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:27,728 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,728 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,730 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,731 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-11-19 15:03:27,732 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,742 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,742 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,742 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,742 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,742 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,743 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,743 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,744 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,754 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:27,755 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,755 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,756 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,757 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2024-11-19 15:03:27,759 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,769 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,769 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,769 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,769 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,769 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,770 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,770 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,771 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,782 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Ended with exit code 0 [2024-11-19 15:03:27,783 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,783 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,784 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,785 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2024-11-19 15:03:27,786 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,798 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,798 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,799 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,799 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,799 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,800 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,800 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,802 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,816 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:27,816 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,817 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,818 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,818 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2024-11-19 15:03:27,819 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,829 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,829 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,829 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,829 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,829 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,830 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,830 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,832 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,842 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2024-11-19 15:03:27,842 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,843 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,844 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,845 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2024-11-19 15:03:27,846 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,856 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,856 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,856 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,856 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,856 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,857 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,857 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,859 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,869 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:27,870 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,870 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,871 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,872 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2024-11-19 15:03:27,874 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,884 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,884 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,884 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,884 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,884 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,884 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,884 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,886 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,896 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:27,896 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,897 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,898 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,899 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2024-11-19 15:03:27,900 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,910 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,910 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,910 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,910 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,910 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,911 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,911 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,912 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,923 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:27,923 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,923 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,925 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,926 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2024-11-19 15:03:27,927 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,940 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,940 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,940 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,940 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,940 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,941 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,941 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,942 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,955 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2024-11-19 15:03:27,955 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,955 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,957 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,958 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2024-11-19 15:03:27,958 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,969 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,969 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,969 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,969 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:27,969 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,970 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:27,970 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,971 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:27,983 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2024-11-19 15:03:27,983 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:27,983 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:27,984 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:27,985 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2024-11-19 15:03:27,986 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:27,996 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:27,997 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:27,997 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:27,997 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-19 15:03:27,997 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:27,997 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-19 15:03:27,997 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:27,999 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:28,009 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:28,010 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:28,010 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:28,012 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:28,014 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2024-11-19 15:03:28,014 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:28,024 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:28,024 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:28,024 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:28,025 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-19 15:03:28,025 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:28,025 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-19 15:03:28,025 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:28,027 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:28,038 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Ended with exit code 0 [2024-11-19 15:03:28,039 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:28,039 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:28,040 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:28,041 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2024-11-19 15:03:28,042 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:28,052 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:28,053 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:28,053 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:28,053 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-19 15:03:28,053 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:28,054 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-19 15:03:28,054 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:28,055 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:28,066 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:28,067 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:28,067 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:28,068 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:28,069 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2024-11-19 15:03:28,070 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:28,080 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:28,080 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:28,080 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:28,080 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:28,080 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:28,081 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:28,081 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:28,083 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:28,093 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:28,093 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:28,093 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:28,095 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:28,096 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2024-11-19 15:03:28,096 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:28,106 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:28,106 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:28,107 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:28,107 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:28,107 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:28,107 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:28,107 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:28,108 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:28,119 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:28,119 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:28,119 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:28,121 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:28,122 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2024-11-19 15:03:28,122 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:28,132 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:28,132 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:28,133 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:28,133 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-19 15:03:28,133 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:28,133 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-19 15:03:28,133 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:28,135 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:28,145 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2024-11-19 15:03:28,146 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:28,146 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:28,147 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:28,148 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2024-11-19 15:03:28,149 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:28,159 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:28,159 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:28,159 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:28,159 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:28,159 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:28,160 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:28,160 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:28,161 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:28,172 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Ended with exit code 0 [2024-11-19 15:03:28,172 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:28,172 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:28,173 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:28,174 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2024-11-19 15:03:28,176 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:28,186 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:28,186 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:28,186 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:28,186 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:28,186 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:28,187 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:28,187 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:28,188 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-19 15:03:28,198 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:28,199 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:28,199 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:28,200 INFO L229 MonitoredProcess]: Starting monitored process 47 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:28,201 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2024-11-19 15:03:28,202 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-19 15:03:28,211 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-19 15:03:28,212 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-19 15:03:28,212 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-19 15:03:28,212 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-19 15:03:28,212 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-19 15:03:28,212 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-19 15:03:28,212 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-19 15:03:28,214 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-19 15:03:28,219 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-19 15:03:28,219 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-19 15:03:28,221 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:28,221 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:28,233 INFO L229 MonitoredProcess]: Starting monitored process 48 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:28,234 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2024-11-19 15:03:28,235 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-19 15:03:28,235 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-19 15:03:28,235 INFO L474 LassoAnalysis]: Proved termination. [2024-11-19 15:03:28,236 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_M~0) = -1*~E_M~0 + 1 Supporting invariants [] [2024-11-19 15:03:28,246 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Ended with exit code 0 [2024-11-19 15:03:28,248 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-19 15:03:28,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:28,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:28,358 INFO L255 TraceCheckSpWp]: Trace formula consists of 271 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-19 15:03:28,360 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 15:03:28,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:28,562 INFO L255 TraceCheckSpWp]: Trace formula consists of 234 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-19 15:03:28,564 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-19 15:03:28,768 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Forceful destruction successful, exit code 0 [2024-11-19 15:03:28,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:28,874 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-19 15:03:28,875 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 56420 states and 73894 transitions. cyclomatic complexity: 17490 Second operand has 5 states, 5 states have (on average 41.2) internal successors, (206), 5 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:29,477 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 56420 states and 73894 transitions. cyclomatic complexity: 17490. Second operand has 5 states, 5 states have (on average 41.2) internal successors, (206), 5 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 156438 states and 206281 transitions. Complement of second has 5 states. [2024-11-19 15:03:29,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-19 15:03:29,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 41.2) internal successors, (206), 5 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:29,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1122 transitions. [2024-11-19 15:03:29,484 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1122 transitions. Stem has 95 letters. Loop has 111 letters. [2024-11-19 15:03:29,487 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-19 15:03:29,487 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1122 transitions. Stem has 206 letters. Loop has 111 letters. [2024-11-19 15:03:29,488 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-19 15:03:29,488 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1122 transitions. Stem has 95 letters. Loop has 222 letters. [2024-11-19 15:03:29,490 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-19 15:03:29,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156438 states and 206281 transitions. [2024-11-19 15:03:30,137 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 105376 [2024-11-19 15:03:30,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156438 states to 156342 states and 206185 transitions. [2024-11-19 15:03:30,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 106189 [2024-11-19 15:03:31,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 106430 [2024-11-19 15:03:31,227 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156342 states and 206185 transitions. [2024-11-19 15:03:31,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 15:03:31,227 INFO L218 hiAutomatonCegarLoop]: Abstraction has 156342 states and 206185 transitions. [2024-11-19 15:03:31,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156342 states and 206185 transitions. [2024-11-19 15:03:32,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156342 to 156005. [2024-11-19 15:03:33,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 156005 states, 156005 states have (on average 1.3179577577641741) internal successors, (205608), 156004 states have internal predecessors, (205608), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:33,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156005 states to 156005 states and 205608 transitions. [2024-11-19 15:03:33,553 INFO L240 hiAutomatonCegarLoop]: Abstraction has 156005 states and 205608 transitions. [2024-11-19 15:03:33,553 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:33,553 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:33,553 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:33,554 INFO L87 Difference]: Start difference. First operand 156005 states and 205608 transitions. Second operand has 3 states, 3 states have (on average 68.66666666666667) internal successors, (206), 3 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:34,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:34,186 INFO L93 Difference]: Finished difference Result 164525 states and 215568 transitions. [2024-11-19 15:03:34,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 164525 states and 215568 transitions. [2024-11-19 15:03:35,899 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 111056 [2024-11-19 15:03:36,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 164525 states to 164525 states and 215568 transitions. [2024-11-19 15:03:36,198 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111773 [2024-11-19 15:03:36,252 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111773 [2024-11-19 15:03:36,252 INFO L73 IsDeterministic]: Start isDeterministic. Operand 164525 states and 215568 transitions. [2024-11-19 15:03:36,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 15:03:36,254 INFO L218 hiAutomatonCegarLoop]: Abstraction has 164525 states and 215568 transitions. [2024-11-19 15:03:36,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164525 states and 215568 transitions. [2024-11-19 15:03:37,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164525 to 156005. [2024-11-19 15:03:38,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 156005 states, 156005 states have (on average 1.3148809333034197) internal successors, (205128), 156004 states have internal predecessors, (205128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:38,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156005 states to 156005 states and 205128 transitions. [2024-11-19 15:03:38,367 INFO L240 hiAutomatonCegarLoop]: Abstraction has 156005 states and 205128 transitions. [2024-11-19 15:03:38,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:38,368 INFO L425 stractBuchiCegarLoop]: Abstraction has 156005 states and 205128 transitions. [2024-11-19 15:03:38,368 INFO L332 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2024-11-19 15:03:38,368 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156005 states and 205128 transitions. [2024-11-19 15:03:38,790 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 105376 [2024-11-19 15:03:38,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:38,791 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:38,792 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:38,792 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:38,793 INFO L745 eck$LassoCheckResult]: Stem: 1868227#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1868228#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1869433#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1869434#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1869621#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1868499#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1868500#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1868743#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1868744#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1868310#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1867928#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1867929#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1868235#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1868236#L781 assume !(0 == ~M_E~0); 1869236#L781-2 assume !(0 == ~T1_E~0); 1869650#L786-1 assume !(0 == ~T2_E~0); 1867859#L791-1 assume !(0 == ~T3_E~0); 1867860#L796-1 assume !(0 == ~T4_E~0); 1868896#L801-1 assume !(0 == ~T5_E~0); 1868897#L806-1 assume !(0 == ~T6_E~0); 1868959#L811-1 assume !(0 == ~T7_E~0); 1868245#L816-1 assume !(0 == ~E_M~0); 1868246#L821-1 assume !(0 == ~E_1~0); 1867912#L826-1 assume !(0 == ~E_2~0); 1867913#L831-1 assume !(0 == ~E_3~0); 1868491#L836-1 assume !(0 == ~E_4~0); 1868492#L841-1 assume !(0 == ~E_5~0); 1868166#L846-1 assume !(0 == ~E_6~0); 1868167#L851-1 assume !(0 == ~E_7~0); 1868207#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1868208#L388 assume !(1 == ~m_pc~0); 1868199#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1868200#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1869179#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1867936#L967 assume !(0 != activate_threads_~tmp~1#1); 1867937#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1867812#L407 assume !(1 == ~t1_pc~0); 1867813#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1867824#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1867825#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1867889#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1869426#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1868410#L426 assume !(1 == ~t2_pc~0); 1868411#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1869488#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1869665#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1869581#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1869582#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1868579#L445 assume !(1 == ~t3_pc~0); 1868580#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1869252#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1867810#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1867811#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1869084#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1869021#L464 assume !(1 == ~t4_pc~0); 1868217#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1867974#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1867975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1868000#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1868538#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1868539#L483 assume !(1 == ~t5_pc~0); 1869016#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1869379#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1869294#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1869295#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1868385#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1868386#L502 assume !(1 == ~t6_pc~0); 1868127#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1868047#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1868048#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1868430#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1868821#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1869323#L521 assume !(1 == ~t7_pc~0); 1869417#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1867930#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1867931#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1869406#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1869339#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1869161#L869 assume !(1 == ~M_E~0); 1868530#L869-2 assume !(1 == ~T1_E~0); 1868531#L874-1 assume !(1 == ~T2_E~0); 1869516#L879-1 assume !(1 == ~T3_E~0); 1868676#L884-1 assume !(1 == ~T4_E~0); 1867788#L889-1 assume !(1 == ~T5_E~0); 1867789#L894-1 assume !(1 == ~T6_E~0); 1868263#L899-1 assume !(1 == ~T7_E~0); 1869060#L904-1 assume !(1 == ~E_M~0); 1868574#L909-1 assume !(1 == ~E_1~0); 1868575#L914-1 assume !(1 == ~E_2~0); 1868929#L919-1 assume !(1 == ~E_3~0); 1868409#L924-1 assume !(1 == ~E_4~0); 1868110#L929-1 assume !(1 == ~E_5~0); 1868111#L934-1 assume !(1 == ~E_6~0); 1868536#L939-1 assume !(1 == ~E_7~0); 1868537#L944-1 assume { :end_inline_reset_delta_events } true; 1869322#L1190-2 assume !false; 1878451#L1191 [2024-11-19 15:03:38,794 INFO L747 eck$LassoCheckResult]: Loop: 1878451#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1939130#L756-1 assume !false; 1939128#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1939127#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1939124#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1939123#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1939122#L653 assume 0 != eval_~tmp~0#1; 1939110#L653-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1939086#L661 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;havoc master_#t~nondet4#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 1939087#L80 assume 0 == ~m_pc~0; 1947303#L116 assume !false; 1947302#L92 havoc master_#t~nondet5#1;~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1947301#L388-3 assume !(1 == ~m_pc~0); 1947300#L388-5 is_master_triggered_~__retres1~0#1 := 0; 1947298#L399-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1947296#is_master_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1947294#L967-3 assume !(0 != activate_threads_~tmp~1#1); 1947287#L967-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1947281#L407-3 assume !(1 == ~t1_pc~0); 1947276#L407-5 is_transmit1_triggered_~__retres1~1#1 := 0; 1947271#L418-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1947265#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1947259#L975-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1947249#L975-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1947241#L426-3 assume !(1 == ~t2_pc~0); 1947233#L426-5 is_transmit2_triggered_~__retres1~2#1 := 0; 1947216#L437-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1947206#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1947196#L983-3 assume !(0 != activate_threads_~tmp___1~0#1); 1946783#L983-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1946748#L445-3 assume !(1 == ~t3_pc~0); 1946738#L445-5 is_transmit3_triggered_~__retres1~3#1 := 0; 1946726#L456-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1946404#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1946395#L991-3 assume !(0 != activate_threads_~tmp___2~0#1); 1946385#L991-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1945562#L464-3 assume !(1 == ~t4_pc~0); 1945501#L464-5 is_transmit4_triggered_~__retres1~4#1 := 0; 1945438#L475-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1944722#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1944674#L999-3 assume !(0 != activate_threads_~tmp___3~0#1); 1943884#L999-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1943750#L483-3 assume !(1 == ~t5_pc~0); 1943749#L483-5 is_transmit5_triggered_~__retres1~5#1 := 0; 1943748#L494-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1943747#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1943743#L1007-3 assume !(0 != activate_threads_~tmp___4~0#1); 1943740#L1007-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1943738#L502-3 assume !(1 == ~t6_pc~0); 1943736#L502-5 is_transmit6_triggered_~__retres1~6#1 := 0; 1943734#L513-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1943732#is_transmit6_triggered_returnLabel#2 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1943730#L1015-3 assume !(0 != activate_threads_~tmp___5~0#1); 1943723#L1015-5 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1943722#L521-3 assume 1 == ~t7_pc~0; 1943721#L522-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1943719#L532-1 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1943717#is_transmit7_triggered_returnLabel#2 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1943711#L1023-3 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1933544#L1023-5 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true; 1928404#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 1928402#master_returnLabel#1 havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;assume { :end_inline_master } true; 1928401#L661-2 havoc eval_~tmp_ndt_1~0#1; 1928398#L658-1 assume !(0 == ~t1_st~0); 1928394#L672-1 assume !(0 == ~t2_st~0); 1928391#L686-1 assume !(0 == ~t3_st~0); 1928387#L700-1 assume !(0 == ~t4_st~0); 1928384#L714-1 assume !(0 == ~t5_st~0); 1928373#L728-1 assume !(0 == ~t6_st~0); 1928369#L742-1 assume !(0 == ~t7_st~0); 1928365#L756-1 assume !false; 1928362#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1928360#L596 assume !(0 == ~m_st~0); 1928358#L600 assume !(0 == ~t1_st~0); 1928356#L604 assume !(0 == ~t2_st~0); 1928354#L608 assume !(0 == ~t3_st~0); 1928353#L612 assume !(0 == ~t4_st~0); 1928352#L616 assume !(0 == ~t5_st~0); 1928349#L620 assume !(0 == ~t6_st~0); 1928346#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1928344#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1928343#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1928339#L653 assume !(0 != eval_~tmp~0#1); 1928338#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1928336#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1928335#L781-3 assume !(0 == ~M_E~0); 1928334#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1928331#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1928326#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1928324#L796-3 assume !(0 == ~T4_E~0); 1928322#L801-3 assume !(0 == ~T5_E~0); 1928320#L806-3 assume !(0 == ~T6_E~0); 1928318#L811-3 assume !(0 == ~T7_E~0); 1928316#L816-3 assume !(0 == ~E_M~0); 1928312#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1928310#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1928307#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1928305#L836-3 assume !(0 == ~E_4~0); 1928303#L841-3 assume !(0 == ~E_5~0); 1928301#L846-3 assume !(0 == ~E_6~0); 1928299#L851-3 assume !(0 == ~E_7~0); 1928297#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1928295#L388-27 assume 1 == ~m_pc~0; 1928292#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1928290#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1928288#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1928283#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1928281#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1928279#L407-27 assume !(1 == ~t1_pc~0); 1928277#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1928274#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1928272#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1928270#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1928268#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1928266#L426-27 assume 1 == ~t2_pc~0; 1928264#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1928265#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1928730#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1928254#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1928252#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1928250#L445-27 assume !(1 == ~t3_pc~0); 1928248#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1928246#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1928244#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1928242#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1928240#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1928238#L464-27 assume !(1 == ~t4_pc~0); 1928235#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1928233#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1928231#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1928229#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 1928227#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1928225#L483-27 assume !(1 == ~t5_pc~0); 1928223#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1928221#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1928219#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1928215#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1928213#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1928211#L502-27 assume !(1 == ~t6_pc~0); 1928209#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1928206#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1928204#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1928203#L1015-27 assume !(0 != activate_threads_~tmp___5~0#1); 1928199#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1928197#L521-27 assume !(1 == ~t7_pc~0); 1928193#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1928192#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1928189#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1926340#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1926337#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1926335#L869-3 assume !(1 == ~M_E~0); 1926184#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1926332#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1926330#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1926328#L884-3 assume !(1 == ~T4_E~0); 1926326#L889-3 assume !(1 == ~T5_E~0); 1926324#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1926322#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1926320#L904-3 assume !(1 == ~E_M~0); 1926318#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1926316#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1926314#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1926312#L924-3 assume !(1 == ~E_4~0); 1926310#L929-3 assume !(1 == ~E_5~0); 1926308#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1926306#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1926304#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1926302#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1926300#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1926298#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1926294#L1209 assume !(0 == start_simulation_~tmp~3#1); 1926295#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1939216#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1939215#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1939214#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1939184#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1939178#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1939169#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1939155#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1939146#L1190-2 assume !false; 1878451#L1191 [2024-11-19 15:03:38,794 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:38,794 INFO L85 PathProgramCache]: Analyzing trace with hash -1048388199, now seen corresponding path program 1 times [2024-11-19 15:03:38,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:38,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450241516] [2024-11-19 15:03:38,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:38,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:38,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:38,804 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:03:38,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:03:38,824 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:03:38,824 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:38,825 INFO L85 PathProgramCache]: Analyzing trace with hash -189629708, now seen corresponding path program 1 times [2024-11-19 15:03:38,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:38,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223079031] [2024-11-19 15:03:38,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:38,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:38,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:38,860 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:38,860 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:38,860 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223079031] [2024-11-19 15:03:38,861 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1223079031] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:38,861 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:38,861 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:38,861 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1809381401] [2024-11-19 15:03:38,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:38,861 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:38,861 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:38,862 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:38,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:38,862 INFO L87 Difference]: Start difference. First operand 156005 states and 205128 transitions. cyclomatic complexity: 49171 Second operand has 3 states, 3 states have (on average 60.0) internal successors, (180), 3 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:40,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:40,671 INFO L93 Difference]: Finished difference Result 299716 states and 391025 transitions. [2024-11-19 15:03:40,672 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 299716 states and 391025 transitions. [2024-11-19 15:03:42,527 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 191360 [2024-11-19 15:03:43,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 299716 states to 299716 states and 391025 transitions. [2024-11-19 15:03:43,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204020 [2024-11-19 15:03:43,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 204020 [2024-11-19 15:03:43,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 299716 states and 391025 transitions. [2024-11-19 15:03:43,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-19 15:03:43,272 INFO L218 hiAutomatonCegarLoop]: Abstraction has 299716 states and 391025 transitions. [2024-11-19 15:03:43,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 299716 states and 391025 transitions. [2024-11-19 15:03:46,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 299716 to 291844. [2024-11-19 15:03:46,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 291844 states, 291844 states have (on average 1.3072771754773098) internal successors, (381521), 291843 states have internal predecessors, (381521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)