./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.12.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3061b6dc Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.12.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-assert-order-craig-3061b6d-m [2024-11-19 15:03:36,516 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-19 15:03:36,612 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-19 15:03:36,617 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-19 15:03:36,618 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-19 15:03:36,642 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-19 15:03:36,643 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-19 15:03:36,644 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-19 15:03:36,644 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-19 15:03:36,645 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-19 15:03:36,646 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-19 15:03:36,647 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-19 15:03:36,647 INFO L153 SettingsManager]: * Use SBE=true [2024-11-19 15:03:36,647 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-19 15:03:36,647 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-19 15:03:36,648 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-19 15:03:36,648 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-19 15:03:36,648 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-19 15:03:36,648 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-19 15:03:36,648 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-19 15:03:36,649 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-19 15:03:36,650 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-19 15:03:36,650 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-19 15:03:36,650 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-19 15:03:36,650 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-19 15:03:36,650 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-19 15:03:36,651 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-19 15:03:36,651 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-19 15:03:36,651 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-19 15:03:36,651 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-19 15:03:36,651 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-19 15:03:36,651 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-19 15:03:36,652 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-19 15:03:36,652 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-19 15:03:36,652 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-19 15:03:36,653 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-19 15:03:36,653 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-19 15:03:36,653 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-19 15:03:36,653 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-19 15:03:36,654 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 [2024-11-19 15:03:36,884 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-19 15:03:36,919 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-19 15:03:36,922 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-19 15:03:36,930 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-19 15:03:36,931 INFO L274 PluginConnector]: CDTParser initialized [2024-11-19 15:03:36,932 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2024-11-19 15:03:38,550 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-19 15:03:38,773 INFO L384 CDTParser]: Found 1 translation units. [2024-11-19 15:03:38,773 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2024-11-19 15:03:38,799 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3d0815825/2f3996cb68ad497786a2f23536ee0af9/FLAGa43ed8ee4 [2024-11-19 15:03:38,820 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3d0815825/2f3996cb68ad497786a2f23536ee0af9 [2024-11-19 15:03:38,823 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-19 15:03:38,825 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-19 15:03:38,830 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-19 15:03:38,831 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-19 15:03:38,837 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-19 15:03:38,838 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 03:03:38" (1/1) ... [2024-11-19 15:03:38,839 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6f22955a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:38, skipping insertion in model container [2024-11-19 15:03:38,842 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 03:03:38" (1/1) ... [2024-11-19 15:03:38,895 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-19 15:03:39,233 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 15:03:39,252 INFO L200 MainTranslator]: Completed pre-run [2024-11-19 15:03:39,305 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 15:03:39,323 INFO L204 MainTranslator]: Completed translation [2024-11-19 15:03:39,324 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39 WrapperNode [2024-11-19 15:03:39,324 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-19 15:03:39,325 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-19 15:03:39,325 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-19 15:03:39,325 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-19 15:03:39,330 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,348 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,456 INFO L138 Inliner]: procedures = 52, calls = 69, calls flagged for inlining = 64, calls inlined = 272, statements flattened = 4175 [2024-11-19 15:03:39,457 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-19 15:03:39,458 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-19 15:03:39,459 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-19 15:03:39,459 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-19 15:03:39,469 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,470 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,481 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,522 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-19 15:03:39,522 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,523 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,548 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,568 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,575 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,584 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,600 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-19 15:03:39,601 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-19 15:03:39,601 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-19 15:03:39,601 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-19 15:03:39,602 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (1/1) ... [2024-11-19 15:03:39,608 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:03:39,617 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:03:39,633 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:03:39,641 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-19 15:03:39,680 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-19 15:03:39,680 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-19 15:03:39,680 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-19 15:03:39,681 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-19 15:03:39,807 INFO L238 CfgBuilder]: Building ICFG [2024-11-19 15:03:39,809 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-19 15:03:42,142 INFO L? ?]: Removed 886 outVars from TransFormulas that were not future-live. [2024-11-19 15:03:42,143 INFO L287 CfgBuilder]: Performing block encoding [2024-11-19 15:03:42,177 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-19 15:03:42,177 INFO L316 CfgBuilder]: Removed 15 assume(true) statements. [2024-11-19 15:03:42,177 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:03:42 BoogieIcfgContainer [2024-11-19 15:03:42,178 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-19 15:03:42,178 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-19 15:03:42,178 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-19 15:03:42,182 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-19 15:03:42,182 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:03:42,182 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 03:03:38" (1/3) ... [2024-11-19 15:03:42,183 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15201a6c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 03:03:42, skipping insertion in model container [2024-11-19 15:03:42,183 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:03:42,183 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:03:39" (2/3) ... [2024-11-19 15:03:42,184 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15201a6c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 03:03:42, skipping insertion in model container [2024-11-19 15:03:42,184 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:03:42,184 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:03:42" (3/3) ... [2024-11-19 15:03:42,185 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-1.c [2024-11-19 15:03:42,294 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-19 15:03:42,295 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-19 15:03:42,295 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-19 15:03:42,295 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-19 15:03:42,295 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-19 15:03:42,295 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-19 15:03:42,295 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-19 15:03:42,295 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-19 15:03:42,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1813 states, 1812 states have (on average 1.4955849889624724) internal successors, (2710), 1812 states have internal predecessors, (2710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:42,366 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1646 [2024-11-19 15:03:42,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:42,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:42,379 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:42,379 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:42,379 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-19 15:03:42,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1813 states, 1812 states have (on average 1.4955849889624724) internal successors, (2710), 1812 states have internal predecessors, (2710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:42,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1646 [2024-11-19 15:03:42,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:42,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:42,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:42,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:42,405 INFO L745 eck$LassoCheckResult]: Stem: 113#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1736#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 673#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1734#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1175#L853true assume !(1 == ~m_i~0);~m_st~0 := 2; 971#L853-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 259#L858-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2#L863-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 750#L868-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 875#L873-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1661#L878-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1625#L883-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1696#L888-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 383#L893-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 780#L898-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1804#L903-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 711#L908-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1406#L913-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 839#L1206true assume !(0 == ~M_E~0); 372#L1206-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1166#L1211-1true assume !(0 == ~T2_E~0); 1340#L1216-1true assume !(0 == ~T3_E~0); 247#L1221-1true assume !(0 == ~T4_E~0); 1258#L1226-1true assume !(0 == ~T5_E~0); 85#L1231-1true assume !(0 == ~T6_E~0); 1413#L1236-1true assume !(0 == ~T7_E~0); 1241#L1241-1true assume !(0 == ~T8_E~0); 286#L1246-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 413#L1251-1true assume !(0 == ~T10_E~0); 916#L1256-1true assume !(0 == ~T11_E~0); 6#L1261-1true assume !(0 == ~T12_E~0); 1636#L1266-1true assume !(0 == ~E_M~0); 1576#L1271-1true assume !(0 == ~E_1~0); 865#L1276-1true assume !(0 == ~E_2~0); 1568#L1281-1true assume !(0 == ~E_3~0); 800#L1286-1true assume 0 == ~E_4~0;~E_4~0 := 1; 197#L1291-1true assume !(0 == ~E_5~0); 1659#L1296-1true assume !(0 == ~E_6~0); 641#L1301-1true assume !(0 == ~E_7~0); 1107#L1306-1true assume !(0 == ~E_8~0); 1069#L1311-1true assume !(0 == ~E_9~0); 179#L1316-1true assume !(0 == ~E_10~0); 1497#L1321-1true assume !(0 == ~E_11~0); 653#L1326-1true assume 0 == ~E_12~0;~E_12~0 := 1; 108#L1331-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1799#L598true assume 1 == ~m_pc~0; 131#L599true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1208#L609true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 565#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1434#L1497true assume !(0 != activate_threads_~tmp~1#1); 1697#L1497-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1299#L617true assume !(1 == ~t1_pc~0); 297#L617-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1742#L628true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 944#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1484#L1505true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 721#L1505-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1331#L636true assume 1 == ~t2_pc~0; 281#L637true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 549#L647true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1472#L1513true assume !(0 != activate_threads_~tmp___1~0#1); 748#L1513-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 484#L655true assume !(1 == ~t3_pc~0); 1443#L655-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1718#L666true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 933#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1806#L1521true assume !(0 != activate_threads_~tmp___2~0#1); 1578#L1521-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1607#L674true assume 1 == ~t4_pc~0; 43#L675true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1670#L685true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 190#L1529true assume !(0 != activate_threads_~tmp___3~0#1); 483#L1529-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1352#L693true assume !(1 == ~t5_pc~0); 604#L693-2true is_transmit5_triggered_~__retres1~5#1 := 0; 373#L704true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1486#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1074#L1537true assume !(0 != activate_threads_~tmp___4~0#1); 421#L1537-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 385#L712true assume 1 == ~t6_pc~0; 892#L713true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 676#L723true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 184#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1679#L1545true assume !(0 != activate_threads_~tmp___5~0#1); 767#L1545-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 759#L731true assume 1 == ~t7_pc~0; 109#L732true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 212#L742true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1757#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1083#L1553true assume !(0 != activate_threads_~tmp___6~0#1); 987#L1553-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 163#L750true assume !(1 == ~t8_pc~0); 853#L750-2true is_transmit8_triggered_~__retres1~8#1 := 0; 265#L761true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1420#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1094#L1561true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 343#L1561-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 719#L769true assume 1 == ~t9_pc~0; 1744#L770true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 93#L780true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 205#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 912#L1569true assume !(0 != activate_threads_~tmp___8~0#1); 1368#L1569-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1013#L788true assume !(1 == ~t10_pc~0); 616#L788-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1243#L799true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1220#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1131#L1577true assume !(0 != activate_threads_~tmp___9~0#1); 161#L1577-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1018#L807true assume 1 == ~t11_pc~0; 1221#L808true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 751#L818true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1337#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1813#L1585true assume !(0 != activate_threads_~tmp___10~0#1); 1800#L1585-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1182#L826true assume !(1 == ~t12_pc~0); 386#L826-2true is_transmit12_triggered_~__retres1~12#1 := 0; 775#L837true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1372#L1593true assume !(0 != activate_threads_~tmp___11~0#1); 479#L1593-2true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425#L1344true assume !(1 == ~M_E~0); 510#L1344-2true assume !(1 == ~T1_E~0); 1761#L1349-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 646#L1354-1true assume !(1 == ~T3_E~0); 1000#L1359-1true assume !(1 == ~T4_E~0); 1600#L1364-1true assume !(1 == ~T5_E~0); 221#L1369-1true assume !(1 == ~T6_E~0); 974#L1374-1true assume !(1 == ~T7_E~0); 652#L1379-1true assume !(1 == ~T8_E~0); 709#L1384-1true assume !(1 == ~T9_E~0); 1786#L1389-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1248#L1394-1true assume !(1 == ~T11_E~0); 1680#L1399-1true assume !(1 == ~T12_E~0); 1473#L1404-1true assume !(1 == ~E_M~0); 288#L1409-1true assume !(1 == ~E_1~0); 1431#L1414-1true assume !(1 == ~E_2~0); 893#L1419-1true assume !(1 == ~E_3~0); 100#L1424-1true assume !(1 == ~E_4~0); 657#L1429-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1276#L1434-1true assume !(1 == ~E_6~0); 1664#L1439-1true assume !(1 == ~E_7~0); 117#L1444-1true assume !(1 == ~E_8~0); 848#L1449-1true assume !(1 == ~E_9~0); 346#L1454-1true assume !(1 == ~E_10~0); 1333#L1459-1true assume !(1 == ~E_11~0); 734#L1464-1true assume !(1 == ~E_12~0); 781#L1469-1true assume { :end_inline_reset_delta_events } true; 1532#L1815-2true [2024-11-19 15:03:42,407 INFO L747 eck$LassoCheckResult]: Loop: 1532#L1815-2true assume !false; 914#L1816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1033#L1181-1true assume false; 518#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 292#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1660#L1206-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1677#L1206-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 733#L1211-3true assume !(0 == ~T2_E~0); 153#L1216-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 493#L1221-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1023#L1226-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 192#L1231-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 369#L1236-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1801#L1241-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1366#L1246-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1151#L1251-3true assume !(0 == ~T10_E~0); 825#L1256-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 166#L1261-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 534#L1266-3true assume 0 == ~E_M~0;~E_M~0 := 1; 191#L1271-3true assume 0 == ~E_1~0;~E_1~0 := 1; 509#L1276-3true assume 0 == ~E_2~0;~E_2~0 := 1; 458#L1281-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1217#L1286-3true assume 0 == ~E_4~0;~E_4~0 := 1; 888#L1291-3true assume !(0 == ~E_5~0); 1673#L1296-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1594#L1301-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1452#L1306-3true assume 0 == ~E_8~0;~E_8~0 := 1; 544#L1311-3true assume 0 == ~E_9~0;~E_9~0 := 1; 125#L1316-3true assume 0 == ~E_10~0;~E_10~0 := 1; 167#L1321-3true assume 0 == ~E_11~0;~E_11~0 := 1; 624#L1326-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1424#L1331-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 899#L598-42true assume !(1 == ~m_pc~0); 1048#L598-44true is_master_triggered_~__retres1~0#1 := 0; 1193#L609-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 387#is_master_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1453#L1497-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1717#L1497-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 663#L617-42true assume 1 == ~t1_pc~0; 489#L618-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 411#L628-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1675#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1444#L1505-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 244#L1505-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1429#L636-42true assume 1 == ~t2_pc~0; 1378#L637-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1758#L647-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 583#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1093#L1513-42true assume !(0 != activate_threads_~tmp___1~0#1); 996#L1513-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 850#L655-42true assume !(1 == ~t3_pc~0); 501#L655-44true is_transmit3_triggered_~__retres1~3#1 := 0; 1058#L666-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 926#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1773#L1521-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1215#L1521-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1104#L674-42true assume 1 == ~t4_pc~0; 1535#L675-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 768#L685-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 982#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 960#L1529-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 603#L1529-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1198#L693-42true assume !(1 == ~t5_pc~0); 1525#L693-44true is_transmit5_triggered_~__retres1~5#1 := 0; 871#L704-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 643#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 867#L1537-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1154#L1537-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 352#L712-42true assume !(1 == ~t6_pc~0); 1604#L712-44true is_transmit6_triggered_~__retres1~6#1 := 0; 989#L723-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 162#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1805#L1545-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 416#L1545-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1383#L731-42true assume !(1 == ~t7_pc~0); 241#L731-44true is_transmit7_triggered_~__retres1~7#1 := 0; 1385#L742-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 660#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 363#L1553-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1055#L1553-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 195#L750-42true assume 1 == ~t8_pc~0; 531#L751-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1573#L761-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 776#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 132#L1561-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1707#L1561-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 602#L769-42true assume !(1 == ~t9_pc~0); 593#L769-44true is_transmit9_triggered_~__retres1~9#1 := 0; 1110#L780-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1689#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1609#L1569-42true assume !(0 != activate_threads_~tmp___8~0#1); 245#L1569-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 610#L788-42true assume 1 == ~t10_pc~0; 790#L789-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1710#L799-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 765#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1683#L1577-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1638#L1577-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1553#L807-42true assume !(1 == ~t11_pc~0); 53#L807-44true is_transmit11_triggered_~__retres1~11#1 := 0; 533#L818-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1393#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 111#L1585-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1149#L1585-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 243#L826-42true assume 1 == ~t12_pc~0; 1755#L827-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 978#L837-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 620#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 239#L1593-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1493#L1593-44true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 830#L1344-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1229#L1344-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 769#L1349-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 327#L1354-3true assume !(1 == ~T3_E~0); 784#L1359-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1669#L1364-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1564#L1369-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1274#L1374-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 199#L1379-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1158#L1384-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 326#L1389-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 504#L1394-3true assume !(1 == ~T11_E~0); 1738#L1399-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1296#L1404-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1236#L1409-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1365#L1414-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1390#L1419-3true assume 1 == ~E_3~0;~E_3~0 := 2; 967#L1424-3true assume 1 == ~E_4~0;~E_4~0 := 2; 140#L1429-3true assume 1 == ~E_5~0;~E_5~0 := 2; 783#L1434-3true assume !(1 == ~E_6~0); 950#L1439-3true assume 1 == ~E_7~0;~E_7~0 := 2; 114#L1444-3true assume 1 == ~E_8~0;~E_8~0 := 2; 172#L1449-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1451#L1454-3true assume 1 == ~E_10~0;~E_10~0 := 2; 779#L1459-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1792#L1464-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1270#L1469-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 665#L926-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 76#L993-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 156#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1605#L1834true assume !(0 == start_simulation_~tmp~3#1); 1100#L1834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 895#L926-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 571#L993-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1255#L1789true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1610#L1796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1247#stop_simulation_returnLabel#1true start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 968#L1847true assume !(0 != start_simulation_~tmp___0~1#1); 1532#L1815-2true [2024-11-19 15:03:42,417 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:42,417 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2024-11-19 15:03:42,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:42,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644523488] [2024-11-19 15:03:42,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:42,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:42,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:42,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:42,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:42,693 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [644523488] [2024-11-19 15:03:42,693 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [644523488] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:42,693 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:42,694 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:42,695 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554396283] [2024-11-19 15:03:42,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:42,702 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:42,702 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:42,702 INFO L85 PathProgramCache]: Analyzing trace with hash -821514815, now seen corresponding path program 1 times [2024-11-19 15:03:42,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:42,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832888612] [2024-11-19 15:03:42,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:42,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:42,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:42,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:42,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:42,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1832888612] [2024-11-19 15:03:42,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1832888612] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:42,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:42,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:03:42,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [646585256] [2024-11-19 15:03:42,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:42,777 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:42,778 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:42,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-19 15:03:42,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-19 15:03:42,808 INFO L87 Difference]: Start difference. First operand has 1813 states, 1812 states have (on average 1.4955849889624724) internal successors, (2710), 1812 states have internal predecessors, (2710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:42,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:42,872 INFO L93 Difference]: Finished difference Result 1809 states and 2674 transitions. [2024-11-19 15:03:42,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1809 states and 2674 transitions. [2024-11-19 15:03:42,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:42,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1809 states to 1803 states and 2668 transitions. [2024-11-19 15:03:42,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:42,921 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:42,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2668 transitions. [2024-11-19 15:03:42,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:42,938 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2668 transitions. [2024-11-19 15:03:42,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2668 transitions. [2024-11-19 15:03:42,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:42,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.4797559622850804) internal successors, (2668), 1802 states have internal predecessors, (2668), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:43,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2668 transitions. [2024-11-19 15:03:43,004 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2668 transitions. [2024-11-19 15:03:43,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-19 15:03:43,010 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2668 transitions. [2024-11-19 15:03:43,011 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-19 15:03:43,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2668 transitions. [2024-11-19 15:03:43,017 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:43,017 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:43,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:43,021 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:43,021 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:43,021 INFO L745 eck$LassoCheckResult]: Stem: 3874#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3875#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4804#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4805#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5263#L853 assume !(1 == ~m_i~0);~m_st~0 := 2; 5131#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4161#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3631#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3632#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4899#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5038#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5421#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5422#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4384#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4385#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4927#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4849#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4850#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5002#L1206 assume !(0 == ~M_E~0); 4366#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4367#L1211-1 assume !(0 == ~T2_E~0); 5256#L1216-1 assume !(0 == ~T3_E~0); 4138#L1221-1 assume !(0 == ~T4_E~0); 4139#L1226-1 assume !(0 == ~T5_E~0); 3811#L1231-1 assume !(0 == ~T6_E~0); 3812#L1236-1 assume !(0 == ~T7_E~0); 5295#L1241-1 assume !(0 == ~T8_E~0); 4208#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4209#L1251-1 assume !(0 == ~T10_E~0); 4440#L1256-1 assume !(0 == ~T11_E~0); 3641#L1261-1 assume !(0 == ~T12_E~0); 3642#L1266-1 assume !(0 == ~E_M~0); 5407#L1271-1 assume !(0 == ~E_1~0); 5028#L1276-1 assume !(0 == ~E_2~0); 5029#L1281-1 assume !(0 == ~E_3~0); 4956#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4037#L1291-1 assume !(0 == ~E_5~0); 4038#L1296-1 assume !(0 == ~E_6~0); 4760#L1301-1 assume !(0 == ~E_7~0); 4761#L1306-1 assume !(0 == ~E_8~0); 5197#L1311-1 assume !(0 == ~E_9~0); 3997#L1316-1 assume !(0 == ~E_10~0); 3998#L1321-1 assume !(0 == ~E_11~0); 4775#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 3862#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3863#L598 assume 1 == ~m_pc~0; 3912#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3913#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4658#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4659#L1497 assume !(0 != activate_threads_~tmp~1#1); 5370#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5319#L617 assume !(1 == ~t1_pc~0); 4230#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4231#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5110#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5111#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4866#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4867#L636 assume 1 == ~t2_pc~0; 4199#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4200#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4019#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4020#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 4898#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4556#L655 assume !(1 == ~t3_pc~0); 4557#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5282#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5098#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5099#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 5408#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5409#L674 assume 1 == ~t4_pc~0; 3725#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3726#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3752#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3753#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 4021#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4555#L693 assume !(1 == ~t5_pc~0); 4711#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4368#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4369#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5199#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 4453#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4388#L712 assume 1 == ~t6_pc~0; 4389#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4809#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4007#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4008#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 4915#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4908#L731 assume 1 == ~t7_pc~0; 3864#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3865#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4065#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5202#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 5140#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3970#L750 assume !(1 == ~t8_pc~0); 3662#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3661#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4172#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5212#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4319#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4320#L769 assume 1 == ~t9_pc~0; 4862#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3829#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3830#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4053#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 5075#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5160#L788 assume !(1 == ~t10_pc~0); 4727#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4728#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5283#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5235#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 3966#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3967#L807 assume 1 == ~t11_pc~0; 5166#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4742#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4900#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5339#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 5433#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5266#L826 assume !(1 == ~t12_pc~0); 4391#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4392#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3706#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3707#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 4549#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4461#L1344 assume !(1 == ~M_E~0); 4462#L1344-2 assume !(1 == ~T1_E~0); 4591#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4766#L1354-1 assume !(1 == ~T3_E~0); 4767#L1359-1 assume !(1 == ~T4_E~0); 5151#L1364-1 assume !(1 == ~T5_E~0); 4084#L1369-1 assume !(1 == ~T6_E~0); 4085#L1374-1 assume !(1 == ~T7_E~0); 4773#L1379-1 assume !(1 == ~T8_E~0); 4774#L1384-1 assume !(1 == ~T9_E~0); 4848#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5297#L1394-1 assume !(1 == ~T11_E~0); 5298#L1399-1 assume !(1 == ~T12_E~0); 5378#L1404-1 assume !(1 == ~E_M~0); 4211#L1409-1 assume !(1 == ~E_1~0); 4212#L1414-1 assume !(1 == ~E_2~0); 5054#L1419-1 assume !(1 == ~E_3~0); 3842#L1424-1 assume !(1 == ~E_4~0); 3843#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 4782#L1434-1 assume !(1 == ~E_6~0); 5312#L1439-1 assume !(1 == ~E_7~0); 3883#L1444-1 assume !(1 == ~E_8~0); 3884#L1449-1 assume !(1 == ~E_9~0); 4324#L1454-1 assume !(1 == ~E_10~0); 4325#L1459-1 assume !(1 == ~E_11~0); 4878#L1464-1 assume !(1 == ~E_12~0); 4879#L1469-1 assume { :end_inline_reset_delta_events } true; 4928#L1815-2 [2024-11-19 15:03:43,024 INFO L747 eck$LassoCheckResult]: Loop: 4928#L1815-2 assume !false; 5076#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4238#L1181-1 assume !false; 5176#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4764#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3634#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4361#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4907#L1008 assume !(0 != eval_~tmp~0#1); 4603#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4219#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4220#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5428#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4877#L1211-3 assume !(0 == ~T2_E~0); 3952#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3953#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4571#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4024#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4025#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4362#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5348#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5250#L1251-3 assume !(0 == ~T10_E~0); 4987#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3976#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3977#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4022#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4023#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4512#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4513#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5051#L1291-3 assume !(0 == ~E_5~0); 5052#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5414#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5375#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4632#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3898#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3899#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3978#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4736#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5062#L598-42 assume 1 == ~m_pc~0; 5063#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5183#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4393#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4394#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5376#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4789#L617-42 assume 1 == ~t1_pc~0; 4565#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4436#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4437#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5373#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4132#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4133#L636-42 assume !(1 == ~t2_pc~0); 4601#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 4602#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4681#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4682#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 5147#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5012#L655-42 assume !(1 == ~t3_pc~0); 4577#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4578#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5089#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5090#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5281#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5218#L674-42 assume !(1 == ~t4_pc~0); 4995#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 4916#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4917#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5122#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4709#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4710#L693-42 assume !(1 == ~t5_pc~0); 4977#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4976#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4762#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4763#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5032#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4334#L712-42 assume 1 == ~t6_pc~0; 4336#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4650#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3968#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3969#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4445#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4446#L731-42 assume !(1 == ~t7_pc~0); 4124#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4125#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4785#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4351#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4352#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4032#L750-42 assume 1 == ~t8_pc~0; 4033#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4619#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4923#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3915#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3916#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4708#L769-42 assume 1 == ~t9_pc~0; 4536#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4537#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5223#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5417#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 4134#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4135#L788-42 assume 1 == ~t10_pc~0; 4716#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4942#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4913#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4914#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5426#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5401#L807-42 assume !(1 == ~t11_pc~0); 3748#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 3749#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4623#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3870#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3871#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4129#L826-42 assume 1 == ~t12_pc~0; 4130#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4340#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4732#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4119#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4120#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4991#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4992#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4918#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4291#L1354-3 assume !(1 == ~T3_E~0); 4292#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4932#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5404#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5311#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4041#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4042#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4289#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4290#L1394-3 assume !(1 == ~T11_E~0); 4583#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5317#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5288#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5289#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5347#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5129#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3929#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3930#L1434-3 assume !(1 == ~E_6~0); 4931#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3876#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3877#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3984#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4925#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4926#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5310#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4793#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3794#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3795#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 3958#L1834 assume !(0 == start_simulation_~tmp~3#1); 5039#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 5056#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4497#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3683#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3684#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5300#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5296#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 5130#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 4928#L1815-2 [2024-11-19 15:03:43,024 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:43,024 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2024-11-19 15:03:43,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:43,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184731106] [2024-11-19 15:03:43,025 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:03:43,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:43,053 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:03:43,053 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:03:43,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:43,152 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:43,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184731106] [2024-11-19 15:03:43,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184731106] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:43,155 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:43,155 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:43,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1722732627] [2024-11-19 15:03:43,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:43,156 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:43,156 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:43,156 INFO L85 PathProgramCache]: Analyzing trace with hash 628269149, now seen corresponding path program 1 times [2024-11-19 15:03:43,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:43,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878183331] [2024-11-19 15:03:43,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:43,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:43,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:43,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:43,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:43,295 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878183331] [2024-11-19 15:03:43,295 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1878183331] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:43,295 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:43,295 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:43,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [528093018] [2024-11-19 15:03:43,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:43,296 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:43,296 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:43,297 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:43,297 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:43,297 INFO L87 Difference]: Start difference. First operand 1803 states and 2668 transitions. cyclomatic complexity: 866 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:43,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:43,338 INFO L93 Difference]: Finished difference Result 1803 states and 2667 transitions. [2024-11-19 15:03:43,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2667 transitions. [2024-11-19 15:03:43,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:43,357 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2667 transitions. [2024-11-19 15:03:43,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:43,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:43,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2667 transitions. [2024-11-19 15:03:43,364 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:43,364 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2667 transitions. [2024-11-19 15:03:43,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2667 transitions. [2024-11-19 15:03:43,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:43,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.4792013311148087) internal successors, (2667), 1802 states have internal predecessors, (2667), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:43,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2667 transitions. [2024-11-19 15:03:43,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2667 transitions. [2024-11-19 15:03:43,392 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:43,396 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2667 transitions. [2024-11-19 15:03:43,396 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-19 15:03:43,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2667 transitions. [2024-11-19 15:03:43,403 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:43,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:43,404 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:43,408 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:43,409 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:43,409 INFO L745 eck$LassoCheckResult]: Stem: 7487#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7488#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8417#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8418#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8876#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 8744#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7774#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7244#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7245#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8512#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8651#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9034#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9035#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7997#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7998#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8540#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8462#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8463#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8615#L1206 assume !(0 == ~M_E~0); 7979#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7980#L1211-1 assume !(0 == ~T2_E~0); 8869#L1216-1 assume !(0 == ~T3_E~0); 7751#L1221-1 assume !(0 == ~T4_E~0); 7752#L1226-1 assume !(0 == ~T5_E~0); 7424#L1231-1 assume !(0 == ~T6_E~0); 7425#L1236-1 assume !(0 == ~T7_E~0); 8908#L1241-1 assume !(0 == ~T8_E~0); 7821#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7822#L1251-1 assume !(0 == ~T10_E~0); 8053#L1256-1 assume !(0 == ~T11_E~0); 7254#L1261-1 assume !(0 == ~T12_E~0); 7255#L1266-1 assume !(0 == ~E_M~0); 9020#L1271-1 assume !(0 == ~E_1~0); 8641#L1276-1 assume !(0 == ~E_2~0); 8642#L1281-1 assume !(0 == ~E_3~0); 8569#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7650#L1291-1 assume !(0 == ~E_5~0); 7651#L1296-1 assume !(0 == ~E_6~0); 8373#L1301-1 assume !(0 == ~E_7~0); 8374#L1306-1 assume !(0 == ~E_8~0); 8810#L1311-1 assume !(0 == ~E_9~0); 7610#L1316-1 assume !(0 == ~E_10~0); 7611#L1321-1 assume !(0 == ~E_11~0); 8388#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 7475#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7476#L598 assume 1 == ~m_pc~0; 7525#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7526#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8271#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8272#L1497 assume !(0 != activate_threads_~tmp~1#1); 8983#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8932#L617 assume !(1 == ~t1_pc~0); 7843#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7844#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8723#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8724#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8479#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8480#L636 assume 1 == ~t2_pc~0; 7812#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7813#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7632#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7633#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 8511#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8169#L655 assume !(1 == ~t3_pc~0); 8170#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8895#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8711#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8712#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 9021#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9022#L674 assume 1 == ~t4_pc~0; 7338#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7339#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7365#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7366#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 7634#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8168#L693 assume !(1 == ~t5_pc~0); 8324#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7981#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7982#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8812#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 8066#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8001#L712 assume 1 == ~t6_pc~0; 8002#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8422#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7620#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7621#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 8528#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8521#L731 assume 1 == ~t7_pc~0; 7477#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7478#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7678#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8815#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 8753#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7583#L750 assume !(1 == ~t8_pc~0); 7275#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7274#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7785#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8825#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7932#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7933#L769 assume 1 == ~t9_pc~0; 8475#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7442#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7443#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7666#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 8688#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8773#L788 assume !(1 == ~t10_pc~0); 8340#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8341#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8896#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8848#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 7579#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7580#L807 assume 1 == ~t11_pc~0; 8779#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8355#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8513#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8952#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 9046#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8879#L826 assume !(1 == ~t12_pc~0); 8004#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8005#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7319#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7320#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 8162#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8074#L1344 assume !(1 == ~M_E~0); 8075#L1344-2 assume !(1 == ~T1_E~0); 8204#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8379#L1354-1 assume !(1 == ~T3_E~0); 8380#L1359-1 assume !(1 == ~T4_E~0); 8764#L1364-1 assume !(1 == ~T5_E~0); 7697#L1369-1 assume !(1 == ~T6_E~0); 7698#L1374-1 assume !(1 == ~T7_E~0); 8386#L1379-1 assume !(1 == ~T8_E~0); 8387#L1384-1 assume !(1 == ~T9_E~0); 8461#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8910#L1394-1 assume !(1 == ~T11_E~0); 8911#L1399-1 assume !(1 == ~T12_E~0); 8991#L1404-1 assume !(1 == ~E_M~0); 7824#L1409-1 assume !(1 == ~E_1~0); 7825#L1414-1 assume !(1 == ~E_2~0); 8667#L1419-1 assume !(1 == ~E_3~0); 7455#L1424-1 assume !(1 == ~E_4~0); 7456#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 8395#L1434-1 assume !(1 == ~E_6~0); 8925#L1439-1 assume !(1 == ~E_7~0); 7496#L1444-1 assume !(1 == ~E_8~0); 7497#L1449-1 assume !(1 == ~E_9~0); 7937#L1454-1 assume !(1 == ~E_10~0); 7938#L1459-1 assume !(1 == ~E_11~0); 8491#L1464-1 assume !(1 == ~E_12~0); 8492#L1469-1 assume { :end_inline_reset_delta_events } true; 8541#L1815-2 [2024-11-19 15:03:43,410 INFO L747 eck$LassoCheckResult]: Loop: 8541#L1815-2 assume !false; 8689#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7851#L1181-1 assume !false; 8789#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8377#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7247#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7974#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8520#L1008 assume !(0 != eval_~tmp~0#1); 8216#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7832#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7833#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9041#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8490#L1211-3 assume !(0 == ~T2_E~0); 7565#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7566#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8184#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7637#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7638#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7975#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8961#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8863#L1251-3 assume !(0 == ~T10_E~0); 8600#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7589#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7590#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7635#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7636#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8125#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8126#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8664#L1291-3 assume !(0 == ~E_5~0); 8665#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9027#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8988#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8245#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7511#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7512#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7591#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 8349#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8675#L598-42 assume 1 == ~m_pc~0; 8676#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8796#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8006#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8007#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8989#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8402#L617-42 assume 1 == ~t1_pc~0; 8178#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8049#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8050#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8986#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7745#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7746#L636-42 assume !(1 == ~t2_pc~0); 8214#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 8215#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8294#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8295#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 8760#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8625#L655-42 assume 1 == ~t3_pc~0; 8626#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8191#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8702#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8703#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8894#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8831#L674-42 assume !(1 == ~t4_pc~0); 8608#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8529#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8530#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8735#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8322#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8323#L693-42 assume 1 == ~t5_pc~0; 8588#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8589#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8375#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8376#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8645#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7947#L712-42 assume !(1 == ~t6_pc~0); 7948#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8263#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7581#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7582#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8058#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8059#L731-42 assume !(1 == ~t7_pc~0); 7737#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 7738#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8398#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7964#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7965#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7645#L750-42 assume 1 == ~t8_pc~0; 7646#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8232#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8536#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7528#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7529#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8321#L769-42 assume 1 == ~t9_pc~0; 8149#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8150#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8836#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9030#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 7747#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7748#L788-42 assume 1 == ~t10_pc~0; 8329#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8555#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8526#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8527#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9039#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9014#L807-42 assume !(1 == ~t11_pc~0); 7361#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 7362#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8236#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7483#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7484#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7742#L826-42 assume !(1 == ~t12_pc~0); 7744#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 7953#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8345#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7732#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 7733#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8604#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8605#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8531#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7904#L1354-3 assume !(1 == ~T3_E~0); 7905#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8545#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9017#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8924#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7654#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7655#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7902#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7903#L1394-3 assume !(1 == ~T11_E~0); 8196#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8930#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8901#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8902#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8960#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8742#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7542#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7543#L1434-3 assume !(1 == ~E_6~0); 8544#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7489#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7490#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7597#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8538#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8539#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8923#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8406#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7407#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7408#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7571#L1834 assume !(0 == start_simulation_~tmp~3#1); 8652#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8669#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8110#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7296#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7297#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8913#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8909#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8743#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 8541#L1815-2 [2024-11-19 15:03:43,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:43,412 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2024-11-19 15:03:43,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:43,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847022256] [2024-11-19 15:03:43,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:43,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:43,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:43,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:43,533 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:43,533 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847022256] [2024-11-19 15:03:43,533 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1847022256] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:43,533 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:43,533 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:43,533 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852404276] [2024-11-19 15:03:43,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:43,534 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:43,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:43,534 INFO L85 PathProgramCache]: Analyzing trace with hash 515624925, now seen corresponding path program 1 times [2024-11-19 15:03:43,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:43,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218200554] [2024-11-19 15:03:43,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:43,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:43,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:43,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:43,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:43,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [218200554] [2024-11-19 15:03:43,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [218200554] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:43,621 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:43,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:43,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1150722240] [2024-11-19 15:03:43,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:43,621 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:43,621 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:43,622 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:43,622 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:43,622 INFO L87 Difference]: Start difference. First operand 1803 states and 2667 transitions. cyclomatic complexity: 865 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:43,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:43,645 INFO L93 Difference]: Finished difference Result 1803 states and 2666 transitions. [2024-11-19 15:03:43,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2666 transitions. [2024-11-19 15:03:43,655 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:43,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2666 transitions. [2024-11-19 15:03:43,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:43,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:43,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2666 transitions. [2024-11-19 15:03:43,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:43,664 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2666 transitions. [2024-11-19 15:03:43,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2666 transitions. [2024-11-19 15:03:43,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:43,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.478646699944537) internal successors, (2666), 1802 states have internal predecessors, (2666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:43,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2666 transitions. [2024-11-19 15:03:43,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2666 transitions. [2024-11-19 15:03:43,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:43,684 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2666 transitions. [2024-11-19 15:03:43,684 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-19 15:03:43,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2666 transitions. [2024-11-19 15:03:43,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:43,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:43,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:43,694 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:43,694 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:43,694 INFO L745 eck$LassoCheckResult]: Stem: 11100#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 12030#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12031#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12489#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 12357#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11387#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10857#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10858#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12125#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12264#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12647#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12648#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11610#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11611#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12153#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12075#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12076#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12228#L1206 assume !(0 == ~M_E~0); 11592#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11593#L1211-1 assume !(0 == ~T2_E~0); 12482#L1216-1 assume !(0 == ~T3_E~0); 11364#L1221-1 assume !(0 == ~T4_E~0); 11365#L1226-1 assume !(0 == ~T5_E~0); 11037#L1231-1 assume !(0 == ~T6_E~0); 11038#L1236-1 assume !(0 == ~T7_E~0); 12521#L1241-1 assume !(0 == ~T8_E~0); 11434#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11435#L1251-1 assume !(0 == ~T10_E~0); 11666#L1256-1 assume !(0 == ~T11_E~0); 10867#L1261-1 assume !(0 == ~T12_E~0); 10868#L1266-1 assume !(0 == ~E_M~0); 12633#L1271-1 assume !(0 == ~E_1~0); 12254#L1276-1 assume !(0 == ~E_2~0); 12255#L1281-1 assume !(0 == ~E_3~0); 12182#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 11263#L1291-1 assume !(0 == ~E_5~0); 11264#L1296-1 assume !(0 == ~E_6~0); 11986#L1301-1 assume !(0 == ~E_7~0); 11987#L1306-1 assume !(0 == ~E_8~0); 12423#L1311-1 assume !(0 == ~E_9~0); 11223#L1316-1 assume !(0 == ~E_10~0); 11224#L1321-1 assume !(0 == ~E_11~0); 12001#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11088#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11089#L598 assume 1 == ~m_pc~0; 11138#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11139#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11884#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11885#L1497 assume !(0 != activate_threads_~tmp~1#1); 12596#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12545#L617 assume !(1 == ~t1_pc~0); 11456#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11457#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12336#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12337#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12092#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12093#L636 assume 1 == ~t2_pc~0; 11425#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11426#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11245#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11246#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 12124#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11782#L655 assume !(1 == ~t3_pc~0); 11783#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12508#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12324#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12325#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 12634#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12635#L674 assume 1 == ~t4_pc~0; 10951#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10952#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10978#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10979#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 11247#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11781#L693 assume !(1 == ~t5_pc~0); 11937#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11594#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11595#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12425#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 11679#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11614#L712 assume 1 == ~t6_pc~0; 11615#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12035#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11233#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11234#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 12141#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12134#L731 assume 1 == ~t7_pc~0; 11090#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11091#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11291#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12428#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 12366#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11196#L750 assume !(1 == ~t8_pc~0); 10888#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10887#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11398#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12438#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11545#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11546#L769 assume 1 == ~t9_pc~0; 12088#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11055#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11056#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11279#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 12301#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12386#L788 assume !(1 == ~t10_pc~0); 11953#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11954#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12509#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12461#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 11192#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 11193#L807 assume 1 == ~t11_pc~0; 12392#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11968#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12126#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12565#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 12659#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12492#L826 assume !(1 == ~t12_pc~0); 11617#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11618#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10932#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10933#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 11775#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11687#L1344 assume !(1 == ~M_E~0); 11688#L1344-2 assume !(1 == ~T1_E~0); 11817#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11992#L1354-1 assume !(1 == ~T3_E~0); 11993#L1359-1 assume !(1 == ~T4_E~0); 12377#L1364-1 assume !(1 == ~T5_E~0); 11310#L1369-1 assume !(1 == ~T6_E~0); 11311#L1374-1 assume !(1 == ~T7_E~0); 11999#L1379-1 assume !(1 == ~T8_E~0); 12000#L1384-1 assume !(1 == ~T9_E~0); 12074#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12523#L1394-1 assume !(1 == ~T11_E~0); 12524#L1399-1 assume !(1 == ~T12_E~0); 12604#L1404-1 assume !(1 == ~E_M~0); 11437#L1409-1 assume !(1 == ~E_1~0); 11438#L1414-1 assume !(1 == ~E_2~0); 12280#L1419-1 assume !(1 == ~E_3~0); 11068#L1424-1 assume !(1 == ~E_4~0); 11069#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 12008#L1434-1 assume !(1 == ~E_6~0); 12538#L1439-1 assume !(1 == ~E_7~0); 11109#L1444-1 assume !(1 == ~E_8~0); 11110#L1449-1 assume !(1 == ~E_9~0); 11550#L1454-1 assume !(1 == ~E_10~0); 11551#L1459-1 assume !(1 == ~E_11~0); 12104#L1464-1 assume !(1 == ~E_12~0); 12105#L1469-1 assume { :end_inline_reset_delta_events } true; 12154#L1815-2 [2024-11-19 15:03:43,695 INFO L747 eck$LassoCheckResult]: Loop: 12154#L1815-2 assume !false; 12302#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11464#L1181-1 assume !false; 12402#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11990#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10860#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11587#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12133#L1008 assume !(0 != eval_~tmp~0#1); 11829#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11445#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11446#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12654#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12103#L1211-3 assume !(0 == ~T2_E~0); 11178#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11179#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11797#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11250#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11251#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11588#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12574#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12476#L1251-3 assume !(0 == ~T10_E~0); 12213#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11202#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11203#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11248#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11249#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11738#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11739#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12277#L1291-3 assume !(0 == ~E_5~0); 12278#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12640#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12601#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11858#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11124#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11125#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11204#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11962#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12288#L598-42 assume 1 == ~m_pc~0; 12289#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12409#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11619#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11620#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12602#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12015#L617-42 assume !(1 == ~t1_pc~0); 11792#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 11662#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11663#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12599#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11358#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11359#L636-42 assume !(1 == ~t2_pc~0); 11827#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 11828#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11907#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11908#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 12373#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12238#L655-42 assume !(1 == ~t3_pc~0); 11803#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 11804#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12315#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12316#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12507#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12444#L674-42 assume !(1 == ~t4_pc~0); 12221#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12142#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12143#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12348#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11935#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11936#L693-42 assume 1 == ~t5_pc~0; 12201#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12202#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11988#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11989#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12258#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11560#L712-42 assume !(1 == ~t6_pc~0); 11561#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 11876#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11194#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11195#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11671#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11672#L731-42 assume !(1 == ~t7_pc~0); 11350#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 11351#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12011#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11577#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11578#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11258#L750-42 assume 1 == ~t8_pc~0; 11259#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11845#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12149#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11141#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11142#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11934#L769-42 assume 1 == ~t9_pc~0; 11762#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11763#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12449#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12643#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 11360#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11361#L788-42 assume 1 == ~t10_pc~0; 11942#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12168#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12139#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12140#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12652#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12627#L807-42 assume 1 == ~t11_pc~0; 12297#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10975#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11849#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11096#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11097#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11355#L826-42 assume 1 == ~t12_pc~0; 11356#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11566#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11958#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11345#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11346#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12217#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12218#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12144#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11517#L1354-3 assume !(1 == ~T3_E~0); 11518#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12158#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12630#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12537#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11267#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11268#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11515#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11516#L1394-3 assume !(1 == ~T11_E~0); 11809#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12543#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12514#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12515#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12573#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12355#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11155#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11156#L1434-3 assume !(1 == ~E_6~0); 12157#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11102#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11103#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11210#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12151#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12152#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12536#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 12019#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11020#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11021#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11184#L1834 assume !(0 == start_simulation_~tmp~3#1); 12265#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 12282#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11723#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10909#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 10910#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12526#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12522#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 12356#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 12154#L1815-2 [2024-11-19 15:03:43,695 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:43,695 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2024-11-19 15:03:43,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:43,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918685564] [2024-11-19 15:03:43,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:43,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:43,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:43,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:43,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:43,744 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [918685564] [2024-11-19 15:03:43,744 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [918685564] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:43,744 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:43,744 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:43,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595765024] [2024-11-19 15:03:43,745 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:43,745 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:43,745 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:43,746 INFO L85 PathProgramCache]: Analyzing trace with hash 2104456605, now seen corresponding path program 1 times [2024-11-19 15:03:43,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:43,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1913924406] [2024-11-19 15:03:43,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:43,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:43,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:43,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:43,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:43,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1913924406] [2024-11-19 15:03:43,812 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1913924406] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:43,812 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:43,813 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:43,813 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690401482] [2024-11-19 15:03:43,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:43,813 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:43,813 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:43,814 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:43,814 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:43,814 INFO L87 Difference]: Start difference. First operand 1803 states and 2666 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:43,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:43,838 INFO L93 Difference]: Finished difference Result 1803 states and 2665 transitions. [2024-11-19 15:03:43,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2665 transitions. [2024-11-19 15:03:43,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:43,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2665 transitions. [2024-11-19 15:03:43,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:43,852 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:43,852 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2665 transitions. [2024-11-19 15:03:43,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:43,855 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2665 transitions. [2024-11-19 15:03:43,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2665 transitions. [2024-11-19 15:03:43,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:43,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.4780920687742651) internal successors, (2665), 1802 states have internal predecessors, (2665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:43,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2665 transitions. [2024-11-19 15:03:43,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2665 transitions. [2024-11-19 15:03:43,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:43,882 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2665 transitions. [2024-11-19 15:03:43,883 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-19 15:03:43,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2665 transitions. [2024-11-19 15:03:43,888 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:43,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:43,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:43,890 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:43,891 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:43,892 INFO L745 eck$LassoCheckResult]: Stem: 14713#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 14714#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15643#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15644#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16102#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 15970#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15000#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14470#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14471#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15738#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15877#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16260#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16261#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15223#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15224#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15766#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15688#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15689#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15841#L1206 assume !(0 == ~M_E~0); 15205#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15206#L1211-1 assume !(0 == ~T2_E~0); 16095#L1216-1 assume !(0 == ~T3_E~0); 14977#L1221-1 assume !(0 == ~T4_E~0); 14978#L1226-1 assume !(0 == ~T5_E~0); 14650#L1231-1 assume !(0 == ~T6_E~0); 14651#L1236-1 assume !(0 == ~T7_E~0); 16134#L1241-1 assume !(0 == ~T8_E~0); 15047#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15048#L1251-1 assume !(0 == ~T10_E~0); 15279#L1256-1 assume !(0 == ~T11_E~0); 14480#L1261-1 assume !(0 == ~T12_E~0); 14481#L1266-1 assume !(0 == ~E_M~0); 16246#L1271-1 assume !(0 == ~E_1~0); 15867#L1276-1 assume !(0 == ~E_2~0); 15868#L1281-1 assume !(0 == ~E_3~0); 15795#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14876#L1291-1 assume !(0 == ~E_5~0); 14877#L1296-1 assume !(0 == ~E_6~0); 15599#L1301-1 assume !(0 == ~E_7~0); 15600#L1306-1 assume !(0 == ~E_8~0); 16036#L1311-1 assume !(0 == ~E_9~0); 14836#L1316-1 assume !(0 == ~E_10~0); 14837#L1321-1 assume !(0 == ~E_11~0); 15614#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 14701#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14702#L598 assume 1 == ~m_pc~0; 14751#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14752#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15497#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15498#L1497 assume !(0 != activate_threads_~tmp~1#1); 16209#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16158#L617 assume !(1 == ~t1_pc~0); 15069#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15070#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15949#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15950#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15705#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15706#L636 assume 1 == ~t2_pc~0; 15038#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15039#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14858#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14859#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 15737#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15395#L655 assume !(1 == ~t3_pc~0); 15396#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16121#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15937#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15938#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 16247#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16248#L674 assume 1 == ~t4_pc~0; 14564#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14565#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14591#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14592#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 14860#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15394#L693 assume !(1 == ~t5_pc~0); 15550#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15207#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15208#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16038#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 15292#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15227#L712 assume 1 == ~t6_pc~0; 15228#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15648#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14846#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14847#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 15754#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15747#L731 assume 1 == ~t7_pc~0; 14703#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14704#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14904#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16041#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 15979#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14809#L750 assume !(1 == ~t8_pc~0); 14501#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14500#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15011#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16051#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15158#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15159#L769 assume 1 == ~t9_pc~0; 15701#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14668#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14669#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14892#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 15914#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15999#L788 assume !(1 == ~t10_pc~0); 15566#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15567#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16122#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16074#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 14805#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14806#L807 assume 1 == ~t11_pc~0; 16005#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15581#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15739#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16178#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 16272#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16105#L826 assume !(1 == ~t12_pc~0); 15230#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15231#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14545#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14546#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 15388#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15300#L1344 assume !(1 == ~M_E~0); 15301#L1344-2 assume !(1 == ~T1_E~0); 15430#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15605#L1354-1 assume !(1 == ~T3_E~0); 15606#L1359-1 assume !(1 == ~T4_E~0); 15990#L1364-1 assume !(1 == ~T5_E~0); 14923#L1369-1 assume !(1 == ~T6_E~0); 14924#L1374-1 assume !(1 == ~T7_E~0); 15612#L1379-1 assume !(1 == ~T8_E~0); 15613#L1384-1 assume !(1 == ~T9_E~0); 15687#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16136#L1394-1 assume !(1 == ~T11_E~0); 16137#L1399-1 assume !(1 == ~T12_E~0); 16217#L1404-1 assume !(1 == ~E_M~0); 15050#L1409-1 assume !(1 == ~E_1~0); 15051#L1414-1 assume !(1 == ~E_2~0); 15893#L1419-1 assume !(1 == ~E_3~0); 14681#L1424-1 assume !(1 == ~E_4~0); 14682#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 15621#L1434-1 assume !(1 == ~E_6~0); 16151#L1439-1 assume !(1 == ~E_7~0); 14722#L1444-1 assume !(1 == ~E_8~0); 14723#L1449-1 assume !(1 == ~E_9~0); 15163#L1454-1 assume !(1 == ~E_10~0); 15164#L1459-1 assume !(1 == ~E_11~0); 15717#L1464-1 assume !(1 == ~E_12~0); 15718#L1469-1 assume { :end_inline_reset_delta_events } true; 15767#L1815-2 [2024-11-19 15:03:43,892 INFO L747 eck$LassoCheckResult]: Loop: 15767#L1815-2 assume !false; 15915#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15077#L1181-1 assume !false; 16015#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15603#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14473#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15200#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15746#L1008 assume !(0 != eval_~tmp~0#1); 15442#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15058#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15059#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16267#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15716#L1211-3 assume !(0 == ~T2_E~0); 14791#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14792#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15410#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14863#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14864#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15201#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16187#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16089#L1251-3 assume !(0 == ~T10_E~0); 15826#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14815#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14816#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14861#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14862#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15351#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15352#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15890#L1291-3 assume !(0 == ~E_5~0); 15891#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16253#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16214#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15471#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14737#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14738#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14817#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 15575#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15901#L598-42 assume 1 == ~m_pc~0; 15902#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16022#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15232#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15233#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16215#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15628#L617-42 assume 1 == ~t1_pc~0; 15404#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15275#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15276#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16212#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14971#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14972#L636-42 assume !(1 == ~t2_pc~0); 15440#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 15441#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15520#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15521#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 15986#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15851#L655-42 assume !(1 == ~t3_pc~0); 15416#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 15417#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15928#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15929#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16120#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16057#L674-42 assume !(1 == ~t4_pc~0); 15834#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 15755#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15756#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15961#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15548#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15549#L693-42 assume 1 == ~t5_pc~0; 15814#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15815#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15601#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15602#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15871#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15173#L712-42 assume !(1 == ~t6_pc~0); 15174#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 15489#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14807#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14808#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15284#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15285#L731-42 assume !(1 == ~t7_pc~0); 14963#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 14964#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15624#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15190#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15191#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14871#L750-42 assume 1 == ~t8_pc~0; 14872#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15458#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15762#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14754#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14755#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15547#L769-42 assume !(1 == ~t9_pc~0); 15377#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 15376#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16062#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16256#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 14973#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14974#L788-42 assume 1 == ~t10_pc~0; 15555#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15781#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15752#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15753#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16265#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16240#L807-42 assume 1 == ~t11_pc~0; 15910#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14588#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15462#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14709#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14710#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14968#L826-42 assume 1 == ~t12_pc~0; 14969#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15179#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15571#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14958#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14959#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15830#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15831#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15757#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15130#L1354-3 assume !(1 == ~T3_E~0); 15131#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15771#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16243#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16150#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14880#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14881#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15128#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15129#L1394-3 assume !(1 == ~T11_E~0); 15422#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16156#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16127#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16128#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16186#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15968#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14768#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14769#L1434-3 assume !(1 == ~E_6~0); 15770#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14715#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14716#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14823#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15764#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15765#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16149#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15632#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14633#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14634#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 14797#L1834 assume !(0 == start_simulation_~tmp~3#1); 15878#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15895#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15336#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14522#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 14523#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16139#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16135#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 15969#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 15767#L1815-2 [2024-11-19 15:03:43,893 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:43,893 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2024-11-19 15:03:43,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:43,893 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184321373] [2024-11-19 15:03:43,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:43,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:43,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:43,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:43,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:43,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184321373] [2024-11-19 15:03:43,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184321373] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:43,932 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:43,932 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:43,932 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132024454] [2024-11-19 15:03:43,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:43,933 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:43,933 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:43,933 INFO L85 PathProgramCache]: Analyzing trace with hash 1956305821, now seen corresponding path program 1 times [2024-11-19 15:03:43,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:43,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433022453] [2024-11-19 15:03:43,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:43,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:43,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:44,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:44,037 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:44,037 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433022453] [2024-11-19 15:03:44,037 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433022453] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:44,037 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:44,038 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:44,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866665468] [2024-11-19 15:03:44,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:44,039 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:44,039 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:44,039 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:44,039 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:44,040 INFO L87 Difference]: Start difference. First operand 1803 states and 2665 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:44,068 INFO L93 Difference]: Finished difference Result 1803 states and 2664 transitions. [2024-11-19 15:03:44,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2664 transitions. [2024-11-19 15:03:44,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2664 transitions. [2024-11-19 15:03:44,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:44,085 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:44,085 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2664 transitions. [2024-11-19 15:03:44,087 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:44,087 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2664 transitions. [2024-11-19 15:03:44,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2664 transitions. [2024-11-19 15:03:44,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:44,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.4775374376039934) internal successors, (2664), 1802 states have internal predecessors, (2664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2664 transitions. [2024-11-19 15:03:44,113 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2664 transitions. [2024-11-19 15:03:44,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:44,114 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2664 transitions. [2024-11-19 15:03:44,114 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-19 15:03:44,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2664 transitions. [2024-11-19 15:03:44,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:44,121 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:44,123 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,123 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,124 INFO L745 eck$LassoCheckResult]: Stem: 18326#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18327#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19257#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19258#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19715#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 19583#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18613#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18083#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18084#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19352#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19490#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19873#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19874#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18838#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18839#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19379#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19301#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19302#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19454#L1206 assume !(0 == ~M_E~0); 18818#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18819#L1211-1 assume !(0 == ~T2_E~0); 19709#L1216-1 assume !(0 == ~T3_E~0); 18590#L1221-1 assume !(0 == ~T4_E~0); 18591#L1226-1 assume !(0 == ~T5_E~0); 18265#L1231-1 assume !(0 == ~T6_E~0); 18266#L1236-1 assume !(0 == ~T7_E~0); 19747#L1241-1 assume !(0 == ~T8_E~0); 18660#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18661#L1251-1 assume !(0 == ~T10_E~0); 18892#L1256-1 assume !(0 == ~T11_E~0); 18093#L1261-1 assume !(0 == ~T12_E~0); 18094#L1266-1 assume !(0 == ~E_M~0); 19859#L1271-1 assume !(0 == ~E_1~0); 19480#L1276-1 assume !(0 == ~E_2~0); 19481#L1281-1 assume !(0 == ~E_3~0); 19410#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 18489#L1291-1 assume !(0 == ~E_5~0); 18490#L1296-1 assume !(0 == ~E_6~0); 19212#L1301-1 assume !(0 == ~E_7~0); 19213#L1306-1 assume !(0 == ~E_8~0); 19649#L1311-1 assume !(0 == ~E_9~0); 18449#L1316-1 assume !(0 == ~E_10~0); 18450#L1321-1 assume !(0 == ~E_11~0); 19227#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18314#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18315#L598 assume 1 == ~m_pc~0; 18364#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18365#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19110#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19111#L1497 assume !(0 != activate_threads_~tmp~1#1); 19822#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19771#L617 assume !(1 == ~t1_pc~0); 18682#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18683#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19562#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19563#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19318#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19319#L636 assume 1 == ~t2_pc~0; 18651#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18652#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18471#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18472#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 19350#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19009#L655 assume !(1 == ~t3_pc~0); 19010#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19734#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19550#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19551#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 19860#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19861#L674 assume 1 == ~t4_pc~0; 18177#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18178#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18205#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 18475#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19007#L693 assume !(1 == ~t5_pc~0); 19164#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18822#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18823#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19651#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 18907#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18840#L712 assume 1 == ~t6_pc~0; 18841#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19261#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18459#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18460#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 19367#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19360#L731 assume 1 == ~t7_pc~0; 18316#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18317#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18517#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19654#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 19593#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18422#L750 assume !(1 == ~t8_pc~0); 18114#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18113#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18624#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19664#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18771#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18772#L769 assume 1 == ~t9_pc~0; 19314#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18281#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18282#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18505#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 19527#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19612#L788 assume !(1 == ~t10_pc~0); 19179#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19180#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19735#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19687#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 18418#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18419#L807 assume 1 == ~t11_pc~0; 19618#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19194#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19351#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19791#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 19885#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19718#L826 assume !(1 == ~t12_pc~0); 18843#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18844#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18158#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18159#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 19001#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18913#L1344 assume !(1 == ~M_E~0); 18914#L1344-2 assume !(1 == ~T1_E~0); 19043#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19218#L1354-1 assume !(1 == ~T3_E~0); 19219#L1359-1 assume !(1 == ~T4_E~0); 19603#L1364-1 assume !(1 == ~T5_E~0); 18536#L1369-1 assume !(1 == ~T6_E~0); 18537#L1374-1 assume !(1 == ~T7_E~0); 19225#L1379-1 assume !(1 == ~T8_E~0); 19226#L1384-1 assume !(1 == ~T9_E~0); 19300#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19749#L1394-1 assume !(1 == ~T11_E~0); 19750#L1399-1 assume !(1 == ~T12_E~0); 19830#L1404-1 assume !(1 == ~E_M~0); 18663#L1409-1 assume !(1 == ~E_1~0); 18664#L1414-1 assume !(1 == ~E_2~0); 19506#L1419-1 assume !(1 == ~E_3~0); 18294#L1424-1 assume !(1 == ~E_4~0); 18295#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19234#L1434-1 assume !(1 == ~E_6~0); 19764#L1439-1 assume !(1 == ~E_7~0); 18335#L1444-1 assume !(1 == ~E_8~0); 18336#L1449-1 assume !(1 == ~E_9~0); 18776#L1454-1 assume !(1 == ~E_10~0); 18777#L1459-1 assume !(1 == ~E_11~0); 19330#L1464-1 assume !(1 == ~E_12~0); 19331#L1469-1 assume { :end_inline_reset_delta_events } true; 19380#L1815-2 [2024-11-19 15:03:44,124 INFO L747 eck$LassoCheckResult]: Loop: 19380#L1815-2 assume !false; 19528#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18690#L1181-1 assume !false; 19628#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19216#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18086#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18813#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19359#L1008 assume !(0 != eval_~tmp~0#1); 19055#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18671#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18672#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19880#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19329#L1211-3 assume !(0 == ~T2_E~0); 18404#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18405#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19023#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18476#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18477#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18814#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19800#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19702#L1251-3 assume !(0 == ~T10_E~0); 19439#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18428#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18429#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18473#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18474#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18964#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18965#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19503#L1291-3 assume !(0 == ~E_5~0); 19504#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19866#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19827#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19084#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18350#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18351#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18430#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 19188#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19514#L598-42 assume 1 == ~m_pc~0; 19515#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19635#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18845#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18846#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19828#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19241#L617-42 assume 1 == ~t1_pc~0; 19017#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18888#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18889#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19825#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18584#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18585#L636-42 assume !(1 == ~t2_pc~0); 19053#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 19054#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19133#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19134#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 19599#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19464#L655-42 assume !(1 == ~t3_pc~0); 19029#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19030#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19541#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19542#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19733#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19670#L674-42 assume !(1 == ~t4_pc~0); 19447#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 19368#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19369#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19574#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19161#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19162#L693-42 assume 1 == ~t5_pc~0; 19427#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19428#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19214#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19215#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19484#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18786#L712-42 assume !(1 == ~t6_pc~0); 18787#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 19102#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18420#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18421#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18897#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18898#L731-42 assume !(1 == ~t7_pc~0); 18576#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18577#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19237#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18803#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18804#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18484#L750-42 assume 1 == ~t8_pc~0; 18485#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19071#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19375#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18367#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18368#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19160#L769-42 assume 1 == ~t9_pc~0; 18988#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18989#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19675#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19869#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 18586#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18587#L788-42 assume 1 == ~t10_pc~0; 19168#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19394#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19365#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19366#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19878#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19853#L807-42 assume 1 == ~t11_pc~0; 19523#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18201#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19075#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18322#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18323#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18581#L826-42 assume 1 == ~t12_pc~0; 18582#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18792#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19184#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18571#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18572#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19443#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19444#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19370#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18743#L1354-3 assume !(1 == ~T3_E~0); 18744#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19384#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19856#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19763#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18493#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18494#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18741#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18742#L1394-3 assume !(1 == ~T11_E~0); 19035#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19769#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19740#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19741#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19799#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19581#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18381#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18382#L1434-3 assume !(1 == ~E_6~0); 19383#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18328#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18329#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18436#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19377#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19378#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19762#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19245#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18246#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18247#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18410#L1834 assume !(0 == start_simulation_~tmp~3#1); 19491#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19508#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18949#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18135#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 18136#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19752#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19748#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19582#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 19380#L1815-2 [2024-11-19 15:03:44,125 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:44,125 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2024-11-19 15:03:44,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:44,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148985148] [2024-11-19 15:03:44,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:44,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:44,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:44,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:44,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:44,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148985148] [2024-11-19 15:03:44,174 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1148985148] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:44,174 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:44,174 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:44,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773238212] [2024-11-19 15:03:44,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:44,175 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:44,175 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:44,175 INFO L85 PathProgramCache]: Analyzing trace with hash 1379377180, now seen corresponding path program 1 times [2024-11-19 15:03:44,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:44,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536389384] [2024-11-19 15:03:44,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:44,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:44,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:44,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:44,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:44,240 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536389384] [2024-11-19 15:03:44,240 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [536389384] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:44,240 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:44,240 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:44,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [290833053] [2024-11-19 15:03:44,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:44,242 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:44,242 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:44,242 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:44,243 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:44,243 INFO L87 Difference]: Start difference. First operand 1803 states and 2664 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:44,272 INFO L93 Difference]: Finished difference Result 1803 states and 2663 transitions. [2024-11-19 15:03:44,272 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2663 transitions. [2024-11-19 15:03:44,279 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2663 transitions. [2024-11-19 15:03:44,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:44,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:44,286 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2663 transitions. [2024-11-19 15:03:44,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:44,288 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2663 transitions. [2024-11-19 15:03:44,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2663 transitions. [2024-11-19 15:03:44,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:44,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.4769828064337216) internal successors, (2663), 1802 states have internal predecessors, (2663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2663 transitions. [2024-11-19 15:03:44,316 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2663 transitions. [2024-11-19 15:03:44,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:44,318 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2663 transitions. [2024-11-19 15:03:44,318 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-19 15:03:44,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2663 transitions. [2024-11-19 15:03:44,323 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:44,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:44,326 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,326 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,326 INFO L745 eck$LassoCheckResult]: Stem: 21939#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 21940#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 22869#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22870#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23328#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 23196#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22226#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21696#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21697#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22964#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23103#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23486#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23487#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22451#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22452#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22992#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22914#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22915#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23067#L1206 assume !(0 == ~M_E~0); 22431#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22432#L1211-1 assume !(0 == ~T2_E~0); 23322#L1216-1 assume !(0 == ~T3_E~0); 22203#L1221-1 assume !(0 == ~T4_E~0); 22204#L1226-1 assume !(0 == ~T5_E~0); 21878#L1231-1 assume !(0 == ~T6_E~0); 21879#L1236-1 assume !(0 == ~T7_E~0); 23360#L1241-1 assume !(0 == ~T8_E~0); 22273#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22274#L1251-1 assume !(0 == ~T10_E~0); 22505#L1256-1 assume !(0 == ~T11_E~0); 21706#L1261-1 assume !(0 == ~T12_E~0); 21707#L1266-1 assume !(0 == ~E_M~0); 23472#L1271-1 assume !(0 == ~E_1~0); 23093#L1276-1 assume !(0 == ~E_2~0); 23094#L1281-1 assume !(0 == ~E_3~0); 23023#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 22102#L1291-1 assume !(0 == ~E_5~0); 22103#L1296-1 assume !(0 == ~E_6~0); 22825#L1301-1 assume !(0 == ~E_7~0); 22826#L1306-1 assume !(0 == ~E_8~0); 23262#L1311-1 assume !(0 == ~E_9~0); 22062#L1316-1 assume !(0 == ~E_10~0); 22063#L1321-1 assume !(0 == ~E_11~0); 22840#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 21927#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21928#L598 assume 1 == ~m_pc~0; 21977#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21978#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22723#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22724#L1497 assume !(0 != activate_threads_~tmp~1#1); 23435#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23384#L617 assume !(1 == ~t1_pc~0); 22295#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22296#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23175#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23176#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22931#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22932#L636 assume 1 == ~t2_pc~0; 22264#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22265#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22084#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22085#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 22963#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22621#L655 assume !(1 == ~t3_pc~0); 22622#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23347#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23163#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23164#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 23473#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23474#L674 assume 1 == ~t4_pc~0; 21790#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21791#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21817#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21818#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 22086#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22620#L693 assume !(1 == ~t5_pc~0); 22777#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 22435#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22436#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23264#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 22520#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22453#L712 assume 1 == ~t6_pc~0; 22454#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22874#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22072#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22073#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 22980#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22973#L731 assume 1 == ~t7_pc~0; 21929#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21930#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22130#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23267#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 23205#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22035#L750 assume !(1 == ~t8_pc~0); 21727#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 21726#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22237#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23277#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22384#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22385#L769 assume 1 == ~t9_pc~0; 22929#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21894#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21895#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22118#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 23140#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23225#L788 assume !(1 == ~t10_pc~0); 22792#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22793#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23348#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23301#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 22031#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22032#L807 assume 1 == ~t11_pc~0; 23231#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22807#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22965#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23404#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 23498#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23331#L826 assume !(1 == ~t12_pc~0); 22456#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22457#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21771#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21772#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 22614#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22526#L1344 assume !(1 == ~M_E~0); 22527#L1344-2 assume !(1 == ~T1_E~0); 22656#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22833#L1354-1 assume !(1 == ~T3_E~0); 22834#L1359-1 assume !(1 == ~T4_E~0); 23216#L1364-1 assume !(1 == ~T5_E~0); 22149#L1369-1 assume !(1 == ~T6_E~0); 22150#L1374-1 assume !(1 == ~T7_E~0); 22838#L1379-1 assume !(1 == ~T8_E~0); 22839#L1384-1 assume !(1 == ~T9_E~0); 22913#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 23362#L1394-1 assume !(1 == ~T11_E~0); 23363#L1399-1 assume !(1 == ~T12_E~0); 23443#L1404-1 assume !(1 == ~E_M~0); 22276#L1409-1 assume !(1 == ~E_1~0); 22277#L1414-1 assume !(1 == ~E_2~0); 23119#L1419-1 assume !(1 == ~E_3~0); 21907#L1424-1 assume !(1 == ~E_4~0); 21908#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22849#L1434-1 assume !(1 == ~E_6~0); 23377#L1439-1 assume !(1 == ~E_7~0); 21948#L1444-1 assume !(1 == ~E_8~0); 21949#L1449-1 assume !(1 == ~E_9~0); 22390#L1454-1 assume !(1 == ~E_10~0); 22391#L1459-1 assume !(1 == ~E_11~0); 22943#L1464-1 assume !(1 == ~E_12~0); 22944#L1469-1 assume { :end_inline_reset_delta_events } true; 22993#L1815-2 [2024-11-19 15:03:44,327 INFO L747 eck$LassoCheckResult]: Loop: 22993#L1815-2 assume !false; 23141#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22305#L1181-1 assume !false; 23241#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22829#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21699#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22426#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22972#L1008 assume !(0 != eval_~tmp~0#1); 22668#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22286#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22287#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23493#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22942#L1211-3 assume !(0 == ~T2_E~0); 22017#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22018#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22636#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22089#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22090#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22427#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23415#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23316#L1251-3 assume !(0 == ~T10_E~0); 23052#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22043#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22044#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22087#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22088#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22577#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22578#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23116#L1291-3 assume !(0 == ~E_5~0); 23117#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23479#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23440#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22697#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21963#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21964#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22045#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22800#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23126#L598-42 assume 1 == ~m_pc~0; 23127#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23248#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22458#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22459#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23441#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22853#L617-42 assume 1 == ~t1_pc~0; 22630#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22501#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22502#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23438#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22197#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22198#L636-42 assume !(1 == ~t2_pc~0); 22666#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 22667#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22746#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22747#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 23212#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23077#L655-42 assume !(1 == ~t3_pc~0); 22642#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 22643#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23152#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23153#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23346#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23283#L674-42 assume !(1 == ~t4_pc~0); 23060#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 22981#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22982#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23187#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22774#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22775#L693-42 assume 1 == ~t5_pc~0; 23040#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23041#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22827#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22828#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23097#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22399#L712-42 assume !(1 == ~t6_pc~0); 22400#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 22715#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22033#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22034#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22510#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22511#L731-42 assume !(1 == ~t7_pc~0); 22189#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 22190#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22850#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22415#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22416#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22097#L750-42 assume 1 == ~t8_pc~0; 22098#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22684#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22988#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21980#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21981#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22773#L769-42 assume 1 == ~t9_pc~0; 22601#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22602#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23288#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23482#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 22199#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22200#L788-42 assume 1 == ~t10_pc~0; 22781#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23007#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22978#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22979#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23491#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23465#L807-42 assume 1 == ~t11_pc~0; 23136#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21814#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22688#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21935#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21936#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22194#L826-42 assume 1 == ~t12_pc~0; 22195#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 22405#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22794#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22184#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22185#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23056#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23057#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22983#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22356#L1354-3 assume !(1 == ~T3_E~0); 22357#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22997#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23469#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23376#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22104#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22105#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22354#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22355#L1394-3 assume !(1 == ~T11_E~0); 22648#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23382#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23353#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23354#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23412#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23194#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21994#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21995#L1434-3 assume !(1 == ~E_6~0); 22996#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21941#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21942#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22049#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22990#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 22991#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 23375#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22858#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21859#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21860#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 22023#L1834 assume !(0 == start_simulation_~tmp~3#1); 23104#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 23121#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22562#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21748#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 21749#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23365#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23361#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 23195#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 22993#L1815-2 [2024-11-19 15:03:44,328 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:44,328 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2024-11-19 15:03:44,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:44,329 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517582528] [2024-11-19 15:03:44,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:44,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:44,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:44,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:44,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:44,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517582528] [2024-11-19 15:03:44,365 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517582528] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:44,365 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:44,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:44,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1050132040] [2024-11-19 15:03:44,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:44,366 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:44,366 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:44,367 INFO L85 PathProgramCache]: Analyzing trace with hash 1379377180, now seen corresponding path program 2 times [2024-11-19 15:03:44,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:44,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770283119] [2024-11-19 15:03:44,367 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:03:44,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:44,380 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:03:44,381 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:03:44,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:44,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:44,421 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770283119] [2024-11-19 15:03:44,421 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770283119] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:44,421 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:44,421 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:44,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1043003124] [2024-11-19 15:03:44,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:44,422 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:44,422 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:44,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:44,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:44,423 INFO L87 Difference]: Start difference. First operand 1803 states and 2663 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:44,445 INFO L93 Difference]: Finished difference Result 1803 states and 2662 transitions. [2024-11-19 15:03:44,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2662 transitions. [2024-11-19 15:03:44,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,456 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2662 transitions. [2024-11-19 15:03:44,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:44,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:44,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2662 transitions. [2024-11-19 15:03:44,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:44,459 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2662 transitions. [2024-11-19 15:03:44,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2662 transitions. [2024-11-19 15:03:44,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:44,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.4764281752634498) internal successors, (2662), 1802 states have internal predecessors, (2662), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2662 transitions. [2024-11-19 15:03:44,479 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2662 transitions. [2024-11-19 15:03:44,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:44,481 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2662 transitions. [2024-11-19 15:03:44,481 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-19 15:03:44,481 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2662 transitions. [2024-11-19 15:03:44,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:44,486 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:44,487 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,487 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,488 INFO L745 eck$LassoCheckResult]: Stem: 25552#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25553#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26482#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26483#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26941#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 26809#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25839#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25309#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25310#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26577#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26716#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27099#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27100#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26064#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26065#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26605#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26527#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26528#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26680#L1206 assume !(0 == ~M_E~0); 26044#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26045#L1211-1 assume !(0 == ~T2_E~0); 26935#L1216-1 assume !(0 == ~T3_E~0); 25816#L1221-1 assume !(0 == ~T4_E~0); 25817#L1226-1 assume !(0 == ~T5_E~0); 25489#L1231-1 assume !(0 == ~T6_E~0); 25490#L1236-1 assume !(0 == ~T7_E~0); 26973#L1241-1 assume !(0 == ~T8_E~0); 25886#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25887#L1251-1 assume !(0 == ~T10_E~0); 26118#L1256-1 assume !(0 == ~T11_E~0); 25319#L1261-1 assume !(0 == ~T12_E~0); 25320#L1266-1 assume !(0 == ~E_M~0); 27085#L1271-1 assume !(0 == ~E_1~0); 26706#L1276-1 assume !(0 == ~E_2~0); 26707#L1281-1 assume !(0 == ~E_3~0); 26634#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 25715#L1291-1 assume !(0 == ~E_5~0); 25716#L1296-1 assume !(0 == ~E_6~0); 26438#L1301-1 assume !(0 == ~E_7~0); 26439#L1306-1 assume !(0 == ~E_8~0); 26875#L1311-1 assume !(0 == ~E_9~0); 25675#L1316-1 assume !(0 == ~E_10~0); 25676#L1321-1 assume !(0 == ~E_11~0); 26453#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 25540#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25541#L598 assume 1 == ~m_pc~0; 25590#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25591#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26336#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26337#L1497 assume !(0 != activate_threads_~tmp~1#1); 27048#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26997#L617 assume !(1 == ~t1_pc~0); 25908#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25909#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26788#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26789#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26544#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26545#L636 assume 1 == ~t2_pc~0; 25877#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25878#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25697#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25698#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 26576#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26234#L655 assume !(1 == ~t3_pc~0); 26235#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26960#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26776#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26777#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 27086#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27087#L674 assume 1 == ~t4_pc~0; 25403#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25404#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25430#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25431#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 25699#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26233#L693 assume !(1 == ~t5_pc~0); 26390#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 26048#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26049#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26877#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 26133#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26066#L712 assume 1 == ~t6_pc~0; 26067#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26487#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25685#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25686#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 26593#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26586#L731 assume 1 == ~t7_pc~0; 25542#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25543#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25743#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26880#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 26818#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25648#L750 assume !(1 == ~t8_pc~0); 25340#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25339#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25850#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26890#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25997#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25998#L769 assume 1 == ~t9_pc~0; 26542#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25507#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25508#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25731#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 26753#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26838#L788 assume !(1 == ~t10_pc~0); 26405#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 26406#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26961#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26914#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 25644#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25645#L807 assume 1 == ~t11_pc~0; 26844#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26420#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26578#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27017#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 27111#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26944#L826 assume !(1 == ~t12_pc~0); 26069#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26070#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25384#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25385#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 26227#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26139#L1344 assume !(1 == ~M_E~0); 26140#L1344-2 assume !(1 == ~T1_E~0); 26269#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26446#L1354-1 assume !(1 == ~T3_E~0); 26447#L1359-1 assume !(1 == ~T4_E~0); 26829#L1364-1 assume !(1 == ~T5_E~0); 25762#L1369-1 assume !(1 == ~T6_E~0); 25763#L1374-1 assume !(1 == ~T7_E~0); 26451#L1379-1 assume !(1 == ~T8_E~0); 26452#L1384-1 assume !(1 == ~T9_E~0); 26526#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26975#L1394-1 assume !(1 == ~T11_E~0); 26976#L1399-1 assume !(1 == ~T12_E~0); 27056#L1404-1 assume !(1 == ~E_M~0); 25889#L1409-1 assume !(1 == ~E_1~0); 25890#L1414-1 assume !(1 == ~E_2~0); 26732#L1419-1 assume !(1 == ~E_3~0); 25520#L1424-1 assume !(1 == ~E_4~0); 25521#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26461#L1434-1 assume !(1 == ~E_6~0); 26990#L1439-1 assume !(1 == ~E_7~0); 25561#L1444-1 assume !(1 == ~E_8~0); 25562#L1449-1 assume !(1 == ~E_9~0); 26003#L1454-1 assume !(1 == ~E_10~0); 26004#L1459-1 assume !(1 == ~E_11~0); 26556#L1464-1 assume !(1 == ~E_12~0); 26557#L1469-1 assume { :end_inline_reset_delta_events } true; 26606#L1815-2 [2024-11-19 15:03:44,488 INFO L747 eck$LassoCheckResult]: Loop: 26606#L1815-2 assume !false; 26754#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25918#L1181-1 assume !false; 26854#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26442#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25312#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26039#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26585#L1008 assume !(0 != eval_~tmp~0#1); 26281#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25899#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25900#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27106#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26555#L1211-3 assume !(0 == ~T2_E~0); 25630#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25631#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26249#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25702#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25703#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26040#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27028#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26928#L1251-3 assume !(0 == ~T10_E~0); 26665#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25654#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25655#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25700#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25701#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26190#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26191#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26729#L1291-3 assume !(0 == ~E_5~0); 26730#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27092#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27053#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26310#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25576#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25577#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25656#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26414#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26741#L598-42 assume 1 == ~m_pc~0; 26742#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26861#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26071#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26072#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27054#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26467#L617-42 assume 1 == ~t1_pc~0; 26244#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26114#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26115#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27051#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25810#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25811#L636-42 assume !(1 == ~t2_pc~0); 26279#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26280#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26362#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26363#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 26825#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26690#L655-42 assume !(1 == ~t3_pc~0); 26257#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 26258#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26767#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26768#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26959#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26896#L674-42 assume !(1 == ~t4_pc~0); 26673#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 26594#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26595#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26800#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26387#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26388#L693-42 assume 1 == ~t5_pc~0; 26653#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26654#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26440#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26441#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26710#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26007#L712-42 assume !(1 == ~t6_pc~0); 26008#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 26326#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25646#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25647#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26123#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26124#L731-42 assume 1 == ~t7_pc~0; 25978#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25803#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26463#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26028#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26029#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25710#L750-42 assume !(1 == ~t8_pc~0); 25712#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 26297#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26601#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25593#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25594#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26386#L769-42 assume 1 == ~t9_pc~0; 26212#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26213#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26901#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27095#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 25812#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25813#L788-42 assume 1 == ~t10_pc~0; 26394#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26618#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26591#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26592#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27104#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27077#L807-42 assume !(1 == ~t11_pc~0); 25426#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 25427#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26301#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25548#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25549#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25807#L826-42 assume 1 == ~t12_pc~0; 25808#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 26018#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26407#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25797#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25798#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26669#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26670#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26596#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25969#L1354-3 assume !(1 == ~T3_E~0); 25970#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26610#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27082#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26989#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25717#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25718#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25967#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25968#L1394-3 assume !(1 == ~T11_E~0); 26261#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26995#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26966#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26967#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27025#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26807#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25607#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25608#L1434-3 assume !(1 == ~E_6~0); 26609#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25554#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25555#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25662#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26603#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26604#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26988#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26471#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25472#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25473#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25636#L1834 assume !(0 == start_simulation_~tmp~3#1); 26717#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26734#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26175#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25361#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 25362#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26978#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26974#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 26808#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 26606#L1815-2 [2024-11-19 15:03:44,489 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:44,489 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2024-11-19 15:03:44,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:44,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020738556] [2024-11-19 15:03:44,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:44,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:44,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:44,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:44,524 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:44,527 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020738556] [2024-11-19 15:03:44,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1020738556] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:44,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:44,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:44,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360035558] [2024-11-19 15:03:44,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:44,529 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:44,529 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:44,529 INFO L85 PathProgramCache]: Analyzing trace with hash 275065309, now seen corresponding path program 1 times [2024-11-19 15:03:44,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:44,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414561344] [2024-11-19 15:03:44,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:44,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:44,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:44,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:44,583 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:44,583 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414561344] [2024-11-19 15:03:44,583 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [414561344] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:44,585 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:44,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:44,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551527889] [2024-11-19 15:03:44,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:44,585 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:44,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:44,586 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:44,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:44,586 INFO L87 Difference]: Start difference. First operand 1803 states and 2662 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:44,628 INFO L93 Difference]: Finished difference Result 1803 states and 2661 transitions. [2024-11-19 15:03:44,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2661 transitions. [2024-11-19 15:03:44,634 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2661 transitions. [2024-11-19 15:03:44,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:44,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:44,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2661 transitions. [2024-11-19 15:03:44,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:44,642 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2661 transitions. [2024-11-19 15:03:44,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2661 transitions. [2024-11-19 15:03:44,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:44,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.475873544093178) internal successors, (2661), 1802 states have internal predecessors, (2661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2661 transitions. [2024-11-19 15:03:44,665 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2661 transitions. [2024-11-19 15:03:44,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:44,666 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2661 transitions. [2024-11-19 15:03:44,666 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-19 15:03:44,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2661 transitions. [2024-11-19 15:03:44,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:44,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:44,672 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,673 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,673 INFO L745 eck$LassoCheckResult]: Stem: 29165#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 30095#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30096#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30554#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 30422#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29452#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28922#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28923#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30190#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30329#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30712#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30713#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29677#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29678#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30218#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30140#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 30141#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30293#L1206 assume !(0 == ~M_E~0); 29657#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29658#L1211-1 assume !(0 == ~T2_E~0); 30548#L1216-1 assume !(0 == ~T3_E~0); 29429#L1221-1 assume !(0 == ~T4_E~0); 29430#L1226-1 assume !(0 == ~T5_E~0); 29102#L1231-1 assume !(0 == ~T6_E~0); 29103#L1236-1 assume !(0 == ~T7_E~0); 30586#L1241-1 assume !(0 == ~T8_E~0); 29499#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29500#L1251-1 assume !(0 == ~T10_E~0); 29731#L1256-1 assume !(0 == ~T11_E~0); 28932#L1261-1 assume !(0 == ~T12_E~0); 28933#L1266-1 assume !(0 == ~E_M~0); 30698#L1271-1 assume !(0 == ~E_1~0); 30319#L1276-1 assume !(0 == ~E_2~0); 30320#L1281-1 assume !(0 == ~E_3~0); 30247#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 29328#L1291-1 assume !(0 == ~E_5~0); 29329#L1296-1 assume !(0 == ~E_6~0); 30051#L1301-1 assume !(0 == ~E_7~0); 30052#L1306-1 assume !(0 == ~E_8~0); 30488#L1311-1 assume !(0 == ~E_9~0); 29288#L1316-1 assume !(0 == ~E_10~0); 29289#L1321-1 assume !(0 == ~E_11~0); 30066#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 29153#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29154#L598 assume 1 == ~m_pc~0; 29203#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29204#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29949#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29950#L1497 assume !(0 != activate_threads_~tmp~1#1); 30661#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30610#L617 assume !(1 == ~t1_pc~0); 29521#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29522#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30401#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30402#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30157#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30158#L636 assume 1 == ~t2_pc~0; 29490#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29491#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29310#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29311#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 30189#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29847#L655 assume !(1 == ~t3_pc~0); 29848#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30573#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30389#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30390#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 30699#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30700#L674 assume 1 == ~t4_pc~0; 29016#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29017#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29043#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29044#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 29312#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29846#L693 assume !(1 == ~t5_pc~0); 30002#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29659#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29660#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30490#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 29744#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29679#L712 assume 1 == ~t6_pc~0; 29680#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30100#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29298#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29299#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 30206#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30199#L731 assume 1 == ~t7_pc~0; 29155#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29156#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29356#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30493#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 30431#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29261#L750 assume !(1 == ~t8_pc~0); 28953#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28952#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29463#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30503#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29610#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29611#L769 assume 1 == ~t9_pc~0; 30155#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29120#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29121#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29344#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 30366#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30451#L788 assume !(1 == ~t10_pc~0); 30018#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 30019#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30574#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30526#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 29257#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29258#L807 assume 1 == ~t11_pc~0; 30457#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30033#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30191#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30630#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 30724#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30557#L826 assume !(1 == ~t12_pc~0); 29682#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29683#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28997#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28998#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 29840#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29752#L1344 assume !(1 == ~M_E~0); 29753#L1344-2 assume !(1 == ~T1_E~0); 29882#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30057#L1354-1 assume !(1 == ~T3_E~0); 30058#L1359-1 assume !(1 == ~T4_E~0); 30442#L1364-1 assume !(1 == ~T5_E~0); 29375#L1369-1 assume !(1 == ~T6_E~0); 29376#L1374-1 assume !(1 == ~T7_E~0); 30064#L1379-1 assume !(1 == ~T8_E~0); 30065#L1384-1 assume !(1 == ~T9_E~0); 30139#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30588#L1394-1 assume !(1 == ~T11_E~0); 30589#L1399-1 assume !(1 == ~T12_E~0); 30669#L1404-1 assume !(1 == ~E_M~0); 29502#L1409-1 assume !(1 == ~E_1~0); 29503#L1414-1 assume !(1 == ~E_2~0); 30345#L1419-1 assume !(1 == ~E_3~0); 29133#L1424-1 assume !(1 == ~E_4~0); 29134#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30073#L1434-1 assume !(1 == ~E_6~0); 30603#L1439-1 assume !(1 == ~E_7~0); 29174#L1444-1 assume !(1 == ~E_8~0); 29175#L1449-1 assume !(1 == ~E_9~0); 29615#L1454-1 assume !(1 == ~E_10~0); 29616#L1459-1 assume !(1 == ~E_11~0); 30169#L1464-1 assume !(1 == ~E_12~0); 30170#L1469-1 assume { :end_inline_reset_delta_events } true; 30219#L1815-2 [2024-11-19 15:03:44,673 INFO L747 eck$LassoCheckResult]: Loop: 30219#L1815-2 assume !false; 30367#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29529#L1181-1 assume !false; 30467#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30055#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28925#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29652#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30198#L1008 assume !(0 != eval_~tmp~0#1); 29894#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29510#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29511#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30719#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30168#L1211-3 assume !(0 == ~T2_E~0); 29243#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29244#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29862#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29315#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29316#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29653#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30639#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30541#L1251-3 assume !(0 == ~T10_E~0); 30278#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29267#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29268#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29313#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29314#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29803#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29804#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30342#L1291-3 assume !(0 == ~E_5~0); 30343#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30705#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30666#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29923#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29189#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29190#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29269#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 30027#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30353#L598-42 assume 1 == ~m_pc~0; 30354#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30474#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29684#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29685#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30667#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30080#L617-42 assume 1 == ~t1_pc~0; 29857#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29727#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29728#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30664#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29423#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29424#L636-42 assume !(1 == ~t2_pc~0); 29892#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 29893#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29972#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29973#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 30438#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30303#L655-42 assume 1 == ~t3_pc~0; 30304#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29871#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30380#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30381#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30572#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30509#L674-42 assume !(1 == ~t4_pc~0); 30286#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 30207#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30208#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30413#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30000#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30001#L693-42 assume 1 == ~t5_pc~0; 30269#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30270#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30053#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30054#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30323#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29625#L712-42 assume !(1 == ~t6_pc~0); 29626#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 29942#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29259#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29260#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29736#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29737#L731-42 assume !(1 == ~t7_pc~0); 29415#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 29416#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30076#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29642#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29643#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29323#L750-42 assume 1 == ~t8_pc~0; 29324#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29913#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30214#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29206#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29207#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29999#L769-42 assume 1 == ~t9_pc~0; 29830#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29831#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30514#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30708#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 29425#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29426#L788-42 assume 1 == ~t10_pc~0; 30007#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30229#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30203#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30204#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30717#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30690#L807-42 assume 1 == ~t11_pc~0; 30362#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29037#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29914#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29161#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29162#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29420#L826-42 assume 1 == ~t12_pc~0; 29421#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29631#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30020#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29410#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29411#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30282#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30283#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30209#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29582#L1354-3 assume !(1 == ~T3_E~0); 29583#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30223#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30695#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30602#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29330#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29331#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29580#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29581#L1394-3 assume !(1 == ~T11_E~0); 29874#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30608#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30579#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30580#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30638#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30420#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29220#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29221#L1434-3 assume !(1 == ~E_6~0); 30222#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29167#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29168#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29275#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30216#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30217#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30601#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30084#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29085#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29086#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29247#L1834 assume !(0 == start_simulation_~tmp~3#1); 30330#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30347#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29788#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28974#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 28975#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30591#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30587#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 30421#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 30219#L1815-2 [2024-11-19 15:03:44,674 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:44,674 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2024-11-19 15:03:44,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:44,674 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829262469] [2024-11-19 15:03:44,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:44,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:44,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:44,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:44,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:44,708 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [829262469] [2024-11-19 15:03:44,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [829262469] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:44,708 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:44,709 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:44,709 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318125649] [2024-11-19 15:03:44,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:44,709 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:44,709 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:44,710 INFO L85 PathProgramCache]: Analyzing trace with hash -805023461, now seen corresponding path program 1 times [2024-11-19 15:03:44,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:44,710 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445534383] [2024-11-19 15:03:44,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:44,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:44,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:44,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:44,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:44,757 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445534383] [2024-11-19 15:03:44,757 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1445534383] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:44,757 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:44,757 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:44,757 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1297315915] [2024-11-19 15:03:44,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:44,757 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:44,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:44,758 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:44,758 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:44,758 INFO L87 Difference]: Start difference. First operand 1803 states and 2661 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:44,780 INFO L93 Difference]: Finished difference Result 1803 states and 2660 transitions. [2024-11-19 15:03:44,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2660 transitions. [2024-11-19 15:03:44,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2660 transitions. [2024-11-19 15:03:44,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:44,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:44,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2660 transitions. [2024-11-19 15:03:44,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:44,794 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2660 transitions. [2024-11-19 15:03:44,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2660 transitions. [2024-11-19 15:03:44,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:44,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.4753189129229063) internal successors, (2660), 1802 states have internal predecessors, (2660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2660 transitions. [2024-11-19 15:03:44,813 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2660 transitions. [2024-11-19 15:03:44,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:44,814 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2660 transitions. [2024-11-19 15:03:44,815 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-19 15:03:44,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2660 transitions. [2024-11-19 15:03:44,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:44,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:44,820 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,820 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,821 INFO L745 eck$LassoCheckResult]: Stem: 32778#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 32779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33708#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33709#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34167#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 34035#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33065#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32535#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32536#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33803#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33942#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34325#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34326#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33288#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33289#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33831#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33753#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33754#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33906#L1206 assume !(0 == ~M_E~0); 33270#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33271#L1211-1 assume !(0 == ~T2_E~0); 34160#L1216-1 assume !(0 == ~T3_E~0); 33042#L1221-1 assume !(0 == ~T4_E~0); 33043#L1226-1 assume !(0 == ~T5_E~0); 32715#L1231-1 assume !(0 == ~T6_E~0); 32716#L1236-1 assume !(0 == ~T7_E~0); 34199#L1241-1 assume !(0 == ~T8_E~0); 33112#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33113#L1251-1 assume !(0 == ~T10_E~0); 33344#L1256-1 assume !(0 == ~T11_E~0); 32545#L1261-1 assume !(0 == ~T12_E~0); 32546#L1266-1 assume !(0 == ~E_M~0); 34311#L1271-1 assume !(0 == ~E_1~0); 33932#L1276-1 assume !(0 == ~E_2~0); 33933#L1281-1 assume !(0 == ~E_3~0); 33860#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 32941#L1291-1 assume !(0 == ~E_5~0); 32942#L1296-1 assume !(0 == ~E_6~0); 33664#L1301-1 assume !(0 == ~E_7~0); 33665#L1306-1 assume !(0 == ~E_8~0); 34101#L1311-1 assume !(0 == ~E_9~0); 32901#L1316-1 assume !(0 == ~E_10~0); 32902#L1321-1 assume !(0 == ~E_11~0); 33679#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 32766#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32767#L598 assume 1 == ~m_pc~0; 32816#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32817#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33562#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33563#L1497 assume !(0 != activate_threads_~tmp~1#1); 34274#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34223#L617 assume !(1 == ~t1_pc~0); 33134#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33135#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34014#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34015#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33770#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33771#L636 assume 1 == ~t2_pc~0; 33103#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33104#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32923#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32924#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 33802#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33460#L655 assume !(1 == ~t3_pc~0); 33461#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34186#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34002#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34003#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 34312#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34313#L674 assume 1 == ~t4_pc~0; 32629#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32630#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32656#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32657#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 32925#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33459#L693 assume !(1 == ~t5_pc~0); 33615#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33272#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33273#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34103#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 33357#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33292#L712 assume 1 == ~t6_pc~0; 33293#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33713#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32911#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32912#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 33819#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33812#L731 assume 1 == ~t7_pc~0; 32768#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32769#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32969#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34106#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 34044#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32874#L750 assume !(1 == ~t8_pc~0); 32566#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32565#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33076#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34116#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33223#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33224#L769 assume 1 == ~t9_pc~0; 33766#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32733#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32734#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32957#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 33979#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34064#L788 assume !(1 == ~t10_pc~0); 33631#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33632#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34187#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34139#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 32870#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32871#L807 assume 1 == ~t11_pc~0; 34070#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33646#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33804#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34243#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 34337#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34170#L826 assume !(1 == ~t12_pc~0); 33295#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33296#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32610#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32611#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 33453#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33365#L1344 assume !(1 == ~M_E~0); 33366#L1344-2 assume !(1 == ~T1_E~0); 33495#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33670#L1354-1 assume !(1 == ~T3_E~0); 33671#L1359-1 assume !(1 == ~T4_E~0); 34055#L1364-1 assume !(1 == ~T5_E~0); 32988#L1369-1 assume !(1 == ~T6_E~0); 32989#L1374-1 assume !(1 == ~T7_E~0); 33677#L1379-1 assume !(1 == ~T8_E~0); 33678#L1384-1 assume !(1 == ~T9_E~0); 33752#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34201#L1394-1 assume !(1 == ~T11_E~0); 34202#L1399-1 assume !(1 == ~T12_E~0); 34282#L1404-1 assume !(1 == ~E_M~0); 33115#L1409-1 assume !(1 == ~E_1~0); 33116#L1414-1 assume !(1 == ~E_2~0); 33958#L1419-1 assume !(1 == ~E_3~0); 32746#L1424-1 assume !(1 == ~E_4~0); 32747#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 33686#L1434-1 assume !(1 == ~E_6~0); 34216#L1439-1 assume !(1 == ~E_7~0); 32787#L1444-1 assume !(1 == ~E_8~0); 32788#L1449-1 assume !(1 == ~E_9~0); 33228#L1454-1 assume !(1 == ~E_10~0); 33229#L1459-1 assume !(1 == ~E_11~0); 33782#L1464-1 assume !(1 == ~E_12~0); 33783#L1469-1 assume { :end_inline_reset_delta_events } true; 33832#L1815-2 [2024-11-19 15:03:44,821 INFO L747 eck$LassoCheckResult]: Loop: 33832#L1815-2 assume !false; 33980#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33142#L1181-1 assume !false; 34080#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33668#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32538#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33265#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33811#L1008 assume !(0 != eval_~tmp~0#1); 33507#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33123#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33124#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34332#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33781#L1211-3 assume !(0 == ~T2_E~0); 32856#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32857#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33475#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32928#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32929#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33266#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 34252#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34154#L1251-3 assume !(0 == ~T10_E~0); 33891#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32880#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32881#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32926#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32927#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33416#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33417#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33955#L1291-3 assume !(0 == ~E_5~0); 33956#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34318#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34279#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33536#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32802#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32803#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32882#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 33640#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33966#L598-42 assume !(1 == ~m_pc~0); 33968#L598-44 is_master_triggered_~__retres1~0#1 := 0; 34087#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33297#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33298#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34280#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33693#L617-42 assume 1 == ~t1_pc~0; 33469#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33340#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33341#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34277#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33036#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33037#L636-42 assume !(1 == ~t2_pc~0); 33505#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 33506#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33585#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33586#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 34051#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33916#L655-42 assume !(1 == ~t3_pc~0); 33481#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 33482#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33993#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33994#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34185#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34122#L674-42 assume !(1 == ~t4_pc~0); 33899#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 33820#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33821#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34026#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33613#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33614#L693-42 assume 1 == ~t5_pc~0; 33879#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33880#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33666#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33667#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33936#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33238#L712-42 assume !(1 == ~t6_pc~0); 33239#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 33554#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32872#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32873#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33349#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33350#L731-42 assume !(1 == ~t7_pc~0); 33028#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 33029#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33689#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33255#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33256#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32936#L750-42 assume 1 == ~t8_pc~0; 32937#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33523#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33827#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32819#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32820#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33612#L769-42 assume 1 == ~t9_pc~0; 33440#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33441#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34127#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34321#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 33038#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33039#L788-42 assume 1 == ~t10_pc~0; 33620#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33846#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33817#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33818#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34330#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34305#L807-42 assume 1 == ~t11_pc~0; 33975#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32653#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33527#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32774#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32775#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33033#L826-42 assume 1 == ~t12_pc~0; 33034#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 33244#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33636#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33023#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33024#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33895#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33896#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33822#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33195#L1354-3 assume !(1 == ~T3_E~0); 33196#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33836#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34308#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34215#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32945#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32946#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33193#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33194#L1394-3 assume !(1 == ~T11_E~0); 33487#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 34221#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34192#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34193#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34251#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34033#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32833#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32834#L1434-3 assume !(1 == ~E_6~0); 33835#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32780#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32781#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32888#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33829#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33830#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34214#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33697#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32698#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32699#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32862#L1834 assume !(0 == start_simulation_~tmp~3#1); 33943#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33960#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33401#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32587#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 32588#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34204#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34200#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 34034#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 33832#L1815-2 [2024-11-19 15:03:44,821 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:44,822 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2024-11-19 15:03:44,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:44,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468100422] [2024-11-19 15:03:44,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:44,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:44,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:44,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:44,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:44,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1468100422] [2024-11-19 15:03:44,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1468100422] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:44,856 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:44,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:44,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [905208299] [2024-11-19 15:03:44,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:44,857 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:44,857 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:44,858 INFO L85 PathProgramCache]: Analyzing trace with hash 796889309, now seen corresponding path program 1 times [2024-11-19 15:03:44,858 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:44,858 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950477955] [2024-11-19 15:03:44,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:44,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:44,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:44,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:44,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:44,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950477955] [2024-11-19 15:03:44,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950477955] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:44,902 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:44,902 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:44,902 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [765702885] [2024-11-19 15:03:44,902 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:44,902 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:44,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:44,903 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:44,903 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:44,903 INFO L87 Difference]: Start difference. First operand 1803 states and 2660 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:44,927 INFO L93 Difference]: Finished difference Result 1803 states and 2659 transitions. [2024-11-19 15:03:44,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2659 transitions. [2024-11-19 15:03:44,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2659 transitions. [2024-11-19 15:03:44,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:44,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:44,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2659 transitions. [2024-11-19 15:03:44,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:44,944 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2659 transitions. [2024-11-19 15:03:44,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2659 transitions. [2024-11-19 15:03:44,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:44,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.4747642817526345) internal successors, (2659), 1802 states have internal predecessors, (2659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:44,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2659 transitions. [2024-11-19 15:03:44,964 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2659 transitions. [2024-11-19 15:03:44,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:44,965 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2659 transitions. [2024-11-19 15:03:44,965 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-19 15:03:44,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2659 transitions. [2024-11-19 15:03:44,970 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:44,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:44,970 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:44,971 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,971 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:44,971 INFO L745 eck$LassoCheckResult]: Stem: 36391#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 37321#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37322#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37780#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 37648#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36678#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36148#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36149#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37416#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37555#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37938#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37939#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36901#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36902#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37444#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37366#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37367#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37519#L1206 assume !(0 == ~M_E~0); 36883#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36884#L1211-1 assume !(0 == ~T2_E~0); 37773#L1216-1 assume !(0 == ~T3_E~0); 36655#L1221-1 assume !(0 == ~T4_E~0); 36656#L1226-1 assume !(0 == ~T5_E~0); 36328#L1231-1 assume !(0 == ~T6_E~0); 36329#L1236-1 assume !(0 == ~T7_E~0); 37812#L1241-1 assume !(0 == ~T8_E~0); 36725#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36726#L1251-1 assume !(0 == ~T10_E~0); 36957#L1256-1 assume !(0 == ~T11_E~0); 36158#L1261-1 assume !(0 == ~T12_E~0); 36159#L1266-1 assume !(0 == ~E_M~0); 37924#L1271-1 assume !(0 == ~E_1~0); 37545#L1276-1 assume !(0 == ~E_2~0); 37546#L1281-1 assume !(0 == ~E_3~0); 37473#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 36554#L1291-1 assume !(0 == ~E_5~0); 36555#L1296-1 assume !(0 == ~E_6~0); 37277#L1301-1 assume !(0 == ~E_7~0); 37278#L1306-1 assume !(0 == ~E_8~0); 37714#L1311-1 assume !(0 == ~E_9~0); 36514#L1316-1 assume !(0 == ~E_10~0); 36515#L1321-1 assume !(0 == ~E_11~0); 37292#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36379#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36380#L598 assume 1 == ~m_pc~0; 36429#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36430#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37175#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37176#L1497 assume !(0 != activate_threads_~tmp~1#1); 37887#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37836#L617 assume !(1 == ~t1_pc~0); 36747#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36748#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37627#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37628#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37383#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37384#L636 assume 1 == ~t2_pc~0; 36716#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36717#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36536#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36537#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 37415#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37073#L655 assume !(1 == ~t3_pc~0); 37074#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37799#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37615#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37616#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 37925#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37926#L674 assume 1 == ~t4_pc~0; 36242#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36243#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36270#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 36538#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37072#L693 assume !(1 == ~t5_pc~0); 37228#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36885#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36886#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37716#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 36970#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36905#L712 assume 1 == ~t6_pc~0; 36906#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37326#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36524#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36525#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 37432#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37425#L731 assume 1 == ~t7_pc~0; 36381#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36382#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36582#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37719#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 37657#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36487#L750 assume !(1 == ~t8_pc~0); 36179#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36178#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36689#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37729#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36836#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36837#L769 assume 1 == ~t9_pc~0; 37379#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36346#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36347#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36570#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 37592#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37677#L788 assume !(1 == ~t10_pc~0); 37244#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37245#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37800#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37752#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 36483#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36484#L807 assume 1 == ~t11_pc~0; 37683#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37259#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37417#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37856#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 37950#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37783#L826 assume !(1 == ~t12_pc~0); 36908#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36909#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36223#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36224#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 37066#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36978#L1344 assume !(1 == ~M_E~0); 36979#L1344-2 assume !(1 == ~T1_E~0); 37108#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37283#L1354-1 assume !(1 == ~T3_E~0); 37284#L1359-1 assume !(1 == ~T4_E~0); 37668#L1364-1 assume !(1 == ~T5_E~0); 36601#L1369-1 assume !(1 == ~T6_E~0); 36602#L1374-1 assume !(1 == ~T7_E~0); 37290#L1379-1 assume !(1 == ~T8_E~0); 37291#L1384-1 assume !(1 == ~T9_E~0); 37365#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37814#L1394-1 assume !(1 == ~T11_E~0); 37815#L1399-1 assume !(1 == ~T12_E~0); 37895#L1404-1 assume !(1 == ~E_M~0); 36728#L1409-1 assume !(1 == ~E_1~0); 36729#L1414-1 assume !(1 == ~E_2~0); 37571#L1419-1 assume !(1 == ~E_3~0); 36359#L1424-1 assume !(1 == ~E_4~0); 36360#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 37299#L1434-1 assume !(1 == ~E_6~0); 37829#L1439-1 assume !(1 == ~E_7~0); 36400#L1444-1 assume !(1 == ~E_8~0); 36401#L1449-1 assume !(1 == ~E_9~0); 36841#L1454-1 assume !(1 == ~E_10~0); 36842#L1459-1 assume !(1 == ~E_11~0); 37395#L1464-1 assume !(1 == ~E_12~0); 37396#L1469-1 assume { :end_inline_reset_delta_events } true; 37445#L1815-2 [2024-11-19 15:03:44,972 INFO L747 eck$LassoCheckResult]: Loop: 37445#L1815-2 assume !false; 37593#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36755#L1181-1 assume !false; 37693#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37281#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36151#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36878#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37424#L1008 assume !(0 != eval_~tmp~0#1); 37120#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36737#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37945#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37394#L1211-3 assume !(0 == ~T2_E~0); 36469#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36470#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37088#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36541#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36542#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36879#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37865#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37767#L1251-3 assume !(0 == ~T10_E~0); 37504#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36493#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36494#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36539#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36540#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37029#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37030#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37568#L1291-3 assume !(0 == ~E_5~0); 37569#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37931#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37892#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37149#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36415#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36416#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36495#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 37253#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37579#L598-42 assume 1 == ~m_pc~0; 37580#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37700#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36910#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36911#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37893#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37306#L617-42 assume 1 == ~t1_pc~0; 37082#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36953#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36954#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37890#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36649#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36650#L636-42 assume !(1 == ~t2_pc~0); 37118#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 37119#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37198#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37199#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 37664#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37529#L655-42 assume !(1 == ~t3_pc~0); 37094#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 37095#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37606#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37607#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37798#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37735#L674-42 assume !(1 == ~t4_pc~0); 37512#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 37433#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37434#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37639#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37226#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37227#L693-42 assume 1 == ~t5_pc~0; 37492#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37493#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37279#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37280#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37549#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36851#L712-42 assume !(1 == ~t6_pc~0); 36852#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 37167#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36485#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36486#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36962#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36963#L731-42 assume !(1 == ~t7_pc~0); 36641#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 36642#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37302#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36868#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36869#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36549#L750-42 assume 1 == ~t8_pc~0; 36550#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37136#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37440#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36432#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36433#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37225#L769-42 assume 1 == ~t9_pc~0; 37053#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37054#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37740#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37934#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 36651#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36652#L788-42 assume 1 == ~t10_pc~0; 37233#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37459#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37430#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37431#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37943#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37918#L807-42 assume 1 == ~t11_pc~0; 37588#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36266#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37140#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36387#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36388#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36646#L826-42 assume 1 == ~t12_pc~0; 36647#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36857#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37249#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36636#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36637#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37508#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37509#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37435#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36808#L1354-3 assume !(1 == ~T3_E~0); 36809#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37449#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37921#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37828#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36558#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36559#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36806#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36807#L1394-3 assume !(1 == ~T11_E~0); 37100#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37834#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37805#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37806#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37864#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37646#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36446#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36447#L1434-3 assume !(1 == ~E_6~0); 37448#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36393#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36394#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36501#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37442#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37443#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37827#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37310#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36311#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36312#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36475#L1834 assume !(0 == start_simulation_~tmp~3#1); 37556#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37573#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37014#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36200#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 36201#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37817#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37813#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 37647#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 37445#L1815-2 [2024-11-19 15:03:44,973 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:44,973 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2024-11-19 15:03:44,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:44,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403525099] [2024-11-19 15:03:44,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:44,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:44,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:45,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:45,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:45,003 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403525099] [2024-11-19 15:03:45,003 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403525099] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:45,003 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:45,004 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:45,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [80124859] [2024-11-19 15:03:45,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:45,004 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:45,004 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:45,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1379377180, now seen corresponding path program 3 times [2024-11-19 15:03:45,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:45,005 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692196414] [2024-11-19 15:03:45,005 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 15:03:45,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:45,017 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 15:03:45,017 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:03:45,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:45,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:45,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [692196414] [2024-11-19 15:03:45,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [692196414] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:45,056 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:45,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:45,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1580957574] [2024-11-19 15:03:45,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:45,056 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:45,057 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:45,058 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:45,058 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:45,058 INFO L87 Difference]: Start difference. First operand 1803 states and 2659 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:45,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:45,081 INFO L93 Difference]: Finished difference Result 1803 states and 2658 transitions. [2024-11-19 15:03:45,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2658 transitions. [2024-11-19 15:03:45,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:45,125 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2658 transitions. [2024-11-19 15:03:45,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:45,131 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:45,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2658 transitions. [2024-11-19 15:03:45,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:45,133 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2658 transitions. [2024-11-19 15:03:45,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2658 transitions. [2024-11-19 15:03:45,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:45,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.4742096505823628) internal successors, (2658), 1802 states have internal predecessors, (2658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:45,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2658 transitions. [2024-11-19 15:03:45,177 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2658 transitions. [2024-11-19 15:03:45,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:45,178 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2658 transitions. [2024-11-19 15:03:45,178 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-19 15:03:45,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2658 transitions. [2024-11-19 15:03:45,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:45,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:45,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:45,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:45,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:45,185 INFO L745 eck$LassoCheckResult]: Stem: 40004#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40005#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40934#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40935#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41393#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 41261#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40291#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39761#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39762#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41029#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41168#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41551#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41552#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40514#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40515#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41057#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40979#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40980#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41132#L1206 assume !(0 == ~M_E~0); 40496#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40497#L1211-1 assume !(0 == ~T2_E~0); 41386#L1216-1 assume !(0 == ~T3_E~0); 40268#L1221-1 assume !(0 == ~T4_E~0); 40269#L1226-1 assume !(0 == ~T5_E~0); 39941#L1231-1 assume !(0 == ~T6_E~0); 39942#L1236-1 assume !(0 == ~T7_E~0); 41425#L1241-1 assume !(0 == ~T8_E~0); 40338#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40339#L1251-1 assume !(0 == ~T10_E~0); 40570#L1256-1 assume !(0 == ~T11_E~0); 39771#L1261-1 assume !(0 == ~T12_E~0); 39772#L1266-1 assume !(0 == ~E_M~0); 41537#L1271-1 assume !(0 == ~E_1~0); 41158#L1276-1 assume !(0 == ~E_2~0); 41159#L1281-1 assume !(0 == ~E_3~0); 41086#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 40167#L1291-1 assume !(0 == ~E_5~0); 40168#L1296-1 assume !(0 == ~E_6~0); 40890#L1301-1 assume !(0 == ~E_7~0); 40891#L1306-1 assume !(0 == ~E_8~0); 41327#L1311-1 assume !(0 == ~E_9~0); 40127#L1316-1 assume !(0 == ~E_10~0); 40128#L1321-1 assume !(0 == ~E_11~0); 40905#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 39992#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39993#L598 assume 1 == ~m_pc~0; 40042#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40043#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40788#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40789#L1497 assume !(0 != activate_threads_~tmp~1#1); 41500#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41449#L617 assume !(1 == ~t1_pc~0); 40360#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40361#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41240#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41241#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40996#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40997#L636 assume 1 == ~t2_pc~0; 40329#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40330#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40149#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40150#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 41028#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40686#L655 assume !(1 == ~t3_pc~0); 40687#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41412#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41228#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41229#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 41538#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41539#L674 assume 1 == ~t4_pc~0; 39855#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39856#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39882#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39883#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 40151#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40685#L693 assume !(1 == ~t5_pc~0); 40841#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40498#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40499#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41329#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 40583#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40518#L712 assume 1 == ~t6_pc~0; 40519#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40939#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40137#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40138#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 41045#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41038#L731 assume 1 == ~t7_pc~0; 39994#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39995#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40195#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41332#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 41270#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40100#L750 assume !(1 == ~t8_pc~0); 39792#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39791#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40302#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41342#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40449#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40450#L769 assume 1 == ~t9_pc~0; 40992#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39959#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39960#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40183#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 41205#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41290#L788 assume !(1 == ~t10_pc~0); 40857#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40858#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41413#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41365#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 40096#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40097#L807 assume 1 == ~t11_pc~0; 41296#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40872#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41030#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41469#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 41563#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41396#L826 assume !(1 == ~t12_pc~0); 40521#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40522#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39836#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39837#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 40679#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40591#L1344 assume !(1 == ~M_E~0); 40592#L1344-2 assume !(1 == ~T1_E~0); 40721#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40896#L1354-1 assume !(1 == ~T3_E~0); 40897#L1359-1 assume !(1 == ~T4_E~0); 41281#L1364-1 assume !(1 == ~T5_E~0); 40214#L1369-1 assume !(1 == ~T6_E~0); 40215#L1374-1 assume !(1 == ~T7_E~0); 40903#L1379-1 assume !(1 == ~T8_E~0); 40904#L1384-1 assume !(1 == ~T9_E~0); 40978#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41427#L1394-1 assume !(1 == ~T11_E~0); 41428#L1399-1 assume !(1 == ~T12_E~0); 41508#L1404-1 assume !(1 == ~E_M~0); 40341#L1409-1 assume !(1 == ~E_1~0); 40342#L1414-1 assume !(1 == ~E_2~0); 41184#L1419-1 assume !(1 == ~E_3~0); 39972#L1424-1 assume !(1 == ~E_4~0); 39973#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 40912#L1434-1 assume !(1 == ~E_6~0); 41442#L1439-1 assume !(1 == ~E_7~0); 40013#L1444-1 assume !(1 == ~E_8~0); 40014#L1449-1 assume !(1 == ~E_9~0); 40454#L1454-1 assume !(1 == ~E_10~0); 40455#L1459-1 assume !(1 == ~E_11~0); 41008#L1464-1 assume !(1 == ~E_12~0); 41009#L1469-1 assume { :end_inline_reset_delta_events } true; 41058#L1815-2 [2024-11-19 15:03:45,186 INFO L747 eck$LassoCheckResult]: Loop: 41058#L1815-2 assume !false; 41206#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40368#L1181-1 assume !false; 41306#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40894#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39764#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40491#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 41037#L1008 assume !(0 != eval_~tmp~0#1); 40733#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40349#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40350#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41558#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41007#L1211-3 assume !(0 == ~T2_E~0); 40082#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40083#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40701#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40154#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40155#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40492#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41478#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41380#L1251-3 assume !(0 == ~T10_E~0); 41117#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40106#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 40107#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40152#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40153#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40642#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40643#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41181#L1291-3 assume !(0 == ~E_5~0); 41182#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41544#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41505#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40762#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40028#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40029#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40108#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40866#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41192#L598-42 assume 1 == ~m_pc~0; 41193#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41313#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40523#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40524#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41506#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40919#L617-42 assume 1 == ~t1_pc~0; 40695#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40566#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40567#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41503#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40262#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40263#L636-42 assume !(1 == ~t2_pc~0); 40731#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40732#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40811#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40812#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 41277#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41142#L655-42 assume !(1 == ~t3_pc~0); 40707#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 40708#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41219#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41220#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41411#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41348#L674-42 assume !(1 == ~t4_pc~0); 41125#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 41046#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41047#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41252#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40839#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40840#L693-42 assume 1 == ~t5_pc~0; 41105#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41106#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40892#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40893#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41162#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40464#L712-42 assume !(1 == ~t6_pc~0); 40465#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 40780#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40098#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40099#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40575#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40576#L731-42 assume 1 == ~t7_pc~0; 40432#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40255#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40915#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40481#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40482#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40162#L750-42 assume 1 == ~t8_pc~0; 40163#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40749#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41053#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40045#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40046#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40838#L769-42 assume 1 == ~t9_pc~0; 40666#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40667#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41353#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41547#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 40264#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40265#L788-42 assume 1 == ~t10_pc~0; 40846#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41072#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41043#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41044#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41556#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41531#L807-42 assume 1 == ~t11_pc~0; 41201#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39879#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40753#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40000#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40001#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40259#L826-42 assume 1 == ~t12_pc~0; 40260#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40470#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40862#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40249#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40250#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41121#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41122#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41048#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40421#L1354-3 assume !(1 == ~T3_E~0); 40422#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41062#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41534#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41441#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40171#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40172#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40419#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40420#L1394-3 assume !(1 == ~T11_E~0); 40713#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41447#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41418#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41419#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41477#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41259#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40059#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40060#L1434-3 assume !(1 == ~E_6~0); 41061#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40006#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40007#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40114#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41055#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41056#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41440#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40923#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39924#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39925#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 40088#L1834 assume !(0 == start_simulation_~tmp~3#1); 41169#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 41186#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40627#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39813#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 39814#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41430#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41426#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 41260#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 41058#L1815-2 [2024-11-19 15:03:45,186 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:45,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2024-11-19 15:03:45,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:45,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148624459] [2024-11-19 15:03:45,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:45,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:45,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:45,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:45,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:45,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [148624459] [2024-11-19 15:03:45,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [148624459] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:45,219 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:45,219 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:45,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841143628] [2024-11-19 15:03:45,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:45,220 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:45,220 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:45,220 INFO L85 PathProgramCache]: Analyzing trace with hash 1238277659, now seen corresponding path program 1 times [2024-11-19 15:03:45,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:45,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160878764] [2024-11-19 15:03:45,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:45,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:45,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:45,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:45,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:45,271 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160878764] [2024-11-19 15:03:45,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [160878764] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:45,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:45,271 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:45,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2107926906] [2024-11-19 15:03:45,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:45,272 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:45,272 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:45,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:45,272 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:45,273 INFO L87 Difference]: Start difference. First operand 1803 states and 2658 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:45,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:45,297 INFO L93 Difference]: Finished difference Result 1803 states and 2657 transitions. [2024-11-19 15:03:45,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2657 transitions. [2024-11-19 15:03:45,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:45,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2657 transitions. [2024-11-19 15:03:45,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:45,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:45,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2657 transitions. [2024-11-19 15:03:45,314 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:45,314 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2657 transitions. [2024-11-19 15:03:45,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2657 transitions. [2024-11-19 15:03:45,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:45,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.473655019412091) internal successors, (2657), 1802 states have internal predecessors, (2657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:45,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2657 transitions. [2024-11-19 15:03:45,363 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2657 transitions. [2024-11-19 15:03:45,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:45,364 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2657 transitions. [2024-11-19 15:03:45,364 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-19 15:03:45,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2657 transitions. [2024-11-19 15:03:45,371 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:45,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:45,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:45,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:45,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:45,377 INFO L745 eck$LassoCheckResult]: Stem: 43617#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43618#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44547#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44548#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45006#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 44874#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43904#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43374#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43375#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44642#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44781#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45164#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45165#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44127#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44128#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44670#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44592#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44593#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44745#L1206 assume !(0 == ~M_E~0); 44109#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44110#L1211-1 assume !(0 == ~T2_E~0); 44999#L1216-1 assume !(0 == ~T3_E~0); 43881#L1221-1 assume !(0 == ~T4_E~0); 43882#L1226-1 assume !(0 == ~T5_E~0); 43554#L1231-1 assume !(0 == ~T6_E~0); 43555#L1236-1 assume !(0 == ~T7_E~0); 45038#L1241-1 assume !(0 == ~T8_E~0); 43951#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43952#L1251-1 assume !(0 == ~T10_E~0); 44183#L1256-1 assume !(0 == ~T11_E~0); 43384#L1261-1 assume !(0 == ~T12_E~0); 43385#L1266-1 assume !(0 == ~E_M~0); 45150#L1271-1 assume !(0 == ~E_1~0); 44771#L1276-1 assume !(0 == ~E_2~0); 44772#L1281-1 assume !(0 == ~E_3~0); 44699#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 43780#L1291-1 assume !(0 == ~E_5~0); 43781#L1296-1 assume !(0 == ~E_6~0); 44503#L1301-1 assume !(0 == ~E_7~0); 44504#L1306-1 assume !(0 == ~E_8~0); 44940#L1311-1 assume !(0 == ~E_9~0); 43740#L1316-1 assume !(0 == ~E_10~0); 43741#L1321-1 assume !(0 == ~E_11~0); 44518#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 43605#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43606#L598 assume 1 == ~m_pc~0; 43655#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43656#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44401#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44402#L1497 assume !(0 != activate_threads_~tmp~1#1); 45113#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45062#L617 assume !(1 == ~t1_pc~0); 43973#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43974#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44853#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44854#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44609#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44610#L636 assume 1 == ~t2_pc~0; 43942#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43943#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43762#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43763#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 44641#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44299#L655 assume !(1 == ~t3_pc~0); 44300#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45025#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44841#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44842#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 45151#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45152#L674 assume 1 == ~t4_pc~0; 43468#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43469#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43495#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43496#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 43764#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44298#L693 assume !(1 == ~t5_pc~0); 44454#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 44111#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44112#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44942#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 44196#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44131#L712 assume 1 == ~t6_pc~0; 44132#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44552#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43750#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43751#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 44658#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44651#L731 assume 1 == ~t7_pc~0; 43607#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43608#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43808#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44945#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 44883#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43713#L750 assume !(1 == ~t8_pc~0); 43405#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43404#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43915#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44955#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44062#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44063#L769 assume 1 == ~t9_pc~0; 44605#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43572#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43573#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43796#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 44818#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44903#L788 assume !(1 == ~t10_pc~0); 44470#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44471#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45026#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44978#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 43709#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43710#L807 assume 1 == ~t11_pc~0; 44909#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44485#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44643#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45082#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 45176#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45009#L826 assume !(1 == ~t12_pc~0); 44134#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44135#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43449#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43450#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 44292#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44204#L1344 assume !(1 == ~M_E~0); 44205#L1344-2 assume !(1 == ~T1_E~0); 44334#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44509#L1354-1 assume !(1 == ~T3_E~0); 44510#L1359-1 assume !(1 == ~T4_E~0); 44894#L1364-1 assume !(1 == ~T5_E~0); 43827#L1369-1 assume !(1 == ~T6_E~0); 43828#L1374-1 assume !(1 == ~T7_E~0); 44516#L1379-1 assume !(1 == ~T8_E~0); 44517#L1384-1 assume !(1 == ~T9_E~0); 44591#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45040#L1394-1 assume !(1 == ~T11_E~0); 45041#L1399-1 assume !(1 == ~T12_E~0); 45121#L1404-1 assume !(1 == ~E_M~0); 43954#L1409-1 assume !(1 == ~E_1~0); 43955#L1414-1 assume !(1 == ~E_2~0); 44797#L1419-1 assume !(1 == ~E_3~0); 43585#L1424-1 assume !(1 == ~E_4~0); 43586#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 44525#L1434-1 assume !(1 == ~E_6~0); 45055#L1439-1 assume !(1 == ~E_7~0); 43626#L1444-1 assume !(1 == ~E_8~0); 43627#L1449-1 assume !(1 == ~E_9~0); 44067#L1454-1 assume !(1 == ~E_10~0); 44068#L1459-1 assume !(1 == ~E_11~0); 44621#L1464-1 assume !(1 == ~E_12~0); 44622#L1469-1 assume { :end_inline_reset_delta_events } true; 44671#L1815-2 [2024-11-19 15:03:45,378 INFO L747 eck$LassoCheckResult]: Loop: 44671#L1815-2 assume !false; 44819#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43981#L1181-1 assume !false; 44919#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44507#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43377#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44104#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44650#L1008 assume !(0 != eval_~tmp~0#1); 44346#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43962#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43963#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45171#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44620#L1211-3 assume !(0 == ~T2_E~0); 43695#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43696#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44314#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43767#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43768#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44105#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45091#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44993#L1251-3 assume !(0 == ~T10_E~0); 44730#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43719#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43720#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43765#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43766#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44255#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44256#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44794#L1291-3 assume !(0 == ~E_5~0); 44795#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45157#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45118#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44375#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43641#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43642#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43721#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 44479#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44805#L598-42 assume 1 == ~m_pc~0; 44806#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 44926#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44136#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44137#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45119#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44532#L617-42 assume 1 == ~t1_pc~0; 44308#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44179#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44180#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45116#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43875#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43876#L636-42 assume !(1 == ~t2_pc~0); 44344#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 44345#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44424#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44425#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 44890#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44755#L655-42 assume !(1 == ~t3_pc~0); 44320#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 44321#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44832#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44833#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45024#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44961#L674-42 assume !(1 == ~t4_pc~0); 44738#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 44659#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44660#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44865#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44452#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44453#L693-42 assume !(1 == ~t5_pc~0); 44720#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 44719#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44505#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44506#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44775#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44077#L712-42 assume !(1 == ~t6_pc~0); 44078#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 44393#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43711#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43712#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44188#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44189#L731-42 assume !(1 == ~t7_pc~0); 43867#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 43868#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44528#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44094#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44095#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43775#L750-42 assume 1 == ~t8_pc~0; 43776#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44362#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44666#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43658#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43659#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44451#L769-42 assume 1 == ~t9_pc~0; 44279#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44280#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44966#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45160#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 43877#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43878#L788-42 assume 1 == ~t10_pc~0; 44459#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44685#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44656#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44657#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45169#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45144#L807-42 assume !(1 == ~t11_pc~0); 43491#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 43492#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44366#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43613#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43614#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43872#L826-42 assume 1 == ~t12_pc~0; 43873#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44083#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44475#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43862#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43863#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44734#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44735#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44661#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44034#L1354-3 assume !(1 == ~T3_E~0); 44035#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44675#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45147#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45054#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43784#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43785#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44032#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44033#L1394-3 assume !(1 == ~T11_E~0); 44326#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45060#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45031#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45032#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45090#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44872#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43672#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43673#L1434-3 assume !(1 == ~E_6~0); 44674#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43619#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43620#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43727#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44668#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44669#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 45053#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44536#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43537#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43538#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43701#L1834 assume !(0 == start_simulation_~tmp~3#1); 44782#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44799#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44240#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43426#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 43427#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 45043#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45039#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 44873#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 44671#L1815-2 [2024-11-19 15:03:45,378 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:45,378 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2024-11-19 15:03:45,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:45,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775093158] [2024-11-19 15:03:45,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:45,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:45,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:45,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:45,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:45,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1775093158] [2024-11-19 15:03:45,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1775093158] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:45,440 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:45,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:03:45,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531049001] [2024-11-19 15:03:45,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:45,441 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:45,441 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:45,441 INFO L85 PathProgramCache]: Analyzing trace with hash 2088263070, now seen corresponding path program 1 times [2024-11-19 15:03:45,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:45,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995433409] [2024-11-19 15:03:45,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:45,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:45,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:45,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:45,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:45,497 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [995433409] [2024-11-19 15:03:45,497 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [995433409] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:45,497 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:45,497 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:45,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443884498] [2024-11-19 15:03:45,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:45,498 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:45,498 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:45,498 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:45,499 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:45,499 INFO L87 Difference]: Start difference. First operand 1803 states and 2657 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:45,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:45,548 INFO L93 Difference]: Finished difference Result 1803 states and 2652 transitions. [2024-11-19 15:03:45,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2652 transitions. [2024-11-19 15:03:45,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:45,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1803 states and 2652 transitions. [2024-11-19 15:03:45,557 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1803 [2024-11-19 15:03:45,558 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1803 [2024-11-19 15:03:45,558 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1803 states and 2652 transitions. [2024-11-19 15:03:45,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:45,561 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2652 transitions. [2024-11-19 15:03:45,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states and 2652 transitions. [2024-11-19 15:03:45,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1803. [2024-11-19 15:03:45,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1803 states, 1803 states have (on average 1.4708818635607321) internal successors, (2652), 1802 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:45,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2652 transitions. [2024-11-19 15:03:45,583 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1803 states and 2652 transitions. [2024-11-19 15:03:45,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:45,584 INFO L425 stractBuchiCegarLoop]: Abstraction has 1803 states and 2652 transitions. [2024-11-19 15:03:45,584 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-19 15:03:45,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1803 states and 2652 transitions. [2024-11-19 15:03:45,588 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1640 [2024-11-19 15:03:45,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:45,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:45,590 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:45,590 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:45,590 INFO L745 eck$LassoCheckResult]: Stem: 47230#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47231#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 48160#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48161#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48619#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 48487#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47517#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46987#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46988#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48255#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48394#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48777#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48778#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47740#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47741#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48283#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48205#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 48206#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48358#L1206 assume !(0 == ~M_E~0); 47722#L1206-2 assume !(0 == ~T1_E~0); 47723#L1211-1 assume !(0 == ~T2_E~0); 48612#L1216-1 assume !(0 == ~T3_E~0); 47494#L1221-1 assume !(0 == ~T4_E~0); 47495#L1226-1 assume !(0 == ~T5_E~0); 47167#L1231-1 assume !(0 == ~T6_E~0); 47168#L1236-1 assume !(0 == ~T7_E~0); 48651#L1241-1 assume !(0 == ~T8_E~0); 47564#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47565#L1251-1 assume !(0 == ~T10_E~0); 47796#L1256-1 assume !(0 == ~T11_E~0); 46997#L1261-1 assume !(0 == ~T12_E~0); 46998#L1266-1 assume !(0 == ~E_M~0); 48763#L1271-1 assume !(0 == ~E_1~0); 48384#L1276-1 assume !(0 == ~E_2~0); 48385#L1281-1 assume !(0 == ~E_3~0); 48312#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 47393#L1291-1 assume !(0 == ~E_5~0); 47394#L1296-1 assume !(0 == ~E_6~0); 48116#L1301-1 assume !(0 == ~E_7~0); 48117#L1306-1 assume !(0 == ~E_8~0); 48553#L1311-1 assume !(0 == ~E_9~0); 47353#L1316-1 assume !(0 == ~E_10~0); 47354#L1321-1 assume !(0 == ~E_11~0); 48131#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 47218#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47219#L598 assume 1 == ~m_pc~0; 47268#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47269#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48014#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48015#L1497 assume !(0 != activate_threads_~tmp~1#1); 48726#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48675#L617 assume !(1 == ~t1_pc~0); 47586#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47587#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48466#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48467#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48222#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48223#L636 assume 1 == ~t2_pc~0; 47555#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47556#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47375#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47376#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 48254#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47912#L655 assume !(1 == ~t3_pc~0); 47913#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48638#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48454#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48455#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 48764#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48765#L674 assume 1 == ~t4_pc~0; 47081#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47082#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47108#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47109#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 47377#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47911#L693 assume !(1 == ~t5_pc~0); 48067#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 47724#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47725#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48555#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 47809#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47744#L712 assume 1 == ~t6_pc~0; 47745#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48165#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47363#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47364#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 48271#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48264#L731 assume 1 == ~t7_pc~0; 47220#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47221#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47421#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48558#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 48496#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47326#L750 assume !(1 == ~t8_pc~0); 47018#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47017#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47528#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48568#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47675#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47676#L769 assume 1 == ~t9_pc~0; 48218#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47185#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47186#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47409#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 48431#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48516#L788 assume !(1 == ~t10_pc~0); 48083#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48084#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48639#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48591#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 47322#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47323#L807 assume 1 == ~t11_pc~0; 48522#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48098#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48256#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48695#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 48789#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48622#L826 assume !(1 == ~t12_pc~0); 47747#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47748#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47062#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47063#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 47905#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47817#L1344 assume !(1 == ~M_E~0); 47818#L1344-2 assume !(1 == ~T1_E~0); 47947#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48122#L1354-1 assume !(1 == ~T3_E~0); 48123#L1359-1 assume !(1 == ~T4_E~0); 48507#L1364-1 assume !(1 == ~T5_E~0); 47440#L1369-1 assume !(1 == ~T6_E~0); 47441#L1374-1 assume !(1 == ~T7_E~0); 48129#L1379-1 assume !(1 == ~T8_E~0); 48130#L1384-1 assume !(1 == ~T9_E~0); 48204#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48653#L1394-1 assume !(1 == ~T11_E~0); 48654#L1399-1 assume !(1 == ~T12_E~0); 48734#L1404-1 assume !(1 == ~E_M~0); 47567#L1409-1 assume !(1 == ~E_1~0); 47568#L1414-1 assume !(1 == ~E_2~0); 48410#L1419-1 assume !(1 == ~E_3~0); 47198#L1424-1 assume !(1 == ~E_4~0); 47199#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 48138#L1434-1 assume !(1 == ~E_6~0); 48668#L1439-1 assume !(1 == ~E_7~0); 47239#L1444-1 assume !(1 == ~E_8~0); 47240#L1449-1 assume !(1 == ~E_9~0); 47680#L1454-1 assume !(1 == ~E_10~0); 47681#L1459-1 assume !(1 == ~E_11~0); 48234#L1464-1 assume !(1 == ~E_12~0); 48235#L1469-1 assume { :end_inline_reset_delta_events } true; 48284#L1815-2 [2024-11-19 15:03:45,591 INFO L747 eck$LassoCheckResult]: Loop: 48284#L1815-2 assume !false; 48432#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47594#L1181-1 assume !false; 48532#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48120#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46990#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47717#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48263#L1008 assume !(0 != eval_~tmp~0#1); 47959#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47575#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47576#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48784#L1206-5 assume !(0 == ~T1_E~0); 48233#L1211-3 assume !(0 == ~T2_E~0); 47308#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47309#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47927#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47380#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47381#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47718#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48704#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48606#L1251-3 assume !(0 == ~T10_E~0); 48343#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47332#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47333#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47378#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47379#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47868#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47869#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48407#L1291-3 assume !(0 == ~E_5~0); 48408#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48770#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48731#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47988#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47254#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47255#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47334#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 48092#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48418#L598-42 assume 1 == ~m_pc~0; 48419#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48539#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47749#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47750#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48732#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48145#L617-42 assume 1 == ~t1_pc~0; 47921#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47792#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47793#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48729#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47488#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47489#L636-42 assume !(1 == ~t2_pc~0); 47957#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47958#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48037#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48038#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 48503#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48368#L655-42 assume 1 == ~t3_pc~0; 48369#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47934#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48445#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48446#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48637#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48574#L674-42 assume !(1 == ~t4_pc~0); 48351#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 48272#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48273#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48478#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48065#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48066#L693-42 assume 1 == ~t5_pc~0; 48331#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48332#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48118#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48119#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48388#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47690#L712-42 assume !(1 == ~t6_pc~0); 47691#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 48006#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47324#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47325#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47801#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47802#L731-42 assume !(1 == ~t7_pc~0); 47480#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 47481#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48141#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47707#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47708#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47388#L750-42 assume 1 == ~t8_pc~0; 47389#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47975#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48279#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47271#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47272#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48064#L769-42 assume 1 == ~t9_pc~0; 47892#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47893#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48579#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48773#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 47490#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47491#L788-42 assume 1 == ~t10_pc~0; 48072#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48298#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48269#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48270#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48782#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48757#L807-42 assume !(1 == ~t11_pc~0); 47104#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 47105#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47979#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47226#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47227#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47485#L826-42 assume 1 == ~t12_pc~0; 47486#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47696#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48088#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47475#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47476#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48347#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48348#L1344-5 assume !(1 == ~T1_E~0); 48274#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47647#L1354-3 assume !(1 == ~T3_E~0); 47648#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48288#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48760#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48667#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47397#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47398#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47645#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47646#L1394-3 assume !(1 == ~T11_E~0); 47939#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48673#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48644#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48645#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48703#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48485#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47285#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47286#L1434-3 assume !(1 == ~E_6~0); 48287#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47232#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47233#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47340#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 48281#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48282#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48666#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48149#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47150#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47151#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 47314#L1834 assume !(0 == start_simulation_~tmp~3#1); 48395#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48412#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47853#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47039#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 47040#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48656#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48652#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 48486#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 48284#L1815-2 [2024-11-19 15:03:45,591 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:45,591 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2024-11-19 15:03:45,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:45,592 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771327786] [2024-11-19 15:03:45,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:45,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:45,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:45,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:45,655 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:45,655 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771327786] [2024-11-19 15:03:45,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771327786] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:45,656 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:45,656 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:45,656 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1376881678] [2024-11-19 15:03:45,656 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:45,656 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:45,657 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:45,657 INFO L85 PathProgramCache]: Analyzing trace with hash 786297820, now seen corresponding path program 1 times [2024-11-19 15:03:45,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:45,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450281127] [2024-11-19 15:03:45,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:45,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:45,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:45,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:45,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:45,700 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450281127] [2024-11-19 15:03:45,700 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450281127] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:45,700 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:45,700 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:45,701 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [21983589] [2024-11-19 15:03:45,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:45,701 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:45,701 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:45,701 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:03:45,701 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:03:45,701 INFO L87 Difference]: Start difference. First operand 1803 states and 2652 transitions. cyclomatic complexity: 850 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:45,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:45,849 INFO L93 Difference]: Finished difference Result 3350 states and 4912 transitions. [2024-11-19 15:03:45,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3350 states and 4912 transitions. [2024-11-19 15:03:45,859 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3161 [2024-11-19 15:03:45,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3350 states to 3350 states and 4912 transitions. [2024-11-19 15:03:45,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3350 [2024-11-19 15:03:45,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3350 [2024-11-19 15:03:45,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3350 states and 4912 transitions. [2024-11-19 15:03:45,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:45,878 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3350 states and 4912 transitions. [2024-11-19 15:03:45,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3350 states and 4912 transitions. [2024-11-19 15:03:45,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3350 to 3350. [2024-11-19 15:03:45,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3350 states, 3350 states have (on average 1.4662686567164178) internal successors, (4912), 3349 states have internal predecessors, (4912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:45,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3350 states to 3350 states and 4912 transitions. [2024-11-19 15:03:45,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3350 states and 4912 transitions. [2024-11-19 15:03:45,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:03:45,936 INFO L425 stractBuchiCegarLoop]: Abstraction has 3350 states and 4912 transitions. [2024-11-19 15:03:45,936 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-19 15:03:45,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3350 states and 4912 transitions. [2024-11-19 15:03:45,943 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3161 [2024-11-19 15:03:45,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:45,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:45,945 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:45,945 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:45,946 INFO L745 eck$LassoCheckResult]: Stem: 52393#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52394#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 53350#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53351#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53842#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 53694#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52680#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52150#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52151#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53448#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53600#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54032#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54033#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 52912#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52913#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53480#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53397#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53398#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53562#L1206 assume !(0 == ~M_E~0); 52890#L1206-2 assume !(0 == ~T1_E~0); 52891#L1211-1 assume !(0 == ~T2_E~0); 53835#L1216-1 assume !(0 == ~T3_E~0); 52657#L1221-1 assume !(0 == ~T4_E~0); 52658#L1226-1 assume !(0 == ~T5_E~0); 52332#L1231-1 assume !(0 == ~T6_E~0); 52333#L1236-1 assume !(0 == ~T7_E~0); 53879#L1241-1 assume !(0 == ~T8_E~0); 52727#L1246-1 assume !(0 == ~T9_E~0); 52728#L1251-1 assume !(0 == ~T10_E~0); 52969#L1256-1 assume !(0 == ~T11_E~0); 52160#L1261-1 assume !(0 == ~T12_E~0); 52161#L1266-1 assume !(0 == ~E_M~0); 54015#L1271-1 assume !(0 == ~E_1~0); 53588#L1276-1 assume !(0 == ~E_2~0); 53589#L1281-1 assume !(0 == ~E_3~0); 53512#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 52556#L1291-1 assume !(0 == ~E_5~0); 52557#L1296-1 assume !(0 == ~E_6~0); 53302#L1301-1 assume !(0 == ~E_7~0); 53303#L1306-1 assume !(0 == ~E_8~0); 53768#L1311-1 assume !(0 == ~E_9~0); 52516#L1316-1 assume !(0 == ~E_10~0); 52517#L1321-1 assume !(0 == ~E_11~0); 53318#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 52381#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52382#L598 assume 1 == ~m_pc~0; 52431#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52432#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53198#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53199#L1497 assume !(0 != activate_threads_~tmp~1#1); 53968#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53910#L617 assume !(1 == ~t1_pc~0); 52749#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52750#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53673#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53674#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53414#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53415#L636 assume 1 == ~t2_pc~0; 52718#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52719#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52538#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52539#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 53446#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53088#L655 assume !(1 == ~t3_pc~0); 53089#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53864#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53661#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53662#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 54016#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54017#L674 assume 1 == ~t4_pc~0; 52244#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52245#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52271#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52272#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 52542#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53086#L693 assume !(1 == ~t5_pc~0); 53253#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52894#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52895#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53770#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 52984#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52914#L712 assume 1 == ~t6_pc~0; 52915#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53354#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52526#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52527#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 53468#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53459#L731 assume 1 == ~t7_pc~0; 52383#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52384#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52584#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53776#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 53704#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52489#L750 assume !(1 == ~t8_pc~0); 52181#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 52180#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52691#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53786#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52842#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52843#L769 assume 1 == ~t9_pc~0; 53412#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52348#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52349#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52572#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 53638#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53727#L788 assume !(1 == ~t10_pc~0); 53268#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53269#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53865#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53811#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 52485#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52486#L807 assume 1 == ~t11_pc~0; 53733#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53283#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53449#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53931#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 54055#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53845#L826 assume !(1 == ~t12_pc~0); 52917#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52918#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52225#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52226#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 53080#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52990#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 52991#L1344-2 assume !(1 == ~T1_E~0); 55413#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55412#L1354-1 assume !(1 == ~T3_E~0); 55411#L1359-1 assume !(1 == ~T4_E~0); 55410#L1364-1 assume !(1 == ~T5_E~0); 55409#L1369-1 assume !(1 == ~T6_E~0); 55408#L1374-1 assume !(1 == ~T7_E~0); 55407#L1379-1 assume !(1 == ~T8_E~0); 55406#L1384-1 assume !(1 == ~T9_E~0); 53393#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 55405#L1394-1 assume !(1 == ~T11_E~0); 54043#L1399-1 assume !(1 == ~T12_E~0); 53980#L1404-1 assume !(1 == ~E_M~0); 52730#L1409-1 assume !(1 == ~E_1~0); 52731#L1414-1 assume !(1 == ~E_2~0); 53616#L1419-1 assume !(1 == ~E_3~0); 52361#L1424-1 assume !(1 == ~E_4~0); 52362#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 53327#L1434-1 assume !(1 == ~E_6~0); 53901#L1439-1 assume !(1 == ~E_7~0); 52402#L1444-1 assume !(1 == ~E_8~0); 52403#L1449-1 assume !(1 == ~E_9~0); 52848#L1454-1 assume !(1 == ~E_10~0); 52849#L1459-1 assume !(1 == ~E_11~0); 53929#L1464-1 assume !(1 == ~E_12~0); 53481#L1469-1 assume { :end_inline_reset_delta_events } true; 53482#L1815-2 [2024-11-19 15:03:45,946 INFO L747 eck$LassoCheckResult]: Loop: 53482#L1815-2 assume !false; 53639#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52757#L1181-1 assume !false; 53882#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53883#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52885#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52886#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53456#L1008 assume !(0 != eval_~tmp~0#1); 53458#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52740#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52741#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54056#L1206-5 assume !(0 == ~T1_E~0); 55302#L1211-3 assume !(0 == ~T2_E~0); 55301#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55300#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55299#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55298#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55297#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55296#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 55295#L1246-3 assume !(0 == ~T9_E~0); 55294#L1251-3 assume !(0 == ~T10_E~0); 55293#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 55292#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 55291#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 55290#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55289#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55288#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55287#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55286#L1291-3 assume !(0 == ~E_5~0); 55285#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55284#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 55283#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 55282#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 55281#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55280#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55279#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 55278#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55277#L598-42 assume 1 == ~m_pc~0; 55275#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 55274#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55273#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55272#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55271#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55270#L617-42 assume 1 == ~t1_pc~0; 53098#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52965#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52966#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53972#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52651#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52652#L636-42 assume !(1 == ~t2_pc~0); 53136#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 53137#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53222#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53223#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 53714#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53572#L655-42 assume 1 == ~t3_pc~0; 53573#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53113#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53652#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53653#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53863#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53792#L674-42 assume 1 == ~t4_pc~0; 53793#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53469#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53470#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53685#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53250#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53251#L693-42 assume 1 == ~t5_pc~0; 53852#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55243#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55242#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55241#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55240#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55239#L712-42 assume !(1 == ~t6_pc~0); 55237#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 55236#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55235#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55234#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 55233#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55232#L731-42 assume 1 == ~t7_pc~0; 55230#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55229#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55228#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55227#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 55226#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55225#L750-42 assume !(1 == ~t8_pc~0); 55223#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 55222#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55221#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55220#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 55219#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55218#L769-42 assume 1 == ~t9_pc~0; 55216#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55215#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55214#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55213#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 55212#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55211#L788-42 assume 1 == ~t10_pc~0; 55209#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 55208#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55207#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55206#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55205#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55204#L807-42 assume 1 == ~t11_pc~0; 53633#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52268#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53161#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52389#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52390#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52648#L826-42 assume 1 == ~t12_pc~0; 52649#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52863#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53273#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52638#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 52639#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53550#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53551#L1344-5 assume !(1 == ~T1_E~0); 53471#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52810#L1354-3 assume !(1 == ~T3_E~0); 52811#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53486#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54011#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53900#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52560#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52561#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52808#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52809#L1394-3 assume !(1 == ~T11_E~0); 53118#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53906#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53872#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53873#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53940#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53692#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52448#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52449#L1434-3 assume !(1 == ~E_6~0); 53485#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52395#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52396#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 52503#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53478#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53479#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53898#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53338#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52313#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52314#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 52477#L1834 assume !(0 == start_simulation_~tmp~3#1); 53601#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53618#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53027#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52202#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 52203#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53888#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54028#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53693#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 53482#L1815-2 [2024-11-19 15:03:45,946 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:45,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1144190578, now seen corresponding path program 1 times [2024-11-19 15:03:45,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:45,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812456734] [2024-11-19 15:03:45,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:45,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:45,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:46,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:46,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:46,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1812456734] [2024-11-19 15:03:46,024 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1812456734] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:46,024 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:46,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:46,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393801385] [2024-11-19 15:03:46,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:46,024 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:46,025 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:46,025 INFO L85 PathProgramCache]: Analyzing trace with hash -129530276, now seen corresponding path program 1 times [2024-11-19 15:03:46,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:46,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077402849] [2024-11-19 15:03:46,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:46,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:46,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:46,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:46,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:46,076 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2077402849] [2024-11-19 15:03:46,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2077402849] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:46,076 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:46,077 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:46,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1935626158] [2024-11-19 15:03:46,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:46,077 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:46,077 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:46,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:03:46,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:03:46,078 INFO L87 Difference]: Start difference. First operand 3350 states and 4912 transitions. cyclomatic complexity: 1564 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:46,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:46,234 INFO L93 Difference]: Finished difference Result 6234 states and 9121 transitions. [2024-11-19 15:03:46,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6234 states and 9121 transitions. [2024-11-19 15:03:46,253 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6017 [2024-11-19 15:03:46,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6234 states to 6234 states and 9121 transitions. [2024-11-19 15:03:46,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6234 [2024-11-19 15:03:46,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6234 [2024-11-19 15:03:46,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6234 states and 9121 transitions. [2024-11-19 15:03:46,274 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:46,274 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6234 states and 9121 transitions. [2024-11-19 15:03:46,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6234 states and 9121 transitions. [2024-11-19 15:03:46,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6234 to 6232. [2024-11-19 15:03:46,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6232 states, 6232 states have (on average 1.4632541720154044) internal successors, (9119), 6231 states have internal predecessors, (9119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:46,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6232 states to 6232 states and 9119 transitions. [2024-11-19 15:03:46,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6232 states and 9119 transitions. [2024-11-19 15:03:46,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:03:46,360 INFO L425 stractBuchiCegarLoop]: Abstraction has 6232 states and 9119 transitions. [2024-11-19 15:03:46,360 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-19 15:03:46,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6232 states and 9119 transitions. [2024-11-19 15:03:46,373 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6017 [2024-11-19 15:03:46,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:46,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:46,375 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:46,375 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:46,375 INFO L745 eck$LassoCheckResult]: Stem: 61989#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 61990#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 62940#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62941#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63443#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 63295#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62280#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61744#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61745#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63040#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63191#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63649#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63650#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62504#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62505#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63069#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 62987#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 62988#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63152#L1206 assume !(0 == ~M_E~0); 62486#L1206-2 assume !(0 == ~T1_E~0); 62487#L1211-1 assume !(0 == ~T2_E~0); 63435#L1216-1 assume !(0 == ~T3_E~0); 62257#L1221-1 assume !(0 == ~T4_E~0); 62258#L1226-1 assume !(0 == ~T5_E~0); 61925#L1231-1 assume !(0 == ~T6_E~0); 61926#L1236-1 assume !(0 == ~T7_E~0); 63481#L1241-1 assume !(0 == ~T8_E~0); 62327#L1246-1 assume !(0 == ~T9_E~0); 62328#L1251-1 assume !(0 == ~T10_E~0); 62562#L1256-1 assume !(0 == ~T11_E~0); 61754#L1261-1 assume !(0 == ~T12_E~0); 61755#L1266-1 assume !(0 == ~E_M~0); 63626#L1271-1 assume !(0 == ~E_1~0); 63180#L1276-1 assume !(0 == ~E_2~0); 63181#L1281-1 assume !(0 == ~E_3~0); 63101#L1286-1 assume !(0 == ~E_4~0); 62154#L1291-1 assume !(0 == ~E_5~0); 62155#L1296-1 assume !(0 == ~E_6~0); 62890#L1301-1 assume !(0 == ~E_7~0); 62891#L1306-1 assume !(0 == ~E_8~0); 63369#L1311-1 assume !(0 == ~E_9~0); 62114#L1316-1 assume !(0 == ~E_10~0); 62115#L1321-1 assume !(0 == ~E_11~0); 62908#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 61977#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61978#L598 assume 1 == ~m_pc~0; 62028#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62029#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62787#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62788#L1497 assume !(0 != activate_threads_~tmp~1#1); 63573#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63508#L617 assume !(1 == ~t1_pc~0); 62349#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62350#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63270#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63271#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 63004#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63005#L636 assume 1 == ~t2_pc~0; 62318#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62319#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62136#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62137#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 63039#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62681#L655 assume !(1 == ~t3_pc~0); 62682#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63467#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63258#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63259#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 63627#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63628#L674 assume 1 == ~t4_pc~0; 61838#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61839#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61865#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61866#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 62138#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62680#L693 assume !(1 == ~t5_pc~0); 62840#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62488#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62489#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63371#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 62575#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62508#L712 assume 1 == ~t6_pc~0; 62509#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62945#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62124#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62125#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 63057#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63050#L731 assume 1 == ~t7_pc~0; 61979#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61980#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62182#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63377#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 63306#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62087#L750 assume !(1 == ~t8_pc~0); 61775#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 61774#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62291#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63387#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62438#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62439#L769 assume 1 == ~t9_pc~0; 63000#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61943#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61944#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62170#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 63234#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 63327#L788 assume !(1 == ~t10_pc~0); 62857#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 62858#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63469#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 63412#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 62083#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62084#L807 assume 1 == ~t11_pc~0; 63335#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62872#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63041#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 63530#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 63695#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 63449#L826 assume !(1 == ~t12_pc~0); 62511#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62512#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61819#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61820#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 62674#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62583#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 62584#L1344-2 assume !(1 == ~T1_E~0); 62717#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62898#L1354-1 assume !(1 == ~T3_E~0); 62899#L1359-1 assume !(1 == ~T4_E~0); 63318#L1364-1 assume !(1 == ~T5_E~0); 62201#L1369-1 assume !(1 == ~T6_E~0); 62202#L1374-1 assume !(1 == ~T7_E~0); 62906#L1379-1 assume !(1 == ~T8_E~0); 62907#L1384-1 assume !(1 == ~T9_E~0); 62986#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63483#L1394-1 assume !(1 == ~T11_E~0); 63484#L1399-1 assume !(1 == ~T12_E~0); 63589#L1404-1 assume !(1 == ~E_M~0); 62330#L1409-1 assume !(1 == ~E_1~0); 62331#L1414-1 assume !(1 == ~E_2~0); 63209#L1419-1 assume !(1 == ~E_3~0); 63210#L1424-1 assume !(1 == ~E_4~0); 64313#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 64311#L1434-1 assume !(1 == ~E_6~0); 64309#L1439-1 assume !(1 == ~E_7~0); 64307#L1444-1 assume !(1 == ~E_8~0); 64305#L1449-1 assume !(1 == ~E_9~0); 64303#L1454-1 assume !(1 == ~E_10~0); 63852#L1459-1 assume !(1 == ~E_11~0); 63829#L1464-1 assume !(1 == ~E_12~0); 63813#L1469-1 assume { :end_inline_reset_delta_events } true; 63732#L1815-2 [2024-11-19 15:03:46,376 INFO L747 eck$LassoCheckResult]: Loop: 63732#L1815-2 assume !false; 63726#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63722#L1181-1 assume !false; 63721#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63718#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63707#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63706#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 63704#L1008 assume !(0 != eval_~tmp~0#1); 63703#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63700#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63701#L1206-5 assume !(0 == ~T1_E~0); 64927#L1211-3 assume !(0 == ~T2_E~0); 64925#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 64923#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 64921#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 64919#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64917#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64914#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64912#L1246-3 assume !(0 == ~T9_E~0); 64910#L1251-3 assume !(0 == ~T10_E~0); 64908#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 64906#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 64904#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 64901#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64899#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64897#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64895#L1286-3 assume !(0 == ~E_4~0); 64893#L1291-3 assume !(0 == ~E_5~0); 64891#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 64888#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64886#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 64884#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 64882#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 64880#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 64878#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 64875#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64873#L598-42 assume 1 == ~m_pc~0; 64870#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 64868#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64866#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64864#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 64861#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64860#L617-42 assume !(1 == ~t1_pc~0); 64858#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 64857#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64856#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64854#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64851#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64849#L636-42 assume 1 == ~t2_pc~0; 64846#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64844#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64842#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64840#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 64837#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64835#L655-42 assume 1 == ~t3_pc~0; 64832#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64830#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64828#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64826#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64823#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64821#L674-42 assume !(1 == ~t4_pc~0); 64818#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 64816#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64814#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64812#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64809#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64807#L693-42 assume 1 == ~t5_pc~0; 64804#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64802#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64800#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64798#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64797#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64796#L712-42 assume !(1 == ~t6_pc~0); 64793#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 64790#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64788#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64786#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64784#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64782#L731-42 assume 1 == ~t7_pc~0; 64779#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64776#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64774#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64772#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64770#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64768#L750-42 assume !(1 == ~t8_pc~0); 64765#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 64762#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64760#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64758#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 64756#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64754#L769-42 assume !(1 == ~t9_pc~0); 64752#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 64748#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64746#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64744#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 64742#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64740#L788-42 assume 1 == ~t10_pc~0; 64737#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64734#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64732#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64730#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 64728#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64726#L807-42 assume 1 == ~t11_pc~0; 64723#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64720#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64718#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64716#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 64714#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64693#L826-42 assume 1 == ~t12_pc~0; 64678#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 64667#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64657#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64642#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64628#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64626#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 63141#L1344-5 assume !(1 == ~T1_E~0); 64603#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64590#L1354-3 assume !(1 == ~T3_E~0); 64574#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64565#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64563#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64553#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64543#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64531#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64528#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64518#L1394-3 assume !(1 == ~T11_E~0); 64510#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64501#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64492#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64482#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64471#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64462#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64453#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64443#L1434-3 assume !(1 == ~E_6~0); 64434#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64412#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 64410#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 64408#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 64406#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 64405#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 64381#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64359#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64353#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64352#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 64351#L1834 assume !(0 == start_simulation_~tmp~3#1); 63192#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64329#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63858#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63855#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 63834#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63830#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63828#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 63812#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 63732#L1815-2 [2024-11-19 15:03:46,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:46,376 INFO L85 PathProgramCache]: Analyzing trace with hash -1221844492, now seen corresponding path program 1 times [2024-11-19 15:03:46,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:46,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372202679] [2024-11-19 15:03:46,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:46,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:46,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:46,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:46,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:46,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372202679] [2024-11-19 15:03:46,541 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [372202679] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:46,541 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:46,541 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:46,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911164765] [2024-11-19 15:03:46,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:46,541 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:46,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:46,542 INFO L85 PathProgramCache]: Analyzing trace with hash 1567697248, now seen corresponding path program 1 times [2024-11-19 15:03:46,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:46,542 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120007732] [2024-11-19 15:03:46,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:46,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:46,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:46,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:46,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:46,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120007732] [2024-11-19 15:03:46,601 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1120007732] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:46,601 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:46,601 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:46,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [971178885] [2024-11-19 15:03:46,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:46,602 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:46,602 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:46,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:03:46,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:03:46,603 INFO L87 Difference]: Start difference. First operand 6232 states and 9119 transitions. cyclomatic complexity: 2891 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:46,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:46,783 INFO L93 Difference]: Finished difference Result 11774 states and 17190 transitions. [2024-11-19 15:03:46,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11774 states and 17190 transitions. [2024-11-19 15:03:46,875 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11543 [2024-11-19 15:03:46,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11774 states to 11774 states and 17190 transitions. [2024-11-19 15:03:46,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11774 [2024-11-19 15:03:46,966 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11774 [2024-11-19 15:03:46,967 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11774 states and 17190 transitions. [2024-11-19 15:03:46,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:46,993 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11774 states and 17190 transitions. [2024-11-19 15:03:47,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11774 states and 17190 transitions. [2024-11-19 15:03:47,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11774 to 11770. [2024-11-19 15:03:47,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11770 states, 11770 states have (on average 1.4601529311809687) internal successors, (17186), 11769 states have internal predecessors, (17186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:47,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11770 states to 11770 states and 17186 transitions. [2024-11-19 15:03:47,274 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11770 states and 17186 transitions. [2024-11-19 15:03:47,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:03:47,275 INFO L425 stractBuchiCegarLoop]: Abstraction has 11770 states and 17186 transitions. [2024-11-19 15:03:47,275 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-19 15:03:47,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11770 states and 17186 transitions. [2024-11-19 15:03:47,318 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11543 [2024-11-19 15:03:47,319 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:47,319 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:47,321 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:47,321 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:47,321 INFO L745 eck$LassoCheckResult]: Stem: 80005#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 80006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 80949#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 80950#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81437#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 81287#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 80292#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79760#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79761#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81046#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81189#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 81623#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 81624#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 80518#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 80519#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 81076#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 80995#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 80996#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81153#L1206 assume !(0 == ~M_E~0); 80500#L1206-2 assume !(0 == ~T1_E~0); 80501#L1211-1 assume !(0 == ~T2_E~0); 81429#L1216-1 assume !(0 == ~T3_E~0); 80269#L1221-1 assume !(0 == ~T4_E~0); 80270#L1226-1 assume !(0 == ~T5_E~0); 79941#L1231-1 assume !(0 == ~T6_E~0); 79942#L1236-1 assume !(0 == ~T7_E~0); 81472#L1241-1 assume !(0 == ~T8_E~0); 80339#L1246-1 assume !(0 == ~T9_E~0); 80340#L1251-1 assume !(0 == ~T10_E~0); 80574#L1256-1 assume !(0 == ~T11_E~0); 79770#L1261-1 assume !(0 == ~T12_E~0); 79771#L1266-1 assume !(0 == ~E_M~0); 81604#L1271-1 assume !(0 == ~E_1~0); 81179#L1276-1 assume !(0 == ~E_2~0); 81180#L1281-1 assume !(0 == ~E_3~0); 81105#L1286-1 assume !(0 == ~E_4~0); 80168#L1291-1 assume !(0 == ~E_5~0); 80169#L1296-1 assume !(0 == ~E_6~0); 80905#L1301-1 assume !(0 == ~E_7~0); 80906#L1306-1 assume !(0 == ~E_8~0); 81362#L1311-1 assume !(0 == ~E_9~0); 80128#L1316-1 assume !(0 == ~E_10~0); 80129#L1321-1 assume !(0 == ~E_11~0); 80920#L1326-1 assume !(0 == ~E_12~0); 79993#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79994#L598 assume 1 == ~m_pc~0; 80043#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 80044#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80801#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80802#L1497 assume !(0 != activate_threads_~tmp~1#1); 81558#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81497#L617 assume !(1 == ~t1_pc~0); 80361#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 80362#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81264#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81265#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81012#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81013#L636 assume 1 == ~t2_pc~0; 80330#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 80331#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80150#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 80151#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 81045#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80691#L655 assume !(1 == ~t3_pc~0); 80692#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81458#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81252#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81253#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 81605#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81606#L674 assume 1 == ~t4_pc~0; 79854#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79855#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79881#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 79882#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 80152#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80690#L693 assume !(1 == ~t5_pc~0); 80855#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 80502#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80503#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81364#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 80587#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80522#L712 assume 1 == ~t6_pc~0; 80523#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 80954#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80138#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 80139#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 81064#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81057#L731 assume 1 == ~t7_pc~0; 79995#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 79996#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 80196#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 81367#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 81300#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 80101#L750 assume !(1 == ~t8_pc~0); 79791#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 79790#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 80303#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 81377#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 80452#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 80453#L769 assume 1 == ~t9_pc~0; 81008#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 79959#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 79960#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 80184#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 81228#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81324#L788 assume !(1 == ~t10_pc~0); 80871#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 80872#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81459#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81402#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 80097#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 80098#L807 assume 1 == ~t11_pc~0; 81330#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80886#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81047#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81518#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 81652#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81440#L826 assume !(1 == ~t12_pc~0); 80525#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 80526#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 79835#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 79836#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 80684#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 80595#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 80596#L1344-2 assume !(1 == ~T1_E~0); 80728#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80911#L1354-1 assume !(1 == ~T3_E~0); 80912#L1359-1 assume !(1 == ~T4_E~0); 81612#L1364-1 assume !(1 == ~T5_E~0); 81613#L1369-1 assume !(1 == ~T6_E~0); 81291#L1374-1 assume !(1 == ~T7_E~0); 81292#L1379-1 assume !(1 == ~T8_E~0); 80993#L1384-1 assume !(1 == ~T9_E~0); 80994#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 81650#L1394-1 assume !(1 == ~T11_E~0); 81636#L1399-1 assume !(1 == ~T12_E~0); 81637#L1404-1 assume !(1 == ~E_M~0); 80342#L1409-1 assume !(1 == ~E_1~0); 80343#L1414-1 assume !(1 == ~E_2~0); 81206#L1419-1 assume !(1 == ~E_3~0); 81207#L1424-1 assume !(1 == ~E_4~0); 81737#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 81735#L1434-1 assume !(1 == ~E_6~0); 81733#L1439-1 assume !(1 == ~E_7~0); 81731#L1444-1 assume !(1 == ~E_8~0); 81729#L1449-1 assume !(1 == ~E_9~0); 81727#L1454-1 assume !(1 == ~E_10~0); 81725#L1459-1 assume !(1 == ~E_11~0); 81706#L1464-1 assume !(1 == ~E_12~0); 81695#L1469-1 assume { :end_inline_reset_delta_events } true; 81687#L1815-2 [2024-11-19 15:03:47,321 INFO L747 eck$LassoCheckResult]: Loop: 81687#L1815-2 assume !false; 81681#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81677#L1181-1 assume !false; 81676#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81673#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81662#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81661#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 81659#L1008 assume !(0 != eval_~tmp~0#1); 81658#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81657#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81655#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 81656#L1206-5 assume !(0 == ~T1_E~0); 85061#L1211-3 assume !(0 == ~T2_E~0); 85059#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85057#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 84662#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 84259#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 84257#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 84255#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 84253#L1246-3 assume !(0 == ~T9_E~0); 84251#L1251-3 assume !(0 == ~T10_E~0); 84249#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 84246#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 84244#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 84243#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 83991#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 83989#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 83987#L1286-3 assume !(0 == ~E_4~0); 83985#L1291-3 assume !(0 == ~E_5~0); 83982#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 83980#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 83978#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 83976#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 83974#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 83972#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 83971#L1326-3 assume !(0 == ~E_12~0); 83970#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83969#L598-42 assume !(1 == ~m_pc~0); 83968#L598-44 is_master_triggered_~__retres1~0#1 := 0; 83965#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83963#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83961#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 83960#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83959#L617-42 assume !(1 == ~t1_pc~0); 82397#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 82394#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82391#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82388#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82385#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82381#L636-42 assume !(1 == ~t2_pc~0); 82377#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 82373#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82370#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82367#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 82364#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82360#L655-42 assume 1 == ~t3_pc~0; 82355#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 82352#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82350#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82348#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82344#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82340#L674-42 assume 1 == ~t4_pc~0; 82337#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82332#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82329#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82326#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82323#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82319#L693-42 assume 1 == ~t5_pc~0; 82315#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82310#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82308#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82306#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82219#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82217#L712-42 assume 1 == ~t6_pc~0; 82215#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 82211#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82209#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82194#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 82193#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82192#L731-42 assume !(1 == ~t7_pc~0); 82191#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 82153#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82147#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82141#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 82136#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82131#L750-42 assume !(1 == ~t8_pc~0); 82125#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 82082#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82079#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82077#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82075#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82073#L769-42 assume 1 == ~t9_pc~0; 82069#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82066#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82064#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 82062#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 82060#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 82058#L788-42 assume !(1 == ~t10_pc~0); 82047#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 82040#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82017#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82015#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 82012#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82010#L807-42 assume 1 == ~t11_pc~0; 82007#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 82005#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 82003#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 82001#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 82000#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81942#L826-42 assume !(1 == ~t12_pc~0); 81935#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 81932#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81930#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 81928#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 81926#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81908#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 81142#L1344-5 assume !(1 == ~T1_E~0); 81905#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81903#L1354-3 assume !(1 == ~T3_E~0); 81901#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81886#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81885#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 81883#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81881#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 81864#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 81427#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 81849#L1394-3 assume !(1 == ~T11_E~0); 81844#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 81839#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 81834#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 81828#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81823#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81818#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81812#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81809#L1434-3 assume !(1 == ~E_6~0); 81806#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 81802#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 81799#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 81796#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 81793#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 81790#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 81786#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81774#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81768#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81767#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 81766#L1834 assume !(0 == start_simulation_~tmp~3#1); 81190#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81755#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81750#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81749#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 81748#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81707#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81703#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 81694#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 81687#L1815-2 [2024-11-19 15:03:47,322 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:47,322 INFO L85 PathProgramCache]: Analyzing trace with hash 931262326, now seen corresponding path program 1 times [2024-11-19 15:03:47,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:47,322 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250963260] [2024-11-19 15:03:47,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:47,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:47,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:47,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:47,362 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:47,362 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250963260] [2024-11-19 15:03:47,362 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [250963260] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:47,362 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:47,362 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:03:47,363 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514858863] [2024-11-19 15:03:47,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:47,363 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:47,363 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:47,363 INFO L85 PathProgramCache]: Analyzing trace with hash 639245924, now seen corresponding path program 1 times [2024-11-19 15:03:47,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:47,363 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618172923] [2024-11-19 15:03:47,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:47,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:47,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:47,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:47,398 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:47,398 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1618172923] [2024-11-19 15:03:47,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1618172923] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:47,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:47,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:47,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461911796] [2024-11-19 15:03:47,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:47,399 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:47,399 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:47,399 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:47,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:47,399 INFO L87 Difference]: Start difference. First operand 11770 states and 17186 transitions. cyclomatic complexity: 5424 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:47,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:47,621 INFO L93 Difference]: Finished difference Result 23151 states and 33588 transitions. [2024-11-19 15:03:47,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23151 states and 33588 transitions. [2024-11-19 15:03:47,731 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22909 [2024-11-19 15:03:47,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23151 states to 23151 states and 33588 transitions. [2024-11-19 15:03:47,774 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23151 [2024-11-19 15:03:47,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23151 [2024-11-19 15:03:47,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23151 states and 33588 transitions. [2024-11-19 15:03:47,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:47,810 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23151 states and 33588 transitions. [2024-11-19 15:03:47,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23151 states and 33588 transitions. [2024-11-19 15:03:48,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23151 to 22431. [2024-11-19 15:03:48,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22431 states, 22431 states have (on average 1.4520975435780838) internal successors, (32572), 22430 states have internal predecessors, (32572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:48,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22431 states to 22431 states and 32572 transitions. [2024-11-19 15:03:48,237 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22431 states and 32572 transitions. [2024-11-19 15:03:48,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:48,237 INFO L425 stractBuchiCegarLoop]: Abstraction has 22431 states and 32572 transitions. [2024-11-19 15:03:48,238 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-19 15:03:48,238 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22431 states and 32572 transitions. [2024-11-19 15:03:48,292 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22189 [2024-11-19 15:03:48,292 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:48,292 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:48,293 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:48,294 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:48,294 INFO L745 eck$LassoCheckResult]: Stem: 114932#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 114933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 115916#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115917#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 116485#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 116313#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115219#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114688#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 114689#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 116029#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116196#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 116766#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 116767#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 115454#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 115455#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 116063#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 115970#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 115971#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 116156#L1206 assume !(0 == ~M_E~0); 115433#L1206-2 assume !(0 == ~T1_E~0); 115434#L1211-1 assume !(0 == ~T2_E~0); 116478#L1216-1 assume !(0 == ~T3_E~0); 115195#L1221-1 assume !(0 == ~T4_E~0); 115196#L1226-1 assume !(0 == ~T5_E~0); 114870#L1231-1 assume !(0 == ~T6_E~0); 114871#L1236-1 assume !(0 == ~T7_E~0); 116531#L1241-1 assume !(0 == ~T8_E~0); 115267#L1246-1 assume !(0 == ~T9_E~0); 115268#L1251-1 assume !(0 == ~T10_E~0); 115510#L1256-1 assume !(0 == ~T11_E~0); 114698#L1261-1 assume !(0 == ~T12_E~0); 114699#L1266-1 assume !(0 == ~E_M~0); 116739#L1271-1 assume !(0 == ~E_1~0); 116185#L1276-1 assume !(0 == ~E_2~0); 116186#L1281-1 assume !(0 == ~E_3~0); 116102#L1286-1 assume !(0 == ~E_4~0); 115093#L1291-1 assume !(0 == ~E_5~0); 115094#L1296-1 assume !(0 == ~E_6~0); 115867#L1301-1 assume !(0 == ~E_7~0); 115868#L1306-1 assume !(0 == ~E_8~0); 116404#L1311-1 assume !(0 == ~E_9~0); 115054#L1316-1 assume !(0 == ~E_10~0); 115055#L1321-1 assume !(0 == ~E_11~0); 115884#L1326-1 assume !(0 == ~E_12~0); 114920#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114921#L598 assume !(1 == ~m_pc~0); 115658#L598-2 is_master_triggered_~__retres1~0#1 := 0; 115659#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115748#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 115749#L1497 assume !(0 != activate_threads_~tmp~1#1); 116656#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116568#L617 assume !(1 == ~t1_pc~0); 115290#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 115291#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116282#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 116283#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 115988#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115989#L636 assume 1 == ~t2_pc~0; 115258#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 115259#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 115075#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 115076#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 116028#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115636#L655 assume !(1 == ~t3_pc~0); 115637#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 116515#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116267#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 116268#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 116741#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116742#L674 assume 1 == ~t4_pc~0; 114781#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 114782#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114808#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 114809#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 115079#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 115632#L693 assume !(1 == ~t5_pc~0); 115810#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 115437#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 115438#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 116406#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 115526#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 115456#L712 assume 1 == ~t6_pc~0; 115457#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 115920#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 115064#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 115065#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 116050#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 116040#L731 assume 1 == ~t7_pc~0; 114922#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 114923#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 115121#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 116409#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 116328#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 115026#L750 assume !(1 == ~t8_pc~0); 114719#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 114718#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 115231#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 116419#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 115382#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 115383#L769 assume 1 == ~t9_pc~0; 115986#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 114886#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 114887#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 115109#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 116242#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 116351#L788 assume !(1 == ~t10_pc~0); 115832#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 115833#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 116516#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 116449#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 115022#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 115023#L807 assume 1 == ~t11_pc~0; 116357#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 115847#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 116030#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 116594#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 116834#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 116492#L826 assume !(1 == ~t12_pc~0); 115459#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 115460#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 114762#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 114763#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 115626#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115532#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 115533#L1344-2 assume !(1 == ~T1_E~0); 128139#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 128138#L1354-1 assume !(1 == ~T3_E~0); 128137#L1359-1 assume !(1 == ~T4_E~0); 128136#L1364-1 assume !(1 == ~T5_E~0); 128135#L1369-1 assume !(1 == ~T6_E~0); 128134#L1374-1 assume !(1 == ~T7_E~0); 115882#L1379-1 assume !(1 == ~T8_E~0); 115883#L1384-1 assume !(1 == ~T9_E~0); 115969#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 129821#L1394-1 assume !(1 == ~T11_E~0); 129819#L1399-1 assume !(1 == ~T12_E~0); 129817#L1404-1 assume !(1 == ~E_M~0); 129815#L1409-1 assume !(1 == ~E_1~0); 129813#L1414-1 assume !(1 == ~E_2~0); 129811#L1419-1 assume !(1 == ~E_3~0); 129809#L1424-1 assume !(1 == ~E_4~0); 129807#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 129805#L1434-1 assume !(1 == ~E_6~0); 129803#L1439-1 assume !(1 == ~E_7~0); 127735#L1444-1 assume !(1 == ~E_8~0); 127733#L1449-1 assume !(1 == ~E_9~0); 127732#L1454-1 assume !(1 == ~E_10~0); 127731#L1459-1 assume !(1 == ~E_11~0); 127710#L1464-1 assume !(1 == ~E_12~0); 127699#L1469-1 assume { :end_inline_reset_delta_events } true; 127691#L1815-2 [2024-11-19 15:03:48,294 INFO L747 eck$LassoCheckResult]: Loop: 127691#L1815-2 assume !false; 127685#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 127681#L1181-1 assume !false; 127680#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 127677#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 127666#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 127665#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 127663#L1008 assume !(0 != eval_~tmp~0#1); 127664#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 129277#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 129275#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 129272#L1206-5 assume !(0 == ~T1_E~0); 129270#L1211-3 assume !(0 == ~T2_E~0); 129268#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 129266#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 129264#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 129262#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 129259#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 129257#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 129255#L1246-3 assume !(0 == ~T9_E~0); 129253#L1251-3 assume !(0 == ~T10_E~0); 129251#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 129249#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 129246#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 129244#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 129242#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 129240#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 129238#L1286-3 assume !(0 == ~E_4~0); 129236#L1291-3 assume !(0 == ~E_5~0); 129233#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 129231#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 129229#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 129227#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 129225#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 129223#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 129220#L1326-3 assume !(0 == ~E_12~0); 129218#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 129216#L598-42 assume !(1 == ~m_pc~0); 129214#L598-44 is_master_triggered_~__retres1~0#1 := 0; 129212#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 129208#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 129206#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 129204#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129203#L617-42 assume !(1 == ~t1_pc~0); 129201#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 129198#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129197#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 129196#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 129195#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129194#L636-42 assume 1 == ~t2_pc~0; 129191#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 129189#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 129187#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 129185#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 129183#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 129180#L655-42 assume 1 == ~t3_pc~0; 129177#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 129175#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 129173#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 129171#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 129170#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 129166#L674-42 assume !(1 == ~t4_pc~0); 129163#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 129161#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 129160#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 129157#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 128827#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128824#L693-42 assume 1 == ~t5_pc~0; 128821#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 128819#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 128817#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 128815#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 128813#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 128810#L712-42 assume 1 == ~t6_pc~0; 128807#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 128804#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 128802#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 128800#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 128797#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 128795#L731-42 assume !(1 == ~t7_pc~0); 128793#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 128790#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 128788#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 128786#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 128785#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 128782#L750-42 assume !(1 == ~t8_pc~0); 128779#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 128777#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 128775#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 128773#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 128771#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 128768#L769-42 assume 1 == ~t9_pc~0; 128765#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 128763#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 128761#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 128759#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 128757#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 128754#L788-42 assume !(1 == ~t10_pc~0); 128749#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 128551#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 128548#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 128546#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 128544#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 128542#L807-42 assume 1 == ~t11_pc~0; 128539#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 128537#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 128534#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 128532#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 128530#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 128528#L826-42 assume !(1 == ~t12_pc~0); 128523#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 128520#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 128518#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 128516#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 128514#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128512#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 116143#L1344-5 assume !(1 == ~T1_E~0); 128508#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 128506#L1354-3 assume !(1 == ~T3_E~0); 128504#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 128502#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 128500#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 128497#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 128495#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 128493#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 116469#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 128490#L1394-3 assume !(1 == ~T11_E~0); 128488#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 128485#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 128483#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 128207#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 127985#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 127982#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 127978#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 127976#L1434-3 assume !(1 == ~E_6~0); 127974#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 127972#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 127970#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 127968#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 127966#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 127965#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 127960#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 127907#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 127901#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 127899#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 127897#L1834 assume !(0 == start_simulation_~tmp~3#1); 116198#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 127828#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 127823#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 127821#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 127729#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 127725#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 127707#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 127698#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 127691#L1815-2 [2024-11-19 15:03:48,296 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:48,296 INFO L85 PathProgramCache]: Analyzing trace with hash 1218722231, now seen corresponding path program 1 times [2024-11-19 15:03:48,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:48,296 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933364581] [2024-11-19 15:03:48,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:48,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:48,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:48,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:48,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:48,511 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [933364581] [2024-11-19 15:03:48,511 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [933364581] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:48,511 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:48,511 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:03:48,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [341590611] [2024-11-19 15:03:48,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:48,512 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:48,512 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:48,512 INFO L85 PathProgramCache]: Analyzing trace with hash 1468970980, now seen corresponding path program 1 times [2024-11-19 15:03:48,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:48,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487893619] [2024-11-19 15:03:48,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:48,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:48,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:48,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:48,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:48,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [487893619] [2024-11-19 15:03:48,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [487893619] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:48,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:48,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:48,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1798423354] [2024-11-19 15:03:48,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:48,616 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:48,616 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:48,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:03:48,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:03:48,617 INFO L87 Difference]: Start difference. First operand 22431 states and 32572 transitions. cyclomatic complexity: 10157 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:48,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:48,965 INFO L93 Difference]: Finished difference Result 23040 states and 33181 transitions. [2024-11-19 15:03:48,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23040 states and 33181 transitions. [2024-11-19 15:03:49,154 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22795 [2024-11-19 15:03:49,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23040 states to 23040 states and 33181 transitions. [2024-11-19 15:03:49,229 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23040 [2024-11-19 15:03:49,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23040 [2024-11-19 15:03:49,246 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23040 states and 33181 transitions. [2024-11-19 15:03:49,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:49,263 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23040 states and 33181 transitions. [2024-11-19 15:03:49,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23040 states and 33181 transitions. [2024-11-19 15:03:49,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23040 to 23040. [2024-11-19 15:03:49,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23040 states, 23040 states have (on average 1.4401475694444446) internal successors, (33181), 23039 states have internal predecessors, (33181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:49,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23040 states to 23040 states and 33181 transitions. [2024-11-19 15:03:49,694 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23040 states and 33181 transitions. [2024-11-19 15:03:49,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:03:49,695 INFO L425 stractBuchiCegarLoop]: Abstraction has 23040 states and 33181 transitions. [2024-11-19 15:03:49,695 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-19 15:03:49,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23040 states and 33181 transitions. [2024-11-19 15:03:49,766 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22795 [2024-11-19 15:03:49,767 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:49,767 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:49,769 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:49,769 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:49,770 INFO L745 eck$LassoCheckResult]: Stem: 160412#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 160413#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 161389#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 161390#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 161964#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 161777#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 160698#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 160168#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 160169#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 161499#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 161662#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 162272#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 162273#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 160928#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 160929#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 161533#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 161441#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 161442#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 161621#L1206 assume !(0 == ~M_E~0); 160908#L1206-2 assume !(0 == ~T1_E~0); 160909#L1211-1 assume !(0 == ~T2_E~0); 161954#L1216-1 assume !(0 == ~T3_E~0); 160675#L1221-1 assume !(0 == ~T4_E~0); 160676#L1226-1 assume !(0 == ~T5_E~0); 160349#L1231-1 assume !(0 == ~T6_E~0); 160350#L1236-1 assume !(0 == ~T7_E~0); 162007#L1241-1 assume !(0 == ~T8_E~0); 160746#L1246-1 assume !(0 == ~T9_E~0); 160747#L1251-1 assume !(0 == ~T10_E~0); 160984#L1256-1 assume !(0 == ~T11_E~0); 160178#L1261-1 assume !(0 == ~T12_E~0); 160179#L1266-1 assume !(0 == ~E_M~0); 162242#L1271-1 assume !(0 == ~E_1~0); 161651#L1276-1 assume !(0 == ~E_2~0); 161652#L1281-1 assume !(0 == ~E_3~0); 161564#L1286-1 assume !(0 == ~E_4~0); 160572#L1291-1 assume !(0 == ~E_5~0); 160573#L1296-1 assume !(0 == ~E_6~0); 161341#L1301-1 assume !(0 == ~E_7~0); 161342#L1306-1 assume !(0 == ~E_8~0); 161874#L1311-1 assume !(0 == ~E_9~0); 160533#L1316-1 assume !(0 == ~E_10~0); 160534#L1321-1 assume !(0 == ~E_11~0); 161358#L1326-1 assume !(0 == ~E_12~0); 160400#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 160401#L598 assume !(1 == ~m_pc~0); 161139#L598-2 is_master_triggered_~__retres1~0#1 := 0; 161140#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161227#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 161228#L1497 assume !(0 != activate_threads_~tmp~1#1); 162145#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 162051#L617 assume !(1 == ~t1_pc~0); 160769#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 160770#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 161750#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 161751#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 161459#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 161460#L636 assume 1 == ~t2_pc~0; 160737#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 160738#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160554#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 160555#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 161498#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 161109#L655 assume !(1 == ~t3_pc~0); 161110#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 161991#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 161735#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 161736#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 162244#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 162245#L674 assume 1 == ~t4_pc~0; 160262#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 160263#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 160289#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 160290#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 160556#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 161108#L693 assume !(1 == ~t5_pc~0); 161287#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 160910#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 160911#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 161878#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 160997#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 160932#L712 assume 1 == ~t6_pc~0; 160933#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 161394#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 160543#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 160544#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 161520#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 161510#L731 assume 1 == ~t7_pc~0; 160402#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 160403#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 160600#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 161881#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 161790#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 160506#L750 assume !(1 == ~t8_pc~0); 160199#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 160198#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 160710#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 161892#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 160859#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 160860#L769 assume 1 == ~t9_pc~0; 161455#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 160367#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 160368#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 160588#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 161710#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 161822#L788 assume !(1 == ~t10_pc~0); 161305#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 161306#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 161992#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 161925#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 160502#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 160503#L807 assume 1 == ~t11_pc~0; 161831#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 161322#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 161500#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 162082#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 162337#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 161971#L826 assume !(1 == ~t12_pc~0); 160935#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 160936#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 160243#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 160244#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 161101#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 161005#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 161006#L1344-2 assume !(1 == ~T1_E~0); 162312#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 161349#L1354-1 assume !(1 == ~T3_E~0); 161350#L1359-1 assume !(1 == ~T4_E~0); 161806#L1364-1 assume !(1 == ~T5_E~0); 171419#L1369-1 assume !(1 == ~T6_E~0); 161781#L1374-1 assume !(1 == ~T7_E~0); 161356#L1379-1 assume !(1 == ~T8_E~0); 161357#L1384-1 assume !(1 == ~T9_E~0); 161440#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 162011#L1394-1 assume !(1 == ~T11_E~0); 162012#L1399-1 assume !(1 == ~T12_E~0); 162163#L1404-1 assume !(1 == ~E_M~0); 160749#L1409-1 assume !(1 == ~E_1~0); 160750#L1414-1 assume !(1 == ~E_2~0); 161683#L1419-1 assume !(1 == ~E_3~0); 160380#L1424-1 assume !(1 == ~E_4~0); 160381#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 161365#L1434-1 assume !(1 == ~E_6~0); 162039#L1439-1 assume !(1 == ~E_7~0); 160421#L1444-1 assume !(1 == ~E_8~0); 160422#L1449-1 assume !(1 == ~E_9~0); 160864#L1454-1 assume !(1 == ~E_10~0); 160865#L1459-1 assume !(1 == ~E_11~0); 182696#L1464-1 assume !(1 == ~E_12~0); 161474#L1469-1 assume { :end_inline_reset_delta_events } true; 162464#L1815-2 [2024-11-19 15:03:49,770 INFO L747 eck$LassoCheckResult]: Loop: 162464#L1815-2 assume !false; 162465#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 181209#L1181-1 assume !false; 162453#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 162441#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 162423#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 162413#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 162406#L1008 assume !(0 != eval_~tmp~0#1); 161168#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 160757#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 160758#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 162285#L1206-5 assume !(0 == ~T1_E~0); 161472#L1211-3 assume !(0 == ~T2_E~0); 160488#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 160489#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 161129#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 160559#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 160560#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 160904#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 162100#L1246-3 assume !(0 == ~T9_E~0); 161943#L1251-3 assume !(0 == ~T10_E~0); 161603#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 160512#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 160513#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 160557#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 160558#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 161063#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 161064#L1286-3 assume !(0 == ~E_4~0); 161680#L1291-3 assume !(0 == ~E_5~0); 161681#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 162256#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 162153#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 161199#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 160437#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 160438#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 160514#L1326-3 assume !(0 == ~E_12~0); 161316#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 161691#L598-42 assume !(1 == ~m_pc~0); 161692#L598-44 is_master_triggered_~__retres1~0#1 := 0; 161852#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160937#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 160938#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 162154#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 161373#L617-42 assume !(1 == ~t1_pc~0); 161122#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 183096#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 183095#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 162151#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 160669#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 160670#L636-42 assume !(1 == ~t2_pc~0); 161166#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 161167#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 161253#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 161254#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 161799#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 161633#L655-42 assume 1 == ~t3_pc~0; 161634#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 161143#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 161726#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 161727#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 161990#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161903#L674-42 assume 1 == ~t4_pc~0; 161904#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 161521#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 161522#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 161762#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 161285#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 161286#L693-42 assume !(1 == ~t5_pc~0); 161591#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 161590#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 161345#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 161346#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 161655#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 160874#L712-42 assume !(1 == ~t6_pc~0); 160875#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 161217#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 160504#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 160505#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 160989#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 160990#L731-42 assume !(1 == ~t7_pc~0); 160661#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 160662#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 161368#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 160893#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 160894#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 160567#L750-42 assume 1 == ~t8_pc~0; 160568#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 161185#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 161529#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 160451#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 160452#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 161284#L769-42 assume !(1 == ~t9_pc~0); 161090#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 161089#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 161909#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 162263#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 160671#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 160672#L788-42 assume 1 == ~t10_pc~0; 161294#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 161548#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 161516#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 161517#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 162279#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 162224#L807-42 assume 1 == ~t11_pc~0; 161703#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 160286#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 161189#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 182943#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 182942#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 182941#L826-42 assume 1 == ~t12_pc~0; 182939#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 161783#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 161311#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 160656#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 160657#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 182928#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 161609#L1344-5 assume !(1 == ~T1_E~0); 182927#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 182926#L1354-3 assume !(1 == ~T3_E~0); 182888#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 182887#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 182886#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 182885#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 182884#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 182883#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 180750#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 182882#L1394-3 assume !(1 == ~T11_E~0); 182881#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 182880#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 182879#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 182878#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 182877#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 182876#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 170640#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 182875#L1434-3 assume !(1 == ~E_6~0); 182874#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 182873#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 182872#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 182871#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 182870#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 182869#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 162336#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 182861#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 182855#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 182854#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 162259#L1834 assume !(0 == start_simulation_~tmp~3#1); 162260#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 162484#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 162479#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 162476#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 162473#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 162474#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 182697#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 182695#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 162464#L1815-2 [2024-11-19 15:03:49,771 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:49,771 INFO L85 PathProgramCache]: Analyzing trace with hash -1724859847, now seen corresponding path program 1 times [2024-11-19 15:03:49,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:49,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040304069] [2024-11-19 15:03:49,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:49,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:49,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:49,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:49,828 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:49,828 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040304069] [2024-11-19 15:03:49,828 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040304069] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:49,828 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:49,828 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:03:49,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165916650] [2024-11-19 15:03:49,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:49,829 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:49,830 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:49,830 INFO L85 PathProgramCache]: Analyzing trace with hash -1455350682, now seen corresponding path program 1 times [2024-11-19 15:03:49,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:49,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [923645281] [2024-11-19 15:03:49,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:49,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:49,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:50,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:50,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:50,018 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [923645281] [2024-11-19 15:03:50,018 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [923645281] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:50,018 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:50,018 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:50,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623145178] [2024-11-19 15:03:50,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:50,019 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:50,019 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:50,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:50,020 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:50,020 INFO L87 Difference]: Start difference. First operand 23040 states and 33181 transitions. cyclomatic complexity: 10157 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:50,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:50,215 INFO L93 Difference]: Finished difference Result 44120 states and 63263 transitions. [2024-11-19 15:03:50,215 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44120 states and 63263 transitions. [2024-11-19 15:03:50,541 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43828 [2024-11-19 15:03:50,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44120 states to 44120 states and 63263 transitions. [2024-11-19 15:03:50,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44120 [2024-11-19 15:03:50,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44120 [2024-11-19 15:03:50,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44120 states and 63263 transitions. [2024-11-19 15:03:50,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:50,750 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44120 states and 63263 transitions. [2024-11-19 15:03:50,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44120 states and 63263 transitions. [2024-11-19 15:03:51,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44120 to 44088. [2024-11-19 15:03:51,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44088 states, 44088 states have (on average 1.4341997822536745) internal successors, (63231), 44087 states have internal predecessors, (63231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:51,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44088 states to 44088 states and 63231 transitions. [2024-11-19 15:03:51,372 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44088 states and 63231 transitions. [2024-11-19 15:03:51,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:51,372 INFO L425 stractBuchiCegarLoop]: Abstraction has 44088 states and 63231 transitions. [2024-11-19 15:03:51,373 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-19 15:03:51,373 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44088 states and 63231 transitions. [2024-11-19 15:03:51,525 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43796 [2024-11-19 15:03:51,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:51,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:51,527 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:51,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:51,528 INFO L745 eck$LassoCheckResult]: Stem: 227577#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 227578#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 228549#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 228550#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 229082#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 228914#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 227862#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 227335#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 227336#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 228655#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 228811#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 229364#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 229365#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 228091#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 228092#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 228688#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 228601#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 228602#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 228771#L1206 assume !(0 == ~M_E~0); 228071#L1206-2 assume !(0 == ~T1_E~0); 228072#L1211-1 assume !(0 == ~T2_E~0); 229076#L1216-1 assume !(0 == ~T3_E~0); 227839#L1221-1 assume !(0 == ~T4_E~0); 227840#L1226-1 assume !(0 == ~T5_E~0); 227516#L1231-1 assume !(0 == ~T6_E~0); 227517#L1236-1 assume !(0 == ~T7_E~0); 229128#L1241-1 assume !(0 == ~T8_E~0); 227907#L1246-1 assume !(0 == ~T9_E~0); 227908#L1251-1 assume !(0 == ~T10_E~0); 228145#L1256-1 assume !(0 == ~T11_E~0); 227345#L1261-1 assume !(0 == ~T12_E~0); 227346#L1266-1 assume !(0 == ~E_M~0); 229334#L1271-1 assume !(0 == ~E_1~0); 228800#L1276-1 assume !(0 == ~E_2~0); 228801#L1281-1 assume !(0 == ~E_3~0); 228722#L1286-1 assume !(0 == ~E_4~0); 227737#L1291-1 assume !(0 == ~E_5~0); 227738#L1296-1 assume !(0 == ~E_6~0); 228500#L1301-1 assume !(0 == ~E_7~0); 228501#L1306-1 assume !(0 == ~E_8~0); 228997#L1311-1 assume !(0 == ~E_9~0); 227698#L1316-1 assume !(0 == ~E_10~0); 227699#L1321-1 assume !(0 == ~E_11~0); 228515#L1326-1 assume !(0 == ~E_12~0); 227565#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227566#L598 assume !(1 == ~m_pc~0); 228292#L598-2 is_master_triggered_~__retres1~0#1 := 0; 228293#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 228384#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 228385#L1497 assume !(0 != activate_threads_~tmp~1#1); 229259#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 229172#L617 assume !(1 == ~t1_pc~0); 227929#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 227930#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 229428#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 229279#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 228618#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 228619#L636 assume !(1 == ~t2_pc~0); 229202#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 228361#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 227719#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 227720#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 228654#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 228268#L655 assume !(1 == ~t3_pc~0); 228269#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 229109#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 228876#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 228877#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 229335#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 229336#L674 assume 1 == ~t4_pc~0; 227428#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 227429#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 227455#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 227456#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 227723#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 228266#L693 assume !(1 == ~t5_pc~0); 228447#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 228075#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 228076#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 229000#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 228161#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 228093#L712 assume 1 == ~t6_pc~0; 228094#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 228553#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 227708#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 227709#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 228675#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 228667#L731 assume 1 == ~t7_pc~0; 227567#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 227568#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 227765#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 229003#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 228930#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 227671#L750 assume !(1 == ~t8_pc~0); 227366#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 227365#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 227873#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 229015#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 228021#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 228022#L769 assume 1 == ~t9_pc~0; 228616#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 227532#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 227533#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 227753#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 228851#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 228954#L788 assume !(1 == ~t10_pc~0); 228463#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 228464#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 229110#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 229050#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 227667#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 227668#L807 assume 1 == ~t11_pc~0; 228962#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 228482#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 228656#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 229207#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 229424#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 229087#L826 assume !(1 == ~t12_pc~0); 228096#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 228097#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 227409#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 227410#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 228260#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 228167#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 228168#L1344-2 assume !(1 == ~T1_E~0); 228309#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 228508#L1354-1 assume !(1 == ~T3_E~0); 228509#L1359-1 assume !(1 == ~T4_E~0); 229350#L1364-1 assume !(1 == ~T5_E~0); 229351#L1369-1 assume !(1 == ~T6_E~0); 228918#L1374-1 assume !(1 == ~T7_E~0); 228919#L1379-1 assume !(1 == ~T8_E~0); 228597#L1384-1 assume !(1 == ~T9_E~0); 228598#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 246774#L1394-1 assume !(1 == ~T11_E~0); 246773#L1399-1 assume !(1 == ~T12_E~0); 246772#L1404-1 assume !(1 == ~E_M~0); 246771#L1409-1 assume !(1 == ~E_1~0); 229257#L1414-1 assume !(1 == ~E_2~0); 228829#L1419-1 assume !(1 == ~E_3~0); 227545#L1424-1 assume !(1 == ~E_4~0); 227546#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 228524#L1434-1 assume !(1 == ~E_6~0); 248181#L1439-1 assume !(1 == ~E_7~0); 227586#L1444-1 assume !(1 == ~E_8~0); 227587#L1449-1 assume !(1 == ~E_9~0); 228028#L1454-1 assume !(1 == ~E_10~0); 228029#L1459-1 assume !(1 == ~E_11~0); 248138#L1464-1 assume !(1 == ~E_12~0); 228633#L1469-1 assume { :end_inline_reset_delta_events } true; 248134#L1815-2 [2024-11-19 15:03:51,529 INFO L747 eck$LassoCheckResult]: Loop: 248134#L1815-2 assume !false; 248132#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 248127#L1181-1 assume !false; 248124#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 248113#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 248101#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 248100#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 246976#L1008 assume !(0 != eval_~tmp~0#1); 246977#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 251021#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 251020#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 251019#L1206-5 assume !(0 == ~T1_E~0); 251018#L1211-3 assume !(0 == ~T2_E~0); 251017#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 251016#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 251015#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 251014#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 251013#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 251012#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 251011#L1246-3 assume !(0 == ~T9_E~0); 251010#L1251-3 assume !(0 == ~T10_E~0); 251009#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 251008#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 251007#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 251006#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 251005#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 251004#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 251003#L1286-3 assume !(0 == ~E_4~0); 251002#L1291-3 assume !(0 == ~E_5~0); 251001#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 251000#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 250999#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 250998#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 250997#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 250996#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 250995#L1326-3 assume !(0 == ~E_12~0); 250994#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 250993#L598-42 assume !(1 == ~m_pc~0); 250992#L598-44 is_master_triggered_~__retres1~0#1 := 0; 250991#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 250990#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 250989#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 250988#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 250987#L617-42 assume !(1 == ~t1_pc~0); 250986#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 250984#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 250982#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 250980#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 250978#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 250977#L636-42 assume !(1 == ~t2_pc~0); 250976#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 250975#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 250974#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 250973#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 250972#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 250971#L655-42 assume !(1 == ~t3_pc~0); 250970#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 250968#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 250967#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 250966#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 250965#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 250964#L674-42 assume 1 == ~t4_pc~0; 250963#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 250961#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 250960#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 250959#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 250958#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 250957#L693-42 assume 1 == ~t5_pc~0; 250955#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 250954#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 250953#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 250952#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 250951#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 250950#L712-42 assume 1 == ~t6_pc~0; 250949#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 250947#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 250946#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 250945#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 250944#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 250943#L731-42 assume !(1 == ~t7_pc~0); 250942#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 250940#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 232214#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 232211#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 232209#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 232207#L750-42 assume 1 == ~t8_pc~0; 232205#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 232202#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 232200#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 232197#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 232195#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 232191#L769-42 assume 1 == ~t9_pc~0; 232193#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 250647#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 250645#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 250643#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 250640#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 250638#L788-42 assume !(1 == ~t10_pc~0); 232173#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 232170#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 232169#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 232168#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 232167#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 232164#L807-42 assume 1 == ~t11_pc~0; 232166#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 232157#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 232158#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 232151#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 232152#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 232143#L826-42 assume !(1 == ~t12_pc~0); 232145#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 250412#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 250411#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 250410#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 250409#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 250408#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 232129#L1344-5 assume !(1 == ~T1_E~0); 250407#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 250406#L1354-3 assume !(1 == ~T3_E~0); 250405#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 250404#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 250403#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 250402#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 250401#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 250400#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 242607#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 250399#L1394-3 assume !(1 == ~T11_E~0); 250398#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 250397#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 250396#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 250395#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 250394#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 250393#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 247980#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 250392#L1434-3 assume !(1 == ~E_6~0); 250377#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 250373#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 250369#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 250367#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 250365#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 250364#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 229531#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 250244#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 250236#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 250234#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 250232#L1834 assume !(0 == start_simulation_~tmp~3#1); 250229#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 249738#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 249733#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 249731#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 249729#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 248250#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 248241#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 248136#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 248134#L1815-2 [2024-11-19 15:03:51,529 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:51,529 INFO L85 PathProgramCache]: Analyzing trace with hash -607674886, now seen corresponding path program 1 times [2024-11-19 15:03:51,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:51,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573801928] [2024-11-19 15:03:51,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:51,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:51,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:51,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:51,583 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:51,583 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573801928] [2024-11-19 15:03:51,583 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573801928] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:51,583 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:51,584 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:03:51,584 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1931338141] [2024-11-19 15:03:51,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:51,584 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:51,585 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:51,585 INFO L85 PathProgramCache]: Analyzing trace with hash -455842778, now seen corresponding path program 1 times [2024-11-19 15:03:51,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:51,585 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278294818] [2024-11-19 15:03:51,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:51,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:51,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:51,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:51,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:51,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [278294818] [2024-11-19 15:03:51,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [278294818] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:51,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:51,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:51,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594992544] [2024-11-19 15:03:51,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:51,634 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:51,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:51,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:51,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:51,634 INFO L87 Difference]: Start difference. First operand 44088 states and 63231 transitions. cyclomatic complexity: 19175 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:52,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:52,164 INFO L93 Difference]: Finished difference Result 84519 states and 120736 transitions. [2024-11-19 15:03:52,164 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84519 states and 120736 transitions. [2024-11-19 15:03:52,535 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 84100 [2024-11-19 15:03:53,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84519 states to 84519 states and 120736 transitions. [2024-11-19 15:03:53,078 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 84519 [2024-11-19 15:03:53,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 84519 [2024-11-19 15:03:53,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84519 states and 120736 transitions. [2024-11-19 15:03:53,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:53,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84519 states and 120736 transitions. [2024-11-19 15:03:53,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84519 states and 120736 transitions. [2024-11-19 15:03:54,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84519 to 84455. [2024-11-19 15:03:54,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84455 states, 84455 states have (on average 1.4288319223254988) internal successors, (120672), 84454 states have internal predecessors, (120672), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:54,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84455 states to 84455 states and 120672 transitions. [2024-11-19 15:03:54,262 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84455 states and 120672 transitions. [2024-11-19 15:03:54,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:03:54,262 INFO L425 stractBuchiCegarLoop]: Abstraction has 84455 states and 120672 transitions. [2024-11-19 15:03:54,263 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-19 15:03:54,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84455 states and 120672 transitions. [2024-11-19 15:03:54,918 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 84036 [2024-11-19 15:03:54,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:03:54,919 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:03:54,925 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:54,925 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:03:54,926 INFO L745 eck$LassoCheckResult]: Stem: 356188#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 356189#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 357144#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 357145#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 357661#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 357501#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 356476#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 355949#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 355950#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 357247#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 357398#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 357890#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 357891#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 356697#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 356698#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 357280#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 357194#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 357195#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 357355#L1206 assume !(0 == ~M_E~0); 356678#L1206-2 assume !(0 == ~T1_E~0); 356679#L1211-1 assume !(0 == ~T2_E~0); 357652#L1216-1 assume !(0 == ~T3_E~0); 356453#L1221-1 assume !(0 == ~T4_E~0); 356454#L1226-1 assume !(0 == ~T5_E~0); 356124#L1231-1 assume !(0 == ~T6_E~0); 356125#L1236-1 assume !(0 == ~T7_E~0); 357702#L1241-1 assume !(0 == ~T8_E~0); 356521#L1246-1 assume !(0 == ~T9_E~0); 356522#L1251-1 assume !(0 == ~T10_E~0); 356755#L1256-1 assume !(0 == ~T11_E~0); 355959#L1261-1 assume !(0 == ~T12_E~0); 355960#L1266-1 assume !(0 == ~E_M~0); 357868#L1271-1 assume !(0 == ~E_1~0); 357385#L1276-1 assume !(0 == ~E_2~0); 357386#L1281-1 assume !(0 == ~E_3~0); 357309#L1286-1 assume !(0 == ~E_4~0); 356350#L1291-1 assume !(0 == ~E_5~0); 356351#L1296-1 assume !(0 == ~E_6~0); 357097#L1301-1 assume !(0 == ~E_7~0); 357098#L1306-1 assume !(0 == ~E_8~0); 357578#L1311-1 assume !(0 == ~E_9~0); 356310#L1316-1 assume !(0 == ~E_10~0); 356311#L1321-1 assume !(0 == ~E_11~0); 357113#L1326-1 assume !(0 == ~E_12~0); 356176#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 356177#L598 assume !(1 == ~m_pc~0); 356898#L598-2 is_master_triggered_~__retres1~0#1 := 0; 356899#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 356989#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 356990#L1497 assume !(0 != activate_threads_~tmp~1#1); 357813#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 357735#L617 assume !(1 == ~t1_pc~0); 356543#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 356544#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 357936#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 357828#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 357211#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 357212#L636 assume !(1 == ~t2_pc~0); 357757#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 356967#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 356332#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 356333#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 357246#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 356876#L655 assume !(1 == ~t3_pc~0); 356877#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 357687#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 357462#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 357463#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 357870#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 357871#L674 assume !(1 == ~t4_pc~0); 357666#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 357667#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 356065#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 356066#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 356334#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 356875#L693 assume !(1 == ~t5_pc~0); 357047#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 356680#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 356681#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 357580#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 356768#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 356701#L712 assume 1 == ~t6_pc~0; 356702#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 357149#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 356320#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 356321#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 357267#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 357259#L731 assume 1 == ~t7_pc~0; 356178#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 356179#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 356378#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 357585#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 357513#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 356283#L750 assume !(1 == ~t8_pc~0); 355980#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 355979#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 356487#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 357595#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 356631#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 356632#L769 assume 1 == ~t9_pc~0; 357207#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 356142#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 356143#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 356366#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 357437#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 357536#L788 assume !(1 == ~t10_pc~0); 357063#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 357064#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 357688#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 357623#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 356279#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 356280#L807 assume 1 == ~t11_pc~0; 357542#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 357079#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 357248#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 357762#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 357935#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 357665#L826 assume !(1 == ~t12_pc~0); 356704#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 356705#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 356022#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 356023#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 356869#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 356776#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 356777#L1344-2 assume !(1 == ~T1_E~0); 356915#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 357103#L1354-1 assume !(1 == ~T3_E~0); 357104#L1359-1 assume !(1 == ~T4_E~0); 357525#L1364-1 assume !(1 == ~T5_E~0); 356397#L1369-1 assume !(1 == ~T6_E~0); 356398#L1374-1 assume !(1 == ~T7_E~0); 357111#L1379-1 assume !(1 == ~T8_E~0); 357112#L1384-1 assume !(1 == ~T9_E~0); 357192#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 362506#L1394-1 assume !(1 == ~T11_E~0); 357909#L1399-1 assume !(1 == ~T12_E~0); 357824#L1404-1 assume !(1 == ~E_M~0); 356524#L1409-1 assume !(1 == ~E_1~0); 356525#L1414-1 assume !(1 == ~E_2~0); 361866#L1419-1 assume !(1 == ~E_3~0); 361864#L1424-1 assume !(1 == ~E_4~0); 361862#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 360763#L1434-1 assume !(1 == ~E_6~0); 360761#L1439-1 assume !(1 == ~E_7~0); 360759#L1444-1 assume !(1 == ~E_8~0); 360757#L1449-1 assume !(1 == ~E_9~0); 360755#L1454-1 assume !(1 == ~E_10~0); 360275#L1459-1 assume !(1 == ~E_11~0); 360122#L1464-1 assume !(1 == ~E_12~0); 360099#L1469-1 assume { :end_inline_reset_delta_events } true; 360088#L1815-2 [2024-11-19 15:03:54,926 INFO L747 eck$LassoCheckResult]: Loop: 360088#L1815-2 assume !false; 360020#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 360001#L1181-1 assume !false; 359998#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 359982#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 359967#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 359962#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 359955#L1008 assume !(0 != eval_~tmp~0#1); 359956#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 365976#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 365974#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 365971#L1206-5 assume !(0 == ~T1_E~0); 365969#L1211-3 assume !(0 == ~T2_E~0); 365967#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 365965#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 365963#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 365959#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 365957#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 365955#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 365953#L1246-3 assume !(0 == ~T9_E~0); 365950#L1251-3 assume !(0 == ~T10_E~0); 365948#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 365946#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 365944#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 365942#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 365940#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 365938#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 365936#L1286-3 assume !(0 == ~E_4~0); 365934#L1291-3 assume !(0 == ~E_5~0); 365931#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 365929#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 365927#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 365925#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 365923#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 365921#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 365919#L1326-3 assume !(0 == ~E_12~0); 365917#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 365915#L598-42 assume !(1 == ~m_pc~0); 365913#L598-44 is_master_triggered_~__retres1~0#1 := 0; 365911#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 365909#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 365906#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 365904#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 365902#L617-42 assume 1 == ~t1_pc~0; 365900#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 365901#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365989#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 365890#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 365888#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 365886#L636-42 assume !(1 == ~t2_pc~0); 365884#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 365882#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 365880#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 365877#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 365875#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 365873#L655-42 assume !(1 == ~t3_pc~0); 365871#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 365868#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 365866#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 365863#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 365861#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 365859#L674-42 assume !(1 == ~t4_pc~0); 365857#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 365855#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 365853#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 365850#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 365848#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 365846#L693-42 assume !(1 == ~t5_pc~0); 365844#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 365841#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 365839#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 365836#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 365835#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 365834#L712-42 assume 1 == ~t6_pc~0; 365833#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 365831#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 365830#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 365829#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 365828#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 365827#L731-42 assume 1 == ~t7_pc~0; 365825#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 365824#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 365823#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 365822#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 365821#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 365820#L750-42 assume 1 == ~t8_pc~0; 365819#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 365817#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 365816#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 365815#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 365814#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 365800#L769-42 assume 1 == ~t9_pc~0; 365797#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 365795#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 365793#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 365791#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 365790#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 358402#L788-42 assume !(1 == ~t10_pc~0); 358396#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 358390#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 358384#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 358379#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 358373#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 358374#L807-42 assume !(1 == ~t11_pc~0); 364551#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 364548#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 364546#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 364544#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 364542#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 364540#L826-42 assume 1 == ~t12_pc~0; 364535#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 364533#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 364531#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 364529#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 364527#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 364525#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 358291#L1344-5 assume !(1 == ~T1_E~0); 364522#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 364520#L1354-3 assume !(1 == ~T3_E~0); 364518#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 364516#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 364514#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 364512#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 364510#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 364509#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 364506#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 364504#L1394-3 assume !(1 == ~T11_E~0); 364502#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 364500#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 364498#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 364496#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 364494#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 364493#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 362819#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 364490#L1434-3 assume !(1 == ~E_6~0); 364488#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 364486#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 364484#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 364482#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 364481#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 364480#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 364477#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 361853#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 360762#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 360280#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 360278#L1834 assume !(0 == start_simulation_~tmp~3#1); 360276#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 360130#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 360125#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 360123#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 360119#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 360115#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 360111#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 360098#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 360088#L1815-2 [2024-11-19 15:03:54,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:54,927 INFO L85 PathProgramCache]: Analyzing trace with hash 852319035, now seen corresponding path program 1 times [2024-11-19 15:03:54,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:54,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761771202] [2024-11-19 15:03:54,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:54,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:54,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:55,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:55,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:55,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761771202] [2024-11-19 15:03:55,029 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [761771202] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:55,029 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:55,030 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:03:55,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717629217] [2024-11-19 15:03:55,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:55,030 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:03:55,031 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:03:55,031 INFO L85 PathProgramCache]: Analyzing trace with hash -775579996, now seen corresponding path program 1 times [2024-11-19 15:03:55,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:03:55,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079449705] [2024-11-19 15:03:55,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:03:55,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:03:55,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:03:55,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:03:55,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:03:55,088 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079449705] [2024-11-19 15:03:55,088 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079449705] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:03:55,088 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:03:55,088 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:03:55,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1731149747] [2024-11-19 15:03:55,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:03:55,089 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:03:55,089 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:03:55,090 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:03:55,090 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:03:55,090 INFO L87 Difference]: Start difference. First operand 84455 states and 120672 transitions. cyclomatic complexity: 36281 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:03:55,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:03:55,738 INFO L93 Difference]: Finished difference Result 161890 states and 230457 transitions. [2024-11-19 15:03:55,738 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 161890 states and 230457 transitions. [2024-11-19 15:03:57,361 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 161152 [2024-11-19 15:03:58,130 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 161890 states to 161890 states and 230457 transitions. [2024-11-19 15:03:58,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161890 [2024-11-19 15:03:58,224 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161890 [2024-11-19 15:03:58,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 161890 states and 230457 transitions. [2024-11-19 15:03:58,304 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:03:58,305 INFO L218 hiAutomatonCegarLoop]: Abstraction has 161890 states and 230457 transitions. [2024-11-19 15:03:58,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161890 states and 230457 transitions. [2024-11-19 15:04:00,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161890 to 161762. [2024-11-19 15:04:00,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 161762 states, 161762 states have (on average 1.4238758175591302) internal successors, (230329), 161761 states have internal predecessors, (230329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:01,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161762 states to 161762 states and 230329 transitions. [2024-11-19 15:04:01,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 161762 states and 230329 transitions. [2024-11-19 15:04:01,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:01,179 INFO L425 stractBuchiCegarLoop]: Abstraction has 161762 states and 230329 transitions. [2024-11-19 15:04:01,182 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-19 15:04:01,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 161762 states and 230329 transitions. [2024-11-19 15:04:01,633 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 161024 [2024-11-19 15:04:01,634 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:01,634 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:01,636 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:01,636 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:01,637 INFO L745 eck$LassoCheckResult]: Stem: 602540#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 602541#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 603499#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 603500#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 604051#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 603878#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 602825#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 602301#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 602302#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 603607#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 603763#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 604277#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 604278#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 603048#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 603049#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 603640#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 603548#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 603549#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 603722#L1206 assume !(0 == ~M_E~0); 603028#L1206-2 assume !(0 == ~T1_E~0); 603029#L1211-1 assume !(0 == ~T2_E~0); 604044#L1216-1 assume !(0 == ~T3_E~0); 602802#L1221-1 assume !(0 == ~T4_E~0); 602803#L1226-1 assume !(0 == ~T5_E~0); 602479#L1231-1 assume !(0 == ~T6_E~0); 602480#L1236-1 assume !(0 == ~T7_E~0); 604095#L1241-1 assume !(0 == ~T8_E~0); 602871#L1246-1 assume !(0 == ~T9_E~0); 602872#L1251-1 assume !(0 == ~T10_E~0); 603103#L1256-1 assume !(0 == ~T11_E~0); 602311#L1261-1 assume !(0 == ~T12_E~0); 602312#L1266-1 assume !(0 == ~E_M~0); 604258#L1271-1 assume !(0 == ~E_1~0); 603751#L1276-1 assume !(0 == ~E_2~0); 603752#L1281-1 assume !(0 == ~E_3~0); 603675#L1286-1 assume !(0 == ~E_4~0); 602701#L1291-1 assume !(0 == ~E_5~0); 602702#L1296-1 assume !(0 == ~E_6~0); 603449#L1301-1 assume !(0 == ~E_7~0); 603450#L1306-1 assume !(0 == ~E_8~0); 603966#L1311-1 assume !(0 == ~E_9~0); 602661#L1316-1 assume !(0 == ~E_10~0); 602662#L1321-1 assume !(0 == ~E_11~0); 603464#L1326-1 assume !(0 == ~E_12~0); 602528#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 602529#L598 assume !(1 == ~m_pc~0); 603251#L598-2 is_master_triggered_~__retres1~0#1 := 0; 603252#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 603338#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 603339#L1497 assume !(0 != activate_threads_~tmp~1#1); 604195#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 604123#L617 assume !(1 == ~t1_pc~0); 602893#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 602894#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 604324#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 604214#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 603566#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 603567#L636 assume !(1 == ~t2_pc~0); 604150#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 603316#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 602683#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 602684#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 603606#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 603226#L655 assume !(1 == ~t3_pc~0); 603227#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 604080#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 603832#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 603833#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 604259#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 604260#L674 assume !(1 == ~t4_pc~0); 604056#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 604057#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 602418#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 602419#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 602687#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 603224#L693 assume !(1 == ~t5_pc~0); 603396#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 603032#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 603033#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 603968#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 603118#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 603050#L712 assume !(1 == ~t6_pc~0); 603051#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 603503#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 602671#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 602672#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 603627#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 603617#L731 assume 1 == ~t7_pc~0; 602530#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 602531#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 602728#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 603971#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 603890#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 602634#L750 assume !(1 == ~t8_pc~0); 602332#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 602331#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 602837#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 603984#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 602982#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 602983#L769 assume 1 == ~t9_pc~0; 603564#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 602495#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 602496#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 602716#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 603807#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 603914#L788 assume !(1 == ~t10_pc~0); 603414#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 603415#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 604082#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 604010#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 602630#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 602631#L807 assume 1 == ~t11_pc~0; 603921#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 603431#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 603608#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 604152#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 604323#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 604055#L826 assume !(1 == ~t12_pc~0); 603052#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 603053#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 602375#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 602376#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 603218#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 603124#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 603125#L1344-2 assume !(1 == ~T1_E~0); 603268#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 603456#L1354-1 assume !(1 == ~T3_E~0); 603457#L1359-1 assume !(1 == ~T4_E~0); 603901#L1364-1 assume !(1 == ~T5_E~0); 602747#L1369-1 assume !(1 == ~T6_E~0); 602748#L1374-1 assume !(1 == ~T7_E~0); 603462#L1379-1 assume !(1 == ~T8_E~0); 603463#L1384-1 assume !(1 == ~T9_E~0); 603547#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 642323#L1394-1 assume !(1 == ~T11_E~0); 642318#L1399-1 assume !(1 == ~T12_E~0); 642312#L1404-1 assume !(1 == ~E_M~0); 640742#L1409-1 assume !(1 == ~E_1~0); 604193#L1414-1 assume !(1 == ~E_2~0); 603781#L1419-1 assume !(1 == ~E_3~0); 602508#L1424-1 assume !(1 == ~E_4~0); 602509#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 658732#L1434-1 assume !(1 == ~E_6~0); 658730#L1439-1 assume !(1 == ~E_7~0); 658728#L1444-1 assume !(1 == ~E_8~0); 658726#L1449-1 assume !(1 == ~E_9~0); 658724#L1454-1 assume !(1 == ~E_10~0); 658722#L1459-1 assume !(1 == ~E_11~0); 658719#L1464-1 assume !(1 == ~E_12~0); 603581#L1469-1 assume { :end_inline_reset_delta_events } true; 658715#L1815-2 [2024-11-19 15:04:01,637 INFO L747 eck$LassoCheckResult]: Loop: 658715#L1815-2 assume !false; 658713#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 658708#L1181-1 assume !false; 658706#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 658698#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 658686#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 658684#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 658680#L1008 assume !(0 != eval_~tmp~0#1); 658681#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 659096#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 659094#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 659092#L1206-5 assume !(0 == ~T1_E~0); 659090#L1211-3 assume !(0 == ~T2_E~0); 659088#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 659086#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 659084#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 659082#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 659080#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 659078#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 659076#L1246-3 assume !(0 == ~T9_E~0); 659074#L1251-3 assume !(0 == ~T10_E~0); 659072#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 659070#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 659068#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 659066#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 659064#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 659062#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 659060#L1286-3 assume !(0 == ~E_4~0); 659058#L1291-3 assume !(0 == ~E_5~0); 659056#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 659054#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 659052#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 659050#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 659048#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 659046#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 659044#L1326-3 assume !(0 == ~E_12~0); 659042#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 659040#L598-42 assume !(1 == ~m_pc~0); 659038#L598-44 is_master_triggered_~__retres1~0#1 := 0; 659036#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 659034#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 659032#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 659030#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 659026#L617-42 assume !(1 == ~t1_pc~0); 659022#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 659020#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 659018#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 659015#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 659012#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 659010#L636-42 assume !(1 == ~t2_pc~0); 659008#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 659006#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 659004#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 659002#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 659000#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 658998#L655-42 assume 1 == ~t3_pc~0; 658994#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 658992#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 658990#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 658988#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 658986#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 658984#L674-42 assume !(1 == ~t4_pc~0); 658982#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 658980#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 658978#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 658976#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 658974#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 658972#L693-42 assume 1 == ~t5_pc~0; 658968#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 658966#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 658964#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 658962#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 658960#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 658958#L712-42 assume !(1 == ~t6_pc~0); 658956#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 658954#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 658952#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 658950#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 658948#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 658946#L731-42 assume 1 == ~t7_pc~0; 658942#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 658940#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 658938#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 658936#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 658934#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 658932#L750-42 assume !(1 == ~t8_pc~0); 658928#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 658926#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 658924#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 658922#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 658920#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 658918#L769-42 assume 1 == ~t9_pc~0; 658914#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 658912#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 658910#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 658908#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 658906#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 658904#L788-42 assume 1 == ~t10_pc~0; 658900#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 658898#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 658896#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 658894#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 658892#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 658890#L807-42 assume 1 == ~t11_pc~0; 658886#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 658884#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 658882#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 658880#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 658878#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 658876#L826-42 assume 1 == ~t12_pc~0; 658872#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 658870#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 658868#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 658866#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 658864#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 658863#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 635438#L1344-5 assume !(1 == ~T1_E~0); 658859#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 658857#L1354-3 assume !(1 == ~T3_E~0); 658855#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 658853#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 658851#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 658849#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 658847#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 658845#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 635418#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 658843#L1394-3 assume !(1 == ~T11_E~0); 658841#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 658839#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 658837#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 658835#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 658833#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 658831#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 648710#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 658829#L1434-3 assume !(1 == ~E_6~0); 658827#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 658825#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 658823#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 658821#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 658819#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 658818#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 658816#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 658808#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 658802#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 658800#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 658797#L1834 assume !(0 == start_simulation_~tmp~3#1); 658794#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 658763#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 658757#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 658755#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 658753#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 658751#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 658749#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 658717#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 658715#L1815-2 [2024-11-19 15:04:01,638 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:01,638 INFO L85 PathProgramCache]: Analyzing trace with hash 1989947900, now seen corresponding path program 1 times [2024-11-19 15:04:01,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:01,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722609324] [2024-11-19 15:04:01,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:01,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:01,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:01,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:01,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:01,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [722609324] [2024-11-19 15:04:01,707 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [722609324] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:01,707 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:01,708 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:01,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288054715] [2024-11-19 15:04:01,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:01,708 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:01,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:01,709 INFO L85 PathProgramCache]: Analyzing trace with hash 1566675173, now seen corresponding path program 1 times [2024-11-19 15:04:01,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:01,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58243377] [2024-11-19 15:04:01,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:01,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:01,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:01,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:01,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:01,751 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58243377] [2024-11-19 15:04:01,751 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58243377] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:01,751 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:01,751 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:01,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1663355378] [2024-11-19 15:04:01,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:01,752 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:01,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:01,752 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:04:01,752 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:04:01,753 INFO L87 Difference]: Start difference. First operand 161762 states and 230329 transitions. cyclomatic complexity: 68695 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:04,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:04,071 INFO L93 Difference]: Finished difference Result 455856 states and 644227 transitions. [2024-11-19 15:04:04,075 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 455856 states and 644227 transitions. [2024-11-19 15:04:07,141 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 453072 [2024-11-19 15:04:08,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 455856 states to 455856 states and 644227 transitions. [2024-11-19 15:04:08,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 455856 [2024-11-19 15:04:08,600 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 455856 [2024-11-19 15:04:08,601 INFO L73 IsDeterministic]: Start isDeterministic. Operand 455856 states and 644227 transitions. [2024-11-19 15:04:09,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:09,196 INFO L218 hiAutomatonCegarLoop]: Abstraction has 455856 states and 644227 transitions. [2024-11-19 15:04:09,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 455856 states and 644227 transitions. [2024-11-19 15:04:13,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 455856 to 449584. [2024-11-19 15:04:14,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449584 states, 449584 states have (on average 1.4141495248941243) internal successors, (635779), 449583 states have internal predecessors, (635779), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:15,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449584 states to 449584 states and 635779 transitions. [2024-11-19 15:04:15,445 INFO L240 hiAutomatonCegarLoop]: Abstraction has 449584 states and 635779 transitions. [2024-11-19 15:04:15,445 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:04:15,445 INFO L425 stractBuchiCegarLoop]: Abstraction has 449584 states and 635779 transitions. [2024-11-19 15:04:15,445 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-19 15:04:15,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449584 states and 635779 transitions. [2024-11-19 15:04:17,515 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 447568 [2024-11-19 15:04:17,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:17,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:17,522 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:17,522 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:17,522 INFO L745 eck$LassoCheckResult]: Stem: 1220168#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1220169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1221151#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1221152#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1221723#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 1221543#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1220458#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1219929#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1219930#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1221269#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1221432#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1222005#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1222006#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1220692#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1220693#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1221306#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1221206#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1221207#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1221390#L1206 assume !(0 == ~M_E~0); 1220670#L1206-2 assume !(0 == ~T1_E~0); 1220671#L1211-1 assume !(0 == ~T2_E~0); 1221716#L1216-1 assume !(0 == ~T3_E~0); 1220435#L1221-1 assume !(0 == ~T4_E~0); 1220436#L1226-1 assume !(0 == ~T5_E~0); 1220110#L1231-1 assume !(0 == ~T6_E~0); 1220111#L1236-1 assume !(0 == ~T7_E~0); 1221766#L1241-1 assume !(0 == ~T8_E~0); 1220507#L1246-1 assume !(0 == ~T9_E~0); 1220508#L1251-1 assume !(0 == ~T10_E~0); 1220750#L1256-1 assume !(0 == ~T11_E~0); 1219939#L1261-1 assume !(0 == ~T12_E~0); 1219940#L1266-1 assume !(0 == ~E_M~0); 1221983#L1271-1 assume !(0 == ~E_1~0); 1221420#L1276-1 assume !(0 == ~E_2~0); 1221421#L1281-1 assume !(0 == ~E_3~0); 1221340#L1286-1 assume !(0 == ~E_4~0); 1220331#L1291-1 assume !(0 == ~E_5~0); 1220332#L1296-1 assume !(0 == ~E_6~0); 1221102#L1301-1 assume !(0 == ~E_7~0); 1221103#L1306-1 assume !(0 == ~E_8~0); 1221640#L1311-1 assume !(0 == ~E_9~0); 1220289#L1316-1 assume !(0 == ~E_10~0); 1220290#L1321-1 assume !(0 == ~E_11~0); 1221123#L1326-1 assume !(0 == ~E_12~0); 1220160#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1220161#L598 assume !(1 == ~m_pc~0); 1220898#L598-2 is_master_triggered_~__retres1~0#1 := 0; 1220899#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1220991#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1220992#L1497 assume !(0 != activate_threads_~tmp~1#1); 1221904#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1221807#L617 assume !(1 == ~t1_pc~0); 1220529#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1220530#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1222082#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1221929#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 1221224#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1221225#L636 assume !(1 == ~t2_pc~0); 1221841#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1220970#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1220313#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1220314#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 1221266#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1220875#L655 assume !(1 == ~t3_pc~0); 1220876#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1221913#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1221503#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1221504#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 1221984#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1221985#L674 assume !(1 == ~t4_pc~0); 1221730#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1221731#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1220047#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1220048#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 1220317#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1220873#L693 assume !(1 == ~t5_pc~0); 1221050#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1220675#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1220676#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1221643#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 1220766#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1220694#L712 assume !(1 == ~t6_pc~0); 1220695#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1221156#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1220301#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1220302#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 1221291#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1221280#L731 assume !(1 == ~t7_pc~0); 1221281#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1220359#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1220360#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1221646#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 1221561#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1220262#L750 assume !(1 == ~t8_pc~0); 1219960#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1219959#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1220470#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1221656#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1220621#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1220622#L769 assume 1 == ~t9_pc~0; 1221222#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1220126#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1220127#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1220347#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 1221477#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1221588#L788 assume !(1 == ~t10_pc~0); 1221066#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1221067#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1221753#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1221688#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 1220258#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1220259#L807 assume 1 == ~t11_pc~0; 1221594#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1221082#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1221270#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1221845#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 1222076#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1221729#L826 assume !(1 == ~t12_pc~0); 1220696#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1220697#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1220004#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1220005#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 1220867#L1593-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1220772#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 1220773#L1344-2 assume !(1 == ~T1_E~0); 1220915#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1221115#L1354-1 assume !(1 == ~T3_E~0); 1221116#L1359-1 assume !(1 == ~T4_E~0); 1221574#L1364-1 assume !(1 == ~T5_E~0); 1220379#L1369-1 assume !(1 == ~T6_E~0); 1220380#L1374-1 assume !(1 == ~T7_E~0); 1221121#L1379-1 assume !(1 == ~T8_E~0); 1221122#L1384-1 assume !(1 == ~T9_E~0); 1221205#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1221770#L1394-1 assume !(1 == ~T11_E~0); 1221771#L1399-1 assume !(1 == ~T12_E~0); 1221926#L1404-1 assume !(1 == ~E_M~0); 1220510#L1409-1 assume !(1 == ~E_1~0); 1220511#L1414-1 assume !(1 == ~E_2~0); 1221453#L1419-1 assume !(1 == ~E_3~0); 1220140#L1424-1 assume !(1 == ~E_4~0); 1220141#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1221131#L1434-1 assume !(1 == ~E_6~0); 1221794#L1439-1 assume !(1 == ~E_7~0); 1220177#L1444-1 assume !(1 == ~E_8~0); 1220178#L1449-1 assume !(1 == ~E_9~0); 1220628#L1454-1 assume !(1 == ~E_10~0); 1220629#L1459-1 assume !(1 == ~E_11~0); 1221241#L1464-1 assume !(1 == ~E_12~0); 1221242#L1469-1 assume { :end_inline_reset_delta_events } true; 1221307#L1815-2 [2024-11-19 15:04:17,523 INFO L747 eck$LassoCheckResult]: Loop: 1221307#L1815-2 assume !false; 1396172#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1396161#L1181-1 assume !false; 1396157#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1395949#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1395939#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1395932#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1395933#L1008 assume !(0 != eval_~tmp~0#1); 1395976#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1398003#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1398002#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1398001#L1206-5 assume !(0 == ~T1_E~0); 1398000#L1211-3 assume !(0 == ~T2_E~0); 1397999#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1397998#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1397997#L1226-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1397996#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1397995#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1397994#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1397993#L1246-3 assume !(0 == ~T9_E~0); 1397992#L1251-3 assume !(0 == ~T10_E~0); 1397991#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1397990#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1397989#L1266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1397988#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1397987#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1397986#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1397985#L1286-3 assume !(0 == ~E_4~0); 1397984#L1291-3 assume !(0 == ~E_5~0); 1397983#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1397982#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1397981#L1306-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1397980#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1397978#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1397976#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1397974#L1326-3 assume !(0 == ~E_12~0); 1397972#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1397970#L598-42 assume !(1 == ~m_pc~0); 1397968#L598-44 is_master_triggered_~__retres1~0#1 := 0; 1397966#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1397963#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1397960#L1497-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1397957#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1397954#L617-42 assume !(1 == ~t1_pc~0); 1397951#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1397947#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1397943#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1397938#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 1397933#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1397929#L636-42 assume !(1 == ~t2_pc~0); 1397925#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1397922#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1397919#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1397916#L1513-42 assume !(0 != activate_threads_~tmp___1~0#1); 1397913#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1397910#L655-42 assume !(1 == ~t3_pc~0); 1397907#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1397904#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1397901#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1397898#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1397895#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1397892#L674-42 assume !(1 == ~t4_pc~0); 1397889#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1397886#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1397883#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1397880#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1397877#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1397874#L693-42 assume 1 == ~t5_pc~0; 1397869#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1397865#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1397861#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1397856#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1397853#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1397850#L712-42 assume !(1 == ~t6_pc~0); 1397847#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1397844#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1397841#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1397838#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1397835#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1397832#L731-42 assume !(1 == ~t7_pc~0); 1397827#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1397823#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1397819#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1397815#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1397811#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1397807#L750-42 assume 1 == ~t8_pc~0; 1397803#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1397797#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1397792#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1397786#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1397781#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1397777#L769-42 assume !(1 == ~t9_pc~0); 1397772#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1397767#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1397763#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1397757#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 1397752#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1397747#L788-42 assume 1 == ~t10_pc~0; 1397741#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1397736#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1397731#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1397725#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1397719#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1397713#L807-42 assume !(1 == ~t11_pc~0); 1397708#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1397701#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1397696#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1397690#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1397685#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1397680#L826-42 assume 1 == ~t12_pc~0; 1397673#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1397667#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1397662#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1397656#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1397650#L1593-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1397645#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1305768#L1344-5 assume !(1 == ~T1_E~0); 1397635#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1397630#L1354-3 assume !(1 == ~T3_E~0); 1397625#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1397620#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1397615#L1369-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1397608#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1397602#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1397596#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1345182#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1397584#L1394-3 assume !(1 == ~T11_E~0); 1397578#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1397571#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1397563#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1397557#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1397551#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1397545#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1359240#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1397535#L1434-3 assume !(1 == ~E_6~0); 1397530#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1397525#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1397520#L1449-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1397516#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1397511#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1397507#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1349943#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1397487#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1397481#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1397480#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1397478#L1834 assume !(0 == start_simulation_~tmp~3#1); 1397476#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1397449#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1397442#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1397438#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1397432#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1397428#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1397423#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1396312#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 1221307#L1815-2 [2024-11-19 15:04:17,523 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:17,523 INFO L85 PathProgramCache]: Analyzing trace with hash -1728090755, now seen corresponding path program 1 times [2024-11-19 15:04:17,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:17,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663622845] [2024-11-19 15:04:17,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:17,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:17,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:17,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:17,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:17,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663622845] [2024-11-19 15:04:17,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [663622845] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:17,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:17,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:04:17,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665864031] [2024-11-19 15:04:17,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:17,616 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:17,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:17,616 INFO L85 PathProgramCache]: Analyzing trace with hash 1230633896, now seen corresponding path program 1 times [2024-11-19 15:04:17,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:17,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221175886] [2024-11-19 15:04:17,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:17,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:17,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:17,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:17,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:17,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221175886] [2024-11-19 15:04:17,647 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221175886] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:17,648 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:17,648 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:17,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1470445689] [2024-11-19 15:04:17,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:17,648 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:17,648 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:17,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:04:17,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:04:17,649 INFO L87 Difference]: Start difference. First operand 449584 states and 635779 transitions. cyclomatic complexity: 186451 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:19,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:19,975 INFO L93 Difference]: Finished difference Result 461443 states and 647638 transitions. [2024-11-19 15:04:19,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 461443 states and 647638 transitions. [2024-11-19 15:04:22,820 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 459424 [2024-11-19 15:04:24,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 461443 states to 461443 states and 647638 transitions. [2024-11-19 15:04:24,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 461443 [2024-11-19 15:04:24,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 461443 [2024-11-19 15:04:24,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 461443 states and 647638 transitions. [2024-11-19 15:04:24,914 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:24,915 INFO L218 hiAutomatonCegarLoop]: Abstraction has 461443 states and 647638 transitions. [2024-11-19 15:04:25,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 461443 states and 647638 transitions.