./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.06.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3061b6dc Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.06.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-assert-order-craig-3061b6d-m [2024-11-19 15:04:23,516 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-19 15:04:23,597 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-19 15:04:23,604 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-19 15:04:23,606 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-19 15:04:23,642 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-19 15:04:23,644 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-19 15:04:23,644 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-19 15:04:23,645 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-19 15:04:23,646 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-19 15:04:23,647 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-19 15:04:23,647 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-19 15:04:23,648 INFO L153 SettingsManager]: * Use SBE=true [2024-11-19 15:04:23,648 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-19 15:04:23,651 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-19 15:04:23,652 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-19 15:04:23,652 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-19 15:04:23,652 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-19 15:04:23,652 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-19 15:04:23,653 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-19 15:04:23,653 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-19 15:04:23,654 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-19 15:04:23,654 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-19 15:04:23,654 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-19 15:04:23,654 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-19 15:04:23,654 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-19 15:04:23,655 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-19 15:04:23,655 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-19 15:04:23,655 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-19 15:04:23,655 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-19 15:04:23,656 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-19 15:04:23,656 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-19 15:04:23,656 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-19 15:04:23,656 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-19 15:04:23,657 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-19 15:04:23,657 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-19 15:04:23,660 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-19 15:04:23,660 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-19 15:04:23,661 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-19 15:04:23,661 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df [2024-11-19 15:04:23,895 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-19 15:04:23,925 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-19 15:04:23,928 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-19 15:04:23,929 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-19 15:04:23,930 INFO L274 PluginConnector]: CDTParser initialized [2024-11-19 15:04:23,931 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.06.cil.c [2024-11-19 15:04:25,390 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-19 15:04:25,607 INFO L384 CDTParser]: Found 1 translation units. [2024-11-19 15:04:25,607 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.06.cil.c [2024-11-19 15:04:25,619 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bb9103227/28ad65bc4cd3434d86137608ddef640a/FLAG41eba9bc7 [2024-11-19 15:04:25,634 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bb9103227/28ad65bc4cd3434d86137608ddef640a [2024-11-19 15:04:25,637 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-19 15:04:25,638 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-19 15:04:25,639 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-19 15:04:25,640 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-19 15:04:25,646 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-19 15:04:25,647 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 03:04:25" (1/1) ... [2024-11-19 15:04:25,650 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7c92b71b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:25, skipping insertion in model container [2024-11-19 15:04:25,650 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 03:04:25" (1/1) ... [2024-11-19 15:04:25,690 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-19 15:04:25,934 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 15:04:25,954 INFO L200 MainTranslator]: Completed pre-run [2024-11-19 15:04:26,027 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-19 15:04:26,050 INFO L204 MainTranslator]: Completed translation [2024-11-19 15:04:26,050 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26 WrapperNode [2024-11-19 15:04:26,050 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-19 15:04:26,051 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-19 15:04:26,052 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-19 15:04:26,052 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-19 15:04:26,057 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,067 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,125 INFO L138 Inliner]: procedures = 40, calls = 49, calls flagged for inlining = 44, calls inlined = 105, statements flattened = 1536 [2024-11-19 15:04:26,126 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-19 15:04:26,127 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-19 15:04:26,127 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-19 15:04:26,127 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-19 15:04:26,142 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,143 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,155 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,178 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-19 15:04:26,179 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,179 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,197 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,212 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,215 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,220 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,226 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-19 15:04:26,227 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-19 15:04:26,228 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-19 15:04:26,228 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-19 15:04:26,229 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (1/1) ... [2024-11-19 15:04:26,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-19 15:04:26,254 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-19 15:04:26,275 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-19 15:04:26,278 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-19 15:04:26,349 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-19 15:04:26,349 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-19 15:04:26,349 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-19 15:04:26,349 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-19 15:04:26,459 INFO L238 CfgBuilder]: Building ICFG [2024-11-19 15:04:26,461 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-19 15:04:27,710 INFO L? ?]: Removed 290 outVars from TransFormulas that were not future-live. [2024-11-19 15:04:27,711 INFO L287 CfgBuilder]: Performing block encoding [2024-11-19 15:04:27,748 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-19 15:04:27,749 INFO L316 CfgBuilder]: Removed 10 assume(true) statements. [2024-11-19 15:04:27,749 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:04:27 BoogieIcfgContainer [2024-11-19 15:04:27,749 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-19 15:04:27,750 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-19 15:04:27,751 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-19 15:04:27,754 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-19 15:04:27,758 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:04:27,759 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 03:04:25" (1/3) ... [2024-11-19 15:04:27,760 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3cedbf45 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 03:04:27, skipping insertion in model container [2024-11-19 15:04:27,760 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:04:27,760 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 03:04:26" (2/3) ... [2024-11-19 15:04:27,761 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3cedbf45 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 03:04:27, skipping insertion in model container [2024-11-19 15:04:27,761 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-19 15:04:27,761 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:04:27" (3/3) ... [2024-11-19 15:04:27,762 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.06.cil.c [2024-11-19 15:04:27,825 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-19 15:04:27,826 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-19 15:04:27,826 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-19 15:04:27,826 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-19 15:04:27,826 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-19 15:04:27,826 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-19 15:04:27,826 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-19 15:04:27,826 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-19 15:04:27,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 641 states, 640 states have (on average 1.521875) internal successors, (974), 640 states have internal predecessors, (974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:27,875 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 548 [2024-11-19 15:04:27,876 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:27,876 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:27,889 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:27,890 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:27,890 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-19 15:04:27,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 641 states, 640 states have (on average 1.521875) internal successors, (974), 640 states have internal predecessors, (974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:27,914 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 548 [2024-11-19 15:04:27,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:27,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:27,917 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:27,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:27,928 INFO L745 eck$LassoCheckResult]: Stem: 183#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 525#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 291#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 521#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2#L461true assume !(1 == ~m_i~0);~m_st~0 := 2; 350#L461-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 565#L466-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 617#L471-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 43#L476-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 277#L481-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 136#L486-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 51#L491-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 536#L670true assume !(0 == ~M_E~0); 306#L670-2true assume !(0 == ~T1_E~0); 255#L675-1true assume !(0 == ~T2_E~0); 349#L680-1true assume !(0 == ~T3_E~0); 445#L685-1true assume !(0 == ~T4_E~0); 313#L690-1true assume !(0 == ~T5_E~0); 616#L695-1true assume !(0 == ~T6_E~0); 395#L700-1true assume 0 == ~E_1~0;~E_1~0 := 1; 382#L705-1true assume !(0 == ~E_2~0); 557#L710-1true assume !(0 == ~E_3~0); 253#L715-1true assume !(0 == ~E_4~0); 199#L720-1true assume !(0 == ~E_5~0); 240#L725-1true assume !(0 == ~E_6~0); 281#L730-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 415#L320true assume 1 == ~m_pc~0; 229#L321true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 162#L331true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 158#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 137#L825true assume !(0 != activate_threads_~tmp~1#1); 460#L825-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 140#L339true assume !(1 == ~t1_pc~0); 432#L339-2true is_transmit1_triggered_~__retres1~1#1 := 0; 122#L350true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54#L833true assume !(0 != activate_threads_~tmp___0~0#1); 550#L833-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13#L358true assume 1 == ~t2_pc~0; 595#L359true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 519#L369true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 243#L841true assume !(0 != activate_threads_~tmp___1~0#1); 134#L841-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 465#L377true assume !(1 == ~t3_pc~0); 330#L377-2true is_transmit3_triggered_~__retres1~3#1 := 0; 341#L388true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 139#L849true assume !(0 != activate_threads_~tmp___2~0#1); 346#L849-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96#L396true assume 1 == ~t4_pc~0; 457#L397true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14#L407true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 268#L857true assume !(0 != activate_threads_~tmp___3~0#1); 79#L857-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125#L415true assume 1 == ~t5_pc~0; 334#L416true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 282#L426true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 435#L865true assume !(0 != activate_threads_~tmp___4~0#1); 32#L865-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 331#L434true assume !(1 == ~t6_pc~0); 220#L434-2true is_transmit6_triggered_~__retres1~6#1 := 0; 361#L445true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 286#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 362#L873true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 146#L873-2true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 548#L743true assume !(1 == ~M_E~0); 73#L743-2true assume !(1 == ~T1_E~0); 496#L748-1true assume !(1 == ~T2_E~0); 274#L753-1true assume !(1 == ~T3_E~0); 399#L758-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 472#L763-1true assume !(1 == ~T5_E~0); 561#L768-1true assume !(1 == ~T6_E~0); 143#L773-1true assume !(1 == ~E_1~0); 629#L778-1true assume !(1 == ~E_2~0); 131#L783-1true assume !(1 == ~E_3~0); 605#L788-1true assume !(1 == ~E_4~0); 347#L793-1true assume !(1 == ~E_5~0); 300#L798-1true assume 1 == ~E_6~0;~E_6~0 := 2; 63#L803-1true assume { :end_inline_reset_delta_events } true; 246#L1024-2true [2024-11-19 15:04:27,931 INFO L747 eck$LassoCheckResult]: Loop: 246#L1024-2true assume !false; 483#L1025true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128#L645-1true assume !true; 91#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 447#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58#L670-3true assume 0 == ~M_E~0;~M_E~0 := 1; 235#L670-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 159#L675-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 438#L680-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 344#L685-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 611#L690-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 567#L695-3true assume !(0 == ~T6_E~0); 355#L700-3true assume 0 == ~E_1~0;~E_1~0 := 1; 638#L705-3true assume 0 == ~E_2~0;~E_2~0 := 1; 86#L710-3true assume 0 == ~E_3~0;~E_3~0 := 1; 390#L715-3true assume 0 == ~E_4~0;~E_4~0 := 1; 244#L720-3true assume 0 == ~E_5~0;~E_5~0 := 1; 314#L725-3true assume 0 == ~E_6~0;~E_6~0 := 1; 506#L730-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144#L320-21true assume 1 == ~m_pc~0; 470#L321-7true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 543#L331-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112#is_master_triggered_returnLabel#8true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 486#L825-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 454#L825-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94#L339-21true assume 1 == ~t1_pc~0; 169#L340-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 626#L350-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 24#L833-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70#L833-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 587#L358-21true assume !(1 == ~t2_pc~0); 100#L358-23true is_transmit2_triggered_~__retres1~2#1 := 0; 64#L369-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 405#L841-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80#L841-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 477#L377-21true assume 1 == ~t3_pc~0; 570#L378-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 267#L388-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 542#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 288#L849-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 178#L849-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 301#L396-21true assume !(1 == ~t4_pc~0); 190#L396-23true is_transmit4_triggered_~__retres1~4#1 := 0; 230#L407-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 499#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16#L857-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 303#L857-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 160#L415-21true assume 1 == ~t5_pc~0; 516#L416-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 437#L426-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 272#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 225#L865-21true assume !(0 != activate_threads_~tmp___4~0#1); 202#L865-23true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 383#L434-21true assume !(1 == ~t6_pc~0); 28#L434-23true is_transmit6_triggered_~__retres1~6#1 := 0; 431#L445-7true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 252#is_transmit6_triggered_returnLabel#8true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 155#L873-21true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 260#L873-23true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 151#L743-3true assume 1 == ~M_E~0;~M_E~0 := 2; 502#L743-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 564#L748-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 261#L753-3true assume !(1 == ~T3_E~0); 214#L758-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 172#L763-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 533#L768-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 478#L773-3true assume 1 == ~E_1~0;~E_1~0 := 2; 110#L778-3true assume 1 == ~E_2~0;~E_2~0 := 2; 265#L783-3true assume 1 == ~E_3~0;~E_3~0 := 2; 580#L788-3true assume 1 == ~E_4~0;~E_4~0 := 2; 528#L793-3true assume !(1 == ~E_5~0); 541#L798-3true assume 1 == ~E_6~0;~E_6~0 := 2; 304#L803-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 104#L504-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 401#L541-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 264#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 448#L1043true assume !(0 == start_simulation_~tmp~3#1); 443#L1043-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 262#L504-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 333#L541-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 41#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 234#L998true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57#L1005true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 466#stop_simulation_returnLabel#1true start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 224#L1056true assume !(0 != start_simulation_~tmp___0~1#1); 246#L1024-2true [2024-11-19 15:04:27,944 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:27,948 INFO L85 PathProgramCache]: Analyzing trace with hash -1010496615, now seen corresponding path program 1 times [2024-11-19 15:04:27,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:27,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199605776] [2024-11-19 15:04:27,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:27,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:28,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:28,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:28,278 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:28,279 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199605776] [2024-11-19 15:04:28,279 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199605776] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:28,280 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:28,280 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:28,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929695284] [2024-11-19 15:04:28,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:28,286 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:28,287 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:28,287 INFO L85 PathProgramCache]: Analyzing trace with hash -1655056166, now seen corresponding path program 1 times [2024-11-19 15:04:28,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:28,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1413471716] [2024-11-19 15:04:28,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:28,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:28,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:28,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:28,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:28,343 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1413471716] [2024-11-19 15:04:28,343 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1413471716] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:28,343 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:28,344 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:04:28,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1092119953] [2024-11-19 15:04:28,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:28,349 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:28,350 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:28,391 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:28,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:28,396 INFO L87 Difference]: Start difference. First operand has 641 states, 640 states have (on average 1.521875) internal successors, (974), 640 states have internal predecessors, (974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:28,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:28,464 INFO L93 Difference]: Finished difference Result 639 states and 950 transitions. [2024-11-19 15:04:28,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 639 states and 950 transitions. [2024-11-19 15:04:28,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:28,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 639 states to 633 states and 944 transitions. [2024-11-19 15:04:28,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2024-11-19 15:04:28,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2024-11-19 15:04:28,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 944 transitions. [2024-11-19 15:04:28,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:28,502 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 944 transitions. [2024-11-19 15:04:28,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 944 transitions. [2024-11-19 15:04:28,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2024-11-19 15:04:28,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4913112164296998) internal successors, (944), 632 states have internal predecessors, (944), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:28,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 944 transitions. [2024-11-19 15:04:28,573 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 944 transitions. [2024-11-19 15:04:28,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:28,581 INFO L425 stractBuchiCegarLoop]: Abstraction has 633 states and 944 transitions. [2024-11-19 15:04:28,581 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-19 15:04:28,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 944 transitions. [2024-11-19 15:04:28,586 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:28,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:28,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:28,592 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:28,593 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:28,593 INFO L745 eck$LassoCheckResult]: Stem: 1630#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1631#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1760#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1761#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1289#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1290#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1816#L466-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1914#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1387#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1388#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1552#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1401#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1402#L670 assume !(0 == ~M_E~0); 1772#L670-2 assume !(0 == ~T1_E~0); 1725#L675-1 assume !(0 == ~T2_E~0); 1726#L680-1 assume !(0 == ~T3_E~0); 1814#L685-1 assume !(0 == ~T4_E~0); 1779#L690-1 assume !(0 == ~T5_E~0); 1780#L695-1 assume !(0 == ~T6_E~0); 1851#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1840#L705-1 assume !(0 == ~E_2~0); 1841#L710-1 assume !(0 == ~E_3~0); 1724#L715-1 assume !(0 == ~E_4~0); 1656#L720-1 assume !(0 == ~E_5~0); 1657#L725-1 assume !(0 == ~E_6~0); 1704#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1749#L320 assume 1 == ~m_pc~0; 1697#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1599#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1593#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1553#L825 assume !(0 != activate_threads_~tmp~1#1); 1554#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1558#L339 assume !(1 == ~t1_pc~0); 1559#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1528#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1383#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1384#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1406#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1315#L358 assume 1 == ~t2_pc~0; 1316#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1833#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1763#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1707#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1548#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1549#L377 assume !(1 == ~t3_pc~0); 1798#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1799#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1311#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1312#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1557#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1483#L396 assume 1 == ~t4_pc~0; 1484#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1318#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1319#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1465#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1450#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1451#L415 assume 1 == ~t5_pc~0; 1533#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1588#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1603#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1604#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1359#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1360#L434 assume !(1 == ~t6_pc~0); 1685#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1686#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1754#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1755#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1572#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1573#L743 assume !(1 == ~M_E~0); 1442#L743-2 assume !(1 == ~T1_E~0); 1443#L748-1 assume !(1 == ~T2_E~0); 1745#L753-1 assume !(1 == ~T3_E~0); 1746#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1854#L763-1 assume !(1 == ~T5_E~0); 1886#L768-1 assume !(1 == ~T6_E~0); 1567#L773-1 assume !(1 == ~E_1~0); 1568#L778-1 assume !(1 == ~E_2~0); 1543#L783-1 assume !(1 == ~E_3~0); 1544#L788-1 assume !(1 == ~E_4~0); 1812#L793-1 assume !(1 == ~E_5~0); 1768#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1423#L803-1 assume { :end_inline_reset_delta_events } true; 1424#L1024-2 [2024-11-19 15:04:28,594 INFO L747 eck$LassoCheckResult]: Loop: 1424#L1024-2 assume !false; 1712#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1297#L645-1 assume !false; 1538#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1653#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1367#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1786#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1787#L556 assume !(0 != eval_~tmp~0#1); 1474#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1475#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1417#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1418#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1596#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1597#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1809#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1810#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1915#L695-3 assume !(0 == ~T6_E~0); 1818#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1819#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1463#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1464#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1708#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1709#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1781#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1569#L320-21 assume !(1 == ~m_pc~0); 1570#L320-23 is_master_triggered_~__retres1~0#1 := 0; 1706#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1513#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1514#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1876#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1478#L339-21 assume 1 == ~t1_pc~0; 1479#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1609#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1447#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1343#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1344#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1440#L358-21 assume !(1 == ~t2_pc~0); 1492#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 1425#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1426#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1654#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1452#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1453#L377-21 assume 1 == ~t3_pc~0; 1888#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1737#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1738#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1756#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1620#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1621#L396-21 assume !(1 == ~t4_pc~0); 1640#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 1641#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1696#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1325#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1326#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1594#L415-21 assume 1 == ~t5_pc~0; 1595#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1566#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1744#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1690#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 1659#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1660#L434-21 assume !(1 == ~t6_pc~0); 1348#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 1349#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1723#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1589#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1590#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1582#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1583#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1898#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1731#L753-3 assume !(1 == ~T3_E~0); 1675#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1611#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1612#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1889#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1507#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1508#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1736#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1906#L793-3 assume !(1 == ~E_5~0); 1907#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1771#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1498#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1395#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1734#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1735#L1043 assume !(0 == start_simulation_~tmp~3#1); 1869#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1732#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1516#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1381#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1382#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1411#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1412#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1689#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 1424#L1024-2 [2024-11-19 15:04:28,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:28,597 INFO L85 PathProgramCache]: Analyzing trace with hash -1849530277, now seen corresponding path program 1 times [2024-11-19 15:04:28,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:28,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707268790] [2024-11-19 15:04:28,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:28,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:28,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:28,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:28,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:28,725 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707268790] [2024-11-19 15:04:28,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1707268790] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:28,726 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:28,726 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:28,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012002514] [2024-11-19 15:04:28,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:28,728 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:28,729 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:28,729 INFO L85 PathProgramCache]: Analyzing trace with hash -721591099, now seen corresponding path program 1 times [2024-11-19 15:04:28,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:28,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [772985117] [2024-11-19 15:04:28,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:28,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:28,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:28,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:28,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:28,857 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [772985117] [2024-11-19 15:04:28,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [772985117] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:28,857 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:28,857 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:28,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1423142883] [2024-11-19 15:04:28,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:28,858 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:28,858 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:28,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:28,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:28,859 INFO L87 Difference]: Start difference. First operand 633 states and 944 transitions. cyclomatic complexity: 312 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:28,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:28,879 INFO L93 Difference]: Finished difference Result 633 states and 943 transitions. [2024-11-19 15:04:28,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 943 transitions. [2024-11-19 15:04:28,885 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:28,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 943 transitions. [2024-11-19 15:04:28,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2024-11-19 15:04:28,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2024-11-19 15:04:28,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 943 transitions. [2024-11-19 15:04:28,894 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:28,894 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 943 transitions. [2024-11-19 15:04:28,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 943 transitions. [2024-11-19 15:04:28,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2024-11-19 15:04:28,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4897314375987363) internal successors, (943), 632 states have internal predecessors, (943), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:28,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 943 transitions. [2024-11-19 15:04:28,914 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 943 transitions. [2024-11-19 15:04:28,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:28,915 INFO L425 stractBuchiCegarLoop]: Abstraction has 633 states and 943 transitions. [2024-11-19 15:04:28,918 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-19 15:04:28,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 943 transitions. [2024-11-19 15:04:28,923 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:28,923 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:28,923 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:28,925 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:28,925 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:28,925 INFO L745 eck$LassoCheckResult]: Stem: 2905#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 2906#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3033#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3034#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2562#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 2563#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3089#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3187#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2660#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2661#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2825#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2675#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2676#L670 assume !(0 == ~M_E~0); 3047#L670-2 assume !(0 == ~T1_E~0); 2998#L675-1 assume !(0 == ~T2_E~0); 2999#L680-1 assume !(0 == ~T3_E~0); 3087#L685-1 assume !(0 == ~T4_E~0); 3053#L690-1 assume !(0 == ~T5_E~0); 3054#L695-1 assume !(0 == ~T6_E~0); 3124#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3113#L705-1 assume !(0 == ~E_2~0); 3114#L710-1 assume !(0 == ~E_3~0); 2997#L715-1 assume !(0 == ~E_4~0); 2929#L720-1 assume !(0 == ~E_5~0); 2930#L725-1 assume !(0 == ~E_6~0); 2977#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3022#L320 assume 1 == ~m_pc~0; 2970#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2872#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2866#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2826#L825 assume !(0 != activate_threads_~tmp~1#1); 2827#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2835#L339 assume !(1 == ~t1_pc~0); 2836#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2801#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2656#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2657#L833 assume !(0 != activate_threads_~tmp___0~0#1); 2679#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2588#L358 assume 1 == ~t2_pc~0; 2589#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3106#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3036#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2980#L841 assume !(0 != activate_threads_~tmp___1~0#1); 2821#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2822#L377 assume !(1 == ~t3_pc~0); 3071#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3072#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2586#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2587#L849 assume !(0 != activate_threads_~tmp___2~0#1); 2830#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2758#L396 assume 1 == ~t4_pc~0; 2759#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2591#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2592#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2738#L857 assume !(0 != activate_threads_~tmp___3~0#1); 2723#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2724#L415 assume 1 == ~t5_pc~0; 2808#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2861#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2879#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2880#L865 assume !(0 != activate_threads_~tmp___4~0#1); 2632#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2633#L434 assume !(1 == ~t6_pc~0); 2959#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2960#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3027#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3028#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2845#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2846#L743 assume !(1 == ~M_E~0); 2715#L743-2 assume !(1 == ~T1_E~0); 2716#L748-1 assume !(1 == ~T2_E~0); 3018#L753-1 assume !(1 == ~T3_E~0); 3019#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3127#L763-1 assume !(1 == ~T5_E~0); 3159#L768-1 assume !(1 == ~T6_E~0); 2843#L773-1 assume !(1 == ~E_1~0); 2844#L778-1 assume !(1 == ~E_2~0); 2816#L783-1 assume !(1 == ~E_3~0); 2817#L788-1 assume !(1 == ~E_4~0); 3085#L793-1 assume !(1 == ~E_5~0); 3041#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2698#L803-1 assume { :end_inline_reset_delta_events } true; 2699#L1024-2 [2024-11-19 15:04:28,925 INFO L747 eck$LassoCheckResult]: Loop: 2699#L1024-2 assume !false; 2985#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2570#L645-1 assume !false; 2813#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2926#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2640#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3059#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3060#L556 assume !(0 != eval_~tmp~0#1); 2747#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2748#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2692#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2693#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2867#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2868#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3082#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3083#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3188#L695-3 assume !(0 == ~T6_E~0); 3090#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3091#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2736#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2737#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2981#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2982#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3052#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2838#L320-21 assume !(1 == ~m_pc~0); 2839#L320-23 is_master_triggered_~__retres1~0#1 := 0; 2979#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2786#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2787#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3148#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2751#L339-21 assume 1 == ~t1_pc~0; 2752#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2881#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2720#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2616#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2617#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2713#L358-21 assume 1 == ~t2_pc~0; 2834#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2696#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2697#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2927#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2725#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2726#L377-21 assume 1 == ~t3_pc~0; 3161#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3012#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3013#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3029#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2893#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2894#L396-21 assume !(1 == ~t4_pc~0); 2913#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 2914#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2969#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2598#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2599#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2869#L415-21 assume 1 == ~t5_pc~0; 2870#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2842#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3017#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2963#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 2932#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2933#L434-21 assume 1 == ~t6_pc~0; 2942#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2624#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2996#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2862#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2863#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2855#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2856#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3171#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3004#L753-3 assume !(1 == ~T3_E~0); 2948#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2884#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2885#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3162#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2780#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2781#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3009#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3179#L793-3 assume !(1 == ~E_5~0); 3180#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3044#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2771#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2668#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3007#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3008#L1043 assume !(0 == start_simulation_~tmp~3#1); 3142#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3005#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2790#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2654#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2655#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2684#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2685#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2962#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 2699#L1024-2 [2024-11-19 15:04:28,926 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:28,929 INFO L85 PathProgramCache]: Analyzing trace with hash 227806621, now seen corresponding path program 1 times [2024-11-19 15:04:28,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:28,930 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372299780] [2024-11-19 15:04:28,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:28,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:28,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:28,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:28,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:28,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1372299780] [2024-11-19 15:04:28,984 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1372299780] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:28,984 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:28,984 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:28,984 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2002961967] [2024-11-19 15:04:28,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:28,985 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:28,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:28,985 INFO L85 PathProgramCache]: Analyzing trace with hash -1648316281, now seen corresponding path program 1 times [2024-11-19 15:04:28,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:28,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019668699] [2024-11-19 15:04:28,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:28,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:29,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:29,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:29,066 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:29,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019668699] [2024-11-19 15:04:29,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019668699] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:29,069 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:29,069 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:29,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953317352] [2024-11-19 15:04:29,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:29,070 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:29,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:29,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:29,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:29,071 INFO L87 Difference]: Start difference. First operand 633 states and 943 transitions. cyclomatic complexity: 311 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:29,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:29,085 INFO L93 Difference]: Finished difference Result 633 states and 942 transitions. [2024-11-19 15:04:29,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 942 transitions. [2024-11-19 15:04:29,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:29,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 942 transitions. [2024-11-19 15:04:29,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2024-11-19 15:04:29,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2024-11-19 15:04:29,095 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 942 transitions. [2024-11-19 15:04:29,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:29,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 942 transitions. [2024-11-19 15:04:29,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 942 transitions. [2024-11-19 15:04:29,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2024-11-19 15:04:29,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4881516587677726) internal successors, (942), 632 states have internal predecessors, (942), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:29,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 942 transitions. [2024-11-19 15:04:29,107 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 942 transitions. [2024-11-19 15:04:29,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:29,108 INFO L425 stractBuchiCegarLoop]: Abstraction has 633 states and 942 transitions. [2024-11-19 15:04:29,108 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-19 15:04:29,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 942 transitions. [2024-11-19 15:04:29,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:29,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:29,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:29,113 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:29,114 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:29,115 INFO L745 eck$LassoCheckResult]: Stem: 4173#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 4174#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4306#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4307#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3835#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 3836#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4361#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4460#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3931#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3932#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4098#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3947#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3948#L670 assume !(0 == ~M_E~0); 4318#L670-2 assume !(0 == ~T1_E~0); 4271#L675-1 assume !(0 == ~T2_E~0); 4272#L680-1 assume !(0 == ~T3_E~0); 4360#L685-1 assume !(0 == ~T4_E~0); 4325#L690-1 assume !(0 == ~T5_E~0); 4326#L695-1 assume !(0 == ~T6_E~0); 4397#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 4386#L705-1 assume !(0 == ~E_2~0); 4387#L710-1 assume !(0 == ~E_3~0); 4270#L715-1 assume !(0 == ~E_4~0); 4201#L720-1 assume !(0 == ~E_5~0); 4202#L725-1 assume !(0 == ~E_6~0); 4250#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4295#L320 assume 1 == ~m_pc~0; 4242#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4145#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4139#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4099#L825 assume !(0 != activate_threads_~tmp~1#1); 4100#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4104#L339 assume !(1 == ~t1_pc~0); 4105#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4074#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3929#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3930#L833 assume !(0 != activate_threads_~tmp___0~0#1); 3952#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3861#L358 assume 1 == ~t2_pc~0; 3862#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4379#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4309#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4253#L841 assume !(0 != activate_threads_~tmp___1~0#1); 4094#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4095#L377 assume !(1 == ~t3_pc~0); 4344#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4345#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3857#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3858#L849 assume !(0 != activate_threads_~tmp___2~0#1); 4103#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4029#L396 assume 1 == ~t4_pc~0; 4030#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3864#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3865#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4011#L857 assume !(0 != activate_threads_~tmp___3~0#1); 3996#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3997#L415 assume 1 == ~t5_pc~0; 4079#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4130#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4148#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4149#L865 assume !(0 != activate_threads_~tmp___4~0#1); 3905#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3906#L434 assume !(1 == ~t6_pc~0); 4231#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4232#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4300#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4301#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4118#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4119#L743 assume !(1 == ~M_E~0); 3988#L743-2 assume !(1 == ~T1_E~0); 3989#L748-1 assume !(1 == ~T2_E~0); 4291#L753-1 assume !(1 == ~T3_E~0); 4292#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4400#L763-1 assume !(1 == ~T5_E~0); 4432#L768-1 assume !(1 == ~T6_E~0); 4111#L773-1 assume !(1 == ~E_1~0); 4112#L778-1 assume !(1 == ~E_2~0); 4089#L783-1 assume !(1 == ~E_3~0); 4090#L788-1 assume !(1 == ~E_4~0); 4358#L793-1 assume !(1 == ~E_5~0); 4314#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3969#L803-1 assume { :end_inline_reset_delta_events } true; 3970#L1024-2 [2024-11-19 15:04:29,116 INFO L747 eck$LassoCheckResult]: Loop: 3970#L1024-2 assume !false; 4258#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3843#L645-1 assume !false; 4084#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4199#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3913#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4332#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4333#L556 assume !(0 != eval_~tmp~0#1); 4018#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4019#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3959#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3960#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4140#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4141#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4355#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4356#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4461#L695-3 assume !(0 == ~T6_E~0); 4363#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4364#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4009#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4010#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4254#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4255#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4327#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4113#L320-21 assume !(1 == ~m_pc~0); 4114#L320-23 is_master_triggered_~__retres1~0#1 := 0; 4252#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4059#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4060#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4421#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4024#L339-21 assume 1 == ~t1_pc~0; 4025#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4155#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3993#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3889#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3890#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3986#L358-21 assume !(1 == ~t2_pc~0); 4038#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 3971#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3972#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4200#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3998#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3999#L377-21 assume 1 == ~t3_pc~0; 4434#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4285#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4286#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4302#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4166#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4167#L396-21 assume !(1 == ~t4_pc~0); 4186#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4187#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4244#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3871#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3872#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4142#L415-21 assume !(1 == ~t5_pc~0); 4116#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4117#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4290#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4236#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 4205#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4206#L434-21 assume 1 == ~t6_pc~0; 4215#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3897#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4269#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4135#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4136#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4128#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4129#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4444#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4277#L753-3 assume !(1 == ~T3_E~0); 4221#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4157#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4158#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4435#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4053#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4054#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4282#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4452#L793-3 assume !(1 == ~E_5~0); 4453#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4317#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4044#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3941#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4280#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4281#L1043 assume !(0 == start_simulation_~tmp~3#1); 4415#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4278#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4063#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3927#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 3928#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3957#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3958#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4235#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 3970#L1024-2 [2024-11-19 15:04:29,117 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:29,118 INFO L85 PathProgramCache]: Analyzing trace with hash -1506297829, now seen corresponding path program 1 times [2024-11-19 15:04:29,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:29,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536710389] [2024-11-19 15:04:29,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:29,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:29,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:29,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:29,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:29,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536710389] [2024-11-19 15:04:29,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [536710389] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:29,196 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:29,196 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:29,196 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952775783] [2024-11-19 15:04:29,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:29,197 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:29,197 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:29,197 INFO L85 PathProgramCache]: Analyzing trace with hash -1117245051, now seen corresponding path program 1 times [2024-11-19 15:04:29,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:29,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259141944] [2024-11-19 15:04:29,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:29,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:29,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:29,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:29,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:29,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259141944] [2024-11-19 15:04:29,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259141944] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:29,250 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:29,250 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:29,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488750252] [2024-11-19 15:04:29,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:29,250 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:29,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:29,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:29,251 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:29,251 INFO L87 Difference]: Start difference. First operand 633 states and 942 transitions. cyclomatic complexity: 310 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:29,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:29,265 INFO L93 Difference]: Finished difference Result 633 states and 941 transitions. [2024-11-19 15:04:29,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 941 transitions. [2024-11-19 15:04:29,269 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:29,272 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 941 transitions. [2024-11-19 15:04:29,272 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2024-11-19 15:04:29,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2024-11-19 15:04:29,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 941 transitions. [2024-11-19 15:04:29,274 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:29,274 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 941 transitions. [2024-11-19 15:04:29,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 941 transitions. [2024-11-19 15:04:29,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2024-11-19 15:04:29,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4865718799368088) internal successors, (941), 632 states have internal predecessors, (941), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:29,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 941 transitions. [2024-11-19 15:04:29,287 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 941 transitions. [2024-11-19 15:04:29,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:29,289 INFO L425 stractBuchiCegarLoop]: Abstraction has 633 states and 941 transitions. [2024-11-19 15:04:29,290 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-19 15:04:29,290 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 941 transitions. [2024-11-19 15:04:29,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:29,292 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:29,293 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:29,294 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:29,294 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:29,295 INFO L745 eck$LassoCheckResult]: Stem: 5446#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 5447#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5579#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5580#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5108#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 5109#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5634#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5733#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5204#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5205#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5371#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5220#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5221#L670 assume !(0 == ~M_E~0); 5591#L670-2 assume !(0 == ~T1_E~0); 5544#L675-1 assume !(0 == ~T2_E~0); 5545#L680-1 assume !(0 == ~T3_E~0); 5633#L685-1 assume !(0 == ~T4_E~0); 5598#L690-1 assume !(0 == ~T5_E~0); 5599#L695-1 assume !(0 == ~T6_E~0); 5670#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5659#L705-1 assume !(0 == ~E_2~0); 5660#L710-1 assume !(0 == ~E_3~0); 5543#L715-1 assume !(0 == ~E_4~0); 5474#L720-1 assume !(0 == ~E_5~0); 5475#L725-1 assume !(0 == ~E_6~0); 5523#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5568#L320 assume 1 == ~m_pc~0; 5515#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5418#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5412#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5372#L825 assume !(0 != activate_threads_~tmp~1#1); 5373#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5377#L339 assume !(1 == ~t1_pc~0); 5378#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5347#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5202#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5203#L833 assume !(0 != activate_threads_~tmp___0~0#1); 5225#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5134#L358 assume 1 == ~t2_pc~0; 5135#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5652#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5582#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5526#L841 assume !(0 != activate_threads_~tmp___1~0#1); 5367#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5368#L377 assume !(1 == ~t3_pc~0); 5617#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5618#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5130#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5131#L849 assume !(0 != activate_threads_~tmp___2~0#1); 5376#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5302#L396 assume 1 == ~t4_pc~0; 5303#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5137#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5138#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5284#L857 assume !(0 != activate_threads_~tmp___3~0#1); 5269#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5270#L415 assume 1 == ~t5_pc~0; 5352#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5403#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5421#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5422#L865 assume !(0 != activate_threads_~tmp___4~0#1); 5178#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5179#L434 assume !(1 == ~t6_pc~0); 5504#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5505#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5573#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5574#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5391#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5392#L743 assume !(1 == ~M_E~0); 5261#L743-2 assume !(1 == ~T1_E~0); 5262#L748-1 assume !(1 == ~T2_E~0); 5564#L753-1 assume !(1 == ~T3_E~0); 5565#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5673#L763-1 assume !(1 == ~T5_E~0); 5705#L768-1 assume !(1 == ~T6_E~0); 5384#L773-1 assume !(1 == ~E_1~0); 5385#L778-1 assume !(1 == ~E_2~0); 5362#L783-1 assume !(1 == ~E_3~0); 5363#L788-1 assume !(1 == ~E_4~0); 5631#L793-1 assume !(1 == ~E_5~0); 5587#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5242#L803-1 assume { :end_inline_reset_delta_events } true; 5243#L1024-2 [2024-11-19 15:04:29,295 INFO L747 eck$LassoCheckResult]: Loop: 5243#L1024-2 assume !false; 5531#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5116#L645-1 assume !false; 5357#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5472#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5186#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5605#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5606#L556 assume !(0 != eval_~tmp~0#1); 5291#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5292#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5232#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5233#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5413#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5414#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5628#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5629#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5734#L695-3 assume !(0 == ~T6_E~0); 5636#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5637#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5282#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5283#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5527#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5528#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5600#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5386#L320-21 assume !(1 == ~m_pc~0); 5387#L320-23 is_master_triggered_~__retres1~0#1 := 0; 5525#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5332#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5333#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5694#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5297#L339-21 assume 1 == ~t1_pc~0; 5298#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5428#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5266#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5162#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5163#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5259#L358-21 assume 1 == ~t2_pc~0; 5383#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5244#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5245#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5473#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5271#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5272#L377-21 assume 1 == ~t3_pc~0; 5707#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5558#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5559#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5575#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5439#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5440#L396-21 assume !(1 == ~t4_pc~0); 5459#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 5460#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5517#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5144#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5145#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5415#L415-21 assume 1 == ~t5_pc~0; 5416#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5390#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5563#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5509#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 5478#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5479#L434-21 assume 1 == ~t6_pc~0; 5488#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5170#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5542#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5408#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5409#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5401#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5402#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5717#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5550#L753-3 assume !(1 == ~T3_E~0); 5494#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5430#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5431#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5708#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5326#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5327#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5555#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5725#L793-3 assume !(1 == ~E_5~0); 5726#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5590#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5317#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5214#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5553#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5554#L1043 assume !(0 == start_simulation_~tmp~3#1); 5688#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5551#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5336#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5200#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5201#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5230#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5231#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 5508#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 5243#L1024-2 [2024-11-19 15:04:29,295 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:29,295 INFO L85 PathProgramCache]: Analyzing trace with hash 1901446621, now seen corresponding path program 1 times [2024-11-19 15:04:29,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:29,296 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734251863] [2024-11-19 15:04:29,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:29,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:29,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:29,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:29,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:29,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [734251863] [2024-11-19 15:04:29,336 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [734251863] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:29,336 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:29,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:29,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460123646] [2024-11-19 15:04:29,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:29,336 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:29,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:29,337 INFO L85 PathProgramCache]: Analyzing trace with hash -1648316281, now seen corresponding path program 2 times [2024-11-19 15:04:29,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:29,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720836207] [2024-11-19 15:04:29,337 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:04:29,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:29,353 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:04:29,353 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:04:29,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:29,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:29,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720836207] [2024-11-19 15:04:29,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1720836207] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:29,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:29,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:29,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742499514] [2024-11-19 15:04:29,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:29,390 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:29,391 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:29,391 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:29,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:29,391 INFO L87 Difference]: Start difference. First operand 633 states and 941 transitions. cyclomatic complexity: 309 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:29,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:29,404 INFO L93 Difference]: Finished difference Result 633 states and 940 transitions. [2024-11-19 15:04:29,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 940 transitions. [2024-11-19 15:04:29,408 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:29,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 940 transitions. [2024-11-19 15:04:29,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2024-11-19 15:04:29,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2024-11-19 15:04:29,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 940 transitions. [2024-11-19 15:04:29,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:29,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 940 transitions. [2024-11-19 15:04:29,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 940 transitions. [2024-11-19 15:04:29,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2024-11-19 15:04:29,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4849921011058451) internal successors, (940), 632 states have internal predecessors, (940), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:29,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 940 transitions. [2024-11-19 15:04:29,422 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 940 transitions. [2024-11-19 15:04:29,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:29,424 INFO L425 stractBuchiCegarLoop]: Abstraction has 633 states and 940 transitions. [2024-11-19 15:04:29,424 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-19 15:04:29,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 940 transitions. [2024-11-19 15:04:29,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:29,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:29,428 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:29,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:29,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:29,431 INFO L745 eck$LassoCheckResult]: Stem: 6722#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 6723#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6852#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6853#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6381#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 6382#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6908#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7006#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6479#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6480#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6644#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6493#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6494#L670 assume !(0 == ~M_E~0); 6864#L670-2 assume !(0 == ~T1_E~0); 6817#L675-1 assume !(0 == ~T2_E~0); 6818#L680-1 assume !(0 == ~T3_E~0); 6906#L685-1 assume !(0 == ~T4_E~0); 6871#L690-1 assume !(0 == ~T5_E~0); 6872#L695-1 assume !(0 == ~T6_E~0); 6943#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6932#L705-1 assume !(0 == ~E_2~0); 6933#L710-1 assume !(0 == ~E_3~0); 6816#L715-1 assume !(0 == ~E_4~0); 6747#L720-1 assume !(0 == ~E_5~0); 6748#L725-1 assume !(0 == ~E_6~0); 6796#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6841#L320 assume 1 == ~m_pc~0; 6789#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6691#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6685#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6645#L825 assume !(0 != activate_threads_~tmp~1#1); 6646#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6650#L339 assume !(1 == ~t1_pc~0); 6651#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6620#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6475#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6476#L833 assume !(0 != activate_threads_~tmp___0~0#1); 6498#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6407#L358 assume 1 == ~t2_pc~0; 6408#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6925#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6855#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6799#L841 assume !(0 != activate_threads_~tmp___1~0#1); 6640#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6641#L377 assume !(1 == ~t3_pc~0); 6890#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6891#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6403#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6404#L849 assume !(0 != activate_threads_~tmp___2~0#1); 6649#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6575#L396 assume 1 == ~t4_pc~0; 6576#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6410#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6411#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6557#L857 assume !(0 != activate_threads_~tmp___3~0#1); 6542#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6543#L415 assume 1 == ~t5_pc~0; 6625#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6680#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6695#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6696#L865 assume !(0 != activate_threads_~tmp___4~0#1); 6451#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6452#L434 assume !(1 == ~t6_pc~0); 6777#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6778#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6846#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6847#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6664#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6665#L743 assume !(1 == ~M_E~0); 6534#L743-2 assume !(1 == ~T1_E~0); 6535#L748-1 assume !(1 == ~T2_E~0); 6837#L753-1 assume !(1 == ~T3_E~0); 6838#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6946#L763-1 assume !(1 == ~T5_E~0); 6978#L768-1 assume !(1 == ~T6_E~0); 6659#L773-1 assume !(1 == ~E_1~0); 6660#L778-1 assume !(1 == ~E_2~0); 6635#L783-1 assume !(1 == ~E_3~0); 6636#L788-1 assume !(1 == ~E_4~0); 6904#L793-1 assume !(1 == ~E_5~0); 6860#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6515#L803-1 assume { :end_inline_reset_delta_events } true; 6516#L1024-2 [2024-11-19 15:04:29,431 INFO L747 eck$LassoCheckResult]: Loop: 6516#L1024-2 assume !false; 6804#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6389#L645-1 assume !false; 6630#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6745#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6459#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6878#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6879#L556 assume !(0 != eval_~tmp~0#1); 6566#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6567#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6509#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6510#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6688#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6689#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6901#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6902#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7007#L695-3 assume !(0 == ~T6_E~0); 6910#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6911#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6555#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6556#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6800#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6801#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6873#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6661#L320-21 assume !(1 == ~m_pc~0); 6662#L320-23 is_master_triggered_~__retres1~0#1 := 0; 6798#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6605#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6606#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6968#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6570#L339-21 assume 1 == ~t1_pc~0; 6571#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6701#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6539#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6435#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6436#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6532#L358-21 assume 1 == ~t2_pc~0; 6656#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6517#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6518#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6746#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6544#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6545#L377-21 assume 1 == ~t3_pc~0; 6980#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6829#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6830#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6848#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6712#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6713#L396-21 assume !(1 == ~t4_pc~0); 6732#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 6733#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6788#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6417#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6418#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6686#L415-21 assume !(1 == ~t5_pc~0); 6657#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 6658#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6836#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6782#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 6751#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6752#L434-21 assume !(1 == ~t6_pc~0); 6440#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 6441#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6815#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6681#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6682#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6674#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6675#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6990#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6823#L753-3 assume !(1 == ~T3_E~0); 6767#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6703#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6704#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6981#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6599#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6600#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6828#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6998#L793-3 assume !(1 == ~E_5~0); 6999#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6863#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6590#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6487#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6826#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6827#L1043 assume !(0 == start_simulation_~tmp~3#1); 6961#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6824#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6608#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6473#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 6474#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6503#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6504#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6781#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 6516#L1024-2 [2024-11-19 15:04:29,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:29,432 INFO L85 PathProgramCache]: Analyzing trace with hash -482478117, now seen corresponding path program 1 times [2024-11-19 15:04:29,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:29,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178211546] [2024-11-19 15:04:29,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:29,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:29,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:29,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:29,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:29,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [178211546] [2024-11-19 15:04:29,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [178211546] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:29,472 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:29,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:29,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615898582] [2024-11-19 15:04:29,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:29,473 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:29,473 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:29,474 INFO L85 PathProgramCache]: Analyzing trace with hash -206020987, now seen corresponding path program 1 times [2024-11-19 15:04:29,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:29,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144086477] [2024-11-19 15:04:29,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:29,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:29,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:29,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:29,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:29,516 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144086477] [2024-11-19 15:04:29,516 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144086477] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:29,516 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:29,516 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:29,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420447723] [2024-11-19 15:04:29,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:29,517 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:29,517 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:29,518 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:29,518 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:29,518 INFO L87 Difference]: Start difference. First operand 633 states and 940 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:29,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:29,533 INFO L93 Difference]: Finished difference Result 633 states and 939 transitions. [2024-11-19 15:04:29,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 939 transitions. [2024-11-19 15:04:29,537 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:29,539 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 939 transitions. [2024-11-19 15:04:29,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2024-11-19 15:04:29,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2024-11-19 15:04:29,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 939 transitions. [2024-11-19 15:04:29,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:29,541 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 939 transitions. [2024-11-19 15:04:29,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 939 transitions. [2024-11-19 15:04:29,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2024-11-19 15:04:29,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4834123222748816) internal successors, (939), 632 states have internal predecessors, (939), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:29,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 939 transitions. [2024-11-19 15:04:29,551 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 939 transitions. [2024-11-19 15:04:29,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:29,552 INFO L425 stractBuchiCegarLoop]: Abstraction has 633 states and 939 transitions. [2024-11-19 15:04:29,552 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-19 15:04:29,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 939 transitions. [2024-11-19 15:04:29,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2024-11-19 15:04:29,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:29,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:29,557 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:29,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:29,559 INFO L745 eck$LassoCheckResult]: Stem: 7997#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 7998#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8125#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8126#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7654#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 7655#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8181#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8279#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7752#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7753#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7917#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7767#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7768#L670 assume !(0 == ~M_E~0); 8139#L670-2 assume !(0 == ~T1_E~0); 8090#L675-1 assume !(0 == ~T2_E~0); 8091#L680-1 assume !(0 == ~T3_E~0); 8179#L685-1 assume !(0 == ~T4_E~0); 8145#L690-1 assume !(0 == ~T5_E~0); 8146#L695-1 assume !(0 == ~T6_E~0); 8216#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8205#L705-1 assume !(0 == ~E_2~0); 8206#L710-1 assume !(0 == ~E_3~0); 8089#L715-1 assume !(0 == ~E_4~0); 8021#L720-1 assume !(0 == ~E_5~0); 8022#L725-1 assume !(0 == ~E_6~0); 8069#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8114#L320 assume 1 == ~m_pc~0; 8062#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7964#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7958#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7918#L825 assume !(0 != activate_threads_~tmp~1#1); 7919#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7924#L339 assume !(1 == ~t1_pc~0); 7925#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7893#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7748#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7749#L833 assume !(0 != activate_threads_~tmp___0~0#1); 7771#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7680#L358 assume 1 == ~t2_pc~0; 7681#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8198#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8128#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8072#L841 assume !(0 != activate_threads_~tmp___1~0#1); 7913#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7914#L377 assume !(1 == ~t3_pc~0); 8163#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8164#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7678#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7679#L849 assume !(0 != activate_threads_~tmp___2~0#1); 7922#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7850#L396 assume 1 == ~t4_pc~0; 7851#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7683#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7684#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7830#L857 assume !(0 != activate_threads_~tmp___3~0#1); 7815#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7816#L415 assume 1 == ~t5_pc~0; 7900#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7953#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7971#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7972#L865 assume !(0 != activate_threads_~tmp___4~0#1); 7724#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7725#L434 assume !(1 == ~t6_pc~0); 8051#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8052#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8119#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8120#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7937#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7938#L743 assume !(1 == ~M_E~0); 7807#L743-2 assume !(1 == ~T1_E~0); 7808#L748-1 assume !(1 == ~T2_E~0); 8110#L753-1 assume !(1 == ~T3_E~0); 8111#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8219#L763-1 assume !(1 == ~T5_E~0); 8251#L768-1 assume !(1 == ~T6_E~0); 7935#L773-1 assume !(1 == ~E_1~0); 7936#L778-1 assume !(1 == ~E_2~0); 7908#L783-1 assume !(1 == ~E_3~0); 7909#L788-1 assume !(1 == ~E_4~0); 8177#L793-1 assume !(1 == ~E_5~0); 8133#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 7790#L803-1 assume { :end_inline_reset_delta_events } true; 7791#L1024-2 [2024-11-19 15:04:29,559 INFO L747 eck$LassoCheckResult]: Loop: 7791#L1024-2 assume !false; 8077#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7662#L645-1 assume !false; 7905#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8018#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7732#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8151#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8152#L556 assume !(0 != eval_~tmp~0#1); 7839#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7784#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7785#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7961#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7962#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8174#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8175#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8280#L695-3 assume !(0 == ~T6_E~0); 8182#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8183#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7828#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7829#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8073#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8074#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8144#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7930#L320-21 assume !(1 == ~m_pc~0); 7931#L320-23 is_master_triggered_~__retres1~0#1 := 0; 8071#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7878#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7879#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8240#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7843#L339-21 assume 1 == ~t1_pc~0; 7844#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7973#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7812#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7708#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7709#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7805#L358-21 assume !(1 == ~t2_pc~0); 7857#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 7788#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7789#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8019#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7817#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7818#L377-21 assume !(1 == ~t3_pc~0); 8192#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 8102#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8103#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8121#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7985#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7986#L396-21 assume !(1 == ~t4_pc~0); 8005#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 8006#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8061#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7690#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7691#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7959#L415-21 assume 1 == ~t5_pc~0; 7960#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7934#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8109#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8055#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 8024#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8025#L434-21 assume 1 == ~t6_pc~0; 8034#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7716#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8088#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7954#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7955#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7947#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7948#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8263#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8096#L753-3 assume !(1 == ~T3_E~0); 8040#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7976#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7977#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8254#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7872#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7873#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8101#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8271#L793-3 assume !(1 == ~E_5~0); 8272#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8136#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7863#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7760#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8099#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 8100#L1043 assume !(0 == start_simulation_~tmp~3#1); 8234#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8097#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7881#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7746#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7747#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7776#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7777#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 8054#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 7791#L1024-2 [2024-11-19 15:04:29,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:29,560 INFO L85 PathProgramCache]: Analyzing trace with hash -559378915, now seen corresponding path program 1 times [2024-11-19 15:04:29,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:29,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200140668] [2024-11-19 15:04:29,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:29,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:29,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:29,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:29,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:29,644 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200140668] [2024-11-19 15:04:29,644 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1200140668] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:29,644 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:29,644 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:29,644 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224513014] [2024-11-19 15:04:29,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:29,645 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:29,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:29,645 INFO L85 PathProgramCache]: Analyzing trace with hash 924064517, now seen corresponding path program 1 times [2024-11-19 15:04:29,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:29,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339929175] [2024-11-19 15:04:29,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:29,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:29,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:29,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:29,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:29,685 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339929175] [2024-11-19 15:04:29,685 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1339929175] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:29,685 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:29,685 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:29,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729216744] [2024-11-19 15:04:29,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:29,686 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:29,686 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:29,686 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:04:29,686 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:04:29,687 INFO L87 Difference]: Start difference. First operand 633 states and 939 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:29,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:29,857 INFO L93 Difference]: Finished difference Result 1138 states and 1686 transitions. [2024-11-19 15:04:29,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1138 states and 1686 transitions. [2024-11-19 15:04:29,863 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1036 [2024-11-19 15:04:29,868 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1138 states to 1138 states and 1686 transitions. [2024-11-19 15:04:29,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1138 [2024-11-19 15:04:29,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1138 [2024-11-19 15:04:29,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1138 states and 1686 transitions. [2024-11-19 15:04:29,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:29,871 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1138 states and 1686 transitions. [2024-11-19 15:04:29,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1138 states and 1686 transitions. [2024-11-19 15:04:29,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1138 to 1136. [2024-11-19 15:04:29,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1136 states, 1136 states have (on average 1.482394366197183) internal successors, (1684), 1135 states have internal predecessors, (1684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:29,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1136 states to 1136 states and 1684 transitions. [2024-11-19 15:04:29,891 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1136 states and 1684 transitions. [2024-11-19 15:04:29,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:04:29,892 INFO L425 stractBuchiCegarLoop]: Abstraction has 1136 states and 1684 transitions. [2024-11-19 15:04:29,892 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-19 15:04:29,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1136 states and 1684 transitions. [2024-11-19 15:04:29,896 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1036 [2024-11-19 15:04:29,897 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:29,897 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:29,898 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:29,898 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:29,898 INFO L745 eck$LassoCheckResult]: Stem: 9774#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 9775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9907#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9908#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9435#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 9436#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9964#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10076#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9531#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9532#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9699#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9547#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9548#L670 assume !(0 == ~M_E~0); 9919#L670-2 assume !(0 == ~T1_E~0); 9872#L675-1 assume !(0 == ~T2_E~0); 9873#L680-1 assume !(0 == ~T3_E~0); 9963#L685-1 assume !(0 == ~T4_E~0); 9926#L690-1 assume !(0 == ~T5_E~0); 9927#L695-1 assume !(0 == ~T6_E~0); 10000#L700-1 assume !(0 == ~E_1~0); 9989#L705-1 assume !(0 == ~E_2~0); 9990#L710-1 assume !(0 == ~E_3~0); 9871#L715-1 assume !(0 == ~E_4~0); 9802#L720-1 assume !(0 == ~E_5~0); 9803#L725-1 assume !(0 == ~E_6~0); 9851#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9896#L320 assume 1 == ~m_pc~0; 9843#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9746#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9740#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9700#L825 assume !(0 != activate_threads_~tmp~1#1); 9701#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9705#L339 assume !(1 == ~t1_pc~0); 9706#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9674#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9529#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9530#L833 assume !(0 != activate_threads_~tmp___0~0#1); 9552#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9461#L358 assume 1 == ~t2_pc~0; 9462#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9982#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9910#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9854#L841 assume !(0 != activate_threads_~tmp___1~0#1); 9695#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9696#L377 assume !(1 == ~t3_pc~0); 9946#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9947#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9457#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9458#L849 assume !(0 != activate_threads_~tmp___2~0#1); 9704#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9629#L396 assume 1 == ~t4_pc~0; 9630#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9464#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9465#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9611#L857 assume !(0 != activate_threads_~tmp___3~0#1); 9596#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9597#L415 assume 1 == ~t5_pc~0; 9679#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9731#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9749#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9750#L865 assume !(0 != activate_threads_~tmp___4~0#1); 9505#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9506#L434 assume !(1 == ~t6_pc~0); 9832#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9833#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9901#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9902#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9719#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9720#L743 assume !(1 == ~M_E~0); 9588#L743-2 assume !(1 == ~T1_E~0); 9589#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9892#L753-1 assume !(1 == ~T3_E~0); 9893#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10003#L763-1 assume !(1 == ~T5_E~0); 10038#L768-1 assume !(1 == ~T6_E~0); 9712#L773-1 assume !(1 == ~E_1~0); 9713#L778-1 assume !(1 == ~E_2~0); 9690#L783-1 assume !(1 == ~E_3~0); 9691#L788-1 assume !(1 == ~E_4~0); 9961#L793-1 assume !(1 == ~E_5~0); 9915#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9569#L803-1 assume { :end_inline_reset_delta_events } true; 9570#L1024-2 [2024-11-19 15:04:29,899 INFO L747 eck$LassoCheckResult]: Loop: 9570#L1024-2 assume !false; 9859#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9684#L645-1 assume !false; 9685#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9800#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9513#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9933#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9934#L556 assume !(0 != eval_~tmp~0#1); 9618#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9619#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10092#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10091#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10089#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10090#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10570#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10569#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10568#L695-3 assume !(0 == ~T6_E~0); 10567#L700-3 assume !(0 == ~E_1~0); 10566#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10565#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10564#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10563#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10562#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10561#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10560#L320-21 assume !(1 == ~m_pc~0); 10558#L320-23 is_master_triggered_~__retres1~0#1 := 0; 10557#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10556#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10555#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10554#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10553#L339-21 assume 1 == ~t1_pc~0; 10551#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10550#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9593#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9489#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9490#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9586#L358-21 assume !(1 == ~t2_pc~0); 10458#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 10455#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10453#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10451#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10449#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10447#L377-21 assume 1 == ~t3_pc~0; 10444#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10441#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10439#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10437#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10435#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10433#L396-21 assume !(1 == ~t4_pc~0); 10430#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 10427#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10425#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10423#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10421#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10419#L415-21 assume 1 == ~t5_pc~0; 10416#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10413#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10411#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10385#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 10384#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10382#L434-21 assume 1 == ~t6_pc~0; 10379#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10377#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10375#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10373#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10370#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10368#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10053#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10054#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9878#L753-3 assume !(1 == ~T3_E~0); 9822#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9758#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9759#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10041#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9653#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9654#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9883#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10067#L793-3 assume !(1 == ~E_5~0); 10068#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9918#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9644#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9541#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9881#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9882#L1043 assume !(0 == start_simulation_~tmp~3#1); 10019#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9879#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9663#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9527#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9528#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9557#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9558#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9836#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 9570#L1024-2 [2024-11-19 15:04:29,899 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:29,899 INFO L85 PathProgramCache]: Analyzing trace with hash -1234940959, now seen corresponding path program 1 times [2024-11-19 15:04:29,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:29,900 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017914510] [2024-11-19 15:04:29,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:29,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:29,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:29,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:29,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:29,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017914510] [2024-11-19 15:04:29,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1017914510] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:29,966 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:29,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:04:29,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164553196] [2024-11-19 15:04:29,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:29,967 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:29,967 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:29,967 INFO L85 PathProgramCache]: Analyzing trace with hash 93538728, now seen corresponding path program 1 times [2024-11-19 15:04:29,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:29,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862147307] [2024-11-19 15:04:29,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:29,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:29,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:30,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:30,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:30,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862147307] [2024-11-19 15:04:30,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862147307] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:30,008 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:30,008 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:30,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672086526] [2024-11-19 15:04:30,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:30,009 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:30,009 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:30,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:30,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:30,009 INFO L87 Difference]: Start difference. First operand 1136 states and 1684 transitions. cyclomatic complexity: 550 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:30,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:30,087 INFO L93 Difference]: Finished difference Result 1660 states and 2431 transitions. [2024-11-19 15:04:30,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1660 states and 2431 transitions. [2024-11-19 15:04:30,097 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1557 [2024-11-19 15:04:30,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1660 states to 1660 states and 2431 transitions. [2024-11-19 15:04:30,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1660 [2024-11-19 15:04:30,105 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1660 [2024-11-19 15:04:30,106 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1660 states and 2431 transitions. [2024-11-19 15:04:30,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:30,108 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1660 states and 2431 transitions. [2024-11-19 15:04:30,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1660 states and 2431 transitions. [2024-11-19 15:04:30,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1660 to 1608. [2024-11-19 15:04:30,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1608 states, 1608 states have (on average 1.467039800995025) internal successors, (2359), 1607 states have internal predecessors, (2359), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:30,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1608 states to 1608 states and 2359 transitions. [2024-11-19 15:04:30,136 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1608 states and 2359 transitions. [2024-11-19 15:04:30,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:30,139 INFO L425 stractBuchiCegarLoop]: Abstraction has 1608 states and 2359 transitions. [2024-11-19 15:04:30,139 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-19 15:04:30,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1608 states and 2359 transitions. [2024-11-19 15:04:30,145 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1507 [2024-11-19 15:04:30,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:30,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:30,146 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:30,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:30,147 INFO L745 eck$LassoCheckResult]: Stem: 12574#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 12575#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 12708#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12709#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12238#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 12239#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12772#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12901#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12333#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12334#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12499#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12349#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12350#L670 assume !(0 == ~M_E~0); 12721#L670-2 assume !(0 == ~T1_E~0); 12673#L675-1 assume !(0 == ~T2_E~0); 12674#L680-1 assume !(0 == ~T3_E~0); 12771#L685-1 assume !(0 == ~T4_E~0); 12729#L690-1 assume !(0 == ~T5_E~0); 12730#L695-1 assume !(0 == ~T6_E~0); 12807#L700-1 assume !(0 == ~E_1~0); 12796#L705-1 assume !(0 == ~E_2~0); 12797#L710-1 assume !(0 == ~E_3~0); 12672#L715-1 assume !(0 == ~E_4~0); 12605#L720-1 assume !(0 == ~E_5~0); 12606#L725-1 assume !(0 == ~E_6~0); 12652#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12697#L320 assume !(1 == ~m_pc~0); 12826#L320-2 is_master_triggered_~__retres1~0#1 := 0; 12546#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12540#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12500#L825 assume !(0 != activate_threads_~tmp~1#1); 12501#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12505#L339 assume !(1 == ~t1_pc~0); 12506#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12475#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12331#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12332#L833 assume !(0 != activate_threads_~tmp___0~0#1); 12354#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12264#L358 assume 1 == ~t2_pc~0; 12265#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12789#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12711#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12655#L841 assume !(0 != activate_threads_~tmp___1~0#1); 12495#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12496#L377 assume !(1 == ~t3_pc~0); 12752#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12753#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12260#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12261#L849 assume !(0 != activate_threads_~tmp___2~0#1); 12504#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12432#L396 assume 1 == ~t4_pc~0; 12433#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12267#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12268#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12414#L857 assume !(0 != activate_threads_~tmp___3~0#1); 12399#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12400#L415 assume 1 == ~t5_pc~0; 12480#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12530#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12549#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12550#L865 assume !(0 != activate_threads_~tmp___4~0#1); 12308#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12309#L434 assume !(1 == ~t6_pc~0); 12635#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12636#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12702#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12703#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12518#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12519#L743 assume !(1 == ~M_E~0); 12390#L743-2 assume !(1 == ~T1_E~0); 12391#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12692#L753-1 assume !(1 == ~T3_E~0); 12693#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12811#L763-1 assume !(1 == ~T5_E~0); 12861#L768-1 assume !(1 == ~T6_E~0); 12512#L773-1 assume !(1 == ~E_1~0); 12513#L778-1 assume !(1 == ~E_2~0); 12490#L783-1 assume !(1 == ~E_3~0); 12491#L788-1 assume !(1 == ~E_4~0); 12769#L793-1 assume !(1 == ~E_5~0); 12716#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 12371#L803-1 assume { :end_inline_reset_delta_events } true; 12372#L1024-2 [2024-11-19 15:04:30,147 INFO L747 eck$LassoCheckResult]: Loop: 12372#L1024-2 assume !false; 12660#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13405#L645-1 assume !false; 12602#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12603#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12315#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12736#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12737#L556 assume !(0 != eval_~tmp~0#1); 12421#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12422#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13393#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13392#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13390#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13391#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13597#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13596#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13595#L695-3 assume !(0 == ~T6_E~0); 13594#L700-3 assume !(0 == ~E_1~0); 13593#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13592#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13591#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13590#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13589#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13588#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13587#L320-21 assume !(1 == ~m_pc~0); 13586#L320-23 is_master_triggered_~__retres1~0#1 := 0; 13585#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13584#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12871#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12847#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12427#L339-21 assume 1 == ~t1_pc~0; 12428#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12556#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12396#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12292#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12293#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12388#L358-21 assume !(1 == ~t2_pc~0); 12441#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 12373#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12374#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12604#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12401#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12402#L377-21 assume !(1 == ~t3_pc~0); 12784#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 12686#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12687#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12704#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12567#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12568#L396-21 assume 1 == ~t4_pc~0; 12717#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12590#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12646#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12274#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12275#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12543#L415-21 assume 1 == ~t5_pc~0; 12544#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12517#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12691#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12640#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 12609#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12610#L434-21 assume 1 == ~t6_pc~0; 12619#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12300#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12671#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12535#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12536#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12528#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12529#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12878#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12678#L753-3 assume !(1 == ~T3_E~0); 12625#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12558#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12559#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12864#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12456#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12457#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12683#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12890#L793-3 assume !(1 == ~E_5~0); 12891#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12719#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12720#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13472#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 13470#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 13467#L1043 assume !(0 == start_simulation_~tmp~3#1); 13464#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12679#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12464#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12329#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 12330#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12359#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12360#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 12639#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 12372#L1024-2 [2024-11-19 15:04:30,148 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:30,148 INFO L85 PathProgramCache]: Analyzing trace with hash -1227190400, now seen corresponding path program 1 times [2024-11-19 15:04:30,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:30,148 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128933755] [2024-11-19 15:04:30,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:30,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:30,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:30,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:30,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:30,207 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128933755] [2024-11-19 15:04:30,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2128933755] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:30,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:30,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:04:30,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804031504] [2024-11-19 15:04:30,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:30,208 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:30,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:30,208 INFO L85 PathProgramCache]: Analyzing trace with hash -361695640, now seen corresponding path program 1 times [2024-11-19 15:04:30,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:30,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425946993] [2024-11-19 15:04:30,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:30,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:30,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:30,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:30,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:30,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425946993] [2024-11-19 15:04:30,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425946993] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:30,270 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:30,270 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:30,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1925379185] [2024-11-19 15:04:30,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:30,270 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:30,270 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:30,271 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:30,271 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:30,271 INFO L87 Difference]: Start difference. First operand 1608 states and 2359 transitions. cyclomatic complexity: 754 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:30,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:30,360 INFO L93 Difference]: Finished difference Result 2943 states and 4289 transitions. [2024-11-19 15:04:30,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2943 states and 4289 transitions. [2024-11-19 15:04:30,379 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2835 [2024-11-19 15:04:30,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2943 states to 2943 states and 4289 transitions. [2024-11-19 15:04:30,395 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2943 [2024-11-19 15:04:30,398 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2943 [2024-11-19 15:04:30,398 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2943 states and 4289 transitions. [2024-11-19 15:04:30,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:30,403 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2943 states and 4289 transitions. [2024-11-19 15:04:30,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2943 states and 4289 transitions. [2024-11-19 15:04:30,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2943 to 2937. [2024-11-19 15:04:30,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2937 states, 2937 states have (on average 1.4582907728975145) internal successors, (4283), 2936 states have internal predecessors, (4283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:30,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2937 states to 2937 states and 4283 transitions. [2024-11-19 15:04:30,461 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2937 states and 4283 transitions. [2024-11-19 15:04:30,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:30,462 INFO L425 stractBuchiCegarLoop]: Abstraction has 2937 states and 4283 transitions. [2024-11-19 15:04:30,462 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-19 15:04:30,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2937 states and 4283 transitions. [2024-11-19 15:04:30,475 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2829 [2024-11-19 15:04:30,475 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:30,475 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:30,476 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:30,477 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:30,477 INFO L745 eck$LassoCheckResult]: Stem: 17139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 17140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 17284#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17285#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16796#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 16797#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17357#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17514#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16889#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16890#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17058#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16905#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16906#L670 assume !(0 == ~M_E~0); 17299#L670-2 assume !(0 == ~T1_E~0); 17245#L675-1 assume !(0 == ~T2_E~0); 17246#L680-1 assume !(0 == ~T3_E~0); 17356#L685-1 assume !(0 == ~T4_E~0); 17307#L690-1 assume !(0 == ~T5_E~0); 17308#L695-1 assume !(0 == ~T6_E~0); 17399#L700-1 assume !(0 == ~E_1~0); 17387#L705-1 assume !(0 == ~E_2~0); 17388#L710-1 assume !(0 == ~E_3~0); 17244#L715-1 assume !(0 == ~E_4~0); 17168#L720-1 assume !(0 == ~E_5~0); 17169#L725-1 assume !(0 == ~E_6~0); 17223#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17273#L320 assume !(1 == ~m_pc~0); 17419#L320-2 is_master_triggered_~__retres1~0#1 := 0; 17105#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17099#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17059#L825 assume !(0 != activate_threads_~tmp~1#1); 17060#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17064#L339 assume !(1 == ~t1_pc~0); 17065#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17033#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16887#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16888#L833 assume !(0 != activate_threads_~tmp___0~0#1); 16910#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16822#L358 assume !(1 == ~t2_pc~0); 16823#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17379#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17287#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17226#L841 assume !(0 != activate_threads_~tmp___1~0#1); 17054#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17055#L377 assume !(1 == ~t3_pc~0); 17334#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17335#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16818#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16819#L849 assume !(0 != activate_threads_~tmp___2~0#1); 17063#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16991#L396 assume 1 == ~t4_pc~0; 16992#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16824#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16825#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16974#L857 assume !(0 != activate_threads_~tmp___3~0#1); 16958#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16959#L415 assume 1 == ~t5_pc~0; 17038#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17094#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17109#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17110#L865 assume !(0 != activate_threads_~tmp___4~0#1); 16864#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16865#L434 assume !(1 == ~t6_pc~0); 17203#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17204#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17278#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17279#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17078#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17079#L743 assume !(1 == ~M_E~0); 16947#L743-2 assume !(1 == ~T1_E~0); 16948#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17480#L753-1 assume !(1 == ~T3_E~0); 19732#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19731#L763-1 assume !(1 == ~T5_E~0); 19730#L768-1 assume !(1 == ~T6_E~0); 19729#L773-1 assume !(1 == ~E_1~0); 17074#L778-1 assume !(1 == ~E_2~0); 19728#L783-1 assume !(1 == ~E_3~0); 19727#L788-1 assume !(1 == ~E_4~0); 19726#L793-1 assume !(1 == ~E_5~0); 19725#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 19303#L803-1 assume { :end_inline_reset_delta_events } true; 19301#L1024-2 [2024-11-19 15:04:30,477 INFO L747 eck$LassoCheckResult]: Loop: 19301#L1024-2 assume !false; 19300#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19296#L645-1 assume !false; 19295#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 17520#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 16871#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17314#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17315#L556 assume !(0 != eval_~tmp~0#1); 17545#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19621#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19620#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19619#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19618#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19617#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19616#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19615#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19614#L695-3 assume !(0 == ~T6_E~0); 19613#L700-3 assume !(0 == ~E_1~0); 19612#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19611#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19610#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19609#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19608#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19607#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19606#L320-21 assume !(1 == ~m_pc~0); 19605#L320-23 is_master_triggered_~__retres1~0#1 := 0; 19604#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19603#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19602#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19601#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19600#L339-21 assume 1 == ~t1_pc~0; 19598#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19597#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19596#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19595#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19594#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19593#L358-21 assume !(1 == ~t2_pc~0); 19592#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 19591#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19590#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19589#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19588#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19587#L377-21 assume 1 == ~t3_pc~0; 19585#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19584#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19583#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19582#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19581#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19580#L396-21 assume !(1 == ~t4_pc~0); 19578#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 19577#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19576#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19575#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19574#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19573#L415-21 assume 1 == ~t5_pc~0; 19571#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19570#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19569#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19568#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 19567#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19566#L434-21 assume 1 == ~t6_pc~0; 19564#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19563#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19562#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19561#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19560#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19559#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19558#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19557#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18863#L753-3 assume !(1 == ~T3_E~0); 19556#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19555#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19554#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19553#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18857#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19552#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19551#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19550#L793-3 assume !(1 == ~E_5~0); 19549#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19548#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 19547#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 19540#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 19539#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 19537#L1043 assume !(0 == start_simulation_~tmp~3#1); 19535#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 19534#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 17339#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17340#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 17217#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17218#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17452#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 17453#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 19301#L1024-2 [2024-11-19 15:04:30,478 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:30,478 INFO L85 PathProgramCache]: Analyzing trace with hash 1792674207, now seen corresponding path program 1 times [2024-11-19 15:04:30,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:30,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85252843] [2024-11-19 15:04:30,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:30,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:30,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:30,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:30,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:30,530 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [85252843] [2024-11-19 15:04:30,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [85252843] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:30,530 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:30,530 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:04:30,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662766731] [2024-11-19 15:04:30,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:30,533 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:30,533 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:30,534 INFO L85 PathProgramCache]: Analyzing trace with hash 93538728, now seen corresponding path program 2 times [2024-11-19 15:04:30,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:30,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418449613] [2024-11-19 15:04:30,534 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:04:30,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:30,545 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:04:30,546 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:04:30,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:30,569 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:30,569 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [418449613] [2024-11-19 15:04:30,570 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [418449613] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:30,570 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:30,570 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:30,570 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1614055343] [2024-11-19 15:04:30,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:30,570 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:30,570 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:30,571 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:30,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:30,571 INFO L87 Difference]: Start difference. First operand 2937 states and 4283 transitions. cyclomatic complexity: 1352 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:30,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:30,662 INFO L93 Difference]: Finished difference Result 5435 states and 7885 transitions. [2024-11-19 15:04:30,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5435 states and 7885 transitions. [2024-11-19 15:04:30,691 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5306 [2024-11-19 15:04:30,720 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5435 states to 5435 states and 7885 transitions. [2024-11-19 15:04:30,720 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5435 [2024-11-19 15:04:30,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5435 [2024-11-19 15:04:30,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5435 states and 7885 transitions. [2024-11-19 15:04:30,735 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:30,736 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5435 states and 7885 transitions. [2024-11-19 15:04:30,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5435 states and 7885 transitions. [2024-11-19 15:04:30,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5435 to 5423. [2024-11-19 15:04:30,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5423 states, 5423 states have (on average 1.4517794578646506) internal successors, (7873), 5422 states have internal predecessors, (7873), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:30,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5423 states to 5423 states and 7873 transitions. [2024-11-19 15:04:30,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5423 states and 7873 transitions. [2024-11-19 15:04:30,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:30,902 INFO L425 stractBuchiCegarLoop]: Abstraction has 5423 states and 7873 transitions. [2024-11-19 15:04:30,902 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-19 15:04:30,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5423 states and 7873 transitions. [2024-11-19 15:04:30,928 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5294 [2024-11-19 15:04:30,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:30,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:30,930 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:30,930 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:30,930 INFO L745 eck$LassoCheckResult]: Stem: 25516#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 25517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 25649#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25650#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25175#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 25176#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25714#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25864#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25270#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25271#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25436#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25286#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25287#L670 assume !(0 == ~M_E~0); 25663#L670-2 assume !(0 == ~T1_E~0); 25614#L675-1 assume !(0 == ~T2_E~0); 25615#L680-1 assume !(0 == ~T3_E~0); 25713#L685-1 assume !(0 == ~T4_E~0); 25670#L690-1 assume !(0 == ~T5_E~0); 25671#L695-1 assume !(0 == ~T6_E~0); 25756#L700-1 assume !(0 == ~E_1~0); 25744#L705-1 assume !(0 == ~E_2~0); 25745#L710-1 assume !(0 == ~E_3~0); 25613#L715-1 assume !(0 == ~E_4~0); 25541#L720-1 assume !(0 == ~E_5~0); 25542#L725-1 assume !(0 == ~E_6~0); 25592#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25638#L320 assume !(1 == ~m_pc~0); 25777#L320-2 is_master_triggered_~__retres1~0#1 := 0; 25484#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25478#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25437#L825 assume !(0 != activate_threads_~tmp~1#1); 25438#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25442#L339 assume !(1 == ~t1_pc~0); 25443#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25412#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25268#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25269#L833 assume !(0 != activate_threads_~tmp___0~0#1); 25291#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25201#L358 assume !(1 == ~t2_pc~0); 25202#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25736#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25652#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25595#L841 assume !(0 != activate_threads_~tmp___1~0#1); 25432#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25433#L377 assume !(1 == ~t3_pc~0); 25693#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25694#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25197#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25198#L849 assume !(0 != activate_threads_~tmp___2~0#1); 25441#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25371#L396 assume !(1 == ~t4_pc~0); 25372#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25203#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25353#L857 assume !(0 != activate_threads_~tmp___3~0#1); 25337#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25338#L415 assume 1 == ~t5_pc~0; 25417#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25473#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25488#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25489#L865 assume !(0 != activate_threads_~tmp___4~0#1); 25245#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25246#L434 assume !(1 == ~t6_pc~0); 25573#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25574#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25643#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25644#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25457#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25458#L743 assume !(1 == ~M_E~0); 25328#L743-2 assume !(1 == ~T1_E~0); 25329#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25633#L753-1 assume !(1 == ~T3_E~0); 25634#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25821#L763-1 assume !(1 == ~T5_E~0); 25822#L768-1 assume !(1 == ~T6_E~0); 25451#L773-1 assume !(1 == ~E_1~0); 25452#L778-1 assume !(1 == ~E_2~0); 25427#L783-1 assume !(1 == ~E_3~0); 25428#L788-1 assume !(1 == ~E_4~0); 29738#L793-1 assume !(1 == ~E_5~0); 29736#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 25308#L803-1 assume { :end_inline_reset_delta_events } true; 25309#L1024-2 [2024-11-19 15:04:30,930 INFO L747 eck$LassoCheckResult]: Loop: 25309#L1024-2 assume !false; 27863#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27860#L645-1 assume !false; 27853#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 27854#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 27840#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 27835#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27705#L556 assume !(0 != eval_~tmp~0#1); 25360#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25361#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25298#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25299#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25479#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25480#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25706#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25707#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25865#L695-3 assume !(0 == ~T6_E~0); 25717#L700-3 assume !(0 == ~E_1~0); 25718#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25351#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25352#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25596#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25597#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25672#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25453#L320-21 assume !(1 == ~m_pc~0); 25454#L320-23 is_master_triggered_~__retres1~0#1 := 0; 25594#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25398#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25399#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25802#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25366#L339-21 assume 1 == ~t1_pc~0; 25367#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25495#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25334#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25229#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25230#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25325#L358-21 assume !(1 == ~t2_pc~0); 25379#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 25310#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25311#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25540#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25765#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30146#L377-21 assume 1 == ~t3_pc~0; 30144#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30143#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30142#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30141#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30140#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30139#L396-21 assume !(1 == ~t4_pc~0); 30138#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 30137#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30136#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30135#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30134#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30133#L415-21 assume 1 == ~t5_pc~0; 30131#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30130#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30129#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30128#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 30127#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30126#L434-21 assume 1 == ~t6_pc~0; 30124#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30123#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25612#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25474#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25475#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25467#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25468#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25838#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25619#L753-3 assume !(1 == ~T3_E~0); 25559#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25497#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25498#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25824#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25393#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25394#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25624#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25851#L793-3 assume !(1 == ~E_5~0); 25852#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25661#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 25662#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29560#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29847#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 29843#L1043 assume !(0 == start_simulation_~tmp~3#1); 28520#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 28521#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29794#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29793#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 29792#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29791#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29790#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 27871#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 25309#L1024-2 [2024-11-19 15:04:30,931 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:30,931 INFO L85 PathProgramCache]: Analyzing trace with hash -1583318466, now seen corresponding path program 1 times [2024-11-19 15:04:30,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:30,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892796949] [2024-11-19 15:04:30,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:30,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:30,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:30,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:30,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:30,979 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892796949] [2024-11-19 15:04:30,979 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [892796949] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:30,979 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:30,979 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:04:30,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755477037] [2024-11-19 15:04:30,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:30,980 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:30,980 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:30,980 INFO L85 PathProgramCache]: Analyzing trace with hash 93538728, now seen corresponding path program 3 times [2024-11-19 15:04:30,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:30,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442662334] [2024-11-19 15:04:30,981 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 15:04:30,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:30,994 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 15:04:30,994 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:04:31,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:31,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:31,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1442662334] [2024-11-19 15:04:31,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1442662334] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:31,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:31,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:31,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1519002126] [2024-11-19 15:04:31,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:31,023 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:31,023 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:31,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:31,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:31,024 INFO L87 Difference]: Start difference. First operand 5423 states and 7873 transitions. cyclomatic complexity: 2462 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:31,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:31,124 INFO L93 Difference]: Finished difference Result 10080 states and 14576 transitions. [2024-11-19 15:04:31,124 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10080 states and 14576 transitions. [2024-11-19 15:04:31,176 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 9896 [2024-11-19 15:04:31,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10080 states to 10080 states and 14576 transitions. [2024-11-19 15:04:31,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10080 [2024-11-19 15:04:31,246 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10080 [2024-11-19 15:04:31,246 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10080 states and 14576 transitions. [2024-11-19 15:04:31,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:31,263 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10080 states and 14576 transitions. [2024-11-19 15:04:31,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10080 states and 14576 transitions. [2024-11-19 15:04:31,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10080 to 10056. [2024-11-19 15:04:31,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10056 states, 10056 states have (on average 1.447096260938743) internal successors, (14552), 10055 states have internal predecessors, (14552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:31,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10056 states to 10056 states and 14552 transitions. [2024-11-19 15:04:31,602 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10056 states and 14552 transitions. [2024-11-19 15:04:31,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:31,603 INFO L425 stractBuchiCegarLoop]: Abstraction has 10056 states and 14552 transitions. [2024-11-19 15:04:31,603 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-19 15:04:31,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10056 states and 14552 transitions. [2024-11-19 15:04:31,642 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 9872 [2024-11-19 15:04:31,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:31,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:31,644 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:31,644 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:31,644 INFO L745 eck$LassoCheckResult]: Stem: 41027#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 41028#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 41166#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41167#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40685#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 40686#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41239#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41421#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40779#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40780#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40945#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40794#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40795#L670 assume !(0 == ~M_E~0); 41183#L670-2 assume !(0 == ~T1_E~0); 41130#L675-1 assume !(0 == ~T2_E~0); 41131#L680-1 assume !(0 == ~T3_E~0); 41237#L685-1 assume !(0 == ~T4_E~0); 41191#L690-1 assume !(0 == ~T5_E~0); 41192#L695-1 assume !(0 == ~T6_E~0); 41287#L700-1 assume !(0 == ~E_1~0); 41272#L705-1 assume !(0 == ~E_2~0); 41273#L710-1 assume !(0 == ~E_3~0); 41129#L715-1 assume !(0 == ~E_4~0); 41053#L720-1 assume !(0 == ~E_5~0); 41054#L725-1 assume !(0 == ~E_6~0); 41107#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41153#L320 assume !(1 == ~m_pc~0); 41308#L320-2 is_master_triggered_~__retres1~0#1 := 0; 40992#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40986#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40946#L825 assume !(0 != activate_threads_~tmp~1#1); 40947#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40955#L339 assume !(1 == ~t1_pc~0); 40956#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40921#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40775#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40776#L833 assume !(0 != activate_threads_~tmp___0~0#1); 40798#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40711#L358 assume !(1 == ~t2_pc~0); 40712#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41264#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41169#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41111#L841 assume !(0 != activate_threads_~tmp___1~0#1); 40941#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40942#L377 assume !(1 == ~t3_pc~0); 41215#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41216#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40709#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40710#L849 assume !(0 != activate_threads_~tmp___2~0#1); 40950#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40878#L396 assume !(1 == ~t4_pc~0); 40879#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40713#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40714#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40858#L857 assume !(0 != activate_threads_~tmp___3~0#1); 40843#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40844#L415 assume !(1 == ~t5_pc~0); 40928#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40981#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40999#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41000#L865 assume !(0 != activate_threads_~tmp___4~0#1); 40752#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40753#L434 assume !(1 == ~t6_pc~0); 41085#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41086#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41159#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41160#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40965#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40966#L743 assume !(1 == ~M_E~0); 40834#L743-2 assume !(1 == ~T1_E~0); 40835#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41378#L753-1 assume !(1 == ~T3_E~0); 41290#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41291#L763-1 assume !(1 == ~T5_E~0); 41419#L768-1 assume !(1 == ~T6_E~0); 41420#L773-1 assume !(1 == ~E_1~0); 40963#L778-1 assume !(1 == ~E_2~0); 41451#L783-1 assume !(1 == ~E_3~0); 41441#L788-1 assume !(1 == ~E_4~0); 41442#L793-1 assume !(1 == ~E_5~0); 41175#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 41176#L803-1 assume { :end_inline_reset_delta_events } true; 46683#L1024-2 [2024-11-19 15:04:31,645 INFO L747 eck$LassoCheckResult]: Loop: 46683#L1024-2 assume !false; 46674#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46668#L645-1 assume !false; 46664#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 46661#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 46652#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 46647#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46643#L556 assume !(0 != eval_~tmp~0#1); 46644#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47159#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47156#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47153#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47150#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47147#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47144#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47141#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47137#L695-3 assume !(0 == ~T6_E~0); 47134#L700-3 assume !(0 == ~E_1~0); 47131#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47128#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47125#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47122#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47119#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47116#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47113#L320-21 assume !(1 == ~m_pc~0); 47110#L320-23 is_master_triggered_~__retres1~0#1 := 0; 47107#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47104#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 47100#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47097#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47093#L339-21 assume 1 == ~t1_pc~0; 47088#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47083#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47079#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 47075#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47071#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47066#L358-21 assume !(1 == ~t2_pc~0); 47060#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 47055#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47051#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 47046#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47041#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47036#L377-21 assume 1 == ~t3_pc~0; 47030#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47024#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47019#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 47013#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47007#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47002#L396-21 assume !(1 == ~t4_pc~0); 46996#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 46991#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46986#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46981#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46977#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46972#L415-21 assume !(1 == ~t5_pc~0); 46967#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 46962#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46958#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46953#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 46947#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46942#L434-21 assume 1 == ~t6_pc~0; 46936#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46929#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46923#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46917#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46910#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46904#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46897#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46891#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46883#L753-3 assume !(1 == ~T3_E~0); 46878#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46873#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46868#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46863#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46854#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46849#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46844#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46837#L793-3 assume !(1 == ~E_5~0); 46832#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46788#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 46787#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 46777#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 46773#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 46768#L1043 assume !(0 == start_simulation_~tmp~3#1); 46765#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 46728#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 46716#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 46710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 46709#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46708#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46699#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 46691#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 46683#L1024-2 [2024-11-19 15:04:31,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:31,645 INFO L85 PathProgramCache]: Analyzing trace with hash -944533987, now seen corresponding path program 1 times [2024-11-19 15:04:31,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:31,648 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182673201] [2024-11-19 15:04:31,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:31,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:31,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:31,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:31,712 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:31,712 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [182673201] [2024-11-19 15:04:31,712 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [182673201] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:31,712 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:31,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:04:31,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400105270] [2024-11-19 15:04:31,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:31,715 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:31,715 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:31,715 INFO L85 PathProgramCache]: Analyzing trace with hash 616859399, now seen corresponding path program 1 times [2024-11-19 15:04:31,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:31,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020078904] [2024-11-19 15:04:31,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:31,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:31,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:31,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:31,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:31,751 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020078904] [2024-11-19 15:04:31,751 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1020078904] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:31,751 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:31,751 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:31,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382512235] [2024-11-19 15:04:31,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:31,752 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:31,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:31,752 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:04:31,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:04:31,753 INFO L87 Difference]: Start difference. First operand 10056 states and 14552 transitions. cyclomatic complexity: 4520 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:32,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:32,026 INFO L93 Difference]: Finished difference Result 10479 states and 14975 transitions. [2024-11-19 15:04:32,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10479 states and 14975 transitions. [2024-11-19 15:04:32,077 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 10292 [2024-11-19 15:04:32,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10479 states to 10479 states and 14975 transitions. [2024-11-19 15:04:32,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10479 [2024-11-19 15:04:32,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10479 [2024-11-19 15:04:32,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10479 states and 14975 transitions. [2024-11-19 15:04:32,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:32,141 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10479 states and 14975 transitions. [2024-11-19 15:04:32,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10479 states and 14975 transitions. [2024-11-19 15:04:32,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10479 to 10479. [2024-11-19 15:04:32,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10479 states, 10479 states have (on average 1.4290485733371505) internal successors, (14975), 10478 states have internal predecessors, (14975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:32,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10479 states to 10479 states and 14975 transitions. [2024-11-19 15:04:32,408 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10479 states and 14975 transitions. [2024-11-19 15:04:32,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:04:32,409 INFO L425 stractBuchiCegarLoop]: Abstraction has 10479 states and 14975 transitions. [2024-11-19 15:04:32,409 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-19 15:04:32,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10479 states and 14975 transitions. [2024-11-19 15:04:32,446 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 10292 [2024-11-19 15:04:32,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:32,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:32,509 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:32,509 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:32,509 INFO L745 eck$LassoCheckResult]: Stem: 61573#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 61574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 61708#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61709#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61229#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 61230#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61782#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61952#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61322#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61323#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 61492#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 61339#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61340#L670 assume !(0 == ~M_E~0); 61724#L670-2 assume !(0 == ~T1_E~0); 61673#L675-1 assume !(0 == ~T2_E~0); 61674#L680-1 assume !(0 == ~T3_E~0); 61781#L685-1 assume !(0 == ~T4_E~0); 61731#L690-1 assume !(0 == ~T5_E~0); 61732#L695-1 assume !(0 == ~T6_E~0); 61830#L700-1 assume !(0 == ~E_1~0); 61817#L705-1 assume !(0 == ~E_2~0); 61818#L710-1 assume !(0 == ~E_3~0); 61672#L715-1 assume !(0 == ~E_4~0); 61601#L720-1 assume !(0 == ~E_5~0); 61602#L725-1 assume !(0 == ~E_6~0); 61652#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61697#L320 assume !(1 == ~m_pc~0); 61849#L320-2 is_master_triggered_~__retres1~0#1 := 0; 61538#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61532#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 61493#L825 assume !(0 != activate_threads_~tmp~1#1); 61494#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61498#L339 assume !(1 == ~t1_pc~0); 61499#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61469#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61320#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61321#L833 assume !(0 != activate_threads_~tmp___0~0#1); 61345#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61255#L358 assume !(1 == ~t2_pc~0); 61256#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61808#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61711#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 61655#L841 assume !(0 != activate_threads_~tmp___1~0#1); 61488#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61489#L377 assume !(1 == ~t3_pc~0); 61759#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 61760#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61251#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 61252#L849 assume !(0 != activate_threads_~tmp___2~0#1); 61497#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61426#L396 assume !(1 == ~t4_pc~0); 61427#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61257#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61258#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 61409#L857 assume !(0 != activate_threads_~tmp___3~0#1); 61394#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61395#L415 assume !(1 == ~t5_pc~0); 61474#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 61523#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61541#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 61542#L865 assume !(0 != activate_threads_~tmp___4~0#1); 61297#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61298#L434 assume !(1 == ~t6_pc~0); 61633#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 61634#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61702#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61703#L873 assume !(0 != activate_threads_~tmp___5~0#1); 61511#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61512#L743 assume !(1 == ~M_E~0); 61383#L743-2 assume !(1 == ~T1_E~0); 61384#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61693#L753-1 assume !(1 == ~T3_E~0); 61694#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61833#L763-1 assume !(1 == ~T5_E~0); 61890#L768-1 assume !(1 == ~T6_E~0); 61505#L773-1 assume !(1 == ~E_1~0); 61506#L778-1 assume !(1 == ~E_2~0); 61483#L783-1 assume !(1 == ~E_3~0); 61484#L788-1 assume !(1 == ~E_4~0); 61778#L793-1 assume !(1 == ~E_5~0); 61719#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 61720#L803-1 assume { :end_inline_reset_delta_events } true; 66370#L1024-2 [2024-11-19 15:04:32,517 INFO L747 eck$LassoCheckResult]: Loop: 66370#L1024-2 assume !false; 66369#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66368#L645-1 assume !false; 66367#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 65784#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 65778#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 65760#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 65761#L556 assume !(0 != eval_~tmp~0#1); 66360#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66358#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66356#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 66354#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 66351#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66352#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 66346#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66347#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66340#L695-3 assume !(0 == ~T6_E~0); 66341#L700-3 assume !(0 == ~E_1~0); 66334#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66335#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66328#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 66329#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66321#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 66322#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66315#L320-21 assume !(1 == ~m_pc~0); 66316#L320-23 is_master_triggered_~__retres1~0#1 := 0; 66309#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66310#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 66303#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66304#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66296#L339-21 assume 1 == ~t1_pc~0; 66297#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 66289#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66290#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 66280#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66281#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66274#L358-21 assume !(1 == ~t2_pc~0); 66275#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 66268#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66269#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66262#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66263#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66255#L377-21 assume !(1 == ~t3_pc~0); 66257#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 66248#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66249#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66242#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66243#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66236#L396-21 assume !(1 == ~t4_pc~0); 66237#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 66230#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66231#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66222#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66223#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66216#L415-21 assume !(1 == ~t5_pc~0); 66217#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 66209#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66210#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 66203#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 66204#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66195#L434-21 assume !(1 == ~t6_pc~0); 66197#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 66187#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66188#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 66181#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 66180#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66173#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 66174#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66167#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66168#L753-3 assume !(1 == ~T3_E~0); 66162#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66163#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66158#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66159#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 66154#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 66155#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66150#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66151#L793-3 assume !(1 == ~E_5~0); 66145#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 66146#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 66140#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 66134#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 66127#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 66128#L1043 assume !(0 == start_simulation_~tmp~3#1); 66384#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 66383#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 66376#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 66375#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 66374#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66373#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66372#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 66371#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 66370#L1024-2 [2024-11-19 15:04:32,521 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:32,522 INFO L85 PathProgramCache]: Analyzing trace with hash -1965602341, now seen corresponding path program 1 times [2024-11-19 15:04:32,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:32,522 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166159114] [2024-11-19 15:04:32,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:32,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:32,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:32,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:32,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:32,669 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1166159114] [2024-11-19 15:04:32,669 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1166159114] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:32,671 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:32,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:04:32,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375510269] [2024-11-19 15:04:32,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:32,672 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:32,672 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:32,672 INFO L85 PathProgramCache]: Analyzing trace with hash -703976125, now seen corresponding path program 1 times [2024-11-19 15:04:32,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:32,673 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [874584530] [2024-11-19 15:04:32,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:32,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:32,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:32,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:32,718 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:32,718 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [874584530] [2024-11-19 15:04:32,719 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [874584530] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:32,719 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:32,719 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:32,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442728166] [2024-11-19 15:04:32,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:32,720 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:32,720 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:32,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:32,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:32,722 INFO L87 Difference]: Start difference. First operand 10479 states and 14975 transitions. cyclomatic complexity: 4520 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:32,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:32,787 INFO L93 Difference]: Finished difference Result 10474 states and 14900 transitions. [2024-11-19 15:04:32,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10474 states and 14900 transitions. [2024-11-19 15:04:32,843 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 10292 [2024-11-19 15:04:32,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10474 states to 10474 states and 14900 transitions. [2024-11-19 15:04:32,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10474 [2024-11-19 15:04:32,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10474 [2024-11-19 15:04:32,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10474 states and 14900 transitions. [2024-11-19 15:04:32,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:32,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10474 states and 14900 transitions. [2024-11-19 15:04:32,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10474 states and 14900 transitions. [2024-11-19 15:04:33,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10474 to 7192. [2024-11-19 15:04:33,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7192 states, 7192 states have (on average 1.4233870967741935) internal successors, (10237), 7191 states have internal predecessors, (10237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:33,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7192 states to 7192 states and 10237 transitions. [2024-11-19 15:04:33,074 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7192 states and 10237 transitions. [2024-11-19 15:04:33,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:33,076 INFO L425 stractBuchiCegarLoop]: Abstraction has 7192 states and 10237 transitions. [2024-11-19 15:04:33,076 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-19 15:04:33,076 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7192 states and 10237 transitions. [2024-11-19 15:04:33,102 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7040 [2024-11-19 15:04:33,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:33,102 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:33,103 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:33,103 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:33,104 INFO L745 eck$LassoCheckResult]: Stem: 82526#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 82527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 82664#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82665#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82189#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 82190#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82728#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82882#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82280#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82281#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82444#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82296#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82297#L670 assume !(0 == ~M_E~0); 82676#L670-2 assume !(0 == ~T1_E~0); 82627#L675-1 assume !(0 == ~T2_E~0); 82628#L680-1 assume !(0 == ~T3_E~0); 82727#L685-1 assume !(0 == ~T4_E~0); 82683#L690-1 assume !(0 == ~T5_E~0); 82684#L695-1 assume !(0 == ~T6_E~0); 82773#L700-1 assume !(0 == ~E_1~0); 82755#L705-1 assume !(0 == ~E_2~0); 82756#L710-1 assume !(0 == ~E_3~0); 82626#L715-1 assume !(0 == ~E_4~0); 82553#L720-1 assume !(0 == ~E_5~0); 82554#L725-1 assume !(0 == ~E_6~0); 82606#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82653#L320 assume !(1 == ~m_pc~0); 82794#L320-2 is_master_triggered_~__retres1~0#1 := 0; 82491#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82484#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 82445#L825 assume !(0 != activate_threads_~tmp~1#1); 82446#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82450#L339 assume !(1 == ~t1_pc~0); 82451#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82421#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82278#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 82279#L833 assume !(0 != activate_threads_~tmp___0~0#1); 82301#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82215#L358 assume !(1 == ~t2_pc~0); 82216#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 82746#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82667#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 82609#L841 assume !(0 != activate_threads_~tmp___1~0#1); 82440#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82441#L377 assume !(1 == ~t3_pc~0); 82708#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82709#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82211#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82212#L849 assume !(0 != activate_threads_~tmp___2~0#1); 82449#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82379#L396 assume !(1 == ~t4_pc~0); 82380#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 82217#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82218#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82362#L857 assume !(0 != activate_threads_~tmp___3~0#1); 82346#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82347#L415 assume !(1 == ~t5_pc~0); 82426#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 82477#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82495#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82496#L865 assume !(0 != activate_threads_~tmp___4~0#1); 82255#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82256#L434 assume !(1 == ~t6_pc~0); 82586#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 82587#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82658#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82659#L873 assume !(0 != activate_threads_~tmp___5~0#1); 82463#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82464#L743 assume !(1 == ~M_E~0); 82337#L743-2 assume !(1 == ~T1_E~0); 82338#L748-1 assume !(1 == ~T2_E~0); 82649#L753-1 assume !(1 == ~T3_E~0); 82650#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82775#L763-1 assume !(1 == ~T5_E~0); 82833#L768-1 assume !(1 == ~T6_E~0); 82457#L773-1 assume !(1 == ~E_1~0); 82458#L778-1 assume !(1 == ~E_2~0); 82435#L783-1 assume !(1 == ~E_3~0); 82436#L788-1 assume !(1 == ~E_4~0); 82725#L793-1 assume !(1 == ~E_5~0); 82673#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 82318#L803-1 assume { :end_inline_reset_delta_events } true; 82319#L1024-2 [2024-11-19 15:04:33,104 INFO L747 eck$LassoCheckResult]: Loop: 82319#L1024-2 assume !false; 88769#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 88766#L645-1 assume !false; 88765#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 88763#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 88307#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 86684#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 86678#L556 assume !(0 != eval_~tmp~0#1); 86679#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88940#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 88939#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 88938#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 88937#L675-3 assume !(0 == ~T2_E~0); 88936#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88935#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 88934#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88933#L695-3 assume !(0 == ~T6_E~0); 88932#L700-3 assume !(0 == ~E_1~0); 88931#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88930#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88929#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 88928#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88927#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 88925#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88924#L320-21 assume !(1 == ~m_pc~0); 88923#L320-23 is_master_triggered_~__retres1~0#1 := 0; 88922#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88921#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 88920#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88918#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88916#L339-21 assume 1 == ~t1_pc~0; 88913#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 88911#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88909#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88907#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88905#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88904#L358-21 assume !(1 == ~t2_pc~0); 88903#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 88901#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88899#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88896#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88894#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88892#L377-21 assume 1 == ~t3_pc~0; 88889#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 88887#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88885#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 88883#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88881#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88879#L396-21 assume !(1 == ~t4_pc~0); 88877#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 88875#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88873#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88870#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88868#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88866#L415-21 assume !(1 == ~t5_pc~0); 88864#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 88862#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88860#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88858#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 88856#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88854#L434-21 assume 1 == ~t6_pc~0; 88851#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 88849#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88847#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 88835#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 88833#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88831#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 88829#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88826#L748-3 assume !(1 == ~T2_E~0); 88824#L753-3 assume !(1 == ~T3_E~0); 88822#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88820#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 88818#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 88816#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 88814#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 88812#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 88810#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 88808#L793-3 assume !(1 == ~E_5~0); 88806#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 88804#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 88802#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 88794#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 88792#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 88790#L1043 assume !(0 == start_simulation_~tmp~3#1); 88788#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 88787#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 88780#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 88779#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 88777#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88775#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88773#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 88772#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 82319#L1024-2 [2024-11-19 15:04:33,105 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:33,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1707436903, now seen corresponding path program 1 times [2024-11-19 15:04:33,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:33,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904706264] [2024-11-19 15:04:33,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:33,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:33,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:33,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:33,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:33,342 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904706264] [2024-11-19 15:04:33,342 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904706264] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:33,343 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:33,343 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:33,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [525742797] [2024-11-19 15:04:33,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:33,343 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:33,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:33,344 INFO L85 PathProgramCache]: Analyzing trace with hash -659656573, now seen corresponding path program 1 times [2024-11-19 15:04:33,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:33,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702225004] [2024-11-19 15:04:33,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:33,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:33,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:33,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:33,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:33,386 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702225004] [2024-11-19 15:04:33,386 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702225004] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:33,386 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:33,386 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:33,386 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811266194] [2024-11-19 15:04:33,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:33,387 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:33,387 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:33,387 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:04:33,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:04:33,388 INFO L87 Difference]: Start difference. First operand 7192 states and 10237 transitions. cyclomatic complexity: 3061 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:33,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:33,507 INFO L93 Difference]: Finished difference Result 15391 states and 21859 transitions. [2024-11-19 15:04:33,507 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15391 states and 21859 transitions. [2024-11-19 15:04:33,580 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 15104 [2024-11-19 15:04:33,637 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15391 states to 15391 states and 21859 transitions. [2024-11-19 15:04:33,637 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15391 [2024-11-19 15:04:33,656 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15391 [2024-11-19 15:04:33,657 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15391 states and 21859 transitions. [2024-11-19 15:04:33,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:33,679 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15391 states and 21859 transitions. [2024-11-19 15:04:33,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15391 states and 21859 transitions. [2024-11-19 15:04:33,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15391 to 8278. [2024-11-19 15:04:33,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8278 states, 8278 states have (on average 1.42087460739309) internal successors, (11762), 8277 states have internal predecessors, (11762), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:33,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8278 states to 8278 states and 11762 transitions. [2024-11-19 15:04:33,829 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8278 states and 11762 transitions. [2024-11-19 15:04:33,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:04:33,830 INFO L425 stractBuchiCegarLoop]: Abstraction has 8278 states and 11762 transitions. [2024-11-19 15:04:33,830 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-19 15:04:33,830 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8278 states and 11762 transitions. [2024-11-19 15:04:33,855 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8064 [2024-11-19 15:04:33,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:33,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:33,857 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:33,857 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:33,857 INFO L745 eck$LassoCheckResult]: Stem: 105124#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 105125#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 105262#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 105263#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 104782#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 104783#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105339#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105494#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104877#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104878#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105040#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 104892#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 104893#L670 assume !(0 == ~M_E~0); 105275#L670-2 assume !(0 == ~T1_E~0); 105220#L675-1 assume !(0 == ~T2_E~0); 105221#L680-1 assume !(0 == ~T3_E~0); 105337#L685-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 105420#L690-1 assume !(0 == ~T5_E~0); 105519#L695-1 assume !(0 == ~T6_E~0); 105520#L700-1 assume !(0 == ~E_1~0); 105370#L705-1 assume !(0 == ~E_2~0); 105371#L710-1 assume !(0 == ~E_3~0); 105539#L715-1 assume !(0 == ~E_4~0); 105149#L720-1 assume !(0 == ~E_5~0); 105150#L725-1 assume !(0 == ~E_6~0); 105247#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105248#L320 assume !(1 == ~m_pc~0); 105502#L320-2 is_master_triggered_~__retres1~0#1 := 0; 105503#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105081#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 105082#L825 assume !(0 != activate_threads_~tmp~1#1); 105430#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105431#L339 assume !(1 == ~t1_pc~0); 105242#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105016#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105017#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 104896#L833 assume !(0 != activate_threads_~tmp___0~0#1); 104897#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104808#L358 assume !(1 == ~t2_pc~0); 104809#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 105537#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105265#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105266#L841 assume !(0 != activate_threads_~tmp___1~0#1); 105036#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105037#L377 assume !(1 == ~t3_pc~0); 105307#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 105308#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104806#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 104807#L849 assume !(0 != activate_threads_~tmp___2~0#1); 105332#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105333#L396 assume !(1 == ~t4_pc~0); 105536#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 104810#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104811#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 105235#L857 assume !(0 != activate_threads_~tmp___3~0#1); 105236#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 105535#L415 assume !(1 == ~t5_pc~0); 105075#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 105076#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 105093#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 105094#L865 assume !(0 != activate_threads_~tmp___4~0#1); 105534#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 105309#L434 assume !(1 == ~t6_pc~0); 105310#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 105531#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 105532#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 105349#L873 assume !(0 != activate_threads_~tmp___5~0#1); 105350#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105480#L743 assume !(1 == ~M_E~0); 105481#L743-2 assume !(1 == ~T1_E~0); 105533#L748-1 assume !(1 == ~T2_E~0); 105243#L753-1 assume !(1 == ~T3_E~0); 105244#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 105386#L763-1 assume !(1 == ~T5_E~0); 105444#L768-1 assume !(1 == ~T6_E~0); 105057#L773-1 assume !(1 == ~E_1~0); 105058#L778-1 assume !(1 == ~E_2~0); 105031#L783-1 assume !(1 == ~E_3~0); 105032#L788-1 assume !(1 == ~E_4~0); 105334#L793-1 assume !(1 == ~E_5~0); 105271#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 104916#L803-1 assume { :end_inline_reset_delta_events } true; 104917#L1024-2 [2024-11-19 15:04:33,858 INFO L747 eck$LassoCheckResult]: Loop: 104917#L1024-2 assume !false; 109950#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 109943#L645-1 assume !false; 109941#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 107949#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 107937#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 107928#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 107918#L556 assume !(0 != eval_~tmp~0#1); 107919#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 110181#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 110180#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 110179#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 110178#L675-3 assume !(0 == ~T2_E~0); 110176#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 110173#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 110172#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 110171#L695-3 assume !(0 == ~T6_E~0); 110170#L700-3 assume !(0 == ~E_1~0); 110169#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 110168#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 110167#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 110166#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 110165#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 110164#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110163#L320-21 assume !(1 == ~m_pc~0); 110162#L320-23 is_master_triggered_~__retres1~0#1 := 0; 110161#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110160#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 110159#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 110158#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110157#L339-21 assume 1 == ~t1_pc~0; 110155#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 110154#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110153#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 110152#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 110151#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110150#L358-21 assume !(1 == ~t2_pc~0); 110149#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 110148#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 110147#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 110146#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 110145#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110144#L377-21 assume !(1 == ~t3_pc~0); 110143#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 110141#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110140#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 110139#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 110138#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110137#L396-21 assume !(1 == ~t4_pc~0); 110136#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 110135#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110134#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 110133#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 110132#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110131#L415-21 assume !(1 == ~t5_pc~0); 110130#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 110129#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 110128#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 110127#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 110126#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110125#L434-21 assume 1 == ~t6_pc~0; 110123#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 110121#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 110119#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 110117#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 110116#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110115#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 110114#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 110113#L748-3 assume !(1 == ~T2_E~0); 110112#L753-3 assume !(1 == ~T3_E~0); 110110#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 110108#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 110106#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 110104#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 110102#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 110100#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 110098#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 110096#L793-3 assume !(1 == ~E_5~0); 110094#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 110092#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 110090#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 110082#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 110080#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 110078#L1043 assume !(0 == start_simulation_~tmp~3#1); 110076#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 110074#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 110005#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 110002#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 110000#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 109998#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 109996#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 109994#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 104917#L1024-2 [2024-11-19 15:04:33,858 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:33,858 INFO L85 PathProgramCache]: Analyzing trace with hash -975469477, now seen corresponding path program 1 times [2024-11-19 15:04:33,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:33,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050415192] [2024-11-19 15:04:33,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:33,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:33,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:33,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:33,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:33,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050415192] [2024-11-19 15:04:33,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050415192] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:33,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:33,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:33,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1581363645] [2024-11-19 15:04:33,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:33,908 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:33,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:33,908 INFO L85 PathProgramCache]: Analyzing trace with hash 1904973666, now seen corresponding path program 1 times [2024-11-19 15:04:33,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:33,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219301072] [2024-11-19 15:04:33,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:33,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:33,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:33,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:33,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:33,982 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1219301072] [2024-11-19 15:04:33,982 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1219301072] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:33,982 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:33,982 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:33,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699002856] [2024-11-19 15:04:33,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:33,982 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:33,982 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:33,983 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:04:33,983 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:04:33,983 INFO L87 Difference]: Start difference. First operand 8278 states and 11762 transitions. cyclomatic complexity: 3500 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:34,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:34,039 INFO L93 Difference]: Finished difference Result 7192 states and 10187 transitions. [2024-11-19 15:04:34,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7192 states and 10187 transitions. [2024-11-19 15:04:34,061 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7040 [2024-11-19 15:04:34,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7192 states to 7192 states and 10187 transitions. [2024-11-19 15:04:34,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7192 [2024-11-19 15:04:34,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7192 [2024-11-19 15:04:34,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7192 states and 10187 transitions. [2024-11-19 15:04:34,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:34,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7192 states and 10187 transitions. [2024-11-19 15:04:34,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7192 states and 10187 transitions. [2024-11-19 15:04:34,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7192 to 7192. [2024-11-19 15:04:34,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7192 states, 7192 states have (on average 1.4164349276974415) internal successors, (10187), 7191 states have internal predecessors, (10187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:34,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7192 states to 7192 states and 10187 transitions. [2024-11-19 15:04:34,191 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7192 states and 10187 transitions. [2024-11-19 15:04:34,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:34,192 INFO L425 stractBuchiCegarLoop]: Abstraction has 7192 states and 10187 transitions. [2024-11-19 15:04:34,192 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-19 15:04:34,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7192 states and 10187 transitions. [2024-11-19 15:04:34,212 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7040 [2024-11-19 15:04:34,212 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:34,212 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:34,213 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:34,213 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:34,214 INFO L745 eck$LassoCheckResult]: Stem: 120600#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 120601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 120736#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 120737#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 120262#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 120263#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 120801#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 120944#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 120355#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 120356#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 120519#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 120370#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 120371#L670 assume !(0 == ~M_E~0); 120753#L670-2 assume !(0 == ~T1_E~0); 120702#L675-1 assume !(0 == ~T2_E~0); 120703#L680-1 assume !(0 == ~T3_E~0); 120799#L685-1 assume !(0 == ~T4_E~0); 120759#L690-1 assume !(0 == ~T5_E~0); 120760#L695-1 assume !(0 == ~T6_E~0); 120844#L700-1 assume !(0 == ~E_1~0); 120829#L705-1 assume !(0 == ~E_2~0); 120830#L710-1 assume !(0 == ~E_3~0); 120701#L715-1 assume !(0 == ~E_4~0); 120625#L720-1 assume !(0 == ~E_5~0); 120626#L725-1 assume !(0 == ~E_6~0); 120678#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 120725#L320 assume !(1 == ~m_pc~0); 120865#L320-2 is_master_triggered_~__retres1~0#1 := 0; 120566#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 120559#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 120520#L825 assume !(0 != activate_threads_~tmp~1#1); 120521#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 120528#L339 assume !(1 == ~t1_pc~0); 120529#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 120496#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120351#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 120352#L833 assume !(0 != activate_threads_~tmp___0~0#1); 120374#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 120288#L358 assume !(1 == ~t2_pc~0); 120289#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 120819#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 120739#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 120682#L841 assume !(0 != activate_threads_~tmp___1~0#1); 120515#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 120516#L377 assume !(1 == ~t3_pc~0); 120782#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 120783#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120286#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 120287#L849 assume !(0 != activate_threads_~tmp___2~0#1); 120523#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120456#L396 assume !(1 == ~t4_pc~0); 120457#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 120290#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 120291#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 120436#L857 assume !(0 != activate_threads_~tmp___3~0#1); 120420#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 120421#L415 assume !(1 == ~t5_pc~0); 120503#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 120553#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 120573#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 120574#L865 assume !(0 != activate_threads_~tmp___4~0#1); 120328#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 120329#L434 assume !(1 == ~t6_pc~0); 120659#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 120660#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 120730#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 120731#L873 assume !(0 != activate_threads_~tmp___5~0#1); 120537#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 120538#L743 assume !(1 == ~M_E~0); 120410#L743-2 assume !(1 == ~T1_E~0); 120411#L748-1 assume !(1 == ~T2_E~0); 120721#L753-1 assume !(1 == ~T3_E~0); 120722#L758-1 assume !(1 == ~T4_E~0); 120846#L763-1 assume !(1 == ~T5_E~0); 120898#L768-1 assume !(1 == ~T6_E~0); 120535#L773-1 assume !(1 == ~E_1~0); 120536#L778-1 assume !(1 == ~E_2~0); 120510#L783-1 assume !(1 == ~E_3~0); 120511#L788-1 assume !(1 == ~E_4~0); 120797#L793-1 assume !(1 == ~E_5~0); 120746#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 120393#L803-1 assume { :end_inline_reset_delta_events } true; 120394#L1024-2 [2024-11-19 15:04:34,214 INFO L747 eck$LassoCheckResult]: Loop: 120394#L1024-2 assume !false; 124268#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 124263#L645-1 assume !false; 124261#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 124259#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 124251#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 124249#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 124246#L556 assume !(0 != eval_~tmp~0#1); 124247#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 124448#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 124446#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 124444#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 124442#L675-3 assume !(0 == ~T2_E~0); 124440#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 124438#L685-3 assume !(0 == ~T4_E~0); 124435#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 124433#L695-3 assume !(0 == ~T6_E~0); 124431#L700-3 assume !(0 == ~E_1~0); 124429#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 124427#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 124425#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 124423#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 124421#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 124419#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124417#L320-21 assume !(1 == ~m_pc~0); 124415#L320-23 is_master_triggered_~__retres1~0#1 := 0; 124413#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124411#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 124409#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 124407#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124405#L339-21 assume !(1 == ~t1_pc~0); 124403#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 124398#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 124396#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 124394#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 124392#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124389#L358-21 assume !(1 == ~t2_pc~0); 124387#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 124385#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124383#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 124381#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 124379#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124377#L377-21 assume !(1 == ~t3_pc~0); 124375#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 124372#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124370#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 124368#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 124366#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124364#L396-21 assume !(1 == ~t4_pc~0); 124362#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 124360#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124359#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 124358#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124357#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124356#L415-21 assume !(1 == ~t5_pc~0); 124355#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 124354#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124353#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124352#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 124351#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124350#L434-21 assume !(1 == ~t6_pc~0); 124346#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 124345#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124344#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124342#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 124339#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124337#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 124335#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 124333#L748-3 assume !(1 == ~T2_E~0); 124331#L753-3 assume !(1 == ~T3_E~0); 124329#L758-3 assume !(1 == ~T4_E~0); 124328#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 124325#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 124323#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 124321#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 124319#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 124317#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 124315#L793-3 assume !(1 == ~E_5~0); 124312#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 124310#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 124308#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 124300#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 124298#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 124295#L1043 assume !(0 == start_simulation_~tmp~3#1); 124291#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 124289#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 124281#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 124279#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 124277#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 124275#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 124273#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 124271#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 120394#L1024-2 [2024-11-19 15:04:34,215 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:34,215 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463913, now seen corresponding path program 1 times [2024-11-19 15:04:34,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:34,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346542442] [2024-11-19 15:04:34,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:34,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:34,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:34,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:34,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:34,262 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [346542442] [2024-11-19 15:04:34,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [346542442] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:34,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:34,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:34,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034038562] [2024-11-19 15:04:34,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:34,263 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:34,264 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:34,264 INFO L85 PathProgramCache]: Analyzing trace with hash 897122202, now seen corresponding path program 1 times [2024-11-19 15:04:34,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:34,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983759806] [2024-11-19 15:04:34,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:34,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:34,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:34,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:34,296 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:34,296 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983759806] [2024-11-19 15:04:34,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983759806] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:34,296 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:34,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:34,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456802690] [2024-11-19 15:04:34,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:34,297 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:34,297 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:34,297 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:04:34,297 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:04:34,297 INFO L87 Difference]: Start difference. First operand 7192 states and 10187 transitions. cyclomatic complexity: 3011 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:34,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:34,464 INFO L93 Difference]: Finished difference Result 14506 states and 20380 transitions. [2024-11-19 15:04:34,464 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14506 states and 20380 transitions. [2024-11-19 15:04:34,533 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14204 [2024-11-19 15:04:34,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14506 states to 14506 states and 20380 transitions. [2024-11-19 15:04:34,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14506 [2024-11-19 15:04:34,604 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14506 [2024-11-19 15:04:34,604 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14506 states and 20380 transitions. [2024-11-19 15:04:34,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:34,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14506 states and 20380 transitions. [2024-11-19 15:04:34,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14506 states and 20380 transitions. [2024-11-19 15:04:34,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14506 to 8011. [2024-11-19 15:04:34,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8011 states, 8011 states have (on average 1.4064411434277868) internal successors, (11267), 8010 states have internal predecessors, (11267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:34,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8011 states to 8011 states and 11267 transitions. [2024-11-19 15:04:34,795 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8011 states and 11267 transitions. [2024-11-19 15:04:34,795 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:04:34,795 INFO L425 stractBuchiCegarLoop]: Abstraction has 8011 states and 11267 transitions. [2024-11-19 15:04:34,795 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-19 15:04:34,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8011 states and 11267 transitions. [2024-11-19 15:04:34,870 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7800 [2024-11-19 15:04:34,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:34,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:34,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:34,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:34,872 INFO L745 eck$LassoCheckResult]: Stem: 142321#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 142322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 142459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 142460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 141970#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 141971#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 142541#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 142713#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 142064#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 142065#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 142233#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 142079#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 142080#L670 assume !(0 == ~M_E~0); 142480#L670-2 assume !(0 == ~T1_E~0); 142417#L675-1 assume !(0 == ~T2_E~0); 142418#L680-1 assume !(0 == ~T3_E~0); 142539#L685-1 assume !(0 == ~T4_E~0); 142488#L690-1 assume !(0 == ~T5_E~0); 142489#L695-1 assume !(0 == ~T6_E~0); 142586#L700-1 assume !(0 == ~E_1~0); 142572#L705-1 assume !(0 == ~E_2~0); 142573#L710-1 assume !(0 == ~E_3~0); 142416#L715-1 assume !(0 == ~E_4~0); 142345#L720-1 assume !(0 == ~E_5~0); 142346#L725-1 assume 0 == ~E_6~0;~E_6~0 := 1; 142394#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 142609#L320 assume !(1 == ~m_pc~0); 142610#L320-2 is_master_triggered_~__retres1~0#1 := 0; 142283#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 142284#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 142234#L825 assume !(0 != activate_threads_~tmp~1#1); 142235#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 142245#L339 assume !(1 == ~t1_pc~0); 142246#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 142208#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 142209#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 142083#L833 assume !(0 != activate_threads_~tmp___0~0#1); 142084#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 141996#L358 assume !(1 == ~t2_pc~0); 141997#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 142767#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 142462#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 142463#L841 assume !(0 != activate_threads_~tmp___1~0#1); 142229#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 142230#L377 assume !(1 == ~t3_pc~0); 142514#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 142515#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 141994#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 141995#L849 assume !(0 != activate_threads_~tmp___2~0#1); 142535#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 142536#L396 assume !(1 == ~t4_pc~0); 142766#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 141998#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 141999#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 142433#L857 assume !(0 != activate_threads_~tmp___3~0#1); 142434#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 142216#L415 assume !(1 == ~t5_pc~0); 142217#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 142448#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 142449#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 142620#L865 assume !(0 != activate_threads_~tmp___4~0#1); 142621#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 142516#L434 assume !(1 == ~t6_pc~0); 142517#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 142765#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 142764#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 142760#L873 assume !(0 != activate_threads_~tmp___5~0#1); 142759#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 142758#L743 assume !(1 == ~M_E~0); 142757#L743-2 assume !(1 == ~T1_E~0); 142756#L748-1 assume !(1 == ~T2_E~0); 142755#L753-1 assume !(1 == ~T3_E~0); 142754#L758-1 assume !(1 == ~T4_E~0); 142753#L763-1 assume !(1 == ~T5_E~0); 142752#L768-1 assume !(1 == ~T6_E~0); 142751#L773-1 assume !(1 == ~E_1~0); 142750#L778-1 assume !(1 == ~E_2~0); 142749#L783-1 assume !(1 == ~E_3~0); 142748#L788-1 assume !(1 == ~E_4~0); 142747#L793-1 assume !(1 == ~E_5~0); 142746#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 142103#L803-1 assume { :end_inline_reset_delta_events } true; 142104#L1024-2 [2024-11-19 15:04:34,873 INFO L747 eck$LassoCheckResult]: Loop: 142104#L1024-2 assume !false; 142665#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 141978#L645-1 assume !false; 142219#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 142342#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 142044#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 142496#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 142497#L556 assume !(0 != eval_~tmp~0#1); 142745#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 149919#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 149917#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 149915#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 149912#L675-3 assume !(0 == ~T2_E~0); 149910#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 149908#L685-3 assume !(0 == ~T4_E~0); 149906#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 149904#L695-3 assume !(0 == ~T6_E~0); 149902#L700-3 assume !(0 == ~E_1~0); 149722#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 149628#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 149598#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 149597#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 149596#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 149595#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 149594#L320-21 assume !(1 == ~m_pc~0); 149593#L320-23 is_master_triggered_~__retres1~0#1 := 0; 149592#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149591#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 149590#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 149589#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 149588#L339-21 assume 1 == ~t1_pc~0; 149586#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 149585#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 149584#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 149583#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 149582#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 149581#L358-21 assume !(1 == ~t2_pc~0); 149580#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 149579#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 149578#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 149577#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 149576#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149575#L377-21 assume !(1 == ~t3_pc~0); 149574#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 149572#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 149571#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 149570#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 149569#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 149568#L396-21 assume !(1 == ~t4_pc~0); 149567#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 149566#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 149565#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 149564#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 149563#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 149562#L415-21 assume !(1 == ~t5_pc~0); 149561#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 149560#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 149559#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 149558#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 149557#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 149556#L434-21 assume !(1 == ~t6_pc~0); 149555#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 149552#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 149550#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 149548#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 149546#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 149545#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 149544#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 149543#L748-3 assume !(1 == ~T2_E~0); 149542#L753-3 assume !(1 == ~T3_E~0); 149541#L758-3 assume !(1 == ~T4_E~0); 149540#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 149539#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 149538#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 149537#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 149536#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 149535#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 149534#L793-3 assume !(1 == ~E_5~0); 149532#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 149530#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 149316#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 149307#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 149305#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 149302#L1043 assume !(0 == start_simulation_~tmp~3#1); 149299#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 149297#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 149289#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 149286#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 149284#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 149282#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 149280#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 149278#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 142104#L1024-2 [2024-11-19 15:04:34,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:34,873 INFO L85 PathProgramCache]: Analyzing trace with hash 1760774297, now seen corresponding path program 1 times [2024-11-19 15:04:34,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:34,874 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301247284] [2024-11-19 15:04:34,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:34,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:34,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:34,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:34,926 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:34,926 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301247284] [2024-11-19 15:04:34,926 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [301247284] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:34,926 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:34,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:34,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [549265825] [2024-11-19 15:04:34,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:34,927 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:34,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:34,927 INFO L85 PathProgramCache]: Analyzing trace with hash -922603717, now seen corresponding path program 1 times [2024-11-19 15:04:34,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:34,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102809244] [2024-11-19 15:04:34,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:34,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:34,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:34,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:34,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:34,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102809244] [2024-11-19 15:04:34,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1102809244] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:34,966 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:34,967 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:34,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787354531] [2024-11-19 15:04:34,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:34,967 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:34,967 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:34,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:04:34,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:04:34,968 INFO L87 Difference]: Start difference. First operand 8011 states and 11267 transitions. cyclomatic complexity: 3272 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:35,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:35,091 INFO L93 Difference]: Finished difference Result 10177 states and 14288 transitions. [2024-11-19 15:04:35,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10177 states and 14288 transitions. [2024-11-19 15:04:35,140 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 9996 [2024-11-19 15:04:35,177 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10177 states to 10177 states and 14288 transitions. [2024-11-19 15:04:35,177 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10177 [2024-11-19 15:04:35,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10177 [2024-11-19 15:04:35,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10177 states and 14288 transitions. [2024-11-19 15:04:35,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:35,202 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10177 states and 14288 transitions. [2024-11-19 15:04:35,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10177 states and 14288 transitions. [2024-11-19 15:04:35,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10177 to 6925. [2024-11-19 15:04:35,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6925 states, 6925 states have (on average 1.3995667870036101) internal successors, (9692), 6924 states have internal predecessors, (9692), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:35,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6925 states to 6925 states and 9692 transitions. [2024-11-19 15:04:35,335 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6925 states and 9692 transitions. [2024-11-19 15:04:35,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:04:35,336 INFO L425 stractBuchiCegarLoop]: Abstraction has 6925 states and 9692 transitions. [2024-11-19 15:04:35,336 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-19 15:04:35,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6925 states and 9692 transitions. [2024-11-19 15:04:35,362 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6776 [2024-11-19 15:04:35,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:35,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:35,364 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:35,364 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:35,365 INFO L745 eck$LassoCheckResult]: Stem: 160508#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 160509#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 160645#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 160646#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 160168#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 160169#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 160715#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 160863#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 160262#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 160263#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 160429#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 160278#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 160279#L670 assume !(0 == ~M_E~0); 160658#L670-2 assume !(0 == ~T1_E~0); 160610#L675-1 assume !(0 == ~T2_E~0); 160611#L680-1 assume !(0 == ~T3_E~0); 160714#L685-1 assume !(0 == ~T4_E~0); 160666#L690-1 assume !(0 == ~T5_E~0); 160667#L695-1 assume !(0 == ~T6_E~0); 160759#L700-1 assume !(0 == ~E_1~0); 160748#L705-1 assume !(0 == ~E_2~0); 160749#L710-1 assume !(0 == ~E_3~0); 160609#L715-1 assume !(0 == ~E_4~0); 160540#L720-1 assume !(0 == ~E_5~0); 160541#L725-1 assume !(0 == ~E_6~0); 160589#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 160633#L320 assume !(1 == ~m_pc~0); 160776#L320-2 is_master_triggered_~__retres1~0#1 := 0; 160478#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160472#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 160430#L825 assume !(0 != activate_threads_~tmp~1#1); 160431#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 160435#L339 assume !(1 == ~t1_pc~0); 160436#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 160405#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 160260#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 160261#L833 assume !(0 != activate_threads_~tmp___0~0#1); 160283#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 160194#L358 assume !(1 == ~t2_pc~0); 160195#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 160739#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160648#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 160592#L841 assume !(0 != activate_threads_~tmp___1~0#1); 160425#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 160426#L377 assume !(1 == ~t3_pc~0); 160694#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 160695#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 160190#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 160191#L849 assume !(0 != activate_threads_~tmp___2~0#1); 160434#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 160362#L396 assume !(1 == ~t4_pc~0); 160363#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 160196#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 160197#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 160345#L857 assume !(0 != activate_threads_~tmp___3~0#1); 160330#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 160331#L415 assume !(1 == ~t5_pc~0); 160410#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 160463#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 160481#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 160482#L865 assume !(0 != activate_threads_~tmp___4~0#1); 160237#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 160238#L434 assume !(1 == ~t6_pc~0); 160571#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 160572#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 160637#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 160638#L873 assume !(0 != activate_threads_~tmp___5~0#1); 160451#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 160452#L743 assume !(1 == ~M_E~0); 160320#L743-2 assume !(1 == ~T1_E~0); 160321#L748-1 assume !(1 == ~T2_E~0); 160628#L753-1 assume !(1 == ~T3_E~0); 160629#L758-1 assume !(1 == ~T4_E~0); 160762#L763-1 assume !(1 == ~T5_E~0); 160815#L768-1 assume !(1 == ~T6_E~0); 160444#L773-1 assume !(1 == ~E_1~0); 160445#L778-1 assume !(1 == ~E_2~0); 160419#L783-1 assume !(1 == ~E_3~0); 160420#L788-1 assume !(1 == ~E_4~0); 160712#L793-1 assume !(1 == ~E_5~0); 160655#L798-1 assume !(1 == ~E_6~0); 160300#L803-1 assume { :end_inline_reset_delta_events } true; 160301#L1024-2 [2024-11-19 15:04:35,365 INFO L747 eck$LassoCheckResult]: Loop: 160301#L1024-2 assume !false; 162827#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 162822#L645-1 assume !false; 162820#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 162818#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 162809#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 162807#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 162804#L556 assume !(0 != eval_~tmp~0#1); 162805#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 164349#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 164347#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 164345#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 164343#L675-3 assume !(0 == ~T2_E~0); 164341#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 164339#L685-3 assume !(0 == ~T4_E~0); 164335#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 164333#L695-3 assume !(0 == ~T6_E~0); 164331#L700-3 assume !(0 == ~E_1~0); 164330#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 164327#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 164317#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 164309#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 163803#L725-3 assume !(0 == ~E_6~0); 163801#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 163799#L320-21 assume !(1 == ~m_pc~0); 163797#L320-23 is_master_triggered_~__retres1~0#1 := 0; 163795#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163792#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 163790#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 163788#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163786#L339-21 assume 1 == ~t1_pc~0; 163783#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 163781#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163778#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 163776#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 163774#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163772#L358-21 assume !(1 == ~t2_pc~0); 163770#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 163768#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163765#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 163763#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 163760#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163757#L377-21 assume !(1 == ~t3_pc~0); 163754#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 163750#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163746#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 163744#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 163742#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163738#L396-21 assume !(1 == ~t4_pc~0); 163735#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 163732#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163729#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 163726#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 163723#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163720#L415-21 assume !(1 == ~t5_pc~0); 163717#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 163714#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163710#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 163707#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 163704#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163700#L434-21 assume !(1 == ~t6_pc~0); 163697#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 163695#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 163692#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163689#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 163686#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163683#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 163680#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 163677#L748-3 assume !(1 == ~T2_E~0); 163674#L753-3 assume !(1 == ~T3_E~0); 163671#L758-3 assume !(1 == ~T4_E~0); 163668#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 163665#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 163662#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 163659#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 163656#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 163653#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 163649#L793-3 assume !(1 == ~E_5~0); 163646#L798-3 assume !(1 == ~E_6~0); 163643#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 163632#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 163623#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 163620#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 163574#L1043 assume !(0 == start_simulation_~tmp~3#1); 163568#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 163537#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 163526#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 163520#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 163512#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 163506#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 163462#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 163192#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 160301#L1024-2 [2024-11-19 15:04:35,366 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:35,366 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 1 times [2024-11-19 15:04:35,366 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:35,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935834886] [2024-11-19 15:04:35,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:35,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:35,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:35,378 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:35,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:35,430 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:35,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:35,432 INFO L85 PathProgramCache]: Analyzing trace with hash -25263177, now seen corresponding path program 1 times [2024-11-19 15:04:35,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:35,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554849056] [2024-11-19 15:04:35,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:35,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:35,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:35,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:35,482 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:35,482 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554849056] [2024-11-19 15:04:35,482 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554849056] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:35,482 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:35,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:35,483 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [842008052] [2024-11-19 15:04:35,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:35,483 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:35,484 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:35,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:35,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:35,484 INFO L87 Difference]: Start difference. First operand 6925 states and 9692 transitions. cyclomatic complexity: 2783 Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:35,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:35,551 INFO L93 Difference]: Finished difference Result 7960 states and 11114 transitions. [2024-11-19 15:04:35,551 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7960 states and 11114 transitions. [2024-11-19 15:04:35,590 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7752 [2024-11-19 15:04:35,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7960 states to 7960 states and 11114 transitions. [2024-11-19 15:04:35,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7960 [2024-11-19 15:04:35,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7960 [2024-11-19 15:04:35,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7960 states and 11114 transitions. [2024-11-19 15:04:35,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:35,634 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7960 states and 11114 transitions. [2024-11-19 15:04:35,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7960 states and 11114 transitions. [2024-11-19 15:04:35,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7960 to 7960. [2024-11-19 15:04:35,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7960 states, 7960 states have (on average 1.3962311557788945) internal successors, (11114), 7959 states have internal predecessors, (11114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:35,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7960 states to 7960 states and 11114 transitions. [2024-11-19 15:04:35,761 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7960 states and 11114 transitions. [2024-11-19 15:04:35,762 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:35,762 INFO L425 stractBuchiCegarLoop]: Abstraction has 7960 states and 11114 transitions. [2024-11-19 15:04:35,762 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-19 15:04:35,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7960 states and 11114 transitions. [2024-11-19 15:04:35,791 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7752 [2024-11-19 15:04:35,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:35,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:35,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:35,793 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:35,793 INFO L745 eck$LassoCheckResult]: Stem: 175399#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 175400#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 175538#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 175539#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 175059#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 175060#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 175602#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 175749#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 175152#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 175153#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 175317#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 175168#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 175169#L670 assume !(0 == ~M_E~0); 175551#L670-2 assume !(0 == ~T1_E~0); 175499#L675-1 assume !(0 == ~T2_E~0); 175500#L680-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 175600#L685-1 assume !(0 == ~T4_E~0); 175558#L690-1 assume !(0 == ~T5_E~0); 175559#L695-1 assume !(0 == ~T6_E~0); 175810#L700-1 assume !(0 == ~E_1~0); 175809#L705-1 assume !(0 == ~E_2~0); 175742#L710-1 assume !(0 == ~E_3~0); 175498#L715-1 assume !(0 == ~E_4~0); 175428#L720-1 assume !(0 == ~E_5~0); 175429#L725-1 assume !(0 == ~E_6~0); 175477#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 175805#L320 assume !(1 == ~m_pc~0); 175756#L320-2 is_master_triggered_~__retres1~0#1 := 0; 175368#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 175369#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 175318#L825 assume !(0 != activate_threads_~tmp~1#1); 175319#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 175691#L339 assume !(1 == ~t1_pc~0); 175801#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 175800#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 175799#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 175798#L833 assume !(0 != activate_threads_~tmp___0~0#1); 175738#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 175085#L358 assume !(1 == ~t2_pc~0); 175086#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 175622#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 175724#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 175794#L841 assume !(0 != activate_threads_~tmp___1~0#1); 175313#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 175314#L377 assume !(1 == ~t3_pc~0); 175583#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 175584#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 175081#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 175082#L849 assume !(0 != activate_threads_~tmp___2~0#1); 175788#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 175787#L396 assume !(1 == ~t4_pc~0); 175786#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 175785#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 175784#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 175514#L857 assume !(0 != activate_threads_~tmp___3~0#1); 175515#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 175783#L415 assume !(1 == ~t5_pc~0); 175350#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 175351#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 175782#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 175781#L865 assume !(0 != activate_threads_~tmp___4~0#1); 175780#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 175779#L434 assume !(1 == ~t6_pc~0); 175777#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 175776#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175532#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 175533#L873 assume !(0 != activate_threads_~tmp___5~0#1); 175338#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175339#L743 assume !(1 == ~M_E~0); 175210#L743-2 assume !(1 == ~T1_E~0); 175211#L748-1 assume !(1 == ~T2_E~0); 175521#L753-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 175522#L758-1 assume !(1 == ~T4_E~0); 175645#L763-1 assume !(1 == ~T5_E~0); 175701#L768-1 assume !(1 == ~T6_E~0); 175332#L773-1 assume !(1 == ~E_1~0); 175333#L778-1 assume !(1 == ~E_2~0); 175308#L783-1 assume !(1 == ~E_3~0); 175309#L788-1 assume !(1 == ~E_4~0); 175598#L793-1 assume !(1 == ~E_5~0); 175546#L798-1 assume !(1 == ~E_6~0); 175190#L803-1 assume { :end_inline_reset_delta_events } true; 175191#L1024-2 [2024-11-19 15:04:35,794 INFO L747 eck$LassoCheckResult]: Loop: 175191#L1024-2 assume !false; 177293#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 177288#L645-1 assume !false; 177286#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 177284#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 177276#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 177274#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 177271#L556 assume !(0 != eval_~tmp~0#1); 177272#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 182849#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 182847#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 182845#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 182843#L675-3 assume !(0 == ~T2_E~0); 182840#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 182838#L685-3 assume !(0 == ~T4_E~0); 182836#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 182834#L695-3 assume !(0 == ~T6_E~0); 182832#L700-3 assume !(0 == ~E_1~0); 182829#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 182827#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 182825#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 182823#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 182821#L725-3 assume !(0 == ~E_6~0); 182819#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 182817#L320-21 assume !(1 == ~m_pc~0); 182815#L320-23 is_master_triggered_~__retres1~0#1 := 0; 182813#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 182811#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 182809#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 182807#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 182804#L339-21 assume !(1 == ~t1_pc~0); 182802#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 182799#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 182797#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 182795#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 182793#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 182791#L358-21 assume !(1 == ~t2_pc~0); 182789#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 182787#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 182785#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 182783#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 182781#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 182779#L377-21 assume 1 == ~t3_pc~0; 182776#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 182774#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 182772#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 182770#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 182767#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 182765#L396-21 assume !(1 == ~t4_pc~0); 182763#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 182761#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 182759#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 182757#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 182755#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 182753#L415-21 assume !(1 == ~t5_pc~0); 182751#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 182750#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 182749#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 182748#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 182747#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 182746#L434-21 assume !(1 == ~t6_pc~0); 182743#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 182740#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 182738#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 182736#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 182734#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 182732#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 182730#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 182727#L748-3 assume !(1 == ~T2_E~0); 182725#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 182722#L758-3 assume !(1 == ~T4_E~0); 182720#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 182718#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 182716#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 182714#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 182712#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 182710#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 182708#L793-3 assume !(1 == ~E_5~0); 182706#L798-3 assume !(1 == ~E_6~0); 182704#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 182559#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 182551#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 182549#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 181451#L1043 assume !(0 == start_simulation_~tmp~3#1); 181438#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 177314#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 177306#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 177304#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 177302#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 177300#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 177298#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 177296#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 175191#L1024-2 [2024-11-19 15:04:35,795 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:35,795 INFO L85 PathProgramCache]: Analyzing trace with hash -1585374703, now seen corresponding path program 1 times [2024-11-19 15:04:35,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:35,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935415688] [2024-11-19 15:04:35,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:35,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:35,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:35,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:35,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:35,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935415688] [2024-11-19 15:04:35,849 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [935415688] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:35,850 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:35,850 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:35,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984918342] [2024-11-19 15:04:35,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:35,851 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:35,851 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:35,852 INFO L85 PathProgramCache]: Analyzing trace with hash 1035270837, now seen corresponding path program 1 times [2024-11-19 15:04:35,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:35,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798303034] [2024-11-19 15:04:35,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:35,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:35,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:35,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:35,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:35,894 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798303034] [2024-11-19 15:04:35,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [798303034] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:35,894 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:35,895 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:35,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242956243] [2024-11-19 15:04:35,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:35,896 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:35,897 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:35,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:04:35,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:04:35,897 INFO L87 Difference]: Start difference. First operand 7960 states and 11114 transitions. cyclomatic complexity: 3170 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:36,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:36,023 INFO L93 Difference]: Finished difference Result 13775 states and 19252 transitions. [2024-11-19 15:04:36,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13775 states and 19252 transitions. [2024-11-19 15:04:36,092 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 13552 [2024-11-19 15:04:36,145 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13775 states to 13775 states and 19252 transitions. [2024-11-19 15:04:36,145 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13775 [2024-11-19 15:04:36,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13775 [2024-11-19 15:04:36,159 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13775 states and 19252 transitions. [2024-11-19 15:04:36,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:36,175 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13775 states and 19252 transitions. [2024-11-19 15:04:36,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13775 states and 19252 transitions. [2024-11-19 15:04:36,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13775 to 6925. [2024-11-19 15:04:36,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6925 states, 6925 states have (on average 1.3971119133574008) internal successors, (9675), 6924 states have internal predecessors, (9675), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:36,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6925 states to 6925 states and 9675 transitions. [2024-11-19 15:04:36,316 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6925 states and 9675 transitions. [2024-11-19 15:04:36,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:04:36,317 INFO L425 stractBuchiCegarLoop]: Abstraction has 6925 states and 9675 transitions. [2024-11-19 15:04:36,318 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-19 15:04:36,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6925 states and 9675 transitions. [2024-11-19 15:04:36,341 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6776 [2024-11-19 15:04:36,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:36,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:36,343 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:36,343 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:36,344 INFO L745 eck$LassoCheckResult]: Stem: 197141#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 197142#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 197275#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 197276#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 196804#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 196805#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 197342#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 197493#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 196896#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 196897#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 197065#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 196912#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 196913#L670 assume !(0 == ~M_E~0); 197289#L670-2 assume !(0 == ~T1_E~0); 197240#L675-1 assume !(0 == ~T2_E~0); 197241#L680-1 assume !(0 == ~T3_E~0); 197341#L685-1 assume !(0 == ~T4_E~0); 197296#L690-1 assume !(0 == ~T5_E~0); 197297#L695-1 assume !(0 == ~T6_E~0); 197389#L700-1 assume !(0 == ~E_1~0); 197374#L705-1 assume !(0 == ~E_2~0); 197375#L710-1 assume !(0 == ~E_3~0); 197239#L715-1 assume !(0 == ~E_4~0); 197169#L720-1 assume !(0 == ~E_5~0); 197170#L725-1 assume !(0 == ~E_6~0); 197218#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 197265#L320 assume !(1 == ~m_pc~0); 197408#L320-2 is_master_triggered_~__retres1~0#1 := 0; 197113#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 197107#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 197066#L825 assume !(0 != activate_threads_~tmp~1#1); 197067#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 197070#L339 assume !(1 == ~t1_pc~0); 197071#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 197042#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 196894#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 196895#L833 assume !(0 != activate_threads_~tmp___0~0#1); 196917#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 196830#L358 assume !(1 == ~t2_pc~0); 196831#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 197364#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 197278#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 197221#L841 assume !(0 != activate_threads_~tmp___1~0#1); 197061#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 197062#L377 assume !(1 == ~t3_pc~0); 197322#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 197323#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 196826#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 196827#L849 assume !(0 != activate_threads_~tmp___2~0#1); 197069#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 197000#L396 assume !(1 == ~t4_pc~0); 197001#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 196832#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 196833#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 196981#L857 assume !(0 != activate_threads_~tmp___3~0#1); 196966#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 196967#L415 assume !(1 == ~t5_pc~0); 197047#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 197100#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 197117#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 197118#L865 assume !(0 != activate_threads_~tmp___4~0#1); 196871#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 196872#L434 assume !(1 == ~t6_pc~0); 197198#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 197199#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 197269#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 197270#L873 assume !(0 != activate_threads_~tmp___5~0#1); 197086#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 197087#L743 assume !(1 == ~M_E~0); 196955#L743-2 assume !(1 == ~T1_E~0); 196956#L748-1 assume !(1 == ~T2_E~0); 197261#L753-1 assume !(1 == ~T3_E~0); 197262#L758-1 assume !(1 == ~T4_E~0); 197391#L763-1 assume !(1 == ~T5_E~0); 197443#L768-1 assume !(1 == ~T6_E~0); 197079#L773-1 assume !(1 == ~E_1~0); 197080#L778-1 assume !(1 == ~E_2~0); 197056#L783-1 assume !(1 == ~E_3~0); 197057#L788-1 assume !(1 == ~E_4~0); 197339#L793-1 assume !(1 == ~E_5~0); 197284#L798-1 assume !(1 == ~E_6~0); 196934#L803-1 assume { :end_inline_reset_delta_events } true; 196935#L1024-2 [2024-11-19 15:04:36,344 INFO L747 eck$LassoCheckResult]: Loop: 196935#L1024-2 assume !false; 200623#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 200618#L645-1 assume !false; 200616#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 200614#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 200607#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 200603#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 200600#L556 assume !(0 != eval_~tmp~0#1); 200601#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 200800#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 200798#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 200796#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 200794#L675-3 assume !(0 == ~T2_E~0); 200792#L680-3 assume !(0 == ~T3_E~0); 200790#L685-3 assume !(0 == ~T4_E~0); 200788#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 200786#L695-3 assume !(0 == ~T6_E~0); 200784#L700-3 assume !(0 == ~E_1~0); 200782#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 200780#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 200778#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 200776#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 200774#L725-3 assume !(0 == ~E_6~0); 200772#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 200770#L320-21 assume !(1 == ~m_pc~0); 200767#L320-23 is_master_triggered_~__retres1~0#1 := 0; 200765#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 200763#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 200761#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 200759#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 200757#L339-21 assume !(1 == ~t1_pc~0); 200755#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 200752#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 200750#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 200748#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 200746#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 200744#L358-21 assume !(1 == ~t2_pc~0); 200742#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 200740#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 200738#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 200736#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 200734#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200732#L377-21 assume !(1 == ~t3_pc~0); 200730#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 200728#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 200727#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 200726#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 200725#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 200724#L396-21 assume !(1 == ~t4_pc~0); 200723#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 200722#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 200721#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 200720#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 200719#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 200718#L415-21 assume !(1 == ~t5_pc~0); 200716#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 200714#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 200712#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 200710#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 200708#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 200706#L434-21 assume !(1 == ~t6_pc~0); 200703#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 200700#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 200698#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 200696#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 200694#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 200692#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 200690#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 200688#L748-3 assume !(1 == ~T2_E~0); 200686#L753-3 assume !(1 == ~T3_E~0); 200684#L758-3 assume !(1 == ~T4_E~0); 200682#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 200680#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 200678#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 200675#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 200673#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 200671#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 200669#L793-3 assume !(1 == ~E_5~0); 200667#L798-3 assume !(1 == ~E_6~0); 200665#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 200663#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 200655#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 200653#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 200650#L1043 assume !(0 == start_simulation_~tmp~3#1); 200647#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 200645#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 200637#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 200635#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 200633#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 200631#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 200629#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 200626#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 196935#L1024-2 [2024-11-19 15:04:36,345 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:36,345 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 2 times [2024-11-19 15:04:36,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:36,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107088320] [2024-11-19 15:04:36,346 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:04:36,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:36,357 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:04:36,357 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:04:36,357 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:36,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:36,381 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:36,381 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:36,382 INFO L85 PathProgramCache]: Analyzing trace with hash 2034702488, now seen corresponding path program 1 times [2024-11-19 15:04:36,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:36,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047305834] [2024-11-19 15:04:36,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:36,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:36,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:36,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:36,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:36,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047305834] [2024-11-19 15:04:36,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2047305834] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:36,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:36,427 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:36,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256302624] [2024-11-19 15:04:36,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:36,427 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:36,427 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:36,428 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:36,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:36,428 INFO L87 Difference]: Start difference. First operand 6925 states and 9675 transitions. cyclomatic complexity: 2766 Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:36,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:36,543 INFO L93 Difference]: Finished difference Result 10396 states and 14454 transitions. [2024-11-19 15:04:36,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10396 states and 14454 transitions. [2024-11-19 15:04:36,595 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10164 [2024-11-19 15:04:36,636 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10396 states to 10396 states and 14454 transitions. [2024-11-19 15:04:36,636 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10396 [2024-11-19 15:04:36,646 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10396 [2024-11-19 15:04:36,647 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10396 states and 14454 transitions. [2024-11-19 15:04:36,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:36,659 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10396 states and 14454 transitions. [2024-11-19 15:04:36,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10396 states and 14454 transitions. [2024-11-19 15:04:36,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10396 to 10392. [2024-11-19 15:04:36,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10392 states, 10392 states have (on average 1.390492686682063) internal successors, (14450), 10391 states have internal predecessors, (14450), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:36,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10392 states to 10392 states and 14450 transitions. [2024-11-19 15:04:36,813 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10392 states and 14450 transitions. [2024-11-19 15:04:36,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:36,814 INFO L425 stractBuchiCegarLoop]: Abstraction has 10392 states and 14450 transitions. [2024-11-19 15:04:36,814 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-19 15:04:36,814 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10392 states and 14450 transitions. [2024-11-19 15:04:36,843 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10160 [2024-11-19 15:04:36,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:36,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:36,845 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:36,845 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:36,845 INFO L745 eck$LassoCheckResult]: Stem: 214473#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 214474#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 214609#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 214610#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 214131#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 214132#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 214669#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 214823#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 214223#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 214224#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 214391#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 214239#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 214240#L670 assume !(0 == ~M_E~0); 214623#L670-2 assume !(0 == ~T1_E~0); 214570#L675-1 assume !(0 == ~T2_E~0); 214571#L680-1 assume !(0 == ~T3_E~0); 214668#L685-1 assume !(0 == ~T4_E~0); 214630#L690-1 assume !(0 == ~T5_E~0); 214631#L695-1 assume !(0 == ~T6_E~0); 214714#L700-1 assume !(0 == ~E_1~0); 214700#L705-1 assume !(0 == ~E_2~0); 214701#L710-1 assume !(0 == ~E_3~0); 214569#L715-1 assume !(0 == ~E_4~0); 214498#L720-1 assume 0 == ~E_5~0;~E_5~0 := 1; 214499#L725-1 assume !(0 == ~E_6~0); 214597#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 214598#L320 assume !(1 == ~m_pc~0); 214736#L320-2 is_master_triggered_~__retres1~0#1 := 0; 214440#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 214441#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 214392#L825 assume !(0 != activate_threads_~tmp~1#1); 214393#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 214765#L339 assume !(1 == ~t1_pc~0); 214890#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 214889#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 214888#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 214887#L833 assume !(0 != activate_threads_~tmp___0~0#1); 214816#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 214156#L358 assume !(1 == ~t2_pc~0); 214157#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 214690#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 214801#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 214883#L841 assume !(0 != activate_threads_~tmp___1~0#1); 214387#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 214388#L377 assume !(1 == ~t3_pc~0); 214649#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 214650#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 214152#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 214153#L849 assume !(0 != activate_threads_~tmp___2~0#1); 214877#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 214876#L396 assume !(1 == ~t4_pc~0); 214875#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 214874#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 214873#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 214586#L857 assume !(0 != activate_threads_~tmp___3~0#1); 214587#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 214872#L415 assume !(1 == ~t5_pc~0); 214426#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 214427#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 214871#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 214870#L865 assume !(0 != activate_threads_~tmp___4~0#1); 214869#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 214868#L434 assume !(1 == ~t6_pc~0); 214866#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 214865#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 214603#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 214604#L873 assume !(0 != activate_threads_~tmp___5~0#1); 214680#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 214815#L743 assume !(1 == ~M_E~0); 214280#L743-2 assume !(1 == ~T1_E~0); 214281#L748-1 assume !(1 == ~T2_E~0); 214794#L753-1 assume !(1 == ~T3_E~0); 214861#L758-1 assume !(1 == ~T4_E~0); 214860#L763-1 assume !(1 == ~T5_E~0); 214859#L768-1 assume !(1 == ~T6_E~0); 214858#L773-1 assume !(1 == ~E_1~0); 214857#L778-1 assume !(1 == ~E_2~0); 214382#L783-1 assume !(1 == ~E_3~0); 214383#L788-1 assume !(1 == ~E_4~0); 214666#L793-1 assume 1 == ~E_5~0;~E_5~0 := 2; 214619#L798-1 assume !(1 == ~E_6~0); 214261#L803-1 assume { :end_inline_reset_delta_events } true; 214262#L1024-2 [2024-11-19 15:04:36,846 INFO L747 eck$LassoCheckResult]: Loop: 214262#L1024-2 assume !false; 215959#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 215954#L645-1 assume !false; 215950#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 215946#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 215883#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 215874#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 215867#L556 assume !(0 != eval_~tmp~0#1); 215868#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 216587#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 216584#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 216581#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 216578#L675-3 assume !(0 == ~T2_E~0); 216575#L680-3 assume !(0 == ~T3_E~0); 216571#L685-3 assume !(0 == ~T4_E~0); 216567#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 216564#L695-3 assume !(0 == ~T6_E~0); 216561#L700-3 assume !(0 == ~E_1~0); 216558#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 216555#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 216552#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 216550#L720-3 assume !(0 == ~E_5~0); 216547#L725-3 assume !(0 == ~E_6~0); 216544#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216541#L320-21 assume !(1 == ~m_pc~0); 216538#L320-23 is_master_triggered_~__retres1~0#1 := 0; 216534#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 216531#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 216528#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 216525#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216522#L339-21 assume !(1 == ~t1_pc~0); 216518#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 216514#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216511#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 216508#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 216505#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216502#L358-21 assume !(1 == ~t2_pc~0); 216499#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 216496#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216493#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 216490#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 216487#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216484#L377-21 assume !(1 == ~t3_pc~0); 216479#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 216475#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216472#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 216469#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 216466#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216463#L396-21 assume !(1 == ~t4_pc~0); 216458#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 216455#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 216452#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 216448#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 216444#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 216439#L415-21 assume !(1 == ~t5_pc~0); 216437#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 216435#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216432#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 216430#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 216428#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 216425#L434-21 assume !(1 == ~t6_pc~0); 216422#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 216419#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 216416#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 216412#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 216408#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 216403#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 216399#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 216395#L748-3 assume !(1 == ~T2_E~0); 216390#L753-3 assume !(1 == ~T3_E~0); 216386#L758-3 assume !(1 == ~T4_E~0); 216382#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 216377#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 216373#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 216369#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 216365#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 216361#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 216357#L793-3 assume !(1 == ~E_5~0); 216354#L798-3 assume !(1 == ~E_6~0); 216351#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 216282#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 216272#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 216268#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 216263#L1043 assume !(0 == start_simulation_~tmp~3#1); 216258#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 216255#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 216246#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 216243#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 216240#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 216236#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 216233#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 216230#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 214262#L1024-2 [2024-11-19 15:04:36,846 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:36,846 INFO L85 PathProgramCache]: Analyzing trace with hash 1633801745, now seen corresponding path program 1 times [2024-11-19 15:04:36,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:36,847 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646807887] [2024-11-19 15:04:36,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:36,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:36,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:36,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:36,890 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:36,890 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646807887] [2024-11-19 15:04:36,890 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646807887] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:36,891 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:36,891 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:36,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449017204] [2024-11-19 15:04:36,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:36,891 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:36,892 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:36,892 INFO L85 PathProgramCache]: Analyzing trace with hash 1067351834, now seen corresponding path program 1 times [2024-11-19 15:04:36,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:36,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668272137] [2024-11-19 15:04:36,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:36,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:36,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:36,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:36,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:36,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668272137] [2024-11-19 15:04:36,947 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [668272137] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:36,947 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:36,947 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:04:36,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306423093] [2024-11-19 15:04:36,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:36,948 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:36,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:36,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-19 15:04:36,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-19 15:04:36,948 INFO L87 Difference]: Start difference. First operand 10392 states and 14450 transitions. cyclomatic complexity: 4074 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:37,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:37,188 INFO L93 Difference]: Finished difference Result 19227 states and 26748 transitions. [2024-11-19 15:04:37,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19227 states and 26748 transitions. [2024-11-19 15:04:37,270 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 18168 [2024-11-19 15:04:37,343 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19227 states to 19227 states and 26748 transitions. [2024-11-19 15:04:37,344 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19227 [2024-11-19 15:04:37,363 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19227 [2024-11-19 15:04:37,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19227 states and 26748 transitions. [2024-11-19 15:04:37,382 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:37,382 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19227 states and 26748 transitions. [2024-11-19 15:04:37,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19227 states and 26748 transitions. [2024-11-19 15:04:37,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19227 to 9849. [2024-11-19 15:04:37,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9849 states, 9849 states have (on average 1.3895826987511422) internal successors, (13686), 9848 states have internal predecessors, (13686), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:37,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9849 states to 9849 states and 13686 transitions. [2024-11-19 15:04:37,555 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9849 states and 13686 transitions. [2024-11-19 15:04:37,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-19 15:04:37,556 INFO L425 stractBuchiCegarLoop]: Abstraction has 9849 states and 13686 transitions. [2024-11-19 15:04:37,556 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-19 15:04:37,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9849 states and 13686 transitions. [2024-11-19 15:04:37,586 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9676 [2024-11-19 15:04:37,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:37,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:37,588 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:37,588 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:37,588 INFO L745 eck$LassoCheckResult]: Stem: 244107#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 244108#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 244239#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 244240#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 243762#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 243763#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 244309#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 244470#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 243858#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 243859#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 244023#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 243874#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 243875#L670 assume !(0 == ~M_E~0); 244257#L670-2 assume !(0 == ~T1_E~0); 244203#L675-1 assume !(0 == ~T2_E~0); 244204#L680-1 assume !(0 == ~T3_E~0); 244307#L685-1 assume !(0 == ~T4_E~0); 244266#L690-1 assume !(0 == ~T5_E~0); 244267#L695-1 assume !(0 == ~T6_E~0); 244353#L700-1 assume !(0 == ~E_1~0); 244338#L705-1 assume !(0 == ~E_2~0); 244339#L710-1 assume !(0 == ~E_3~0); 244202#L715-1 assume !(0 == ~E_4~0); 244132#L720-1 assume !(0 == ~E_5~0); 244133#L725-1 assume !(0 == ~E_6~0); 244181#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 244229#L320 assume !(1 == ~m_pc~0); 244377#L320-2 is_master_triggered_~__retres1~0#1 := 0; 244072#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 244065#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 244024#L825 assume !(0 != activate_threads_~tmp~1#1); 244025#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 244035#L339 assume !(1 == ~t1_pc~0); 244036#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 243999#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 243854#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 243855#L833 assume !(0 != activate_threads_~tmp___0~0#1); 243878#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 243787#L358 assume !(1 == ~t2_pc~0); 243788#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 244329#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 244243#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 244185#L841 assume !(0 != activate_threads_~tmp___1~0#1); 244019#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 244020#L377 assume !(1 == ~t3_pc~0); 244286#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 244287#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 243785#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 243786#L849 assume !(0 != activate_threads_~tmp___2~0#1); 244028#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 243958#L396 assume !(1 == ~t4_pc~0); 243959#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 243789#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 243790#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 243940#L857 assume !(0 != activate_threads_~tmp___3~0#1); 243925#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 243926#L415 assume !(1 == ~t5_pc~0); 244006#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 244060#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 244079#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 244080#L865 assume !(0 != activate_threads_~tmp___4~0#1); 243830#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 243831#L434 assume !(1 == ~t6_pc~0); 244164#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 244165#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 244233#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 244234#L873 assume !(0 != activate_threads_~tmp___5~0#1); 244044#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 244045#L743 assume !(1 == ~M_E~0); 243916#L743-2 assume !(1 == ~T1_E~0); 243917#L748-1 assume !(1 == ~T2_E~0); 244223#L753-1 assume !(1 == ~T3_E~0); 244224#L758-1 assume !(1 == ~T4_E~0); 244356#L763-1 assume !(1 == ~T5_E~0); 244414#L768-1 assume !(1 == ~T6_E~0); 244042#L773-1 assume !(1 == ~E_1~0); 244043#L778-1 assume !(1 == ~E_2~0); 244014#L783-1 assume !(1 == ~E_3~0); 244015#L788-1 assume !(1 == ~E_4~0); 244305#L793-1 assume !(1 == ~E_5~0); 244249#L798-1 assume !(1 == ~E_6~0); 243898#L803-1 assume { :end_inline_reset_delta_events } true; 243899#L1024-2 [2024-11-19 15:04:37,589 INFO L747 eck$LassoCheckResult]: Loop: 243899#L1024-2 assume !false; 247411#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 247402#L645-1 assume !false; 247398#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 247371#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 247360#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 247352#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 247345#L556 assume !(0 != eval_~tmp~0#1); 247346#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 247705#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 247704#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 247703#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 247702#L675-3 assume !(0 == ~T2_E~0); 247701#L680-3 assume !(0 == ~T3_E~0); 247700#L685-3 assume !(0 == ~T4_E~0); 247699#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 247698#L695-3 assume !(0 == ~T6_E~0); 247697#L700-3 assume !(0 == ~E_1~0); 247696#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 247695#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 247694#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 247693#L720-3 assume !(0 == ~E_5~0); 247692#L725-3 assume !(0 == ~E_6~0); 247691#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247690#L320-21 assume !(1 == ~m_pc~0); 247689#L320-23 is_master_triggered_~__retres1~0#1 := 0; 247688#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247687#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 247686#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 247685#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247684#L339-21 assume !(1 == ~t1_pc~0); 247683#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 247681#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247680#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 247679#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 247678#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247677#L358-21 assume !(1 == ~t2_pc~0); 247676#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 247675#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247674#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 247673#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 247672#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247671#L377-21 assume !(1 == ~t3_pc~0); 247670#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 247667#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247665#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 247663#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 247661#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247659#L396-21 assume !(1 == ~t4_pc~0); 247657#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 247655#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247652#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 247650#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 247648#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247646#L415-21 assume !(1 == ~t5_pc~0); 247644#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 247642#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247640#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 247638#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 247635#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 247632#L434-21 assume !(1 == ~t6_pc~0); 247628#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 247625#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 247621#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 247618#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 247615#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 247611#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 247608#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 247605#L748-3 assume !(1 == ~T2_E~0); 247602#L753-3 assume !(1 == ~T3_E~0); 247599#L758-3 assume !(1 == ~T4_E~0); 247596#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 247593#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 247590#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 247587#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 247584#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 247581#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 247578#L793-3 assume !(1 == ~E_5~0); 247574#L798-3 assume !(1 == ~E_6~0); 247571#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 247535#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 247525#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 247521#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 247516#L1043 assume !(0 == start_simulation_~tmp~3#1); 247511#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 247481#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 247471#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 247464#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 247459#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 247454#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 247453#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 247440#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 243899#L1024-2 [2024-11-19 15:04:37,589 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:37,589 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 3 times [2024-11-19 15:04:37,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:37,590 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243895477] [2024-11-19 15:04:37,590 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 15:04:37,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:37,600 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 15:04:37,600 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:04:37,600 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:37,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:37,624 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:37,625 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:37,625 INFO L85 PathProgramCache]: Analyzing trace with hash 1067351834, now seen corresponding path program 2 times [2024-11-19 15:04:37,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:37,626 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713025317] [2024-11-19 15:04:37,626 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:04:37,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:37,637 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:04:37,637 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-19 15:04:37,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:37,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:37,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713025317] [2024-11-19 15:04:37,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713025317] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:37,682 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:37,682 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:04:37,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012872855] [2024-11-19 15:04:37,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:37,682 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:37,682 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:37,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:04:37,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:04:37,683 INFO L87 Difference]: Start difference. First operand 9849 states and 13686 transitions. cyclomatic complexity: 3853 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:37,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:37,791 INFO L93 Difference]: Finished difference Result 9985 states and 13822 transitions. [2024-11-19 15:04:37,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9985 states and 13822 transitions. [2024-11-19 15:04:37,832 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9812 [2024-11-19 15:04:37,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9985 states to 9985 states and 13822 transitions. [2024-11-19 15:04:37,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9985 [2024-11-19 15:04:37,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9985 [2024-11-19 15:04:37,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9985 states and 13822 transitions. [2024-11-19 15:04:37,881 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:37,882 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9985 states and 13822 transitions. [2024-11-19 15:04:37,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9985 states and 13822 transitions. [2024-11-19 15:04:37,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9985 to 9921. [2024-11-19 15:04:37,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9921 states, 9921 states have (on average 1.3867553674024795) internal successors, (13758), 9920 states have internal predecessors, (13758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:37,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9921 states to 9921 states and 13758 transitions. [2024-11-19 15:04:38,000 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9921 states and 13758 transitions. [2024-11-19 15:04:38,000 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:04:38,001 INFO L425 stractBuchiCegarLoop]: Abstraction has 9921 states and 13758 transitions. [2024-11-19 15:04:38,001 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-19 15:04:38,001 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9921 states and 13758 transitions. [2024-11-19 15:04:38,033 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9748 [2024-11-19 15:04:38,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:38,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:38,035 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:38,035 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:38,035 INFO L745 eck$LassoCheckResult]: Stem: 263950#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 263951#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 264082#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 264083#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 263604#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 263605#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 264152#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 264318#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 263697#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 263698#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 263864#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 263713#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 263714#L670 assume !(0 == ~M_E~0); 264098#L670-2 assume !(0 == ~T1_E~0); 264046#L675-1 assume !(0 == ~T2_E~0); 264047#L680-1 assume !(0 == ~T3_E~0); 264151#L685-1 assume !(0 == ~T4_E~0); 264107#L690-1 assume !(0 == ~T5_E~0); 264108#L695-1 assume !(0 == ~T6_E~0); 264200#L700-1 assume !(0 == ~E_1~0); 264186#L705-1 assume !(0 == ~E_2~0); 264187#L710-1 assume !(0 == ~E_3~0); 264045#L715-1 assume !(0 == ~E_4~0); 263976#L720-1 assume !(0 == ~E_5~0); 263977#L725-1 assume !(0 == ~E_6~0); 264025#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264071#L320 assume !(1 == ~m_pc~0); 264224#L320-2 is_master_triggered_~__retres1~0#1 := 0; 263913#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 263906#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 263865#L825 assume !(0 != activate_threads_~tmp~1#1); 263866#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 263869#L339 assume !(1 == ~t1_pc~0); 263870#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 263841#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 263695#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 263696#L833 assume !(0 != activate_threads_~tmp___0~0#1); 263718#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 263629#L358 assume !(1 == ~t2_pc~0); 263630#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 264176#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264087#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 264028#L841 assume !(0 != activate_threads_~tmp___1~0#1); 263860#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 263861#L377 assume !(1 == ~t3_pc~0); 264129#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 264130#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 263625#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 263626#L849 assume !(0 != activate_threads_~tmp___2~0#1); 263868#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 263797#L396 assume !(1 == ~t4_pc~0); 263798#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 263631#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263632#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 263779#L857 assume !(0 != activate_threads_~tmp___3~0#1); 263764#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 263765#L415 assume !(1 == ~t5_pc~0); 263846#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 263900#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 263917#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 263918#L865 assume !(0 != activate_threads_~tmp___4~0#1); 263672#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 263673#L434 assume !(1 == ~t6_pc~0); 264007#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 264008#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 264075#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 264076#L873 assume !(0 != activate_threads_~tmp___5~0#1); 263884#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 263885#L743 assume !(1 == ~M_E~0); 263755#L743-2 assume !(1 == ~T1_E~0); 263756#L748-1 assume !(1 == ~T2_E~0); 264064#L753-1 assume !(1 == ~T3_E~0); 264065#L758-1 assume !(1 == ~T4_E~0); 264202#L763-1 assume !(1 == ~T5_E~0); 264263#L768-1 assume !(1 == ~T6_E~0); 263880#L773-1 assume !(1 == ~E_1~0); 263881#L778-1 assume !(1 == ~E_2~0); 263855#L783-1 assume !(1 == ~E_3~0); 263856#L788-1 assume !(1 == ~E_4~0); 264149#L793-1 assume !(1 == ~E_5~0); 264094#L798-1 assume !(1 == ~E_6~0); 263736#L803-1 assume { :end_inline_reset_delta_events } true; 263737#L1024-2 [2024-11-19 15:04:38,036 INFO L747 eck$LassoCheckResult]: Loop: 263737#L1024-2 assume !false; 271441#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 271438#L645-1 assume !false; 271437#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 271436#L504 assume !(0 == ~m_st~0); 271431#L508 assume !(0 == ~t1_st~0); 271432#L512 assume !(0 == ~t2_st~0); 271434#L516 assume !(0 == ~t3_st~0); 271429#L520 assume !(0 == ~t4_st~0); 271430#L524 assume !(0 == ~t5_st~0); 271433#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 271435#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 270987#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 270988#L556 assume !(0 != eval_~tmp~0#1); 271862#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 271861#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 271860#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 271859#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 271858#L675-3 assume !(0 == ~T2_E~0); 271857#L680-3 assume !(0 == ~T3_E~0); 271856#L685-3 assume !(0 == ~T4_E~0); 271855#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 271854#L695-3 assume !(0 == ~T6_E~0); 271853#L700-3 assume !(0 == ~E_1~0); 271852#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 271851#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 271850#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 271849#L720-3 assume !(0 == ~E_5~0); 271848#L725-3 assume !(0 == ~E_6~0); 271847#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 271846#L320-21 assume !(1 == ~m_pc~0); 271845#L320-23 is_master_triggered_~__retres1~0#1 := 0; 271844#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 271843#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 271842#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 271841#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 271840#L339-21 assume 1 == ~t1_pc~0; 271838#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 271837#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 271836#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 271835#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 271834#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 271833#L358-21 assume !(1 == ~t2_pc~0); 271832#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 271831#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 271830#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 271829#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 271828#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 271827#L377-21 assume 1 == ~t3_pc~0; 271825#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 271824#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 271823#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 271822#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 271821#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 271820#L396-21 assume !(1 == ~t4_pc~0); 271819#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 271818#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 271817#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 271816#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 271815#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 271814#L415-21 assume !(1 == ~t5_pc~0); 271813#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 271812#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 271811#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 271810#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 271809#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 271808#L434-21 assume !(1 == ~t6_pc~0); 271806#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 271805#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 271804#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 271803#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 271802#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 271801#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 271800#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 271799#L748-3 assume !(1 == ~T2_E~0); 271798#L753-3 assume !(1 == ~T3_E~0); 271797#L758-3 assume !(1 == ~T4_E~0); 271796#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 271795#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 271794#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 271793#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 271792#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 271791#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 271790#L793-3 assume !(1 == ~E_5~0); 271789#L798-3 assume !(1 == ~E_6~0); 271788#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 271787#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 271746#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 271688#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 271685#L1043 assume !(0 == start_simulation_~tmp~3#1); 271683#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 271682#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 271490#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 271451#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 271450#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 271449#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 271447#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 271445#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 263737#L1024-2 [2024-11-19 15:04:38,036 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:38,036 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 4 times [2024-11-19 15:04:38,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:38,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412137029] [2024-11-19 15:04:38,038 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 15:04:38,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:38,051 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 15:04:38,052 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:04:38,052 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:38,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:38,078 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:38,079 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:38,079 INFO L85 PathProgramCache]: Analyzing trace with hash -1313003349, now seen corresponding path program 1 times [2024-11-19 15:04:38,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:38,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474591161] [2024-11-19 15:04:38,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:38,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:38,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:38,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:38,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:38,160 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474591161] [2024-11-19 15:04:38,160 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1474591161] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:38,160 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:38,160 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-19 15:04:38,160 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418541425] [2024-11-19 15:04:38,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:38,161 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:38,161 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:38,161 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-19 15:04:38,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-19 15:04:38,162 INFO L87 Difference]: Start difference. First operand 9921 states and 13758 transitions. cyclomatic complexity: 3853 Second operand has 5 states, 5 states have (on average 19.6) internal successors, (98), 5 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:38,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:38,340 INFO L93 Difference]: Finished difference Result 10143 states and 13917 transitions. [2024-11-19 15:04:38,340 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10143 states and 13917 transitions. [2024-11-19 15:04:38,383 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9970 [2024-11-19 15:04:38,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10143 states to 10143 states and 13917 transitions. [2024-11-19 15:04:38,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10143 [2024-11-19 15:04:38,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10143 [2024-11-19 15:04:38,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10143 states and 13917 transitions. [2024-11-19 15:04:38,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:38,428 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10143 states and 13917 transitions. [2024-11-19 15:04:38,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10143 states and 13917 transitions. [2024-11-19 15:04:38,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10143 to 10143. [2024-11-19 15:04:38,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10143 states, 10143 states have (on average 1.3720792664892043) internal successors, (13917), 10142 states have internal predecessors, (13917), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:38,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10143 states to 10143 states and 13917 transitions. [2024-11-19 15:04:38,544 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10143 states and 13917 transitions. [2024-11-19 15:04:38,544 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-19 15:04:38,545 INFO L425 stractBuchiCegarLoop]: Abstraction has 10143 states and 13917 transitions. [2024-11-19 15:04:38,545 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-19 15:04:38,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10143 states and 13917 transitions. [2024-11-19 15:04:38,576 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9970 [2024-11-19 15:04:38,576 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:38,576 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:38,577 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:38,577 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:38,578 INFO L745 eck$LassoCheckResult]: Stem: 284022#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 284023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 284154#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 284155#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 283676#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 283677#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 284219#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 284386#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 283770#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 283771#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 283937#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 283786#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 283787#L670 assume !(0 == ~M_E~0); 284169#L670-2 assume !(0 == ~T1_E~0); 284119#L675-1 assume !(0 == ~T2_E~0); 284120#L680-1 assume !(0 == ~T3_E~0); 284217#L685-1 assume !(0 == ~T4_E~0); 284177#L690-1 assume !(0 == ~T5_E~0); 284178#L695-1 assume !(0 == ~T6_E~0); 284263#L700-1 assume !(0 == ~E_1~0); 284247#L705-1 assume !(0 == ~E_2~0); 284248#L710-1 assume !(0 == ~E_3~0); 284118#L715-1 assume !(0 == ~E_4~0); 284047#L720-1 assume !(0 == ~E_5~0); 284048#L725-1 assume !(0 == ~E_6~0); 284098#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 284144#L320 assume !(1 == ~m_pc~0); 284283#L320-2 is_master_triggered_~__retres1~0#1 := 0; 283988#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 283980#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 283938#L825 assume !(0 != activate_threads_~tmp~1#1); 283939#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 283945#L339 assume !(1 == ~t1_pc~0); 283946#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 283914#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 283766#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 283767#L833 assume !(0 != activate_threads_~tmp___0~0#1); 283790#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 283701#L358 assume !(1 == ~t2_pc~0); 283702#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 284238#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 284157#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 284101#L841 assume !(0 != activate_threads_~tmp___1~0#1); 283933#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 283934#L377 assume !(1 == ~t3_pc~0); 284199#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 284200#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 283699#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 283700#L849 assume !(0 != activate_threads_~tmp___2~0#1); 283941#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 283870#L396 assume !(1 == ~t4_pc~0); 283871#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 283703#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 283704#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 283852#L857 assume !(0 != activate_threads_~tmp___3~0#1); 283836#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 283837#L415 assume !(1 == ~t5_pc~0); 283921#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 283975#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 283995#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 283996#L865 assume !(0 != activate_threads_~tmp___4~0#1); 283742#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 283743#L434 assume !(1 == ~t6_pc~0); 284080#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 284081#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 284148#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 284149#L873 assume !(0 != activate_threads_~tmp___5~0#1); 283958#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 283959#L743 assume !(1 == ~M_E~0); 283827#L743-2 assume !(1 == ~T1_E~0); 283828#L748-1 assume !(1 == ~T2_E~0); 284140#L753-1 assume !(1 == ~T3_E~0); 284141#L758-1 assume !(1 == ~T4_E~0); 284265#L763-1 assume !(1 == ~T5_E~0); 284326#L768-1 assume !(1 == ~T6_E~0); 283956#L773-1 assume !(1 == ~E_1~0); 283957#L778-1 assume !(1 == ~E_2~0); 283928#L783-1 assume !(1 == ~E_3~0); 283929#L788-1 assume !(1 == ~E_4~0); 284215#L793-1 assume !(1 == ~E_5~0); 284165#L798-1 assume !(1 == ~E_6~0); 283809#L803-1 assume { :end_inline_reset_delta_events } true; 283810#L1024-2 [2024-11-19 15:04:38,578 INFO L747 eck$LassoCheckResult]: Loop: 283810#L1024-2 assume !false; 286058#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 286054#L645-1 assume !false; 286053#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 286052#L504 assume !(0 == ~m_st~0); 286047#L508 assume !(0 == ~t1_st~0); 286048#L512 assume !(0 == ~t2_st~0); 286050#L516 assume !(0 == ~t3_st~0); 286045#L520 assume !(0 == ~t4_st~0); 286046#L524 assume !(0 == ~t5_st~0); 286049#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 286051#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 285452#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 285453#L556 assume !(0 != eval_~tmp~0#1); 286225#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 286224#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 286223#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 286222#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 286221#L675-3 assume !(0 == ~T2_E~0); 286220#L680-3 assume !(0 == ~T3_E~0); 286219#L685-3 assume !(0 == ~T4_E~0); 286218#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 286217#L695-3 assume !(0 == ~T6_E~0); 286216#L700-3 assume !(0 == ~E_1~0); 286215#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 286214#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 286213#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 286212#L720-3 assume !(0 == ~E_5~0); 286211#L725-3 assume !(0 == ~E_6~0); 286210#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 286209#L320-21 assume !(1 == ~m_pc~0); 286208#L320-23 is_master_triggered_~__retres1~0#1 := 0; 286207#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 286206#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 286205#L825-21 assume !(0 != activate_threads_~tmp~1#1); 286203#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 286201#L339-21 assume 1 == ~t1_pc~0; 286198#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 286196#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 286194#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 286192#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 286190#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 286187#L358-21 assume !(1 == ~t2_pc~0); 286185#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 286183#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 286181#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 286179#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 286177#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 286175#L377-21 assume 1 == ~t3_pc~0; 286172#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 286170#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 286168#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 286166#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 286164#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 286161#L396-21 assume !(1 == ~t4_pc~0); 286159#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 286157#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 286155#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 286153#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 286151#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 286149#L415-21 assume !(1 == ~t5_pc~0); 286147#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 286145#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 286143#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 286141#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 286139#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 286137#L434-21 assume !(1 == ~t6_pc~0); 286134#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 286132#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 286130#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 286128#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 286125#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 286123#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 286121#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 286119#L748-3 assume !(1 == ~T2_E~0); 286117#L753-3 assume !(1 == ~T3_E~0); 286115#L758-3 assume !(1 == ~T4_E~0); 286113#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 286111#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 286109#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 286107#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 286105#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 286103#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 286101#L793-3 assume !(1 == ~E_5~0); 286099#L798-3 assume !(1 == ~E_6~0); 286097#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 286095#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 286087#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 286085#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 286082#L1043 assume !(0 == start_simulation_~tmp~3#1); 286080#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 286079#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 286072#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 286071#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 286070#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 286069#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 286067#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 286065#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 283810#L1024-2 [2024-11-19 15:04:38,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:38,579 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 5 times [2024-11-19 15:04:38,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:38,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [129168008] [2024-11-19 15:04:38,579 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 15:04:38,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:38,590 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:04:38,590 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:04:38,590 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:38,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:38,608 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:38,609 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:38,609 INFO L85 PathProgramCache]: Analyzing trace with hash -1367396247, now seen corresponding path program 1 times [2024-11-19 15:04:38,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:38,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453178608] [2024-11-19 15:04:38,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:38,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:38,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:38,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:38,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:38,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1453178608] [2024-11-19 15:04:38,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1453178608] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:38,653 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:38,653 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:38,653 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1759808169] [2024-11-19 15:04:38,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:38,654 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-19 15:04:38,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:38,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:38,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:38,656 INFO L87 Difference]: Start difference. First operand 10143 states and 13917 transitions. cyclomatic complexity: 3790 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:38,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:38,771 INFO L93 Difference]: Finished difference Result 17623 states and 23871 transitions. [2024-11-19 15:04:38,771 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17623 states and 23871 transitions. [2024-11-19 15:04:38,851 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 17384 [2024-11-19 15:04:38,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17623 states to 17623 states and 23871 transitions. [2024-11-19 15:04:38,910 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17623 [2024-11-19 15:04:38,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17623 [2024-11-19 15:04:38,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17623 states and 23871 transitions. [2024-11-19 15:04:38,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:38,941 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17623 states and 23871 transitions. [2024-11-19 15:04:38,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17623 states and 23871 transitions. [2024-11-19 15:04:39,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17623 to 17087. [2024-11-19 15:04:39,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17087 states, 17087 states have (on average 1.3565283548896823) internal successors, (23179), 17086 states have internal predecessors, (23179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:39,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17087 states to 17087 states and 23179 transitions. [2024-11-19 15:04:39,198 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17087 states and 23179 transitions. [2024-11-19 15:04:39,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:39,199 INFO L425 stractBuchiCegarLoop]: Abstraction has 17087 states and 23179 transitions. [2024-11-19 15:04:39,199 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-19 15:04:39,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17087 states and 23179 transitions. [2024-11-19 15:04:39,250 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 16848 [2024-11-19 15:04:39,251 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:39,251 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:39,252 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:39,253 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:39,253 INFO L745 eck$LassoCheckResult]: Stem: 311793#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 311794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 311922#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 311923#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 311448#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 311449#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 311987#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 312143#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 311543#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 311544#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 311712#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 311559#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 311560#L670 assume !(0 == ~M_E~0); 311939#L670-2 assume !(0 == ~T1_E~0); 311887#L675-1 assume !(0 == ~T2_E~0); 311888#L680-1 assume !(0 == ~T3_E~0); 311985#L685-1 assume !(0 == ~T4_E~0); 311945#L690-1 assume !(0 == ~T5_E~0); 311946#L695-1 assume !(0 == ~T6_E~0); 312026#L700-1 assume !(0 == ~E_1~0); 312013#L705-1 assume !(0 == ~E_2~0); 312014#L710-1 assume !(0 == ~E_3~0); 311886#L715-1 assume !(0 == ~E_4~0); 311818#L720-1 assume !(0 == ~E_5~0); 311819#L725-1 assume !(0 == ~E_6~0); 311866#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 311912#L320 assume !(1 == ~m_pc~0); 312049#L320-2 is_master_triggered_~__retres1~0#1 := 0; 311759#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 311752#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 311713#L825 assume !(0 != activate_threads_~tmp~1#1); 311714#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 311721#L339 assume !(1 == ~t1_pc~0); 311722#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 311689#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 311539#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 311540#L833 assume !(0 != activate_threads_~tmp___0~0#1); 311563#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 311473#L358 assume !(1 == ~t2_pc~0); 311474#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 312005#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 311927#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 311869#L841 assume !(0 != activate_threads_~tmp___1~0#1); 311708#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 311709#L377 assume !(1 == ~t3_pc~0); 311966#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 311967#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 311471#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 311472#L849 assume !(0 != activate_threads_~tmp___2~0#1); 311716#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 311645#L396 assume !(1 == ~t4_pc~0); 311646#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 311475#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 311476#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 311624#L857 assume !(0 != activate_threads_~tmp___3~0#1); 311609#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 311610#L415 assume !(1 == ~t5_pc~0); 311696#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 311746#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 311766#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 311767#L865 assume !(0 != activate_threads_~tmp___4~0#1); 311516#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 311517#L434 assume !(1 == ~t6_pc~0); 311849#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 311850#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 311916#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 311917#L873 assume !(0 != activate_threads_~tmp___5~0#1); 311730#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 311731#L743 assume !(1 == ~M_E~0); 311599#L743-2 assume !(1 == ~T1_E~0); 311600#L748-1 assume !(1 == ~T2_E~0); 311906#L753-1 assume !(1 == ~T3_E~0); 311907#L758-1 assume !(1 == ~T4_E~0); 312028#L763-1 assume !(1 == ~T5_E~0); 312090#L768-1 assume !(1 == ~T6_E~0); 311728#L773-1 assume !(1 == ~E_1~0); 311729#L778-1 assume !(1 == ~E_2~0); 311703#L783-1 assume !(1 == ~E_3~0); 311704#L788-1 assume !(1 == ~E_4~0); 311983#L793-1 assume !(1 == ~E_5~0); 311934#L798-1 assume !(1 == ~E_6~0); 311582#L803-1 assume { :end_inline_reset_delta_events } true; 311583#L1024-2 assume !false; 317002#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 316997#L645-1 [2024-11-19 15:04:39,253 INFO L747 eck$LassoCheckResult]: Loop: 316997#L645-1 assume !false; 316996#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 316994#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 316992#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 316990#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 316988#L556 assume 0 != eval_~tmp~0#1; 316985#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 316982#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 316980#L564-2 havoc eval_~tmp_ndt_1~0#1; 316977#L561-1 assume !(0 == ~t1_st~0); 316972#L575-1 assume !(0 == ~t2_st~0); 316968#L589-1 assume !(0 == ~t3_st~0); 316913#L603-1 assume !(0 == ~t4_st~0); 316903#L617-1 assume !(0 == ~t5_st~0); 316904#L631-1 assume !(0 == ~t6_st~0); 316997#L645-1 [2024-11-19 15:04:39,254 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:39,254 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 1 times [2024-11-19 15:04:39,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:39,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329564852] [2024-11-19 15:04:39,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:39,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:39,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:39,268 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:39,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:39,292 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:39,293 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:39,293 INFO L85 PathProgramCache]: Analyzing trace with hash -2144970051, now seen corresponding path program 1 times [2024-11-19 15:04:39,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:39,293 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2132211852] [2024-11-19 15:04:39,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:39,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:39,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:39,297 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:39,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:39,301 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:39,301 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:39,301 INFO L85 PathProgramCache]: Analyzing trace with hash -444216697, now seen corresponding path program 1 times [2024-11-19 15:04:39,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:39,301 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142126958] [2024-11-19 15:04:39,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:39,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:39,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:39,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:39,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:39,346 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142126958] [2024-11-19 15:04:39,347 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142126958] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:39,347 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:39,347 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:39,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1791630068] [2024-11-19 15:04:39,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:39,449 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:39,450 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:39,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:39,450 INFO L87 Difference]: Start difference. First operand 17087 states and 23179 transitions. cyclomatic complexity: 6118 Second operand has 3 states, 3 states have (on average 33.0) internal successors, (99), 3 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:39,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:39,618 INFO L93 Difference]: Finished difference Result 32100 states and 43203 transitions. [2024-11-19 15:04:39,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32100 states and 43203 transitions. [2024-11-19 15:04:39,762 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 31628 [2024-11-19 15:04:39,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32100 states to 32100 states and 43203 transitions. [2024-11-19 15:04:39,877 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32100 [2024-11-19 15:04:39,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32100 [2024-11-19 15:04:39,903 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32100 states and 43203 transitions. [2024-11-19 15:04:39,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:39,928 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32100 states and 43203 transitions. [2024-11-19 15:04:39,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32100 states and 43203 transitions. [2024-11-19 15:04:40,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32100 to 30292. [2024-11-19 15:04:40,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30292 states, 30292 states have (on average 1.3506866499405783) internal successors, (40915), 30291 states have internal predecessors, (40915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:40,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30292 states to 30292 states and 40915 transitions. [2024-11-19 15:04:40,282 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30292 states and 40915 transitions. [2024-11-19 15:04:40,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:40,283 INFO L425 stractBuchiCegarLoop]: Abstraction has 30292 states and 40915 transitions. [2024-11-19 15:04:40,283 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-19 15:04:40,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30292 states and 40915 transitions. [2024-11-19 15:04:40,371 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 29820 [2024-11-19 15:04:40,372 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:40,372 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:40,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:40,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:40,373 INFO L745 eck$LassoCheckResult]: Stem: 360984#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 360985#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 361126#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 361127#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 360643#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 360644#L461-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 361192#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 366673#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 366672#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 366671#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 366670#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 366669#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 366668#L670 assume !(0 == ~M_E~0); 366667#L670-2 assume !(0 == ~T1_E~0); 366666#L675-1 assume !(0 == ~T2_E~0); 366665#L680-1 assume !(0 == ~T3_E~0); 366664#L685-1 assume !(0 == ~T4_E~0); 366663#L690-1 assume !(0 == ~T5_E~0); 366662#L695-1 assume !(0 == ~T6_E~0); 366661#L700-1 assume !(0 == ~E_1~0); 366660#L705-1 assume !(0 == ~E_2~0); 366659#L710-1 assume !(0 == ~E_3~0); 366658#L715-1 assume !(0 == ~E_4~0); 366657#L720-1 assume !(0 == ~E_5~0); 366656#L725-1 assume !(0 == ~E_6~0); 366655#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 366654#L320 assume !(1 == ~m_pc~0); 366653#L320-2 is_master_triggered_~__retres1~0#1 := 0; 366652#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 366651#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 366650#L825 assume !(0 != activate_threads_~tmp~1#1); 366649#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 366648#L339 assume !(1 == ~t1_pc~0); 366646#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 366645#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 366644#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 366643#L833 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 360756#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 360668#L358 assume !(1 == ~t2_pc~0); 360669#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 361224#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 361129#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 361068#L841 assume !(0 != activate_threads_~tmp___1~0#1); 360897#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 360898#L377 assume !(1 == ~t3_pc~0); 361171#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 361172#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 360664#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 360665#L849 assume !(0 != activate_threads_~tmp___2~0#1); 360906#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 360834#L396 assume !(1 == ~t4_pc~0); 360835#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 360670#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 360671#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 360816#L857 assume !(0 != activate_threads_~tmp___3~0#1); 360801#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 360802#L415 assume !(1 == ~t5_pc~0); 360881#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 360934#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 360955#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 360956#L865 assume !(0 != activate_threads_~tmp___4~0#1); 360711#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 360712#L434 assume !(1 == ~t6_pc~0); 366082#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 366081#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 366080#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 366079#L873 assume !(0 != activate_threads_~tmp___5~0#1); 366078#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 366077#L743 assume !(1 == ~M_E~0); 366076#L743-2 assume !(1 == ~T1_E~0); 366075#L748-1 assume !(1 == ~T2_E~0); 366074#L753-1 assume !(1 == ~T3_E~0); 366073#L758-1 assume !(1 == ~T4_E~0); 366072#L763-1 assume !(1 == ~T5_E~0); 366071#L768-1 assume !(1 == ~T6_E~0); 366070#L773-1 assume !(1 == ~E_1~0); 366069#L778-1 assume !(1 == ~E_2~0); 366068#L783-1 assume !(1 == ~E_3~0); 366065#L788-1 assume !(1 == ~E_4~0); 361189#L793-1 assume !(1 == ~E_5~0); 361134#L798-1 assume !(1 == ~E_6~0); 360773#L803-1 assume { :end_inline_reset_delta_events } true; 360774#L1024-2 assume !false; 368693#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 368688#L645-1 [2024-11-19 15:04:40,373 INFO L747 eck$LassoCheckResult]: Loop: 368688#L645-1 assume !false; 368686#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 368683#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 368681#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 368679#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 368676#L556 assume 0 != eval_~tmp~0#1; 368673#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 368670#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 368668#L564-2 havoc eval_~tmp_ndt_1~0#1; 368666#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 366695#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 368662#L578-2 havoc eval_~tmp_ndt_2~0#1; 368659#L575-1 assume !(0 == ~t2_st~0); 368660#L589-1 assume !(0 == ~t3_st~0); 368732#L603-1 assume !(0 == ~t4_st~0); 368725#L617-1 assume !(0 == ~t5_st~0); 368690#L631-1 assume !(0 == ~t6_st~0); 368688#L645-1 [2024-11-19 15:04:40,374 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:40,374 INFO L85 PathProgramCache]: Analyzing trace with hash -1610041797, now seen corresponding path program 1 times [2024-11-19 15:04:40,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:40,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962932400] [2024-11-19 15:04:40,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:40,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:40,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:40,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:40,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:40,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1962932400] [2024-11-19 15:04:40,405 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1962932400] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:40,405 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:40,405 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:40,405 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [750340532] [2024-11-19 15:04:40,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:40,406 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-19 15:04:40,406 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:40,406 INFO L85 PathProgramCache]: Analyzing trace with hash 2044493828, now seen corresponding path program 1 times [2024-11-19 15:04:40,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:40,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122268861] [2024-11-19 15:04:40,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:40,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:40,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:40,413 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:40,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:40,417 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:40,497 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:40,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:40,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:40,497 INFO L87 Difference]: Start difference. First operand 30292 states and 40915 transitions. cyclomatic complexity: 10649 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:40,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:40,629 INFO L93 Difference]: Finished difference Result 30211 states and 40806 transitions. [2024-11-19 15:04:40,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30211 states and 40806 transitions. [2024-11-19 15:04:40,771 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 29820 [2024-11-19 15:04:41,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30211 states to 30211 states and 40806 transitions. [2024-11-19 15:04:41,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30211 [2024-11-19 15:04:41,135 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30211 [2024-11-19 15:04:41,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30211 states and 40806 transitions. [2024-11-19 15:04:41,152 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:41,152 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30211 states and 40806 transitions. [2024-11-19 15:04:41,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30211 states and 40806 transitions. [2024-11-19 15:04:41,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30211 to 30211. [2024-11-19 15:04:41,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30211 states, 30211 states have (on average 1.3507000761312105) internal successors, (40806), 30210 states have internal predecessors, (40806), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:41,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30211 states to 30211 states and 40806 transitions. [2024-11-19 15:04:41,726 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30211 states and 40806 transitions. [2024-11-19 15:04:41,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:41,727 INFO L425 stractBuchiCegarLoop]: Abstraction has 30211 states and 40806 transitions. [2024-11-19 15:04:41,727 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-19 15:04:41,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30211 states and 40806 transitions. [2024-11-19 15:04:41,835 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 29820 [2024-11-19 15:04:41,835 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:41,835 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:41,837 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:41,837 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:41,838 INFO L745 eck$LassoCheckResult]: Stem: 421502#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 421503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 421639#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 421640#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 421152#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 421153#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 421710#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 421895#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 421245#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 421246#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 421412#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 421260#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 421261#L670 assume !(0 == ~M_E~0); 421657#L670-2 assume !(0 == ~T1_E~0); 421602#L675-1 assume !(0 == ~T2_E~0); 421603#L680-1 assume !(0 == ~T3_E~0); 421708#L685-1 assume !(0 == ~T4_E~0); 421666#L690-1 assume !(0 == ~T5_E~0); 421667#L695-1 assume !(0 == ~T6_E~0); 421760#L700-1 assume !(0 == ~E_1~0); 421745#L705-1 assume !(0 == ~E_2~0); 421746#L710-1 assume !(0 == ~E_3~0); 421601#L715-1 assume !(0 == ~E_4~0); 421528#L720-1 assume !(0 == ~E_5~0); 421529#L725-1 assume !(0 == ~E_6~0); 421581#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 421628#L320 assume !(1 == ~m_pc~0); 421785#L320-2 is_master_triggered_~__retres1~0#1 := 0; 421460#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 421453#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 421413#L825 assume !(0 != activate_threads_~tmp~1#1); 421414#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 421423#L339 assume !(1 == ~t1_pc~0); 421424#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 421387#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 421241#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 421242#L833 assume !(0 != activate_threads_~tmp___0~0#1); 421264#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 421177#L358 assume !(1 == ~t2_pc~0); 421178#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 421736#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 421643#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 421584#L841 assume !(0 != activate_threads_~tmp___1~0#1); 421408#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 421409#L377 assume !(1 == ~t3_pc~0); 421689#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 421690#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 421175#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 421176#L849 assume !(0 != activate_threads_~tmp___2~0#1); 421416#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 421346#L396 assume !(1 == ~t4_pc~0); 421347#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 421179#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 421180#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 421327#L857 assume !(0 != activate_threads_~tmp___3~0#1); 421311#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 421312#L415 assume !(1 == ~t5_pc~0); 421395#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 421448#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 421467#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 421468#L865 assume !(0 != activate_threads_~tmp___4~0#1); 421219#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 421220#L434 assume !(1 == ~t6_pc~0); 421562#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 421563#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 421633#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 421634#L873 assume !(0 != activate_threads_~tmp___5~0#1); 421432#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 421433#L743 assume !(1 == ~M_E~0); 421301#L743-2 assume !(1 == ~T1_E~0); 421302#L748-1 assume !(1 == ~T2_E~0); 421621#L753-1 assume !(1 == ~T3_E~0); 421622#L758-1 assume !(1 == ~T4_E~0); 421762#L763-1 assume !(1 == ~T5_E~0); 421835#L768-1 assume !(1 == ~T6_E~0); 421430#L773-1 assume !(1 == ~E_1~0); 421431#L778-1 assume !(1 == ~E_2~0); 421403#L783-1 assume !(1 == ~E_3~0); 421404#L788-1 assume !(1 == ~E_4~0); 421706#L793-1 assume !(1 == ~E_5~0); 421649#L798-1 assume !(1 == ~E_6~0); 421283#L803-1 assume { :end_inline_reset_delta_events } true; 421284#L1024-2 assume !false; 430550#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 430541#L645-1 [2024-11-19 15:04:41,838 INFO L747 eck$LassoCheckResult]: Loop: 430541#L645-1 assume !false; 430536#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 430531#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 430527#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 430518#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 430509#L556 assume 0 != eval_~tmp~0#1; 430504#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 430498#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 430499#L564-2 havoc eval_~tmp_ndt_1~0#1; 430519#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 430496#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 430506#L578-2 havoc eval_~tmp_ndt_2~0#1; 430500#L575-1 assume !(0 == ~t2_st~0); 430501#L589-1 assume !(0 == ~t3_st~0); 430565#L603-1 assume !(0 == ~t4_st~0); 430555#L617-1 assume !(0 == ~t5_st~0); 430547#L631-1 assume !(0 == ~t6_st~0); 430541#L645-1 [2024-11-19 15:04:41,839 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:41,839 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 2 times [2024-11-19 15:04:41,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:41,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159948265] [2024-11-19 15:04:41,840 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:04:41,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:41,854 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:04:41,854 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:04:41,854 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:41,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:41,877 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:41,880 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:41,880 INFO L85 PathProgramCache]: Analyzing trace with hash 2044493828, now seen corresponding path program 2 times [2024-11-19 15:04:41,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:41,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078351191] [2024-11-19 15:04:41,882 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-19 15:04:41,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:41,886 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:04:41,887 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:04:41,887 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:41,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:41,890 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:41,891 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:41,891 INFO L85 PathProgramCache]: Analyzing trace with hash 85927246, now seen corresponding path program 1 times [2024-11-19 15:04:41,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:41,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195042904] [2024-11-19 15:04:41,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:41,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:41,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:41,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:41,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:41,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195042904] [2024-11-19 15:04:41,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1195042904] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:41,945 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:41,945 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:41,945 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888622506] [2024-11-19 15:04:41,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:42,031 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:42,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:42,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:42,032 INFO L87 Difference]: Start difference. First operand 30211 states and 40806 transitions. cyclomatic complexity: 10621 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:42,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:42,336 INFO L93 Difference]: Finished difference Result 40171 states and 53854 transitions. [2024-11-19 15:04:42,336 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40171 states and 53854 transitions. [2024-11-19 15:04:42,514 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 39676 [2024-11-19 15:04:42,740 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40171 states to 40171 states and 53854 transitions. [2024-11-19 15:04:42,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40171 [2024-11-19 15:04:42,761 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40171 [2024-11-19 15:04:42,762 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40171 states and 53854 transitions. [2024-11-19 15:04:42,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:42,785 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40171 states and 53854 transitions. [2024-11-19 15:04:42,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40171 states and 53854 transitions. [2024-11-19 15:04:43,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40171 to 38675. [2024-11-19 15:04:43,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38675 states, 38675 states have (on average 1.3438655462184874) internal successors, (51974), 38674 states have internal predecessors, (51974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:43,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38675 states to 38675 states and 51974 transitions. [2024-11-19 15:04:43,450 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38675 states and 51974 transitions. [2024-11-19 15:04:43,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:43,451 INFO L425 stractBuchiCegarLoop]: Abstraction has 38675 states and 51974 transitions. [2024-11-19 15:04:43,451 INFO L332 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-19 15:04:43,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38675 states and 51974 transitions. [2024-11-19 15:04:43,663 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 38180 [2024-11-19 15:04:43,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:43,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:43,665 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:43,665 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:43,665 INFO L745 eck$LassoCheckResult]: Stem: 491883#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 491884#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 492024#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 492025#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 491542#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 491543#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 492095#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 492281#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 491635#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 491636#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 491800#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 491650#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 491651#L670 assume !(0 == ~M_E~0); 492041#L670-2 assume !(0 == ~T1_E~0); 491982#L675-1 assume !(0 == ~T2_E~0); 491983#L680-1 assume !(0 == ~T3_E~0); 492093#L685-1 assume !(0 == ~T4_E~0); 492049#L690-1 assume !(0 == ~T5_E~0); 492050#L695-1 assume !(0 == ~T6_E~0); 492148#L700-1 assume !(0 == ~E_1~0); 492132#L705-1 assume !(0 == ~E_2~0); 492133#L710-1 assume !(0 == ~E_3~0); 491981#L715-1 assume !(0 == ~E_4~0); 491909#L720-1 assume !(0 == ~E_5~0); 491910#L725-1 assume !(0 == ~E_6~0); 491960#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 492013#L320 assume !(1 == ~m_pc~0); 492176#L320-2 is_master_triggered_~__retres1~0#1 := 0; 491846#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 491839#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 491801#L825 assume !(0 != activate_threads_~tmp~1#1); 491802#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 491809#L339 assume !(1 == ~t1_pc~0); 491810#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 491776#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 491631#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 491632#L833 assume !(0 != activate_threads_~tmp___0~0#1); 491654#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 491567#L358 assume !(1 == ~t2_pc~0); 491568#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 492122#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 492027#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 491964#L841 assume !(0 != activate_threads_~tmp___1~0#1); 491796#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 491797#L377 assume !(1 == ~t3_pc~0); 492071#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 492072#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 491565#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 491566#L849 assume !(0 != activate_threads_~tmp___2~0#1); 491804#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 491735#L396 assume !(1 == ~t4_pc~0); 491736#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 491569#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 491570#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 491716#L857 assume !(0 != activate_threads_~tmp___3~0#1); 491701#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 491702#L415 assume !(1 == ~t5_pc~0); 491783#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 491834#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 491854#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 491855#L865 assume !(0 != activate_threads_~tmp___4~0#1); 491609#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 491610#L434 assume !(1 == ~t6_pc~0); 491940#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 491941#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 492017#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 492018#L873 assume !(0 != activate_threads_~tmp___5~0#1); 491818#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 491819#L743 assume !(1 == ~M_E~0); 491692#L743-2 assume !(1 == ~T1_E~0); 491693#L748-1 assume !(1 == ~T2_E~0); 492006#L753-1 assume !(1 == ~T3_E~0); 492007#L758-1 assume !(1 == ~T4_E~0); 492150#L763-1 assume !(1 == ~T5_E~0); 492218#L768-1 assume !(1 == ~T6_E~0); 491816#L773-1 assume !(1 == ~E_1~0); 491817#L778-1 assume !(1 == ~E_2~0); 491790#L783-1 assume !(1 == ~E_3~0); 491791#L788-1 assume !(1 == ~E_4~0); 492091#L793-1 assume !(1 == ~E_5~0); 492032#L798-1 assume !(1 == ~E_6~0); 491673#L803-1 assume { :end_inline_reset_delta_events } true; 491674#L1024-2 assume !false; 517701#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 517696#L645-1 [2024-11-19 15:04:43,665 INFO L747 eck$LassoCheckResult]: Loop: 517696#L645-1 assume !false; 517694#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 517691#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 517688#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 517686#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 517684#L556 assume 0 != eval_~tmp~0#1; 517682#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 517679#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 517677#L564-2 havoc eval_~tmp_ndt_1~0#1; 517675#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 517616#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 517673#L578-2 havoc eval_~tmp_ndt_2~0#1; 521492#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 513900#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 513901#L592-2 havoc eval_~tmp_ndt_3~0#1; 514953#L589-1 assume !(0 == ~t3_st~0); 514950#L603-1 assume !(0 == ~t4_st~0); 514450#L617-1 assume !(0 == ~t5_st~0); 514451#L631-1 assume !(0 == ~t6_st~0); 517696#L645-1 [2024-11-19 15:04:43,666 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:43,666 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 3 times [2024-11-19 15:04:43,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:43,667 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876727692] [2024-11-19 15:04:43,667 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-19 15:04:43,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:43,679 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-19 15:04:43,679 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:04:43,679 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:43,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:43,699 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:43,700 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:43,700 INFO L85 PathProgramCache]: Analyzing trace with hash 1877482429, now seen corresponding path program 1 times [2024-11-19 15:04:43,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:43,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050246095] [2024-11-19 15:04:43,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:43,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:43,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:43,706 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:43,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:43,709 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:43,710 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:43,710 INFO L85 PathProgramCache]: Analyzing trace with hash 890672775, now seen corresponding path program 1 times [2024-11-19 15:04:43,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:43,710 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226459350] [2024-11-19 15:04:43,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:43,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:43,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:43,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:43,760 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:43,760 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226459350] [2024-11-19 15:04:43,760 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226459350] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:43,760 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:43,760 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:43,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763489726] [2024-11-19 15:04:43,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:43,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:43,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:43,854 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:43,855 INFO L87 Difference]: Start difference. First operand 38675 states and 51974 transitions. cyclomatic complexity: 13327 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:44,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:44,120 INFO L93 Difference]: Finished difference Result 71281 states and 95256 transitions. [2024-11-19 15:04:44,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71281 states and 95256 transitions. [2024-11-19 15:04:44,602 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 70378 [2024-11-19 15:04:44,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71281 states to 71281 states and 95256 transitions. [2024-11-19 15:04:44,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71281 [2024-11-19 15:04:44,834 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71281 [2024-11-19 15:04:44,834 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71281 states and 95256 transitions. [2024-11-19 15:04:44,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:44,892 INFO L218 hiAutomatonCegarLoop]: Abstraction has 71281 states and 95256 transitions. [2024-11-19 15:04:44,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71281 states and 95256 transitions. [2024-11-19 15:04:45,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71281 to 67801. [2024-11-19 15:04:45,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67801 states, 67801 states have (on average 1.3429890414595655) internal successors, (91056), 67800 states have internal predecessors, (91056), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:46,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67801 states to 67801 states and 91056 transitions. [2024-11-19 15:04:46,032 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67801 states and 91056 transitions. [2024-11-19 15:04:46,033 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:46,036 INFO L425 stractBuchiCegarLoop]: Abstraction has 67801 states and 91056 transitions. [2024-11-19 15:04:46,036 INFO L332 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-19 15:04:46,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67801 states and 91056 transitions. [2024-11-19 15:04:46,207 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 66898 [2024-11-19 15:04:46,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:46,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:46,208 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:46,208 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:46,209 INFO L745 eck$LassoCheckResult]: Stem: 601851#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 601852#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 601999#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 602000#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 601506#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 601507#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 602074#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 602247#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 601599#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 601600#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 601772#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 601615#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 601616#L670 assume !(0 == ~M_E~0); 602014#L670-2 assume !(0 == ~T1_E~0); 601958#L675-1 assume !(0 == ~T2_E~0); 601959#L680-1 assume !(0 == ~T3_E~0); 602073#L685-1 assume !(0 == ~T4_E~0); 602022#L690-1 assume !(0 == ~T5_E~0); 602023#L695-1 assume !(0 == ~T6_E~0); 602125#L700-1 assume !(0 == ~E_1~0); 602110#L705-1 assume !(0 == ~E_2~0); 602111#L710-1 assume !(0 == ~E_3~0); 601957#L715-1 assume !(0 == ~E_4~0); 601881#L720-1 assume !(0 == ~E_5~0); 601882#L725-1 assume !(0 == ~E_6~0); 601936#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 601987#L320 assume !(1 == ~m_pc~0); 602146#L320-2 is_master_triggered_~__retres1~0#1 := 0; 601820#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 601813#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 601773#L825 assume !(0 != activate_threads_~tmp~1#1); 601774#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 601778#L339 assume !(1 == ~t1_pc~0); 601779#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 601747#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 601597#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 601598#L833 assume !(0 != activate_threads_~tmp___0~0#1); 601620#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 601531#L358 assume !(1 == ~t2_pc~0); 601532#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 602101#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 602004#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 601940#L841 assume !(0 != activate_threads_~tmp___1~0#1); 601768#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 601769#L377 assume !(1 == ~t3_pc~0); 602046#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 602047#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 601527#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 601528#L849 assume !(0 != activate_threads_~tmp___2~0#1); 601777#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 601702#L396 assume !(1 == ~t4_pc~0); 601703#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 601533#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 601534#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 601684#L857 assume !(0 != activate_threads_~tmp___3~0#1); 601668#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 601669#L415 assume !(1 == ~t5_pc~0); 601752#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 601804#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 601823#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 601824#L865 assume !(0 != activate_threads_~tmp___4~0#1); 601575#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 601576#L434 assume !(1 == ~t6_pc~0); 601915#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 601916#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 601991#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 601992#L873 assume !(0 != activate_threads_~tmp___5~0#1); 601791#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 601792#L743 assume !(1 == ~M_E~0); 601658#L743-2 assume !(1 == ~T1_E~0); 601659#L748-1 assume !(1 == ~T2_E~0); 601979#L753-1 assume !(1 == ~T3_E~0); 601980#L758-1 assume !(1 == ~T4_E~0); 602129#L763-1 assume !(1 == ~T5_E~0); 602185#L768-1 assume !(1 == ~T6_E~0); 601785#L773-1 assume !(1 == ~E_1~0); 601786#L778-1 assume !(1 == ~E_2~0); 601762#L783-1 assume !(1 == ~E_3~0); 601763#L788-1 assume !(1 == ~E_4~0); 602071#L793-1 assume !(1 == ~E_5~0); 602010#L798-1 assume !(1 == ~E_6~0); 601637#L803-1 assume { :end_inline_reset_delta_events } true; 601638#L1024-2 assume !false; 608149#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 608141#L645-1 [2024-11-19 15:04:46,209 INFO L747 eck$LassoCheckResult]: Loop: 608141#L645-1 assume !false; 608134#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 608127#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 608120#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 608111#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 608103#L556 assume 0 != eval_~tmp~0#1; 608094#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 608085#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 608076#L564-2 havoc eval_~tmp_ndt_1~0#1; 608069#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 608022#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 608061#L578-2 havoc eval_~tmp_ndt_2~0#1; 608203#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 608194#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 608190#L592-2 havoc eval_~tmp_ndt_3~0#1; 608186#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 606403#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 608174#L606-2 havoc eval_~tmp_ndt_4~0#1; 608164#L603-1 assume !(0 == ~t4_st~0); 608154#L617-1 assume !(0 == ~t5_st~0); 608146#L631-1 assume !(0 == ~t6_st~0); 608141#L645-1 [2024-11-19 15:04:46,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:46,210 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 4 times [2024-11-19 15:04:46,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:46,210 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451465190] [2024-11-19 15:04:46,210 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-19 15:04:46,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:46,221 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-19 15:04:46,222 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:04:46,222 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:46,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:46,239 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:46,239 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:46,239 INFO L85 PathProgramCache]: Analyzing trace with hash -1290620220, now seen corresponding path program 1 times [2024-11-19 15:04:46,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:46,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819996351] [2024-11-19 15:04:46,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:46,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:46,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:46,243 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:46,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:46,246 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:46,247 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:46,247 INFO L85 PathProgramCache]: Analyzing trace with hash -426925298, now seen corresponding path program 1 times [2024-11-19 15:04:46,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:46,247 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685733486] [2024-11-19 15:04:46,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:46,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:46,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:46,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:46,287 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:46,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685733486] [2024-11-19 15:04:46,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685733486] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:46,287 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:46,288 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:46,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760689831] [2024-11-19 15:04:46,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:46,601 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:46,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:46,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:46,603 INFO L87 Difference]: Start difference. First operand 67801 states and 91056 transitions. cyclomatic complexity: 23283 Second operand has 3 states, 3 states have (on average 35.0) internal successors, (105), 3 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:46,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:46,912 INFO L93 Difference]: Finished difference Result 91830 states and 122575 transitions. [2024-11-19 15:04:46,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91830 states and 122575 transitions. [2024-11-19 15:04:47,295 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 90663 [2024-11-19 15:04:47,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91830 states to 91830 states and 122575 transitions. [2024-11-19 15:04:47,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91830 [2024-11-19 15:04:47,892 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91830 [2024-11-19 15:04:47,892 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91830 states and 122575 transitions. [2024-11-19 15:04:47,923 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:47,923 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91830 states and 122575 transitions. [2024-11-19 15:04:47,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91830 states and 122575 transitions. [2024-11-19 15:04:48,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91830 to 90150. [2024-11-19 15:04:48,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90150 states, 90150 states have (on average 1.3383804769828065) internal successors, (120655), 90149 states have internal predecessors, (120655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:48,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90150 states to 90150 states and 120655 transitions. [2024-11-19 15:04:48,836 INFO L240 hiAutomatonCegarLoop]: Abstraction has 90150 states and 120655 transitions. [2024-11-19 15:04:48,837 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:48,837 INFO L425 stractBuchiCegarLoop]: Abstraction has 90150 states and 120655 transitions. [2024-11-19 15:04:48,837 INFO L332 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-19 15:04:48,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90150 states and 120655 transitions. [2024-11-19 15:04:49,367 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 88983 [2024-11-19 15:04:49,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:49,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:49,368 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:49,368 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:49,368 INFO L745 eck$LassoCheckResult]: Stem: 761486#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 761487#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 761633#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 761634#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 761145#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 761146#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 761705#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 761896#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 761238#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 761239#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 761407#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 761254#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 761255#L670 assume !(0 == ~M_E~0); 761648#L670-2 assume !(0 == ~T1_E~0); 761591#L675-1 assume !(0 == ~T2_E~0); 761592#L680-1 assume !(0 == ~T3_E~0); 761704#L685-1 assume !(0 == ~T4_E~0); 761657#L690-1 assume !(0 == ~T5_E~0); 761658#L695-1 assume !(0 == ~T6_E~0); 761759#L700-1 assume !(0 == ~E_1~0); 761743#L705-1 assume !(0 == ~E_2~0); 761744#L710-1 assume !(0 == ~E_3~0); 761589#L715-1 assume !(0 == ~E_4~0); 761515#L720-1 assume !(0 == ~E_5~0); 761516#L725-1 assume !(0 == ~E_6~0); 761566#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 761620#L320 assume !(1 == ~m_pc~0); 761785#L320-2 is_master_triggered_~__retres1~0#1 := 0; 761453#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 761446#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 761408#L825 assume !(0 != activate_threads_~tmp~1#1); 761409#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 761412#L339 assume !(1 == ~t1_pc~0); 761413#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 761382#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 761236#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 761237#L833 assume !(0 != activate_threads_~tmp___0~0#1); 761259#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 761170#L358 assume !(1 == ~t2_pc~0); 761171#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 761732#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 761636#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 761571#L841 assume !(0 != activate_threads_~tmp___1~0#1); 761403#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 761404#L377 assume !(1 == ~t3_pc~0); 761682#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 761683#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 761166#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 761167#L849 assume !(0 != activate_threads_~tmp___2~0#1); 761411#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 761338#L396 assume !(1 == ~t4_pc~0); 761339#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 761172#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 761173#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 761321#L857 assume !(0 != activate_threads_~tmp___3~0#1); 761306#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 761307#L415 assume !(1 == ~t5_pc~0); 761387#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 761437#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 761456#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 761457#L865 assume !(0 != activate_threads_~tmp___4~0#1); 761214#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 761215#L434 assume !(1 == ~t6_pc~0); 761546#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 761547#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 761624#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 761625#L873 assume !(0 != activate_threads_~tmp___5~0#1); 761425#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 761426#L743 assume !(1 == ~M_E~0); 761297#L743-2 assume !(1 == ~T1_E~0); 761298#L748-1 assume !(1 == ~T2_E~0); 761616#L753-1 assume !(1 == ~T3_E~0); 761617#L758-1 assume !(1 == ~T4_E~0); 761762#L763-1 assume !(1 == ~T5_E~0); 761831#L768-1 assume !(1 == ~T6_E~0); 761419#L773-1 assume !(1 == ~E_1~0); 761420#L778-1 assume !(1 == ~E_2~0); 761397#L783-1 assume !(1 == ~E_3~0); 761398#L788-1 assume !(1 == ~E_4~0); 761702#L793-1 assume !(1 == ~E_5~0); 761643#L798-1 assume !(1 == ~E_6~0); 761276#L803-1 assume { :end_inline_reset_delta_events } true; 761277#L1024-2 assume !false; 771704#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 771699#L645-1 [2024-11-19 15:04:49,373 INFO L747 eck$LassoCheckResult]: Loop: 771699#L645-1 assume !false; 771697#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 771694#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 771691#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 771689#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 771687#L556 assume 0 != eval_~tmp~0#1; 771682#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 771679#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 771677#L564-2 havoc eval_~tmp_ndt_1~0#1; 771675#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 771619#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 771673#L578-2 havoc eval_~tmp_ndt_2~0#1; 771734#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 771731#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 771729#L592-2 havoc eval_~tmp_ndt_3~0#1; 771727#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 771588#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 771723#L606-2 havoc eval_~tmp_ndt_4~0#1; 771721#L603-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 771718#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 771717#L620-2 havoc eval_~tmp_ndt_5~0#1; 771713#L617-1 assume !(0 == ~t5_st~0); 771701#L631-1 assume !(0 == ~t6_st~0); 771699#L645-1 [2024-11-19 15:04:49,374 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:49,374 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 5 times [2024-11-19 15:04:49,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:49,378 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121558541] [2024-11-19 15:04:49,378 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-19 15:04:49,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:49,404 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-19 15:04:49,404 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:04:49,404 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:49,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:49,449 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:49,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:49,450 INFO L85 PathProgramCache]: Analyzing trace with hash 767472829, now seen corresponding path program 1 times [2024-11-19 15:04:49,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:49,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232766517] [2024-11-19 15:04:49,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:49,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:49,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:49,457 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:49,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:49,460 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:49,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:49,461 INFO L85 PathProgramCache]: Analyzing trace with hash 1849604743, now seen corresponding path program 1 times [2024-11-19 15:04:49,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:49,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453967038] [2024-11-19 15:04:49,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:49,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:49,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:49,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:49,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:49,552 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453967038] [2024-11-19 15:04:49,552 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [453967038] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:49,552 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:49,553 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-19 15:04:49,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197236470] [2024-11-19 15:04:49,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:49,669 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:49,669 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:49,669 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:49,670 INFO L87 Difference]: Start difference. First operand 90150 states and 120655 transitions. cyclomatic complexity: 30535 Second operand has 3 states, 3 states have (on average 35.666666666666664) internal successors, (107), 3 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:50,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:50,083 INFO L93 Difference]: Finished difference Result 133761 states and 177880 transitions. [2024-11-19 15:04:50,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133761 states and 177880 transitions. [2024-11-19 15:04:51,196 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 132066 [2024-11-19 15:04:51,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133761 states to 133761 states and 177880 transitions. [2024-11-19 15:04:51,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 133761 [2024-11-19 15:04:51,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 133761 [2024-11-19 15:04:51,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 133761 states and 177880 transitions. [2024-11-19 15:04:51,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:51,867 INFO L218 hiAutomatonCegarLoop]: Abstraction has 133761 states and 177880 transitions. [2024-11-19 15:04:51,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133761 states and 177880 transitions. [2024-11-19 15:04:53,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133761 to 129729. [2024-11-19 15:04:53,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129729 states, 129729 states have (on average 1.3334258338536487) internal successors, (172984), 129728 states have internal predecessors, (172984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:53,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129729 states to 129729 states and 172984 transitions. [2024-11-19 15:04:53,516 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129729 states and 172984 transitions. [2024-11-19 15:04:53,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:04:53,517 INFO L425 stractBuchiCegarLoop]: Abstraction has 129729 states and 172984 transitions. [2024-11-19 15:04:53,517 INFO L332 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2024-11-19 15:04:53,517 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129729 states and 172984 transitions. [2024-11-19 15:04:54,511 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 128034 [2024-11-19 15:04:54,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:04:54,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:04:54,512 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:54,512 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:04:54,512 INFO L745 eck$LassoCheckResult]: Stem: 985413#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 985414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 985565#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 985566#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 985064#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 985065#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 985640#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 985839#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 985158#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 985159#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 985332#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 985174#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 985175#L670 assume !(0 == ~M_E~0); 985585#L670-2 assume !(0 == ~T1_E~0); 985522#L675-1 assume !(0 == ~T2_E~0); 985523#L680-1 assume !(0 == ~T3_E~0); 985639#L685-1 assume !(0 == ~T4_E~0); 985593#L690-1 assume !(0 == ~T5_E~0); 985594#L695-1 assume !(0 == ~T6_E~0); 985696#L700-1 assume !(0 == ~E_1~0); 985678#L705-1 assume !(0 == ~E_2~0); 985679#L710-1 assume !(0 == ~E_3~0); 985521#L715-1 assume !(0 == ~E_4~0); 985444#L720-1 assume !(0 == ~E_5~0); 985445#L725-1 assume !(0 == ~E_6~0); 985499#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 985552#L320 assume !(1 == ~m_pc~0); 985721#L320-2 is_master_triggered_~__retres1~0#1 := 0; 985381#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 985374#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 985333#L825 assume !(0 != activate_threads_~tmp~1#1); 985334#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 985338#L339 assume !(1 == ~t1_pc~0); 985339#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 985307#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 985156#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 985157#L833 assume !(0 != activate_threads_~tmp___0~0#1); 985180#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 985089#L358 assume !(1 == ~t2_pc~0); 985090#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 985669#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 985568#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 985504#L841 assume !(0 != activate_threads_~tmp___1~0#1); 985328#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 985329#L377 assume !(1 == ~t3_pc~0); 985617#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 985618#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 985085#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 985086#L849 assume !(0 != activate_threads_~tmp___2~0#1); 985337#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 985261#L396 assume !(1 == ~t4_pc~0); 985262#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 985091#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 985092#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 985243#L857 assume !(0 != activate_threads_~tmp___3~0#1); 985228#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 985229#L415 assume !(1 == ~t5_pc~0); 985312#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 985363#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 985384#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 985385#L865 assume !(0 != activate_threads_~tmp___4~0#1); 985134#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 985135#L434 assume !(1 == ~t6_pc~0); 985477#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 985478#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 985556#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 985557#L873 assume !(0 != activate_threads_~tmp___5~0#1); 985350#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 985351#L743 assume !(1 == ~M_E~0); 985217#L743-2 assume !(1 == ~T1_E~0); 985218#L748-1 assume !(1 == ~T2_E~0); 985546#L753-1 assume !(1 == ~T3_E~0); 985547#L758-1 assume !(1 == ~T4_E~0); 985698#L763-1 assume !(1 == ~T5_E~0); 985766#L768-1 assume !(1 == ~T6_E~0); 985344#L773-1 assume !(1 == ~E_1~0); 985345#L778-1 assume !(1 == ~E_2~0); 985322#L783-1 assume !(1 == ~E_3~0); 985323#L788-1 assume !(1 == ~E_4~0); 985636#L793-1 assume !(1 == ~E_5~0); 985577#L798-1 assume !(1 == ~E_6~0); 985197#L803-1 assume { :end_inline_reset_delta_events } true; 985198#L1024-2 assume !false; 1051808#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1051803#L645-1 [2024-11-19 15:04:54,513 INFO L747 eck$LassoCheckResult]: Loop: 1051803#L645-1 assume !false; 1051801#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1051798#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1051796#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1051793#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1051791#L556 assume 0 != eval_~tmp~0#1; 1051788#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1051785#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1051783#L564-2 havoc eval_~tmp_ndt_1~0#1; 1051781#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1051713#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1051780#L578-2 havoc eval_~tmp_ndt_2~0#1; 1052293#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1052290#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1052288#L592-2 havoc eval_~tmp_ndt_3~0#1; 1051479#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1051477#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1051475#L606-2 havoc eval_~tmp_ndt_4~0#1; 1051472#L603-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1051469#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1051470#L620-2 havoc eval_~tmp_ndt_5~0#1; 1051828#L617-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1051825#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 1051823#L634-2 havoc eval_~tmp_ndt_6~0#1; 1051805#L631-1 assume !(0 == ~t6_st~0); 1051803#L645-1 [2024-11-19 15:04:54,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:54,513 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 6 times [2024-11-19 15:04:54,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:54,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850713047] [2024-11-19 15:04:54,514 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-19 15:04:54,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:54,525 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2024-11-19 15:04:54,525 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-19 15:04:54,525 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:54,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:54,544 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:54,545 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:54,545 INFO L85 PathProgramCache]: Analyzing trace with hash -1198969468, now seen corresponding path program 1 times [2024-11-19 15:04:54,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:54,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654241899] [2024-11-19 15:04:54,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:54,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:54,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:54,551 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:04:54,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:04:54,554 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:04:54,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:04:54,555 INFO L85 PathProgramCache]: Analyzing trace with hash -652285746, now seen corresponding path program 1 times [2024-11-19 15:04:54,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:04:54,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304191015] [2024-11-19 15:04:54,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:04:54,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:04:54,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-19 15:04:54,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-19 15:04:54,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-19 15:04:54,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1304191015] [2024-11-19 15:04:54,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1304191015] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-19 15:04:54,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-19 15:04:54,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-19 15:04:54,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [528507876] [2024-11-19 15:04:54,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-19 15:04:54,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-19 15:04:54,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-19 15:04:54,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-19 15:04:54,689 INFO L87 Difference]: Start difference. First operand 129729 states and 172984 transitions. cyclomatic complexity: 43285 Second operand has 3 states, 2 states have (on average 54.5) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:04:55,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-19 15:04:55,912 INFO L93 Difference]: Finished difference Result 245428 states and 325593 transitions. [2024-11-19 15:04:55,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245428 states and 325593 transitions. [2024-11-19 15:04:56,887 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 242125 [2024-11-19 15:04:58,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245428 states to 245428 states and 325593 transitions. [2024-11-19 15:04:58,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245428 [2024-11-19 15:04:58,317 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245428 [2024-11-19 15:04:58,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 245428 states and 325593 transitions. [2024-11-19 15:04:58,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-19 15:04:58,444 INFO L218 hiAutomatonCegarLoop]: Abstraction has 245428 states and 325593 transitions. [2024-11-19 15:04:58,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245428 states and 325593 transitions. [2024-11-19 15:05:01,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245428 to 245428. [2024-11-19 15:05:01,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 245428 states, 245428 states have (on average 1.3266334729533713) internal successors, (325593), 245427 states have internal predecessors, (325593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-19 15:05:01,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245428 states to 245428 states and 325593 transitions. [2024-11-19 15:05:01,929 INFO L240 hiAutomatonCegarLoop]: Abstraction has 245428 states and 325593 transitions. [2024-11-19 15:05:01,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-19 15:05:01,930 INFO L425 stractBuchiCegarLoop]: Abstraction has 245428 states and 325593 transitions. [2024-11-19 15:05:01,930 INFO L332 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2024-11-19 15:05:01,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 245428 states and 325593 transitions. [2024-11-19 15:05:02,569 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 242125 [2024-11-19 15:05:02,569 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-19 15:05:02,569 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-19 15:05:02,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:05:02,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-19 15:05:02,570 INFO L745 eck$LassoCheckResult]: Stem: 1360573#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1360574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1360720#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1360721#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1360229#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1360230#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1360792#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1360969#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1360321#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1360322#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1360491#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1360336#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1360337#L670 assume !(0 == ~M_E~0); 1360738#L670-2 assume !(0 == ~T1_E~0); 1360677#L675-1 assume !(0 == ~T2_E~0); 1360678#L680-1 assume !(0 == ~T3_E~0); 1360791#L685-1 assume !(0 == ~T4_E~0); 1360745#L690-1 assume !(0 == ~T5_E~0); 1360746#L695-1 assume !(0 == ~T6_E~0); 1360846#L700-1 assume !(0 == ~E_1~0); 1360829#L705-1 assume !(0 == ~E_2~0); 1360830#L710-1 assume !(0 == ~E_3~0); 1360676#L715-1 assume !(0 == ~E_4~0); 1360603#L720-1 assume !(0 == ~E_5~0); 1360604#L725-1 assume !(0 == ~E_6~0); 1360655#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1360708#L320 assume !(1 == ~m_pc~0); 1360863#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1360539#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1360532#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1360492#L825 assume !(0 != activate_threads_~tmp~1#1); 1360493#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1360497#L339 assume !(1 == ~t1_pc~0); 1360498#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1360467#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1360319#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1360320#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1360341#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1360254#L358 assume !(1 == ~t2_pc~0); 1360255#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1360819#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1360723#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1360659#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1360487#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1360488#L377 assume !(1 == ~t3_pc~0); 1360771#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1360772#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1360250#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1360251#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1360496#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1360423#L396 assume !(1 == ~t4_pc~0); 1360424#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1360256#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1360257#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1360404#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1360389#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1360390#L415 assume !(1 == ~t5_pc~0); 1360472#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1360522#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1360542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1360543#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1360296#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1360297#L434 assume !(1 == ~t6_pc~0); 1360635#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1360636#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1360712#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1360713#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1360509#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1360510#L743 assume !(1 == ~M_E~0); 1360378#L743-2 assume !(1 == ~T1_E~0); 1360379#L748-1 assume !(1 == ~T2_E~0); 1360701#L753-1 assume !(1 == ~T3_E~0); 1360702#L758-1 assume !(1 == ~T4_E~0); 1360848#L763-1 assume !(1 == ~T5_E~0); 1360910#L768-1 assume !(1 == ~T6_E~0); 1360503#L773-1 assume !(1 == ~E_1~0); 1360504#L778-1 assume !(1 == ~E_2~0); 1360481#L783-1 assume !(1 == ~E_3~0); 1360482#L788-1 assume !(1 == ~E_4~0); 1360789#L793-1 assume !(1 == ~E_5~0); 1360731#L798-1 assume !(1 == ~E_6~0); 1360358#L803-1 assume { :end_inline_reset_delta_events } true; 1360359#L1024-2 assume !false; 1396235#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1396233#L645-1 [2024-11-19 15:05:02,571 INFO L747 eck$LassoCheckResult]: Loop: 1396233#L645-1 assume !false; 1396232#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1396230#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1396228#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1396226#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1396224#L556 assume 0 != eval_~tmp~0#1; 1396221#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1396218#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1396216#L564-2 havoc eval_~tmp_ndt_1~0#1; 1396214#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1396166#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1396211#L578-2 havoc eval_~tmp_ndt_2~0#1; 1396619#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1396617#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1396615#L592-2 havoc eval_~tmp_ndt_3~0#1; 1396613#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1393722#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1396611#L606-2 havoc eval_~tmp_ndt_4~0#1; 1446066#L603-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1419549#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1419548#L620-2 havoc eval_~tmp_ndt_5~0#1; 1419547#L617-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1419544#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 1419542#L634-2 havoc eval_~tmp_ndt_6~0#1; 1396242#L631-1 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1396239#L648 assume !(0 != eval_~tmp_ndt_7~0#1); 1396234#L648-2 havoc eval_~tmp_ndt_7~0#1; 1396233#L645-1 [2024-11-19 15:05:02,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:05:02,571 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 7 times [2024-11-19 15:05:02,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:05:02,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609106312] [2024-11-19 15:05:02,572 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-19 15:05:02,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:05:02,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:05:02,581 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:05:02,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:05:02,601 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:05:02,601 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:05:02,602 INFO L85 PathProgramCache]: Analyzing trace with hash -1158409573, now seen corresponding path program 1 times [2024-11-19 15:05:02,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:05:02,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538484793] [2024-11-19 15:05:02,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:05:02,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:05:02,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:05:02,606 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:05:02,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:05:02,609 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:05:02,610 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-19 15:05:02,610 INFO L85 PathProgramCache]: Analyzing trace with hash 218637157, now seen corresponding path program 1 times [2024-11-19 15:05:02,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-19 15:05:02,610 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286158349] [2024-11-19 15:05:02,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-19 15:05:02,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-19 15:05:02,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:05:02,621 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:05:02,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:05:03,345 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-19 15:05:04,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:05:04,869 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-19 15:05:04,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-19 15:05:05,102 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.11 03:05:05 BoogieIcfgContainer [2024-11-19 15:05:05,103 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-19 15:05:05,103 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-19 15:05:05,103 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-19 15:05:05,103 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-19 15:05:05,104 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 03:04:27" (3/4) ... [2024-11-19 15:05:05,108 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-19 15:05:05,193 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-19 15:05:05,193 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-19 15:05:05,194 INFO L158 Benchmark]: Toolchain (without parser) took 39555.56ms. Allocated memory was 167.8MB in the beginning and 12.8GB in the end (delta: 12.6GB). Free memory was 119.4MB in the beginning and 9.8GB in the end (delta: -9.7GB). Peak memory consumption was 2.9GB. Max. memory is 16.1GB. [2024-11-19 15:05:05,194 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 167.8MB. Free memory is still 131.8MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-19 15:05:05,194 INFO L158 Benchmark]: CACSL2BoogieTranslator took 411.29ms. Allocated memory is still 167.8MB. Free memory was 118.6MB in the beginning and 99.1MB in the end (delta: 19.5MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2024-11-19 15:05:05,194 INFO L158 Benchmark]: Boogie Procedure Inliner took 74.46ms. Allocated memory is still 167.8MB. Free memory was 99.1MB in the beginning and 93.4MB in the end (delta: 5.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-19 15:05:05,194 INFO L158 Benchmark]: Boogie Preprocessor took 100.18ms. Allocated memory is still 167.8MB. Free memory was 93.4MB in the beginning and 86.5MB in the end (delta: 6.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-19 15:05:05,195 INFO L158 Benchmark]: RCFGBuilder took 1522.09ms. Allocated memory is still 167.8MB. Free memory was 86.5MB in the beginning and 81.2MB in the end (delta: 5.3MB). Peak memory consumption was 57.9MB. Max. memory is 16.1GB. [2024-11-19 15:05:05,195 INFO L158 Benchmark]: BuchiAutomizer took 37352.18ms. Allocated memory was 167.8MB in the beginning and 12.8GB in the end (delta: 12.6GB). Free memory was 81.2MB in the beginning and 9.8GB in the end (delta: -9.7GB). Peak memory consumption was 2.9GB. Max. memory is 16.1GB. [2024-11-19 15:05:05,195 INFO L158 Benchmark]: Witness Printer took 90.02ms. Allocated memory is still 12.8GB. Free memory was 9.8GB in the beginning and 9.8GB in the end (delta: 14.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2024-11-19 15:05:05,196 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 167.8MB. Free memory is still 131.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 411.29ms. Allocated memory is still 167.8MB. Free memory was 118.6MB in the beginning and 99.1MB in the end (delta: 19.5MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 74.46ms. Allocated memory is still 167.8MB. Free memory was 99.1MB in the beginning and 93.4MB in the end (delta: 5.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 100.18ms. Allocated memory is still 167.8MB. Free memory was 93.4MB in the beginning and 86.5MB in the end (delta: 6.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 1522.09ms. Allocated memory is still 167.8MB. Free memory was 86.5MB in the beginning and 81.2MB in the end (delta: 5.3MB). Peak memory consumption was 57.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 37352.18ms. Allocated memory was 167.8MB in the beginning and 12.8GB in the end (delta: 12.6GB). Free memory was 81.2MB in the beginning and 9.8GB in the end (delta: -9.7GB). Peak memory consumption was 2.9GB. Max. memory is 16.1GB. * Witness Printer took 90.02ms. Allocated memory is still 12.8GB. Free memory was 9.8GB in the beginning and 9.8GB in the end (delta: 14.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 31 terminating modules (31 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.31 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 245428 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 37.1s and 32 iterations. TraceHistogramMax:1. Analysis of lassos took 7.2s. Construction of modules took 1.0s. Büchi inclusion checks took 25.2s. Highest rank in rank-based complementation 0. Minimization of det autom 31. Minimization of nondet autom 0. Automata minimization 11.6s AutomataMinimizationTime, 31 MinimizatonAttempts, 49566 StatesRemovedByMinimization, 19 NontrivialMinimizations. Non-live state removal took 8.2s Buchi closure took 0.5s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 28712 SdHoareTripleChecker+Valid, 1.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 28712 mSDsluCounter, 56493 SdHoareTripleChecker+Invalid, 1.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 23452 mSDsCounter, 330 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1000 IncrementalHoareTripleChecker+Invalid, 1330 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 330 mSolverCounterUnsat, 33041 mSDtfsCounter, 1000 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc6 concLT0 SILN1 SILU0 SILI19 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 551]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int m_st ; [L33] int t1_st ; [L34] int t2_st ; [L35] int t3_st ; [L36] int t4_st ; [L37] int t5_st ; [L38] int t6_st ; [L39] int m_i ; [L40] int t1_i ; [L41] int t2_i ; [L42] int t3_i ; [L43] int t4_i ; [L44] int t5_i ; [L45] int t6_i ; [L46] int M_E = 2; [L47] int T1_E = 2; [L48] int T2_E = 2; [L49] int T3_E = 2; [L50] int T4_E = 2; [L51] int T5_E = 2; [L52] int T6_E = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0] [L1069] int __retres1 ; [L1073] CALL init_model() [L979] m_i = 1 [L980] t1_i = 1 [L981] t2_i = 1 [L982] t3_i = 1 [L983] t4_i = 1 [L984] t5_i = 1 [L985] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1073] RET init_model() [L1074] CALL start_simulation() [L1010] int kernel_st ; [L1011] int tmp ; [L1012] int tmp___0 ; [L1016] kernel_st = 0 [L1017] FCALL update_channels() [L1018] CALL init_threads() [L461] COND TRUE m_i == 1 [L462] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L466] COND TRUE t1_i == 1 [L467] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L471] COND TRUE t2_i == 1 [L472] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L476] COND TRUE t3_i == 1 [L477] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L481] COND TRUE t4_i == 1 [L482] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L486] COND TRUE t5_i == 1 [L487] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L491] COND TRUE t6_i == 1 [L492] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1018] RET init_threads() [L1019] CALL fire_delta_events() [L670] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L675] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L680] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L685] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L690] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L695] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L700] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L705] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L710] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L715] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L720] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L725] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L730] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1019] RET fire_delta_events() [L1020] CALL activate_threads() [L813] int tmp ; [L814] int tmp___0 ; [L815] int tmp___1 ; [L816] int tmp___2 ; [L817] int tmp___3 ; [L818] int tmp___4 ; [L819] int tmp___5 ; [L823] CALL, EXPR is_master_triggered() [L317] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L320] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L330] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L332] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L823] RET, EXPR is_master_triggered() [L823] tmp = is_master_triggered() [L825] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] CALL, EXPR is_transmit1_triggered() [L336] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L339] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L349] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L351] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] RET, EXPR is_transmit1_triggered() [L831] tmp___0 = is_transmit1_triggered() [L833] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] CALL, EXPR is_transmit2_triggered() [L355] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L358] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L368] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L370] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] RET, EXPR is_transmit2_triggered() [L839] tmp___1 = is_transmit2_triggered() [L841] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] CALL, EXPR is_transmit3_triggered() [L374] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L377] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L387] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L389] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] RET, EXPR is_transmit3_triggered() [L847] tmp___2 = is_transmit3_triggered() [L849] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] CALL, EXPR is_transmit4_triggered() [L393] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L396] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L406] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L408] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] RET, EXPR is_transmit4_triggered() [L855] tmp___3 = is_transmit4_triggered() [L857] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] CALL, EXPR is_transmit5_triggered() [L412] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L415] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L425] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L427] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] RET, EXPR is_transmit5_triggered() [L863] tmp___4 = is_transmit5_triggered() [L865] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] CALL, EXPR is_transmit6_triggered() [L431] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L434] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L444] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L446] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] RET, EXPR is_transmit6_triggered() [L871] tmp___5 = is_transmit6_triggered() [L873] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1020] RET activate_threads() [L1021] CALL reset_delta_events() [L743] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L748] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L753] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L758] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L763] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L768] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L773] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L778] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L783] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L788] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L793] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L798] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L803] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1021] RET reset_delta_events() [L1024] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1027] kernel_st = 1 [L1028] CALL eval() [L547] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] Loop: [L551] COND TRUE 1 [L554] CALL, EXPR exists_runnable_thread() [L501] int __retres1 ; [L504] COND TRUE m_st == 0 [L505] __retres1 = 1 [L542] return (__retres1); [L554] RET, EXPR exists_runnable_thread() [L554] tmp = exists_runnable_thread() [L556] COND TRUE \read(tmp) [L561] COND TRUE m_st == 0 [L562] int tmp_ndt_1; [L563] tmp_ndt_1 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_1)) [L575] COND TRUE t1_st == 0 [L576] int tmp_ndt_2; [L577] tmp_ndt_2 = __VERIFIER_nondet_int() [L578] COND FALSE !(\read(tmp_ndt_2)) [L589] COND TRUE t2_st == 0 [L590] int tmp_ndt_3; [L591] tmp_ndt_3 = __VERIFIER_nondet_int() [L592] COND FALSE !(\read(tmp_ndt_3)) [L603] COND TRUE t3_st == 0 [L604] int tmp_ndt_4; [L605] tmp_ndt_4 = __VERIFIER_nondet_int() [L606] COND FALSE !(\read(tmp_ndt_4)) [L617] COND TRUE t4_st == 0 [L618] int tmp_ndt_5; [L619] tmp_ndt_5 = __VERIFIER_nondet_int() [L620] COND FALSE !(\read(tmp_ndt_5)) [L631] COND TRUE t5_st == 0 [L632] int tmp_ndt_6; [L633] tmp_ndt_6 = __VERIFIER_nondet_int() [L634] COND FALSE !(\read(tmp_ndt_6)) [L645] COND TRUE t6_st == 0 [L646] int tmp_ndt_7; [L647] tmp_ndt_7 = __VERIFIER_nondet_int() [L648] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 551]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int m_st ; [L33] int t1_st ; [L34] int t2_st ; [L35] int t3_st ; [L36] int t4_st ; [L37] int t5_st ; [L38] int t6_st ; [L39] int m_i ; [L40] int t1_i ; [L41] int t2_i ; [L42] int t3_i ; [L43] int t4_i ; [L44] int t5_i ; [L45] int t6_i ; [L46] int M_E = 2; [L47] int T1_E = 2; [L48] int T2_E = 2; [L49] int T3_E = 2; [L50] int T4_E = 2; [L51] int T5_E = 2; [L52] int T6_E = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0] [L1069] int __retres1 ; [L1073] CALL init_model() [L979] m_i = 1 [L980] t1_i = 1 [L981] t2_i = 1 [L982] t3_i = 1 [L983] t4_i = 1 [L984] t5_i = 1 [L985] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1073] RET init_model() [L1074] CALL start_simulation() [L1010] int kernel_st ; [L1011] int tmp ; [L1012] int tmp___0 ; [L1016] kernel_st = 0 [L1017] FCALL update_channels() [L1018] CALL init_threads() [L461] COND TRUE m_i == 1 [L462] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L466] COND TRUE t1_i == 1 [L467] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L471] COND TRUE t2_i == 1 [L472] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L476] COND TRUE t3_i == 1 [L477] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L481] COND TRUE t4_i == 1 [L482] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L486] COND TRUE t5_i == 1 [L487] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L491] COND TRUE t6_i == 1 [L492] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1018] RET init_threads() [L1019] CALL fire_delta_events() [L670] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L675] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L680] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L685] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L690] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L695] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L700] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L705] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L710] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L715] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L720] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L725] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L730] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1019] RET fire_delta_events() [L1020] CALL activate_threads() [L813] int tmp ; [L814] int tmp___0 ; [L815] int tmp___1 ; [L816] int tmp___2 ; [L817] int tmp___3 ; [L818] int tmp___4 ; [L819] int tmp___5 ; [L823] CALL, EXPR is_master_triggered() [L317] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L320] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L330] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L332] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L823] RET, EXPR is_master_triggered() [L823] tmp = is_master_triggered() [L825] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] CALL, EXPR is_transmit1_triggered() [L336] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L339] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L349] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L351] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] RET, EXPR is_transmit1_triggered() [L831] tmp___0 = is_transmit1_triggered() [L833] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] CALL, EXPR is_transmit2_triggered() [L355] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L358] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L368] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L370] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] RET, EXPR is_transmit2_triggered() [L839] tmp___1 = is_transmit2_triggered() [L841] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] CALL, EXPR is_transmit3_triggered() [L374] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L377] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L387] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L389] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] RET, EXPR is_transmit3_triggered() [L847] tmp___2 = is_transmit3_triggered() [L849] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] CALL, EXPR is_transmit4_triggered() [L393] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L396] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L406] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L408] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] RET, EXPR is_transmit4_triggered() [L855] tmp___3 = is_transmit4_triggered() [L857] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] CALL, EXPR is_transmit5_triggered() [L412] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L415] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L425] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L427] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] RET, EXPR is_transmit5_triggered() [L863] tmp___4 = is_transmit5_triggered() [L865] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] CALL, EXPR is_transmit6_triggered() [L431] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L434] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L444] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L446] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] RET, EXPR is_transmit6_triggered() [L871] tmp___5 = is_transmit6_triggered() [L873] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1020] RET activate_threads() [L1021] CALL reset_delta_events() [L743] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L748] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L753] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L758] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L763] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L768] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L773] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L778] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L783] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L788] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L793] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L798] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L803] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1021] RET reset_delta_events() [L1024] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1027] kernel_st = 1 [L1028] CALL eval() [L547] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] Loop: [L551] COND TRUE 1 [L554] CALL, EXPR exists_runnable_thread() [L501] int __retres1 ; [L504] COND TRUE m_st == 0 [L505] __retres1 = 1 [L542] return (__retres1); [L554] RET, EXPR exists_runnable_thread() [L554] tmp = exists_runnable_thread() [L556] COND TRUE \read(tmp) [L561] COND TRUE m_st == 0 [L562] int tmp_ndt_1; [L563] tmp_ndt_1 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_1)) [L575] COND TRUE t1_st == 0 [L576] int tmp_ndt_2; [L577] tmp_ndt_2 = __VERIFIER_nondet_int() [L578] COND FALSE !(\read(tmp_ndt_2)) [L589] COND TRUE t2_st == 0 [L590] int tmp_ndt_3; [L591] tmp_ndt_3 = __VERIFIER_nondet_int() [L592] COND FALSE !(\read(tmp_ndt_3)) [L603] COND TRUE t3_st == 0 [L604] int tmp_ndt_4; [L605] tmp_ndt_4 = __VERIFIER_nondet_int() [L606] COND FALSE !(\read(tmp_ndt_4)) [L617] COND TRUE t4_st == 0 [L618] int tmp_ndt_5; [L619] tmp_ndt_5 = __VERIFIER_nondet_int() [L620] COND FALSE !(\read(tmp_ndt_5)) [L631] COND TRUE t5_st == 0 [L632] int tmp_ndt_6; [L633] tmp_ndt_6 = __VERIFIER_nondet_int() [L634] COND FALSE !(\read(tmp_ndt_6)) [L645] COND TRUE t6_st == 0 [L646] int tmp_ndt_7; [L647] tmp_ndt_7 = __VERIFIER_nondet_int() [L648] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-19 15:05:05,233 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)