./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.11.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version fca748b1 Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.11.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 --- Real Ultimate output --- This is Ultimate 0.2.5-wip.dd.update-z3-fca748b-m [2024-11-20 22:59:04,574 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-20 22:59:04,637 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-20 22:59:04,649 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-20 22:59:04,650 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-20 22:59:04,694 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-20 22:59:04,694 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-20 22:59:04,695 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-20 22:59:04,695 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-20 22:59:04,695 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-20 22:59:04,696 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-20 22:59:04,696 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-20 22:59:04,698 INFO L153 SettingsManager]: * Use SBE=true [2024-11-20 22:59:04,699 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-20 22:59:04,701 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-20 22:59:04,701 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-20 22:59:04,701 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-20 22:59:04,701 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-20 22:59:04,701 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-20 22:59:04,702 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-20 22:59:04,702 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-20 22:59:04,702 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-20 22:59:04,703 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-20 22:59:04,703 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-20 22:59:04,703 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-20 22:59:04,706 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-20 22:59:04,707 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-20 22:59:04,707 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-20 22:59:04,707 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-20 22:59:04,707 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-20 22:59:04,707 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-20 22:59:04,707 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-20 22:59:04,707 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-20 22:59:04,708 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-20 22:59:04,708 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-20 22:59:04,708 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-20 22:59:04,708 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-20 22:59:04,708 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-20 22:59:04,709 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-20 22:59:04,709 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 [2024-11-20 22:59:04,894 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-20 22:59:04,909 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-20 22:59:04,911 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-20 22:59:04,912 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-20 22:59:04,912 INFO L274 PluginConnector]: CDTParser initialized [2024-11-20 22:59:04,913 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.11.cil.c [2024-11-20 22:59:06,500 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-20 22:59:06,681 INFO L384 CDTParser]: Found 1 translation units. [2024-11-20 22:59:06,681 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.11.cil.c [2024-11-20 22:59:06,693 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2ae02a047/39be5e82ebf745c9beaa6c46947f112f/FLAG583b6d6f8 [2024-11-20 22:59:06,709 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2ae02a047/39be5e82ebf745c9beaa6c46947f112f [2024-11-20 22:59:06,711 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-20 22:59:06,712 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-20 22:59:06,714 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-20 22:59:06,714 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-20 22:59:06,722 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-20 22:59:06,723 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 10:59:06" (1/1) ... [2024-11-20 22:59:06,723 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@44b21f5a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:06, skipping insertion in model container [2024-11-20 22:59:06,724 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 10:59:06" (1/1) ... [2024-11-20 22:59:06,811 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-20 22:59:07,036 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-20 22:59:07,046 INFO L200 MainTranslator]: Completed pre-run [2024-11-20 22:59:07,136 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-20 22:59:07,158 INFO L204 MainTranslator]: Completed translation [2024-11-20 22:59:07,158 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07 WrapperNode [2024-11-20 22:59:07,159 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-20 22:59:07,159 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-20 22:59:07,160 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-20 22:59:07,160 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-20 22:59:07,166 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,177 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,259 INFO L138 Inliner]: procedures = 50, calls = 64, calls flagged for inlining = 59, calls inlined = 225, statements flattened = 3461 [2024-11-20 22:59:07,260 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-20 22:59:07,260 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-20 22:59:07,260 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-20 22:59:07,261 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-20 22:59:07,271 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,271 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,283 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,335 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-20 22:59:07,336 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,336 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,379 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,419 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,425 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,435 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,445 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-20 22:59:07,447 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-20 22:59:07,447 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-20 22:59:07,448 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-20 22:59:07,448 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (1/1) ... [2024-11-20 22:59:07,456 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-20 22:59:07,466 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-20 22:59:07,482 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-20 22:59:07,486 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-20 22:59:07,530 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-20 22:59:07,530 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-20 22:59:07,531 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-20 22:59:07,531 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-20 22:59:07,619 INFO L238 CfgBuilder]: Building ICFG [2024-11-20 22:59:07,621 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-20 22:59:09,782 INFO L? ?]: Removed 720 outVars from TransFormulas that were not future-live. [2024-11-20 22:59:09,782 INFO L287 CfgBuilder]: Performing block encoding [2024-11-20 22:59:09,814 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-20 22:59:09,814 INFO L316 CfgBuilder]: Removed 15 assume(true) statements. [2024-11-20 22:59:09,815 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 10:59:09 BoogieIcfgContainer [2024-11-20 22:59:09,815 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-20 22:59:09,816 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-20 22:59:09,816 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-20 22:59:09,819 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-20 22:59:09,820 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-20 22:59:09,820 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 20.11 10:59:06" (1/3) ... [2024-11-20 22:59:09,821 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@66bec0b4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 10:59:09, skipping insertion in model container [2024-11-20 22:59:09,821 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-20 22:59:09,821 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:59:07" (2/3) ... [2024-11-20 22:59:09,821 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@66bec0b4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 10:59:09, skipping insertion in model container [2024-11-20 22:59:09,821 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-20 22:59:09,821 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 10:59:09" (3/3) ... [2024-11-20 22:59:09,823 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.11.cil.c [2024-11-20 22:59:09,892 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-20 22:59:09,892 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-20 22:59:09,892 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-20 22:59:09,892 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-20 22:59:09,892 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-20 22:59:09,892 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-20 22:59:09,893 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-20 22:59:09,893 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-20 22:59:09,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:09,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1343 [2024-11-20 22:59:09,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:09,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:09,972 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:09,973 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:09,973 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-20 22:59:09,975 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:09,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1343 [2024-11-20 22:59:09,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:09,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:09,988 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:09,988 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:09,996 INFO L745 eck$LassoCheckResult]: Stem: 227#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1380#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1124#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1376#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 510#L761true assume !(1 == ~m_i~0);~m_st~0 := 2; 528#L761-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 424#L766-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 355#L771-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 197#L776-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18#L781-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1480#L786-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 39#L791-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 657#L796-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 621#L801-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 665#L806-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1359#L811-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 255#L816-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1175#L1090true assume !(0 == ~M_E~0); 280#L1090-2true assume !(0 == ~T1_E~0); 1333#L1095-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 801#L1100-1true assume !(0 == ~T3_E~0); 828#L1105-1true assume !(0 == ~T4_E~0); 151#L1110-1true assume !(0 == ~T5_E~0); 375#L1115-1true assume !(0 == ~T6_E~0); 601#L1120-1true assume !(0 == ~T7_E~0); 1368#L1125-1true assume !(0 == ~T8_E~0); 1360#L1130-1true assume !(0 == ~T9_E~0); 826#L1135-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 258#L1140-1true assume !(0 == ~T11_E~0); 757#L1145-1true assume !(0 == ~E_1~0); 796#L1150-1true assume !(0 == ~E_2~0); 364#L1155-1true assume !(0 == ~E_3~0); 1344#L1160-1true assume !(0 == ~E_4~0); 429#L1165-1true assume !(0 == ~E_5~0); 1097#L1170-1true assume !(0 == ~E_6~0); 1285#L1175-1true assume 0 == ~E_7~0;~E_7~0 := 1; 481#L1180-1true assume !(0 == ~E_8~0); 914#L1185-1true assume !(0 == ~E_9~0); 256#L1190-1true assume !(0 == ~E_10~0); 491#L1195-1true assume !(0 == ~E_11~0); 1041#L1200-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371#L525true assume !(1 == ~m_pc~0); 60#L525-2true is_master_triggered_~__retres1~0#1 := 0; 1035#L536true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 925#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 894#L1350true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 248#L1350-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 532#L544true assume 1 == ~t1_pc~0; 410#L545true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 754#L555true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163#L1358true assume !(0 != activate_threads_~tmp___0~0#1); 578#L1358-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1030#L563true assume !(1 == ~t2_pc~0); 744#L563-2true is_transmit2_triggered_~__retres1~2#1 := 0; 69#L574true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 362#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 295#L1366true assume !(0 != activate_threads_~tmp___1~0#1); 643#L1366-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 755#L582true assume 1 == ~t3_pc~0; 136#L583true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1246#L593true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1108#L1374true assume !(0 != activate_threads_~tmp___2~0#1); 103#L1374-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1404#L601true assume !(1 == ~t4_pc~0); 847#L601-2true is_transmit4_triggered_~__retres1~4#1 := 0; 376#L612true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 765#L1382true assume !(0 != activate_threads_~tmp___3~0#1); 1411#L1382-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1218#L620true assume 1 == ~t5_pc~0; 83#L621true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 662#L631true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 932#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1479#L1390true assume !(0 != activate_threads_~tmp___4~0#1); 1274#L1390-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1372#L639true assume !(1 == ~t6_pc~0); 599#L639-2true is_transmit6_triggered_~__retres1~6#1 := 0; 315#L650true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 347#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1269#L1398true assume !(0 != activate_threads_~tmp___5~0#1); 379#L1398-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 961#L658true assume 1 == ~t7_pc~0; 600#L659true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1293#L669true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1396#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 704#L1406true assume !(0 != activate_threads_~tmp___6~0#1); 251#L1406-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 383#L677true assume 1 == ~t8_pc~0; 883#L678true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 143#L688true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 849#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 292#L1414true assume !(0 != activate_threads_~tmp___7~0#1); 884#L1414-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 996#L696true assume !(1 == ~t9_pc~0); 588#L696-2true is_transmit9_triggered_~__retres1~9#1 := 0; 672#L707true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 416#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 605#L1422true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 805#L1422-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1152#L715true assume 1 == ~t10_pc~0; 814#L716true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 690#L726true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 520#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 781#L1430true assume !(0 != activate_threads_~tmp___9~0#1); 477#L1430-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 141#L734true assume !(1 == ~t11_pc~0); 430#L734-2true is_transmit11_triggered_~__retres1~11#1 := 0; 483#L745true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 711#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12#L1438true assume !(0 != activate_threads_~tmp___10~0#1); 663#L1438-2true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1214#L1213true assume !(1 == ~M_E~0); 475#L1213-2true assume !(1 == ~T1_E~0); 981#L1218-1true assume !(1 == ~T2_E~0); 29#L1223-1true assume !(1 == ~T3_E~0); 459#L1228-1true assume !(1 == ~T4_E~0); 1275#L1233-1true assume !(1 == ~T5_E~0); 1460#L1238-1true assume !(1 == ~T6_E~0); 764#L1243-1true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1418#L1248-1true assume !(1 == ~T8_E~0); 811#L1253-1true assume !(1 == ~T9_E~0); 1112#L1258-1true assume !(1 == ~T10_E~0); 789#L1263-1true assume !(1 == ~T11_E~0); 1160#L1268-1true assume !(1 == ~E_1~0); 617#L1273-1true assume !(1 == ~E_2~0); 1256#L1278-1true assume !(1 == ~E_3~0); 314#L1283-1true assume 1 == ~E_4~0;~E_4~0 := 2; 1306#L1288-1true assume !(1 == ~E_5~0); 939#L1293-1true assume !(1 == ~E_6~0); 890#L1298-1true assume !(1 == ~E_7~0); 647#L1303-1true assume !(1 == ~E_8~0); 321#L1308-1true assume !(1 == ~E_9~0); 260#L1313-1true assume !(1 == ~E_10~0); 1385#L1318-1true assume !(1 == ~E_11~0); 265#L1323-1true assume { :end_inline_reset_delta_events } true; 1165#L1644-2true [2024-11-20 22:59:09,998 INFO L747 eck$LassoCheckResult]: Loop: 1165#L1644-2true assume !false; 702#L1645true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 208#L1065-1true assume !true; 857#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 543#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 966#L1090-3true assume !(0 == ~M_E~0); 1054#L1090-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1388#L1095-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 999#L1100-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1267#L1105-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 193#L1110-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1102#L1115-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 356#L1120-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 762#L1125-3true assume !(0 == ~T8_E~0); 1140#L1130-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1305#L1135-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 308#L1140-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 43#L1145-3true assume 0 == ~E_1~0;~E_1~0 := 1; 497#L1150-3true assume 0 == ~E_2~0;~E_2~0 := 1; 104#L1155-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1440#L1160-3true assume 0 == ~E_4~0;~E_4~0 := 1; 299#L1165-3true assume !(0 == ~E_5~0); 1494#L1170-3true assume 0 == ~E_6~0;~E_6~0 := 1; 573#L1175-3true assume 0 == ~E_7~0;~E_7~0 := 1; 250#L1180-3true assume 0 == ~E_8~0;~E_8~0 := 1; 117#L1185-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1308#L1190-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1117#L1195-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1492#L1200-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 446#L525-36true assume 1 == ~m_pc~0; 1121#L526-12true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 168#L536-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1127#is_master_triggered_returnLabel#13true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 329#L1350-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 572#L1350-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 282#L544-36true assume !(1 == ~t1_pc~0); 936#L544-38true is_transmit1_triggered_~__retres1~1#1 := 0; 679#L555-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1125#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1286#L1358-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1093#L1358-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 927#L563-36true assume !(1 == ~t2_pc~0); 974#L563-38true is_transmit2_triggered_~__retres1~2#1 := 0; 41#L574-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 904#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1284#L1366-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 457#L1366-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1387#L582-36true assume 1 == ~t3_pc~0; 350#L583-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 509#L593-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 411#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 670#L1374-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 482#L1374-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 443#L601-36true assume 1 == ~t4_pc~0; 368#L602-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1475#L612-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 557#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1064#L1382-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1208#L1382-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 911#L620-36true assume !(1 == ~t5_pc~0); 1472#L620-38true is_transmit5_triggered_~__retres1~5#1 := 0; 747#L631-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1075#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 382#L1390-36true assume !(0 != activate_threads_~tmp___4~0#1); 174#L1390-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65#L639-36true assume !(1 == ~t6_pc~0); 1429#L639-38true is_transmit6_triggered_~__retres1~6#1 := 0; 85#L650-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 387#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 203#L1398-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 603#L1398-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1207#L658-36true assume 1 == ~t7_pc~0; 123#L659-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1032#L669-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1038#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61#L1406-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 733#L1406-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 950#L677-36true assume 1 == ~t8_pc~0; 1110#L678-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 644#L688-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 645#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1205#L1414-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 558#L1414-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1114#L696-36true assume !(1 == ~t9_pc~0); 1330#L696-38true is_transmit9_triggered_~__retres1~9#1 := 0; 846#L707-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 436#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1033#L1422-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 574#L1422-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1281#L715-36true assume !(1 == ~t10_pc~0); 545#L715-38true is_transmit10_triggered_~__retres1~10#1 := 0; 13#L726-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 320#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2#L1430-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1079#L1430-38true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 200#L734-36true assume !(1 == ~t11_pc~0); 49#L734-38true is_transmit11_triggered_~__retres1~11#1 := 0; 209#L745-12true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1331#is_transmit11_triggered_returnLabel#13true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9#L1438-36true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 625#L1438-38true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1119#L1213-3true assume 1 == ~M_E~0;~M_E~0 := 2; 361#L1213-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 730#L1218-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 225#L1223-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 770#L1228-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 332#L1233-3true assume !(1 == ~T5_E~0); 1295#L1238-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 507#L1243-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1063#L1248-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1423#L1253-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1070#L1258-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 216#L1263-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1015#L1268-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1040#L1273-3true assume !(1 == ~E_2~0); 1473#L1278-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1043#L1283-3true assume 1 == ~E_4~0;~E_4~0 := 2; 428#L1288-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1316#L1293-3true assume 1 == ~E_6~0;~E_6~0 := 2; 328#L1298-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1167#L1303-3true assume 1 == ~E_8~0;~E_8~0 := 2; 699#L1308-3true assume 1 == ~E_9~0;~E_9~0 := 2; 326#L1313-3true assume !(1 == ~E_10~0); 1066#L1318-3true assume 1 == ~E_11~0;~E_11~0 := 2; 217#L1323-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1450#L829-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 439#L891-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 316#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1451#L1663true assume !(0 == start_simulation_~tmp~3#1); 1355#L1663-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 602#L829-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 526#L891-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 76#L1618true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 254#L1625true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 560#stop_simulation_returnLabel#1true start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1194#L1676true assume !(0 != start_simulation_~tmp___0~1#1); 1165#L1644-2true [2024-11-20 22:59:10,003 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:10,004 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 1 times [2024-11-20 22:59:10,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:10,027 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359642039] [2024-11-20 22:59:10,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:10,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:10,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:10,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:10,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:10,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359642039] [2024-11-20 22:59:10,277 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359642039] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:10,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:10,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:10,279 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125448240] [2024-11-20 22:59:10,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:10,283 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:10,283 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:10,284 INFO L85 PathProgramCache]: Analyzing trace with hash -1163004199, now seen corresponding path program 1 times [2024-11-20 22:59:10,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:10,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394470717] [2024-11-20 22:59:10,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:10,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:10,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:10,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:10,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:10,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [394470717] [2024-11-20 22:59:10,329 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [394470717] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:10,329 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:10,329 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-20 22:59:10,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880733122] [2024-11-20 22:59:10,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:10,330 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:10,331 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:10,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-20 22:59:10,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-20 22:59:10,358 INFO L87 Difference]: Start difference. First operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 68.5) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:10,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:10,408 INFO L93 Difference]: Finished difference Result 1494 states and 2211 transitions. [2024-11-20 22:59:10,414 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1494 states and 2211 transitions. [2024-11-20 22:59:10,423 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:10,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1494 states to 1488 states and 2205 transitions. [2024-11-20 22:59:10,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:10,435 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:10,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2205 transitions. [2024-11-20 22:59:10,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:10,442 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2024-11-20 22:59:10,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2205 transitions. [2024-11-20 22:59:10,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:10,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4818548387096775) internal successors, (2205), 1487 states have internal predecessors, (2205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:10,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2205 transitions. [2024-11-20 22:59:10,508 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2024-11-20 22:59:10,510 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-20 22:59:10,515 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2024-11-20 22:59:10,515 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-20 22:59:10,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2205 transitions. [2024-11-20 22:59:10,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:10,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:10,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:10,524 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:10,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:10,526 INFO L745 eck$LassoCheckResult]: Stem: 3441#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 3442#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3891#L761 assume !(1 == ~m_i~0);~m_st~0 := 2; 3892#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3763#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3656#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3385#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3033#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3034#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3078#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3079#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4023#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4024#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4066#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3482#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3483#L1090 assume !(0 == ~M_E~0); 3528#L1090-2 assume !(0 == ~T1_E~0); 3529#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4214#L1100-1 assume !(0 == ~T3_E~0); 4215#L1105-1 assume !(0 == ~T4_E~0); 3306#L1110-1 assume !(0 == ~T5_E~0); 3307#L1115-1 assume !(0 == ~T6_E~0); 3692#L1120-1 assume !(0 == ~T7_E~0); 4000#L1125-1 assume !(0 == ~T8_E~0); 4472#L1130-1 assume !(0 == ~T9_E~0); 4235#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3487#L1140-1 assume !(0 == ~T11_E~0); 3488#L1145-1 assume !(0 == ~E_1~0); 4169#L1150-1 assume !(0 == ~E_2~0); 3669#L1155-1 assume !(0 == ~E_3~0); 3670#L1160-1 assume !(0 == ~E_4~0); 3768#L1165-1 assume !(0 == ~E_5~0); 3769#L1170-1 assume !(0 == ~E_6~0); 4407#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3849#L1180-1 assume !(0 == ~E_8~0); 3850#L1185-1 assume !(0 == ~E_9~0); 3484#L1190-1 assume !(0 == ~E_10~0); 3485#L1195-1 assume !(0 == ~E_11~0); 3865#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3689#L525 assume !(1 == ~m_pc~0); 3123#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3124#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4309#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4284#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3474#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3475#L544 assume 1 == ~t1_pc~0; 3744#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3691#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3103#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3329#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3969#L563 assume !(1 == ~t2_pc~0); 4155#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3142#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3143#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3556#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3557#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4047#L582 assume 1 == ~t3_pc~0; 3275#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3276#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3025#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3026#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3211#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3212#L601 assume !(1 == ~t4_pc~0); 4181#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3693#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3225#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3226#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4176#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4448#L620 assume 1 == ~t5_pc~0; 3174#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3175#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4063#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4315#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4457#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4458#L639 assume !(1 == ~t6_pc~0); 3998#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3593#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3594#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3642#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3699#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3700#L658 assume 1 == ~t7_pc~0; 3999#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3916#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4463#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4116#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3477#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3478#L677 assume 1 == ~t8_pc~0; 3707#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3288#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3289#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3549#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3550#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4276#L696 assume !(1 == ~t9_pc~0); 3983#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3984#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3754#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3755#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4005#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4218#L715 assume 1 == ~t10_pc~0; 4225#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4097#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3903#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3904#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3843#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3282#L734 assume !(1 == ~t11_pc~0); 3283#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3770#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3854#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3023#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3024#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4064#L1213 assume !(1 == ~M_E~0); 3841#L1213-2 assume !(1 == ~T1_E~0); 3842#L1218-1 assume !(1 == ~T2_E~0); 3056#L1223-1 assume !(1 == ~T3_E~0); 3057#L1228-1 assume !(1 == ~T4_E~0); 3816#L1233-1 assume !(1 == ~T5_E~0); 4459#L1238-1 assume !(1 == ~T6_E~0); 4174#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4175#L1248-1 assume !(1 == ~T8_E~0); 4221#L1253-1 assume !(1 == ~T9_E~0); 4222#L1258-1 assume !(1 == ~T10_E~0); 4197#L1263-1 assume !(1 == ~T11_E~0); 4198#L1268-1 assume !(1 == ~E_1~0); 4018#L1273-1 assume !(1 == ~E_2~0); 4019#L1278-1 assume !(1 == ~E_3~0); 3589#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3590#L1288-1 assume !(1 == ~E_5~0); 4320#L1293-1 assume !(1 == ~E_6~0); 4280#L1298-1 assume !(1 == ~E_7~0); 4051#L1303-1 assume !(1 == ~E_8~0); 3599#L1308-1 assume !(1 == ~E_9~0); 3491#L1313-1 assume !(1 == ~E_10~0); 3492#L1318-1 assume !(1 == ~E_11~0); 3502#L1323-1 assume { :end_inline_reset_delta_events } true; 3503#L1644-2 [2024-11-20 22:59:10,528 INFO L747 eck$LassoCheckResult]: Loop: 3503#L1644-2 assume !false; 4113#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3407#L1065-1 assume !false; 3408#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4455#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3138#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3715#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3604#L906 assume !(0 != eval_~tmp~0#1); 3606#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3926#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3927#L1090-3 assume !(0 == ~M_E~0); 4335#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4392#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4357#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4358#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3380#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3381#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3657#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3658#L1125-3 assume !(0 == ~T8_E~0); 4173#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4430#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3581#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3090#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3091#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3214#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3215#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3562#L1165-3 assume !(0 == ~E_5~0); 3563#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3962#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3476#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3240#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3241#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4418#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4419#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3797#L525-36 assume !(1 == ~m_pc~0); 3798#L525-38 is_master_triggered_~__retres1~0#1 := 0; 3338#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3339#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3614#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3615#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3525#L544-36 assume 1 == ~t1_pc~0; 3526#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4085#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4086#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4423#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4405#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4310#L563-36 assume !(1 == ~t2_pc~0); 3328#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3086#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3087#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4291#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3813#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3814#L582-36 assume !(1 == ~t3_pc~0); 3648#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3647#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3745#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3746#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3851#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3791#L601-36 assume 1 == ~t4_pc~0; 3677#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3678#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3943#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3944#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4396#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4297#L620-36 assume 1 == ~t5_pc~0; 3728#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3729#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4158#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3704#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 3347#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3134#L639-36 assume !(1 == ~t6_pc~0); 3136#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3172#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3173#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3397#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3398#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4003#L658-36 assume !(1 == ~t7_pc~0); 3147#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3148#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4382#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3125#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3126#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4147#L677-36 assume 1 == ~t8_pc~0; 4324#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3919#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4048#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4049#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3945#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3946#L696-36 assume 1 == ~t9_pc~0; 3837#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3838#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3779#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3780#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3963#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3964#L715-36 assume !(1 == ~t10_pc~0); 3925#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3021#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3022#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2999#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3000#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3390#L734-36 assume !(1 == ~t11_pc~0); 3100#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 3101#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3406#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3015#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3016#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4027#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3663#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3664#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3438#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3439#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3618#L1233-3 assume !(1 == ~T5_E~0); 3619#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3888#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3889#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4395#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4397#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3420#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3421#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4370#L1273-3 assume !(1 == ~E_2~0); 4385#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4387#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3766#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3767#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3612#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3613#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4109#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3609#L1313-3 assume !(1 == ~E_10~0); 3610#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3422#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3423#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3365#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3591#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3592#L1663 assume !(0 == start_simulation_~tmp~3#1); 3263#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4001#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3209#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3092#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3093#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3158#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3481#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3947#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3503#L1644-2 [2024-11-20 22:59:10,529 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:10,529 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 2 times [2024-11-20 22:59:10,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:10,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453522844] [2024-11-20 22:59:10,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:10,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:10,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:10,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:10,601 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:10,601 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453522844] [2024-11-20 22:59:10,601 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [453522844] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:10,601 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:10,601 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:10,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [757256158] [2024-11-20 22:59:10,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:10,602 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:10,602 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:10,602 INFO L85 PathProgramCache]: Analyzing trace with hash -825746646, now seen corresponding path program 1 times [2024-11-20 22:59:10,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:10,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328425868] [2024-11-20 22:59:10,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:10,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:10,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:10,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:10,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:10,696 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328425868] [2024-11-20 22:59:10,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328425868] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:10,697 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:10,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:10,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [379345667] [2024-11-20 22:59:10,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:10,697 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:10,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:10,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:10,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:10,698 INFO L87 Difference]: Start difference. First operand 1488 states and 2205 transitions. cyclomatic complexity: 718 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:10,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:10,733 INFO L93 Difference]: Finished difference Result 1488 states and 2204 transitions. [2024-11-20 22:59:10,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2204 transitions. [2024-11-20 22:59:10,739 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:10,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2204 transitions. [2024-11-20 22:59:10,745 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:10,746 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:10,747 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2204 transitions. [2024-11-20 22:59:10,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:10,750 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2024-11-20 22:59:10,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2204 transitions. [2024-11-20 22:59:10,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:10,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4811827956989247) internal successors, (2204), 1487 states have internal predecessors, (2204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:10,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2204 transitions. [2024-11-20 22:59:10,769 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2024-11-20 22:59:10,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:10,770 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2024-11-20 22:59:10,771 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-20 22:59:10,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2204 transitions. [2024-11-20 22:59:10,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:10,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:10,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:10,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:10,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:10,778 INFO L745 eck$LassoCheckResult]: Stem: 6424#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 6425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7406#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7407#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6874#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 6875#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6746#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6639#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6368#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6016#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6017#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6061#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6062#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7004#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7005#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7049#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6465#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6466#L1090 assume !(0 == ~M_E~0); 6508#L1090-2 assume !(0 == ~T1_E~0); 6509#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7196#L1100-1 assume !(0 == ~T3_E~0); 7197#L1105-1 assume !(0 == ~T4_E~0); 6288#L1110-1 assume !(0 == ~T5_E~0); 6289#L1115-1 assume !(0 == ~T6_E~0); 6675#L1120-1 assume !(0 == ~T7_E~0); 6983#L1125-1 assume !(0 == ~T8_E~0); 7455#L1130-1 assume !(0 == ~T9_E~0); 7218#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6470#L1140-1 assume !(0 == ~T11_E~0); 6471#L1145-1 assume !(0 == ~E_1~0); 7152#L1150-1 assume !(0 == ~E_2~0); 6652#L1155-1 assume !(0 == ~E_3~0); 6653#L1160-1 assume !(0 == ~E_4~0); 6751#L1165-1 assume !(0 == ~E_5~0); 6752#L1170-1 assume !(0 == ~E_6~0); 7390#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6832#L1180-1 assume !(0 == ~E_8~0); 6833#L1185-1 assume !(0 == ~E_9~0); 6467#L1190-1 assume !(0 == ~E_10~0); 6468#L1195-1 assume !(0 == ~E_11~0); 6848#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6667#L525 assume !(1 == ~m_pc~0); 6106#L525-2 is_master_triggered_~__retres1~0#1 := 0; 6107#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7292#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7265#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6457#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6458#L544 assume 1 == ~t1_pc~0; 6727#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6674#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6080#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6081#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 6312#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6952#L563 assume !(1 == ~t2_pc~0); 7138#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6125#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6126#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6536#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 6537#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7030#L582 assume 1 == ~t3_pc~0; 6256#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6257#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6008#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6009#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 6194#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6195#L601 assume !(1 == ~t4_pc~0); 7164#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6676#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6205#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 7159#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7431#L620 assume 1 == ~t5_pc~0; 6153#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6154#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7046#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7297#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 7440#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7441#L639 assume !(1 == ~t6_pc~0); 6981#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6574#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6575#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6625#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 6682#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6683#L658 assume 1 == ~t7_pc~0; 6982#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6898#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7446#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7098#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 6460#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6461#L677 assume 1 == ~t8_pc~0; 6688#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6271#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6272#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6532#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 6533#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7259#L696 assume !(1 == ~t9_pc~0); 6964#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6965#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6737#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6738#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6988#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7201#L715 assume 1 == ~t10_pc~0; 7208#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7080#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6886#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6887#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 6826#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6265#L734 assume !(1 == ~t11_pc~0); 6266#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 6753#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6835#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6004#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 6005#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7047#L1213 assume !(1 == ~M_E~0); 6823#L1213-2 assume !(1 == ~T1_E~0); 6824#L1218-1 assume !(1 == ~T2_E~0); 6039#L1223-1 assume !(1 == ~T3_E~0); 6040#L1228-1 assume !(1 == ~T4_E~0); 6799#L1233-1 assume !(1 == ~T5_E~0); 7442#L1238-1 assume !(1 == ~T6_E~0); 7157#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7158#L1248-1 assume !(1 == ~T8_E~0); 7204#L1253-1 assume !(1 == ~T9_E~0); 7205#L1258-1 assume !(1 == ~T10_E~0); 7180#L1263-1 assume !(1 == ~T11_E~0); 7181#L1268-1 assume !(1 == ~E_1~0); 7001#L1273-1 assume !(1 == ~E_2~0); 7002#L1278-1 assume !(1 == ~E_3~0); 6572#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6573#L1288-1 assume !(1 == ~E_5~0); 7303#L1293-1 assume !(1 == ~E_6~0); 7263#L1298-1 assume !(1 == ~E_7~0); 7034#L1303-1 assume !(1 == ~E_8~0); 6582#L1308-1 assume !(1 == ~E_9~0); 6474#L1313-1 assume !(1 == ~E_10~0); 6475#L1318-1 assume !(1 == ~E_11~0); 6482#L1323-1 assume { :end_inline_reset_delta_events } true; 6483#L1644-2 [2024-11-20 22:59:10,778 INFO L747 eck$LassoCheckResult]: Loop: 6483#L1644-2 assume !false; 7096#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6389#L1065-1 assume !false; 6390#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7438#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6121#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6698#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6587#L906 assume !(0 != eval_~tmp~0#1); 6589#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6908#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6909#L1090-3 assume !(0 == ~M_E~0); 7318#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7375#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7340#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7341#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6363#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6364#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6640#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6641#L1125-3 assume !(0 == ~T8_E~0); 7156#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7413#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6562#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 6071#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6072#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6196#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6197#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6545#L1165-3 assume !(0 == ~E_5~0); 6546#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6945#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6459#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6220#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6221#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7401#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7402#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6780#L525-36 assume !(1 == ~m_pc~0); 6781#L525-38 is_master_triggered_~__retres1~0#1 := 0; 6321#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6322#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6597#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6598#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6511#L544-36 assume 1 == ~t1_pc~0; 6512#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7068#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7069#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7408#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7388#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7293#L563-36 assume 1 == ~t2_pc~0; 6310#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6069#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6070#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7274#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6796#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6797#L582-36 assume 1 == ~t3_pc~0; 6629#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6630#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6728#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6729#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6834#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6774#L601-36 assume 1 == ~t4_pc~0; 6660#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6661#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6926#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6927#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7379#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7280#L620-36 assume 1 == ~t5_pc~0; 6713#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6714#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7141#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6687#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 6330#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6117#L639-36 assume 1 == ~t6_pc~0; 6118#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6158#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6159#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6380#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6381#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6986#L658-36 assume !(1 == ~t7_pc~0); 6130#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 6131#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7365#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6108#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6109#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7130#L677-36 assume !(1 == ~t8_pc~0); 6901#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6902#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7031#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7032#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6928#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6929#L696-36 assume 1 == ~t9_pc~0; 6820#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6821#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6762#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6763#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6946#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6947#L715-36 assume 1 == ~t10_pc~0; 7091#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 6006#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6007#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5982#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5983#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6373#L734-36 assume !(1 == ~t11_pc~0); 6085#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 6086#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6391#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5998#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5999#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7010#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6648#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6649#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6421#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6422#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6601#L1233-3 assume !(1 == ~T5_E~0); 6602#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6871#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6872#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7378#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7380#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6404#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6405#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7353#L1273-3 assume !(1 == ~E_2~0); 7368#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7370#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6749#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6750#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6595#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6596#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7092#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6592#L1313-3 assume !(1 == ~E_10~0); 6593#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 6406#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6407#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6348#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6576#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6577#L1663 assume !(0 == start_simulation_~tmp~3#1); 6246#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6984#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6192#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6078#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 6079#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6141#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6464#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6930#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 6483#L1644-2 [2024-11-20 22:59:10,779 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:10,779 INFO L85 PathProgramCache]: Analyzing trace with hash -456355416, now seen corresponding path program 1 times [2024-11-20 22:59:10,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:10,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517962597] [2024-11-20 22:59:10,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:10,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:10,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:10,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:10,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:10,830 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517962597] [2024-11-20 22:59:10,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517962597] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:10,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:10,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:10,831 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596238646] [2024-11-20 22:59:10,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:10,832 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:10,832 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:10,832 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 1 times [2024-11-20 22:59:10,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:10,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532557623] [2024-11-20 22:59:10,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:10,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:10,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:10,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:10,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:10,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1532557623] [2024-11-20 22:59:10,897 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1532557623] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:10,897 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:10,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:10,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742268720] [2024-11-20 22:59:10,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:10,898 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:10,898 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:10,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:10,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:10,899 INFO L87 Difference]: Start difference. First operand 1488 states and 2204 transitions. cyclomatic complexity: 717 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:10,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:10,946 INFO L93 Difference]: Finished difference Result 1488 states and 2203 transitions. [2024-11-20 22:59:10,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2203 transitions. [2024-11-20 22:59:10,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:10,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2203 transitions. [2024-11-20 22:59:10,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:10,957 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:10,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2203 transitions. [2024-11-20 22:59:10,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:10,959 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2024-11-20 22:59:10,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2203 transitions. [2024-11-20 22:59:10,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:10,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.480510752688172) internal successors, (2203), 1487 states have internal predecessors, (2203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:10,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2203 transitions. [2024-11-20 22:59:10,976 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2024-11-20 22:59:10,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:10,978 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2024-11-20 22:59:10,978 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-20 22:59:10,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2203 transitions. [2024-11-20 22:59:10,983 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:10,983 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:10,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:10,985 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:10,985 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:10,985 INFO L745 eck$LassoCheckResult]: Stem: 9407#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 9408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10389#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10390#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9857#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 9858#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9729#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9622#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9351#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8999#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9000#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9044#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9045#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9987#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9988#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10032#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9448#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9449#L1090 assume !(0 == ~M_E~0); 9491#L1090-2 assume !(0 == ~T1_E~0); 9492#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10180#L1100-1 assume !(0 == ~T3_E~0); 10181#L1105-1 assume !(0 == ~T4_E~0); 9272#L1110-1 assume !(0 == ~T5_E~0); 9273#L1115-1 assume !(0 == ~T6_E~0); 9658#L1120-1 assume !(0 == ~T7_E~0); 9966#L1125-1 assume !(0 == ~T8_E~0); 10438#L1130-1 assume !(0 == ~T9_E~0); 10201#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9453#L1140-1 assume !(0 == ~T11_E~0); 9454#L1145-1 assume !(0 == ~E_1~0); 10135#L1150-1 assume !(0 == ~E_2~0); 9635#L1155-1 assume !(0 == ~E_3~0); 9636#L1160-1 assume !(0 == ~E_4~0); 9734#L1165-1 assume !(0 == ~E_5~0); 9735#L1170-1 assume !(0 == ~E_6~0); 10373#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9815#L1180-1 assume !(0 == ~E_8~0); 9816#L1185-1 assume !(0 == ~E_9~0); 9450#L1190-1 assume !(0 == ~E_10~0); 9451#L1195-1 assume !(0 == ~E_11~0); 9831#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9655#L525 assume !(1 == ~m_pc~0); 9089#L525-2 is_master_triggered_~__retres1~0#1 := 0; 9090#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10275#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10250#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9440#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9441#L544 assume 1 == ~t1_pc~0; 9710#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9657#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9068#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9069#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 9295#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9935#L563 assume !(1 == ~t2_pc~0); 10121#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9108#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9109#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9519#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 9520#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10013#L582 assume 1 == ~t3_pc~0; 9241#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9242#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8991#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8992#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 9177#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9178#L601 assume !(1 == ~t4_pc~0); 10147#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9659#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9191#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9192#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 10142#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10414#L620 assume 1 == ~t5_pc~0; 9140#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9141#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10029#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10281#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 10423#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10424#L639 assume !(1 == ~t6_pc~0); 9964#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9559#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9560#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9608#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 9665#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9666#L658 assume 1 == ~t7_pc~0; 9965#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9882#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10429#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10082#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 9443#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9444#L677 assume 1 == ~t8_pc~0; 9673#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9254#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9255#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9515#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 9516#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10242#L696 assume !(1 == ~t9_pc~0); 9949#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9950#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9720#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9721#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9971#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10184#L715 assume 1 == ~t10_pc~0; 10191#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10063#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9869#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9870#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 9809#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9248#L734 assume !(1 == ~t11_pc~0); 9249#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 9736#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9818#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8989#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 8990#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10030#L1213 assume !(1 == ~M_E~0); 9807#L1213-2 assume !(1 == ~T1_E~0); 9808#L1218-1 assume !(1 == ~T2_E~0); 9022#L1223-1 assume !(1 == ~T3_E~0); 9023#L1228-1 assume !(1 == ~T4_E~0); 9782#L1233-1 assume !(1 == ~T5_E~0); 10425#L1238-1 assume !(1 == ~T6_E~0); 10140#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10141#L1248-1 assume !(1 == ~T8_E~0); 10187#L1253-1 assume !(1 == ~T9_E~0); 10188#L1258-1 assume !(1 == ~T10_E~0); 10163#L1263-1 assume !(1 == ~T11_E~0); 10164#L1268-1 assume !(1 == ~E_1~0); 9984#L1273-1 assume !(1 == ~E_2~0); 9985#L1278-1 assume !(1 == ~E_3~0); 9555#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9556#L1288-1 assume !(1 == ~E_5~0); 10286#L1293-1 assume !(1 == ~E_6~0); 10246#L1298-1 assume !(1 == ~E_7~0); 10017#L1303-1 assume !(1 == ~E_8~0); 9565#L1308-1 assume !(1 == ~E_9~0); 9457#L1313-1 assume !(1 == ~E_10~0); 9458#L1318-1 assume !(1 == ~E_11~0); 9468#L1323-1 assume { :end_inline_reset_delta_events } true; 9469#L1644-2 [2024-11-20 22:59:10,986 INFO L747 eck$LassoCheckResult]: Loop: 9469#L1644-2 assume !false; 10079#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9373#L1065-1 assume !false; 9374#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10421#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9104#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9681#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9570#L906 assume !(0 != eval_~tmp~0#1); 9572#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9892#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9893#L1090-3 assume !(0 == ~M_E~0); 10301#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10358#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10323#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10324#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9346#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9347#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9623#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9624#L1125-3 assume !(0 == ~T8_E~0); 10139#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10396#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9547#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9056#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9057#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9180#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9181#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9528#L1165-3 assume !(0 == ~E_5~0); 9529#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9928#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9442#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9204#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9205#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10384#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10385#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9763#L525-36 assume !(1 == ~m_pc~0); 9764#L525-38 is_master_triggered_~__retres1~0#1 := 0; 9309#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9310#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9580#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9581#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9494#L544-36 assume 1 == ~t1_pc~0; 9495#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10051#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10052#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10391#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10372#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10276#L563-36 assume 1 == ~t2_pc~0; 9293#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9049#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9050#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10257#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9779#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9780#L582-36 assume 1 == ~t3_pc~0; 9612#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9613#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9711#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9712#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9817#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9754#L601-36 assume 1 == ~t4_pc~0; 9643#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9644#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9909#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9910#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10362#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10263#L620-36 assume !(1 == ~t5_pc~0); 9696#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9695#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10124#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9670#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 9313#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9100#L639-36 assume 1 == ~t6_pc~0; 9101#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9138#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9139#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9363#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9364#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9969#L658-36 assume !(1 == ~t7_pc~0); 9113#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 9114#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10348#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9091#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9092#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10113#L677-36 assume 1 == ~t8_pc~0; 10290#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9885#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10014#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10015#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9911#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9912#L696-36 assume 1 == ~t9_pc~0; 9803#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9804#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9745#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9746#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9929#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9930#L715-36 assume !(1 == ~t10_pc~0); 9891#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 8987#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8988#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8965#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8966#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9356#L734-36 assume !(1 == ~t11_pc~0); 9066#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 9067#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9372#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8981#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8982#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9993#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9629#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9630#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9404#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9405#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9584#L1233-3 assume !(1 == ~T5_E~0); 9585#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9854#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9855#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10361#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10363#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9386#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9387#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10336#L1273-3 assume !(1 == ~E_2~0); 10351#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10353#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9732#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9733#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9578#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9579#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10075#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9575#L1313-3 assume !(1 == ~E_10~0); 9576#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9388#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9389#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9331#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9557#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9558#L1663 assume !(0 == start_simulation_~tmp~3#1); 9224#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9967#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9175#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9058#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 9059#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9124#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9447#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9913#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 9469#L1644-2 [2024-11-20 22:59:10,987 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:10,987 INFO L85 PathProgramCache]: Analyzing trace with hash 88517158, now seen corresponding path program 1 times [2024-11-20 22:59:10,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:10,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061380938] [2024-11-20 22:59:10,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:10,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:10,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061380938] [2024-11-20 22:59:11,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061380938] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,032 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,032 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416390537] [2024-11-20 22:59:11,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,033 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:11,034 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,034 INFO L85 PathProgramCache]: Analyzing trace with hash -1935633556, now seen corresponding path program 1 times [2024-11-20 22:59:11,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097004147] [2024-11-20 22:59:11,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097004147] [2024-11-20 22:59:11,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097004147] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946074726] [2024-11-20 22:59:11,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,090 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:11,090 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:11,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:11,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:11,091 INFO L87 Difference]: Start difference. First operand 1488 states and 2203 transitions. cyclomatic complexity: 716 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:11,111 INFO L93 Difference]: Finished difference Result 1488 states and 2202 transitions. [2024-11-20 22:59:11,112 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2202 transitions. [2024-11-20 22:59:11,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,122 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2202 transitions. [2024-11-20 22:59:11,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:11,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:11,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2202 transitions. [2024-11-20 22:59:11,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:11,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2024-11-20 22:59:11,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2202 transitions. [2024-11-20 22:59:11,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:11,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4798387096774193) internal successors, (2202), 1487 states have internal predecessors, (2202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2202 transitions. [2024-11-20 22:59:11,145 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2024-11-20 22:59:11,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:11,147 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2024-11-20 22:59:11,147 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-20 22:59:11,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2202 transitions. [2024-11-20 22:59:11,151 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:11,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:11,153 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,153 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,153 INFO L745 eck$LassoCheckResult]: Stem: 12390#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 12391#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13372#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13373#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12840#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 12841#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12712#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12605#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12334#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11982#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11983#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12027#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12028#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12970#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12971#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13015#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12431#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12432#L1090 assume !(0 == ~M_E~0); 12474#L1090-2 assume !(0 == ~T1_E~0); 12475#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13162#L1100-1 assume !(0 == ~T3_E~0); 13163#L1105-1 assume !(0 == ~T4_E~0); 12254#L1110-1 assume !(0 == ~T5_E~0); 12255#L1115-1 assume !(0 == ~T6_E~0); 12641#L1120-1 assume !(0 == ~T7_E~0); 12949#L1125-1 assume !(0 == ~T8_E~0); 13421#L1130-1 assume !(0 == ~T9_E~0); 13184#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12436#L1140-1 assume !(0 == ~T11_E~0); 12437#L1145-1 assume !(0 == ~E_1~0); 13118#L1150-1 assume !(0 == ~E_2~0); 12618#L1155-1 assume !(0 == ~E_3~0); 12619#L1160-1 assume !(0 == ~E_4~0); 12717#L1165-1 assume !(0 == ~E_5~0); 12718#L1170-1 assume !(0 == ~E_6~0); 13356#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12798#L1180-1 assume !(0 == ~E_8~0); 12799#L1185-1 assume !(0 == ~E_9~0); 12433#L1190-1 assume !(0 == ~E_10~0); 12434#L1195-1 assume !(0 == ~E_11~0); 12814#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12633#L525 assume !(1 == ~m_pc~0); 12072#L525-2 is_master_triggered_~__retres1~0#1 := 0; 12073#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13258#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13231#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12423#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12424#L544 assume 1 == ~t1_pc~0; 12693#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12640#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12046#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12047#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 12278#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12918#L563 assume !(1 == ~t2_pc~0); 13104#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12091#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12092#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12502#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 12503#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12996#L582 assume 1 == ~t3_pc~0; 12222#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12223#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11974#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11975#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 12160#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12161#L601 assume !(1 == ~t4_pc~0); 13130#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12642#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12170#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12171#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 13125#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13397#L620 assume 1 == ~t5_pc~0; 12119#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12120#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13012#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13263#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 13406#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13407#L639 assume !(1 == ~t6_pc~0); 12947#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12540#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12541#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12591#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 12648#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12649#L658 assume 1 == ~t7_pc~0; 12948#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12864#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13412#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13064#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 12426#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12427#L677 assume 1 == ~t8_pc~0; 12654#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12237#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12238#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12498#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 12499#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13225#L696 assume !(1 == ~t9_pc~0); 12930#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 12931#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12703#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12704#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12954#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13167#L715 assume 1 == ~t10_pc~0; 13174#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13046#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12852#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12853#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 12792#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12231#L734 assume !(1 == ~t11_pc~0); 12232#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 12719#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12801#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11970#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 11971#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13013#L1213 assume !(1 == ~M_E~0); 12789#L1213-2 assume !(1 == ~T1_E~0); 12790#L1218-1 assume !(1 == ~T2_E~0); 12005#L1223-1 assume !(1 == ~T3_E~0); 12006#L1228-1 assume !(1 == ~T4_E~0); 12765#L1233-1 assume !(1 == ~T5_E~0); 13408#L1238-1 assume !(1 == ~T6_E~0); 13123#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13124#L1248-1 assume !(1 == ~T8_E~0); 13170#L1253-1 assume !(1 == ~T9_E~0); 13171#L1258-1 assume !(1 == ~T10_E~0); 13146#L1263-1 assume !(1 == ~T11_E~0); 13147#L1268-1 assume !(1 == ~E_1~0); 12967#L1273-1 assume !(1 == ~E_2~0); 12968#L1278-1 assume !(1 == ~E_3~0); 12538#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12539#L1288-1 assume !(1 == ~E_5~0); 13269#L1293-1 assume !(1 == ~E_6~0); 13229#L1298-1 assume !(1 == ~E_7~0); 13000#L1303-1 assume !(1 == ~E_8~0); 12548#L1308-1 assume !(1 == ~E_9~0); 12440#L1313-1 assume !(1 == ~E_10~0); 12441#L1318-1 assume !(1 == ~E_11~0); 12448#L1323-1 assume { :end_inline_reset_delta_events } true; 12449#L1644-2 [2024-11-20 22:59:11,155 INFO L747 eck$LassoCheckResult]: Loop: 12449#L1644-2 assume !false; 13062#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12355#L1065-1 assume !false; 12356#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13404#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12087#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12664#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12553#L906 assume !(0 != eval_~tmp~0#1); 12555#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12874#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12875#L1090-3 assume !(0 == ~M_E~0); 13284#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13341#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13306#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13307#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12329#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12330#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12606#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12607#L1125-3 assume !(0 == ~T8_E~0); 13122#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13379#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12528#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12037#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12038#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12162#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12163#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12511#L1165-3 assume !(0 == ~E_5~0); 12512#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12911#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12425#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12186#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12187#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13367#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13368#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12746#L525-36 assume !(1 == ~m_pc~0); 12747#L525-38 is_master_triggered_~__retres1~0#1 := 0; 12287#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12288#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12563#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12564#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12477#L544-36 assume 1 == ~t1_pc~0; 12478#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13034#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13035#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13374#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13354#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13259#L563-36 assume 1 == ~t2_pc~0; 12276#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12035#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12036#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13240#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12762#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12763#L582-36 assume 1 == ~t3_pc~0; 12595#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12596#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12694#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12695#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12800#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12740#L601-36 assume 1 == ~t4_pc~0; 12626#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12627#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12892#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12893#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13345#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13246#L620-36 assume 1 == ~t5_pc~0; 12679#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12680#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13107#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12653#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 12296#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12083#L639-36 assume 1 == ~t6_pc~0; 12084#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12124#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12125#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12346#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12347#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12952#L658-36 assume !(1 == ~t7_pc~0); 12096#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 12097#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13331#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12074#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12075#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13096#L677-36 assume !(1 == ~t8_pc~0); 12867#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12868#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12997#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12998#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12894#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12895#L696-36 assume 1 == ~t9_pc~0; 12786#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12787#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12728#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12729#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12912#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12913#L715-36 assume 1 == ~t10_pc~0; 13057#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11972#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11973#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11948#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11949#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12339#L734-36 assume !(1 == ~t11_pc~0); 12051#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 12052#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12357#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11964#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11965#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12976#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12614#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12615#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12387#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12388#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12567#L1233-3 assume !(1 == ~T5_E~0); 12568#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12837#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12838#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13344#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13346#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12370#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12371#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13319#L1273-3 assume !(1 == ~E_2~0); 13334#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13336#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12715#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12716#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12561#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12562#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13058#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12558#L1313-3 assume !(1 == ~E_10~0); 12559#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12372#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12373#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12314#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12542#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 12543#L1663 assume !(0 == start_simulation_~tmp~3#1); 12212#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12950#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12158#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12044#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 12045#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12107#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12430#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 12896#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 12449#L1644-2 [2024-11-20 22:59:11,155 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,155 INFO L85 PathProgramCache]: Analyzing trace with hash -586642968, now seen corresponding path program 1 times [2024-11-20 22:59:11,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [887989582] [2024-11-20 22:59:11,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [887989582] [2024-11-20 22:59:11,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [887989582] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,191 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,191 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1088933177] [2024-11-20 22:59:11,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,191 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:11,192 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,193 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 2 times [2024-11-20 22:59:11,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,193 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368998190] [2024-11-20 22:59:11,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,247 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368998190] [2024-11-20 22:59:11,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368998190] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,247 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612967877] [2024-11-20 22:59:11,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,248 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:11,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:11,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:11,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:11,249 INFO L87 Difference]: Start difference. First operand 1488 states and 2202 transitions. cyclomatic complexity: 715 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:11,269 INFO L93 Difference]: Finished difference Result 1488 states and 2201 transitions. [2024-11-20 22:59:11,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2201 transitions. [2024-11-20 22:59:11,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2201 transitions. [2024-11-20 22:59:11,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:11,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:11,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2201 transitions. [2024-11-20 22:59:11,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:11,282 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2024-11-20 22:59:11,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2201 transitions. [2024-11-20 22:59:11,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:11,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4791666666666667) internal successors, (2201), 1487 states have internal predecessors, (2201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2201 transitions. [2024-11-20 22:59:11,299 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2024-11-20 22:59:11,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:11,302 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2024-11-20 22:59:11,302 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-20 22:59:11,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2201 transitions. [2024-11-20 22:59:11,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:11,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:11,308 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,309 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,309 INFO L745 eck$LassoCheckResult]: Stem: 15373#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 15374#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16355#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16356#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15823#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 15824#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15695#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15588#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15317#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14965#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14966#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15010#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15011#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15953#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15954#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15998#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15414#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15415#L1090 assume !(0 == ~M_E~0); 15457#L1090-2 assume !(0 == ~T1_E~0); 15458#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16146#L1100-1 assume !(0 == ~T3_E~0); 16147#L1105-1 assume !(0 == ~T4_E~0); 15238#L1110-1 assume !(0 == ~T5_E~0); 15239#L1115-1 assume !(0 == ~T6_E~0); 15624#L1120-1 assume !(0 == ~T7_E~0); 15932#L1125-1 assume !(0 == ~T8_E~0); 16404#L1130-1 assume !(0 == ~T9_E~0); 16167#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15419#L1140-1 assume !(0 == ~T11_E~0); 15420#L1145-1 assume !(0 == ~E_1~0); 16101#L1150-1 assume !(0 == ~E_2~0); 15601#L1155-1 assume !(0 == ~E_3~0); 15602#L1160-1 assume !(0 == ~E_4~0); 15700#L1165-1 assume !(0 == ~E_5~0); 15701#L1170-1 assume !(0 == ~E_6~0); 16339#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15781#L1180-1 assume !(0 == ~E_8~0); 15782#L1185-1 assume !(0 == ~E_9~0); 15416#L1190-1 assume !(0 == ~E_10~0); 15417#L1195-1 assume !(0 == ~E_11~0); 15797#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15621#L525 assume !(1 == ~m_pc~0); 15055#L525-2 is_master_triggered_~__retres1~0#1 := 0; 15056#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16241#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16216#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15406#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15407#L544 assume 1 == ~t1_pc~0; 15676#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15623#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15034#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15035#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 15261#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15901#L563 assume !(1 == ~t2_pc~0); 16087#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15074#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15075#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15485#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 15486#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15979#L582 assume 1 == ~t3_pc~0; 15207#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15208#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14957#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14958#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 15143#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15144#L601 assume !(1 == ~t4_pc~0); 16113#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15625#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15157#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15158#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 16108#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16380#L620 assume 1 == ~t5_pc~0; 15104#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15105#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15995#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16247#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 16389#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16390#L639 assume !(1 == ~t6_pc~0); 15930#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15525#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15526#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15574#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 15631#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15632#L658 assume 1 == ~t7_pc~0; 15931#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15848#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16395#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16047#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 15409#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15410#L677 assume 1 == ~t8_pc~0; 15639#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15220#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15221#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15481#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 15482#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16208#L696 assume !(1 == ~t9_pc~0); 15915#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15916#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15686#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15687#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15937#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16150#L715 assume 1 == ~t10_pc~0; 16157#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16029#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15835#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15836#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 15775#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15214#L734 assume !(1 == ~t11_pc~0); 15215#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 15702#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15784#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14955#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 14956#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15996#L1213 assume !(1 == ~M_E~0); 15773#L1213-2 assume !(1 == ~T1_E~0); 15774#L1218-1 assume !(1 == ~T2_E~0); 14988#L1223-1 assume !(1 == ~T3_E~0); 14989#L1228-1 assume !(1 == ~T4_E~0); 15748#L1233-1 assume !(1 == ~T5_E~0); 16391#L1238-1 assume !(1 == ~T6_E~0); 16106#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16107#L1248-1 assume !(1 == ~T8_E~0); 16153#L1253-1 assume !(1 == ~T9_E~0); 16154#L1258-1 assume !(1 == ~T10_E~0); 16129#L1263-1 assume !(1 == ~T11_E~0); 16130#L1268-1 assume !(1 == ~E_1~0); 15950#L1273-1 assume !(1 == ~E_2~0); 15951#L1278-1 assume !(1 == ~E_3~0); 15521#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15522#L1288-1 assume !(1 == ~E_5~0); 16252#L1293-1 assume !(1 == ~E_6~0); 16212#L1298-1 assume !(1 == ~E_7~0); 15983#L1303-1 assume !(1 == ~E_8~0); 15531#L1308-1 assume !(1 == ~E_9~0); 15423#L1313-1 assume !(1 == ~E_10~0); 15424#L1318-1 assume !(1 == ~E_11~0); 15434#L1323-1 assume { :end_inline_reset_delta_events } true; 15435#L1644-2 [2024-11-20 22:59:11,310 INFO L747 eck$LassoCheckResult]: Loop: 15435#L1644-2 assume !false; 16045#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15339#L1065-1 assume !false; 15340#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16387#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15070#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15647#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15536#L906 assume !(0 != eval_~tmp~0#1); 15538#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15858#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15859#L1090-3 assume !(0 == ~M_E~0); 16267#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16324#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16289#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16290#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15312#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15313#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15589#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15590#L1125-3 assume !(0 == ~T8_E~0); 16105#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16362#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15513#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15022#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15023#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15146#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15147#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15494#L1165-3 assume !(0 == ~E_5~0); 15495#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15894#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15408#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15170#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15171#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16350#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16351#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15729#L525-36 assume !(1 == ~m_pc~0); 15730#L525-38 is_master_triggered_~__retres1~0#1 := 0; 15275#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15276#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15546#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15547#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15460#L544-36 assume 1 == ~t1_pc~0; 15461#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16017#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16018#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16357#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16338#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16242#L563-36 assume 1 == ~t2_pc~0; 15259#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15018#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15019#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16223#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15745#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15746#L582-36 assume 1 == ~t3_pc~0; 15578#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15579#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15677#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15678#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15783#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15723#L601-36 assume 1 == ~t4_pc~0; 15609#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15610#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15875#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15876#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16328#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16227#L620-36 assume 1 == ~t5_pc~0; 15660#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15661#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16090#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15636#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 15279#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15063#L639-36 assume 1 == ~t6_pc~0; 15064#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15102#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15103#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15329#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15330#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15935#L658-36 assume !(1 == ~t7_pc~0); 15079#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 15080#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16314#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15057#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15058#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16079#L677-36 assume 1 == ~t8_pc~0; 16256#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15851#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15980#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15981#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15877#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15878#L696-36 assume 1 == ~t9_pc~0; 15769#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15770#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15711#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15712#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15895#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15896#L715-36 assume !(1 == ~t10_pc~0); 15857#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14953#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14954#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14931#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14932#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15322#L734-36 assume !(1 == ~t11_pc~0); 15032#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 15033#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15338#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14947#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14948#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15959#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15595#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15596#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15370#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15371#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15550#L1233-3 assume !(1 == ~T5_E~0); 15551#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15820#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15821#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16327#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16329#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15352#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15353#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16302#L1273-3 assume !(1 == ~E_2~0); 16317#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16319#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15698#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15699#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15544#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15545#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16041#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15541#L1313-3 assume !(1 == ~E_10~0); 15542#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15354#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15355#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15297#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15523#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 15524#L1663 assume !(0 == start_simulation_~tmp~3#1); 15190#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15933#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15141#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15024#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 15025#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15087#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15413#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 15879#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 15435#L1644-2 [2024-11-20 22:59:11,310 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,310 INFO L85 PathProgramCache]: Analyzing trace with hash 361408998, now seen corresponding path program 1 times [2024-11-20 22:59:11,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141187833] [2024-11-20 22:59:11,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1141187833] [2024-11-20 22:59:11,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1141187833] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,345 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [632499494] [2024-11-20 22:59:11,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,346 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:11,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,346 INFO L85 PathProgramCache]: Analyzing trace with hash -658480883, now seen corresponding path program 1 times [2024-11-20 22:59:11,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937841203] [2024-11-20 22:59:11,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,446 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,446 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937841203] [2024-11-20 22:59:11,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937841203] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,447 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,447 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989557066] [2024-11-20 22:59:11,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,447 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:11,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:11,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:11,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:11,448 INFO L87 Difference]: Start difference. First operand 1488 states and 2201 transitions. cyclomatic complexity: 714 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:11,468 INFO L93 Difference]: Finished difference Result 1488 states and 2200 transitions. [2024-11-20 22:59:11,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2200 transitions. [2024-11-20 22:59:11,474 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2200 transitions. [2024-11-20 22:59:11,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:11,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:11,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2200 transitions. [2024-11-20 22:59:11,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:11,482 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2024-11-20 22:59:11,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2200 transitions. [2024-11-20 22:59:11,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:11,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.478494623655914) internal successors, (2200), 1487 states have internal predecessors, (2200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2200 transitions. [2024-11-20 22:59:11,500 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2024-11-20 22:59:11,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:11,501 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2024-11-20 22:59:11,501 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-20 22:59:11,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2200 transitions. [2024-11-20 22:59:11,505 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:11,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:11,507 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,507 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,507 INFO L745 eck$LassoCheckResult]: Stem: 18356#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 18357#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 19338#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19339#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18806#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 18807#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18678#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18571#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18300#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17948#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17949#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17993#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17994#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18936#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18937#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18981#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18397#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18398#L1090 assume !(0 == ~M_E~0); 18440#L1090-2 assume !(0 == ~T1_E~0); 18441#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19128#L1100-1 assume !(0 == ~T3_E~0); 19129#L1105-1 assume !(0 == ~T4_E~0); 18220#L1110-1 assume !(0 == ~T5_E~0); 18221#L1115-1 assume !(0 == ~T6_E~0); 18607#L1120-1 assume !(0 == ~T7_E~0); 18915#L1125-1 assume !(0 == ~T8_E~0); 19387#L1130-1 assume !(0 == ~T9_E~0); 19150#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18402#L1140-1 assume !(0 == ~T11_E~0); 18403#L1145-1 assume !(0 == ~E_1~0); 19084#L1150-1 assume !(0 == ~E_2~0); 18584#L1155-1 assume !(0 == ~E_3~0); 18585#L1160-1 assume !(0 == ~E_4~0); 18683#L1165-1 assume !(0 == ~E_5~0); 18684#L1170-1 assume !(0 == ~E_6~0); 19322#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 18764#L1180-1 assume !(0 == ~E_8~0); 18765#L1185-1 assume !(0 == ~E_9~0); 18399#L1190-1 assume !(0 == ~E_10~0); 18400#L1195-1 assume !(0 == ~E_11~0); 18780#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18599#L525 assume !(1 == ~m_pc~0); 18038#L525-2 is_master_triggered_~__retres1~0#1 := 0; 18039#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19224#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19197#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18389#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18390#L544 assume 1 == ~t1_pc~0; 18659#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18606#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18012#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18013#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 18244#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18884#L563 assume !(1 == ~t2_pc~0); 19070#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18057#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18058#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18468#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 18469#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18962#L582 assume 1 == ~t3_pc~0; 18188#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18189#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17940#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17941#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 18126#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18127#L601 assume !(1 == ~t4_pc~0); 19096#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18608#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18136#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18137#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 19091#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19363#L620 assume 1 == ~t5_pc~0; 18085#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18086#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18978#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19229#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 19372#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19373#L639 assume !(1 == ~t6_pc~0); 18913#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18506#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18507#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18557#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 18614#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18615#L658 assume 1 == ~t7_pc~0; 18914#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18830#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19378#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19030#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 18392#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18393#L677 assume 1 == ~t8_pc~0; 18620#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18203#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18204#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18464#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 18465#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19191#L696 assume !(1 == ~t9_pc~0); 18896#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18897#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18669#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18670#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18920#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19133#L715 assume 1 == ~t10_pc~0; 19140#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19012#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18818#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18819#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 18758#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18197#L734 assume !(1 == ~t11_pc~0); 18198#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 18685#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18767#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17936#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 17937#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18979#L1213 assume !(1 == ~M_E~0); 18755#L1213-2 assume !(1 == ~T1_E~0); 18756#L1218-1 assume !(1 == ~T2_E~0); 17971#L1223-1 assume !(1 == ~T3_E~0); 17972#L1228-1 assume !(1 == ~T4_E~0); 18731#L1233-1 assume !(1 == ~T5_E~0); 19374#L1238-1 assume !(1 == ~T6_E~0); 19089#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19090#L1248-1 assume !(1 == ~T8_E~0); 19136#L1253-1 assume !(1 == ~T9_E~0); 19137#L1258-1 assume !(1 == ~T10_E~0); 19112#L1263-1 assume !(1 == ~T11_E~0); 19113#L1268-1 assume !(1 == ~E_1~0); 18933#L1273-1 assume !(1 == ~E_2~0); 18934#L1278-1 assume !(1 == ~E_3~0); 18504#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18505#L1288-1 assume !(1 == ~E_5~0); 19235#L1293-1 assume !(1 == ~E_6~0); 19195#L1298-1 assume !(1 == ~E_7~0); 18966#L1303-1 assume !(1 == ~E_8~0); 18514#L1308-1 assume !(1 == ~E_9~0); 18406#L1313-1 assume !(1 == ~E_10~0); 18407#L1318-1 assume !(1 == ~E_11~0); 18414#L1323-1 assume { :end_inline_reset_delta_events } true; 18415#L1644-2 [2024-11-20 22:59:11,508 INFO L747 eck$LassoCheckResult]: Loop: 18415#L1644-2 assume !false; 19028#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18321#L1065-1 assume !false; 18322#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19370#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18053#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18630#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18519#L906 assume !(0 != eval_~tmp~0#1); 18521#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18841#L1090-3 assume !(0 == ~M_E~0); 19250#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19307#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19272#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19273#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18295#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18296#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18572#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18573#L1125-3 assume !(0 == ~T8_E~0); 19088#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19345#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18494#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18003#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18004#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18128#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18129#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18477#L1165-3 assume !(0 == ~E_5~0); 18478#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18877#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18391#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18152#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18153#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19333#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19334#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18712#L525-36 assume !(1 == ~m_pc~0); 18713#L525-38 is_master_triggered_~__retres1~0#1 := 0; 18253#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18254#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18529#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18530#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18443#L544-36 assume 1 == ~t1_pc~0; 18444#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19000#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19001#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19340#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19320#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19225#L563-36 assume 1 == ~t2_pc~0; 18242#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18001#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18002#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19206#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18728#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18729#L582-36 assume 1 == ~t3_pc~0; 18561#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18562#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18660#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18661#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18766#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18706#L601-36 assume 1 == ~t4_pc~0; 18592#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18593#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18858#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18859#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19311#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19212#L620-36 assume 1 == ~t5_pc~0; 18645#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18646#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19073#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18619#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 18262#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18049#L639-36 assume 1 == ~t6_pc~0; 18050#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18090#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18091#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18312#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18313#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18918#L658-36 assume 1 == ~t7_pc~0; 18162#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18063#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19297#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18040#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18041#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19062#L677-36 assume !(1 == ~t8_pc~0); 18833#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 18834#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18963#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18964#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18860#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18861#L696-36 assume 1 == ~t9_pc~0; 18752#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18753#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18694#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18695#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18878#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18879#L715-36 assume !(1 == ~t10_pc~0); 18842#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 17938#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17939#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17914#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17915#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18305#L734-36 assume !(1 == ~t11_pc~0); 18017#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 18018#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18323#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17930#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17931#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18942#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18580#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18581#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18353#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18354#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18533#L1233-3 assume !(1 == ~T5_E~0); 18534#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18803#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18804#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19310#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19312#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18336#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18337#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19285#L1273-3 assume !(1 == ~E_2~0); 19300#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19302#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18681#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18682#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18527#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18528#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19024#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18524#L1313-3 assume !(1 == ~E_10~0); 18525#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18338#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18339#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18280#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18508#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 18509#L1663 assume !(0 == start_simulation_~tmp~3#1); 18178#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18916#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18124#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18010#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 18011#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18073#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18396#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 18862#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 18415#L1644-2 [2024-11-20 22:59:11,508 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,508 INFO L85 PathProgramCache]: Analyzing trace with hash 946180648, now seen corresponding path program 1 times [2024-11-20 22:59:11,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,509 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765798506] [2024-11-20 22:59:11,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,543 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765798506] [2024-11-20 22:59:11,543 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765798506] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,543 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,543 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [492749648] [2024-11-20 22:59:11,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,544 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:11,544 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,544 INFO L85 PathProgramCache]: Analyzing trace with hash -1386990515, now seen corresponding path program 1 times [2024-11-20 22:59:11,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1724357885] [2024-11-20 22:59:11,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,592 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1724357885] [2024-11-20 22:59:11,592 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1724357885] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,592 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,592 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,592 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1822531259] [2024-11-20 22:59:11,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,593 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:11,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:11,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:11,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:11,593 INFO L87 Difference]: Start difference. First operand 1488 states and 2200 transitions. cyclomatic complexity: 713 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:11,617 INFO L93 Difference]: Finished difference Result 1488 states and 2199 transitions. [2024-11-20 22:59:11,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2199 transitions. [2024-11-20 22:59:11,621 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2199 transitions. [2024-11-20 22:59:11,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:11,627 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:11,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2199 transitions. [2024-11-20 22:59:11,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:11,628 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2024-11-20 22:59:11,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2199 transitions. [2024-11-20 22:59:11,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:11,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4778225806451613) internal successors, (2199), 1487 states have internal predecessors, (2199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2199 transitions. [2024-11-20 22:59:11,646 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2024-11-20 22:59:11,646 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:11,648 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2024-11-20 22:59:11,648 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-20 22:59:11,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2199 transitions. [2024-11-20 22:59:11,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:11,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:11,652 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,652 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,653 INFO L745 eck$LassoCheckResult]: Stem: 21339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 21340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 22321#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22322#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21789#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 21790#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21661#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21554#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21283#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20931#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20932#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20976#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20977#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21919#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21920#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21964#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21380#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21381#L1090 assume !(0 == ~M_E~0); 21423#L1090-2 assume !(0 == ~T1_E~0); 21424#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22112#L1100-1 assume !(0 == ~T3_E~0); 22113#L1105-1 assume !(0 == ~T4_E~0); 21203#L1110-1 assume !(0 == ~T5_E~0); 21204#L1115-1 assume !(0 == ~T6_E~0); 21590#L1120-1 assume !(0 == ~T7_E~0); 21898#L1125-1 assume !(0 == ~T8_E~0); 22370#L1130-1 assume !(0 == ~T9_E~0); 22133#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21385#L1140-1 assume !(0 == ~T11_E~0); 21386#L1145-1 assume !(0 == ~E_1~0); 22067#L1150-1 assume !(0 == ~E_2~0); 21567#L1155-1 assume !(0 == ~E_3~0); 21568#L1160-1 assume !(0 == ~E_4~0); 21666#L1165-1 assume !(0 == ~E_5~0); 21667#L1170-1 assume !(0 == ~E_6~0); 22305#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 21747#L1180-1 assume !(0 == ~E_8~0); 21748#L1185-1 assume !(0 == ~E_9~0); 21382#L1190-1 assume !(0 == ~E_10~0); 21383#L1195-1 assume !(0 == ~E_11~0); 21763#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21587#L525 assume !(1 == ~m_pc~0); 21021#L525-2 is_master_triggered_~__retres1~0#1 := 0; 21022#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22207#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22180#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21372#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21373#L544 assume 1 == ~t1_pc~0; 21642#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21589#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21000#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21001#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 21227#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21867#L563 assume !(1 == ~t2_pc~0); 22053#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21040#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21041#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21451#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 21452#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21945#L582 assume 1 == ~t3_pc~0; 21173#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21174#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20923#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20924#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 21109#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21110#L601 assume !(1 == ~t4_pc~0); 22079#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21591#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21123#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21124#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 22074#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22346#L620 assume 1 == ~t5_pc~0; 21068#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21069#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21961#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22212#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 22355#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22356#L639 assume !(1 == ~t6_pc~0); 21896#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21491#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21492#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21540#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 21597#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21598#L658 assume 1 == ~t7_pc~0; 21897#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21813#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22361#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22013#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 21375#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21376#L677 assume 1 == ~t8_pc~0; 21603#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21186#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21187#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21447#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 21448#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22174#L696 assume !(1 == ~t9_pc~0); 21881#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21882#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21652#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21653#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21903#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22116#L715 assume 1 == ~t10_pc~0; 22123#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21995#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21801#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21802#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 21741#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21180#L734 assume !(1 == ~t11_pc~0); 21181#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21668#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21750#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20921#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 20922#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21962#L1213 assume !(1 == ~M_E~0); 21739#L1213-2 assume !(1 == ~T1_E~0); 21740#L1218-1 assume !(1 == ~T2_E~0); 20954#L1223-1 assume !(1 == ~T3_E~0); 20955#L1228-1 assume !(1 == ~T4_E~0); 21714#L1233-1 assume !(1 == ~T5_E~0); 22357#L1238-1 assume !(1 == ~T6_E~0); 22072#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22073#L1248-1 assume !(1 == ~T8_E~0); 22119#L1253-1 assume !(1 == ~T9_E~0); 22120#L1258-1 assume !(1 == ~T10_E~0); 22095#L1263-1 assume !(1 == ~T11_E~0); 22096#L1268-1 assume !(1 == ~E_1~0); 21916#L1273-1 assume !(1 == ~E_2~0); 21917#L1278-1 assume !(1 == ~E_3~0); 21487#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21488#L1288-1 assume !(1 == ~E_5~0); 22218#L1293-1 assume !(1 == ~E_6~0); 22178#L1298-1 assume !(1 == ~E_7~0); 21949#L1303-1 assume !(1 == ~E_8~0); 21497#L1308-1 assume !(1 == ~E_9~0); 21389#L1313-1 assume !(1 == ~E_10~0); 21390#L1318-1 assume !(1 == ~E_11~0); 21397#L1323-1 assume { :end_inline_reset_delta_events } true; 21398#L1644-2 [2024-11-20 22:59:11,653 INFO L747 eck$LassoCheckResult]: Loop: 21398#L1644-2 assume !false; 22011#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21305#L1065-1 assume !false; 21306#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22353#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21036#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21613#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21502#L906 assume !(0 != eval_~tmp~0#1); 21504#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21824#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21825#L1090-3 assume !(0 == ~M_E~0); 22233#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22290#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22255#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22256#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21278#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21279#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21555#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21556#L1125-3 assume !(0 == ~T8_E~0); 22071#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22328#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21477#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20988#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20989#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21112#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21113#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21460#L1165-3 assume !(0 == ~E_5~0); 21461#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21860#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21374#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21136#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21137#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22316#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22317#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21695#L525-36 assume !(1 == ~m_pc~0); 21696#L525-38 is_master_triggered_~__retres1~0#1 := 0; 21241#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21242#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21512#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21513#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21426#L544-36 assume 1 == ~t1_pc~0; 21427#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21983#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21984#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22323#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22304#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22208#L563-36 assume 1 == ~t2_pc~0; 21225#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20984#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20985#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22189#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21711#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21712#L582-36 assume 1 == ~t3_pc~0; 21544#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21545#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21643#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21644#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21749#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21689#L601-36 assume 1 == ~t4_pc~0; 21575#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21576#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21841#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21842#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22294#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22195#L620-36 assume !(1 == ~t5_pc~0); 21632#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 21631#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22060#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21602#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 21245#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21032#L639-36 assume 1 == ~t6_pc~0; 21033#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21073#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21074#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21293#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21294#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21901#L658-36 assume !(1 == ~t7_pc~0); 21042#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 21043#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22280#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21023#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21024#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22045#L677-36 assume !(1 == ~t8_pc~0); 21815#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 21816#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21946#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21947#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21843#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21844#L696-36 assume 1 == ~t9_pc~0; 21735#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21736#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21677#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21678#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21861#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21862#L715-36 assume 1 == ~t10_pc~0; 22006#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20919#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20920#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20897#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20898#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21288#L734-36 assume !(1 == ~t11_pc~0); 20998#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 20999#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21304#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20913#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20914#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21925#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21561#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21562#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21336#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21337#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21516#L1233-3 assume !(1 == ~T5_E~0); 21517#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21786#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21787#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22293#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22295#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21318#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21319#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22268#L1273-3 assume !(1 == ~E_2~0); 22283#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22285#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21664#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21665#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21509#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21510#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22007#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21507#L1313-3 assume !(1 == ~E_10~0); 21508#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21320#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21321#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21263#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 21490#L1663 assume !(0 == start_simulation_~tmp~3#1); 21154#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21899#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21107#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20990#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 20991#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21053#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21379#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 21845#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 21398#L1644-2 [2024-11-20 22:59:11,653 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,654 INFO L85 PathProgramCache]: Analyzing trace with hash 1380686246, now seen corresponding path program 1 times [2024-11-20 22:59:11,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801530322] [2024-11-20 22:59:11,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,684 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801530322] [2024-11-20 22:59:11,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801530322] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,686 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,686 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1609226862] [2024-11-20 22:59:11,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,686 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:11,687 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,687 INFO L85 PathProgramCache]: Analyzing trace with hash -979985172, now seen corresponding path program 1 times [2024-11-20 22:59:11,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354753518] [2024-11-20 22:59:11,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [354753518] [2024-11-20 22:59:11,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [354753518] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,729 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,729 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [138898229] [2024-11-20 22:59:11,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,730 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:11,730 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:11,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:11,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:11,731 INFO L87 Difference]: Start difference. First operand 1488 states and 2199 transitions. cyclomatic complexity: 712 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:11,750 INFO L93 Difference]: Finished difference Result 1488 states and 2198 transitions. [2024-11-20 22:59:11,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2198 transitions. [2024-11-20 22:59:11,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2198 transitions. [2024-11-20 22:59:11,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:11,761 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:11,761 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2198 transitions. [2024-11-20 22:59:11,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:11,763 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2024-11-20 22:59:11,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2198 transitions. [2024-11-20 22:59:11,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:11,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4771505376344085) internal successors, (2198), 1487 states have internal predecessors, (2198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2198 transitions. [2024-11-20 22:59:11,780 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2024-11-20 22:59:11,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:11,781 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2024-11-20 22:59:11,781 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-20 22:59:11,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2198 transitions. [2024-11-20 22:59:11,784 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,784 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:11,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:11,786 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,786 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,787 INFO L745 eck$LassoCheckResult]: Stem: 24322#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 24323#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 25305#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25306#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24772#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 24773#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24644#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24537#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24266#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23914#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23915#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23959#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23960#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24906#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24907#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24954#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24363#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24364#L1090 assume !(0 == ~M_E~0); 24410#L1090-2 assume !(0 == ~T1_E~0); 24411#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25095#L1100-1 assume !(0 == ~T3_E~0); 25096#L1105-1 assume !(0 == ~T4_E~0); 24187#L1110-1 assume !(0 == ~T5_E~0); 24188#L1115-1 assume !(0 == ~T6_E~0); 24576#L1120-1 assume !(0 == ~T7_E~0); 24881#L1125-1 assume !(0 == ~T8_E~0); 25353#L1130-1 assume !(0 == ~T9_E~0); 25116#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24368#L1140-1 assume !(0 == ~T11_E~0); 24369#L1145-1 assume !(0 == ~E_1~0); 25050#L1150-1 assume !(0 == ~E_2~0); 24550#L1155-1 assume !(0 == ~E_3~0); 24551#L1160-1 assume !(0 == ~E_4~0); 24649#L1165-1 assume !(0 == ~E_5~0); 24650#L1170-1 assume !(0 == ~E_6~0); 25288#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 24730#L1180-1 assume !(0 == ~E_8~0); 24731#L1185-1 assume !(0 == ~E_9~0); 24365#L1190-1 assume !(0 == ~E_10~0); 24366#L1195-1 assume !(0 == ~E_11~0); 24746#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24570#L525 assume !(1 == ~m_pc~0); 24004#L525-2 is_master_triggered_~__retres1~0#1 := 0; 24005#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25190#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25165#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24355#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24356#L544 assume 1 == ~t1_pc~0; 24625#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24572#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23983#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23984#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 24210#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24850#L563 assume !(1 == ~t2_pc~0); 25038#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24023#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24024#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24437#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 24438#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24928#L582 assume 1 == ~t3_pc~0; 24156#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24157#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23906#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23907#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 24092#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24093#L601 assume !(1 == ~t4_pc~0); 25062#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24577#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24106#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24107#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 25057#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25329#L620 assume 1 == ~t5_pc~0; 24055#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24056#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24944#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25196#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 25338#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25339#L639 assume !(1 == ~t6_pc~0); 24879#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24474#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24475#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24523#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 24582#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24583#L658 assume 1 == ~t7_pc~0; 24880#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24797#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25344#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24997#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 24358#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24359#L677 assume 1 == ~t8_pc~0; 24588#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24175#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24176#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24430#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 24431#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25157#L696 assume !(1 == ~t9_pc~0); 24865#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24866#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24635#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24636#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24888#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25100#L715 assume 1 == ~t10_pc~0; 25106#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24978#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24784#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24785#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 24724#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24163#L734 assume !(1 == ~t11_pc~0); 24164#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24652#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24735#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23904#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 23905#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24945#L1213 assume !(1 == ~M_E~0); 24722#L1213-2 assume !(1 == ~T1_E~0); 24723#L1218-1 assume !(1 == ~T2_E~0); 23937#L1223-1 assume !(1 == ~T3_E~0); 23938#L1228-1 assume !(1 == ~T4_E~0); 24697#L1233-1 assume !(1 == ~T5_E~0); 25340#L1238-1 assume !(1 == ~T6_E~0); 25055#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25056#L1248-1 assume !(1 == ~T8_E~0); 25102#L1253-1 assume !(1 == ~T9_E~0); 25103#L1258-1 assume !(1 == ~T10_E~0); 25078#L1263-1 assume !(1 == ~T11_E~0); 25079#L1268-1 assume !(1 == ~E_1~0); 24899#L1273-1 assume !(1 == ~E_2~0); 24900#L1278-1 assume !(1 == ~E_3~0); 24470#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 24471#L1288-1 assume !(1 == ~E_5~0); 25201#L1293-1 assume !(1 == ~E_6~0); 25161#L1298-1 assume !(1 == ~E_7~0); 24932#L1303-1 assume !(1 == ~E_8~0); 24480#L1308-1 assume !(1 == ~E_9~0); 24372#L1313-1 assume !(1 == ~E_10~0); 24373#L1318-1 assume !(1 == ~E_11~0); 24379#L1323-1 assume { :end_inline_reset_delta_events } true; 24380#L1644-2 [2024-11-20 22:59:11,787 INFO L747 eck$LassoCheckResult]: Loop: 24380#L1644-2 assume !false; 24994#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24287#L1065-1 assume !false; 24288#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25336#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24019#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24596#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24485#L906 assume !(0 != eval_~tmp~0#1); 24487#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24806#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24807#L1090-3 assume !(0 == ~M_E~0); 25216#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25273#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25238#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25239#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24261#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24262#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24538#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24539#L1125-3 assume !(0 == ~T8_E~0); 25054#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25311#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24460#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23969#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23970#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24094#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24095#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24443#L1165-3 assume !(0 == ~E_5~0); 24444#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24843#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24357#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24118#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24119#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25299#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25300#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24678#L525-36 assume !(1 == ~m_pc~0); 24679#L525-38 is_master_triggered_~__retres1~0#1 := 0; 24219#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24220#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24495#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24496#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24407#L544-36 assume 1 == ~t1_pc~0; 24408#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24966#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24967#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25304#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25286#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25191#L563-36 assume 1 == ~t2_pc~0; 24208#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23967#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23968#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25172#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24694#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24695#L582-36 assume !(1 == ~t3_pc~0); 24529#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 24528#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24626#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24627#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24732#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24672#L601-36 assume !(1 == ~t4_pc~0); 24560#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 24559#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24824#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24825#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25277#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25178#L620-36 assume 1 == ~t5_pc~0; 24611#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24612#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25039#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24585#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 24228#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24015#L639-36 assume 1 == ~t6_pc~0; 24016#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24053#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24054#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24278#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24279#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24884#L658-36 assume 1 == ~t7_pc~0; 24128#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24029#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25263#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24006#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24007#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25028#L677-36 assume 1 == ~t8_pc~0; 25205#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24800#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24929#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24930#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24826#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24827#L696-36 assume !(1 == ~t9_pc~0); 24720#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 24719#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24660#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24661#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24844#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24845#L715-36 assume !(1 == ~t10_pc~0); 24808#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 23902#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23903#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23880#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23881#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24271#L734-36 assume 1 == ~t11_pc~0; 24272#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23982#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24289#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23896#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23897#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24908#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24546#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24547#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24319#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24320#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24499#L1233-3 assume !(1 == ~T5_E~0); 24500#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24769#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24770#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25276#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25278#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24302#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24303#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25251#L1273-3 assume !(1 == ~E_2~0); 25266#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25268#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24647#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24648#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24493#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24494#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24990#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24490#L1313-3 assume !(1 == ~E_10~0); 24491#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24304#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24305#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24246#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24472#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 24473#L1663 assume !(0 == start_simulation_~tmp~3#1); 24144#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24882#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24090#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23976#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 23977#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24039#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24362#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 24828#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 24380#L1644-2 [2024-11-20 22:59:11,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,787 INFO L85 PathProgramCache]: Analyzing trace with hash 1810344552, now seen corresponding path program 1 times [2024-11-20 22:59:11,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999970829] [2024-11-20 22:59:11,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,822 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [999970829] [2024-11-20 22:59:11,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [999970829] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402399174] [2024-11-20 22:59:11,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,823 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:11,823 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,823 INFO L85 PathProgramCache]: Analyzing trace with hash -2009510740, now seen corresponding path program 1 times [2024-11-20 22:59:11,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,823 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619546111] [2024-11-20 22:59:11,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:11,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:11,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:11,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619546111] [2024-11-20 22:59:11,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619546111] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:11,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:11,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:11,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085067336] [2024-11-20 22:59:11,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:11,905 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:11,905 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:11,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:11,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:11,906 INFO L87 Difference]: Start difference. First operand 1488 states and 2198 transitions. cyclomatic complexity: 711 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:11,931 INFO L93 Difference]: Finished difference Result 1488 states and 2197 transitions. [2024-11-20 22:59:11,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2197 transitions. [2024-11-20 22:59:11,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2197 transitions. [2024-11-20 22:59:11,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:11,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:11,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2197 transitions. [2024-11-20 22:59:11,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:11,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2024-11-20 22:59:11,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2197 transitions. [2024-11-20 22:59:11,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:11,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.476478494623656) internal successors, (2197), 1487 states have internal predecessors, (2197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:11,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2197 transitions. [2024-11-20 22:59:11,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2024-11-20 22:59:11,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:11,970 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2024-11-20 22:59:11,970 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-20 22:59:11,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2197 transitions. [2024-11-20 22:59:11,975 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:11,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:11,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:11,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:11,977 INFO L745 eck$LassoCheckResult]: Stem: 27305#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 27306#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 28287#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28288#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27755#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 27756#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27627#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27520#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27249#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26897#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26898#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26942#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26943#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27885#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27886#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27930#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27346#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27347#L1090 assume !(0 == ~M_E~0); 27389#L1090-2 assume !(0 == ~T1_E~0); 27390#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28077#L1100-1 assume !(0 == ~T3_E~0); 28078#L1105-1 assume !(0 == ~T4_E~0); 27169#L1110-1 assume !(0 == ~T5_E~0); 27170#L1115-1 assume !(0 == ~T6_E~0); 27556#L1120-1 assume !(0 == ~T7_E~0); 27864#L1125-1 assume !(0 == ~T8_E~0); 28336#L1130-1 assume !(0 == ~T9_E~0); 28099#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27351#L1140-1 assume !(0 == ~T11_E~0); 27352#L1145-1 assume !(0 == ~E_1~0); 28033#L1150-1 assume !(0 == ~E_2~0); 27533#L1155-1 assume !(0 == ~E_3~0); 27534#L1160-1 assume !(0 == ~E_4~0); 27632#L1165-1 assume !(0 == ~E_5~0); 27633#L1170-1 assume !(0 == ~E_6~0); 28271#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 27713#L1180-1 assume !(0 == ~E_8~0); 27714#L1185-1 assume !(0 == ~E_9~0); 27348#L1190-1 assume !(0 == ~E_10~0); 27349#L1195-1 assume !(0 == ~E_11~0); 27729#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27548#L525 assume !(1 == ~m_pc~0); 26987#L525-2 is_master_triggered_~__retres1~0#1 := 0; 26988#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28173#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28146#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27338#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27339#L544 assume 1 == ~t1_pc~0; 27608#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27555#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26963#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26964#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 27193#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27833#L563 assume !(1 == ~t2_pc~0); 28019#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27006#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27007#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27417#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 27418#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27911#L582 assume 1 == ~t3_pc~0; 27137#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27138#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26889#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26890#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 27075#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27076#L601 assume !(1 == ~t4_pc~0); 28045#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27557#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27089#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27090#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 28040#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28312#L620 assume 1 == ~t5_pc~0; 27034#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27035#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27927#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28178#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 28321#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28322#L639 assume !(1 == ~t6_pc~0); 27862#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27457#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27458#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27506#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 27563#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27564#L658 assume 1 == ~t7_pc~0; 27863#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27779#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28327#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27979#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 27341#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27342#L677 assume 1 == ~t8_pc~0; 27569#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27152#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27153#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27413#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 27414#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28140#L696 assume !(1 == ~t9_pc~0); 27845#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27846#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27618#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27619#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27869#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28082#L715 assume 1 == ~t10_pc~0; 28089#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27961#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27767#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27768#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 27707#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27146#L734 assume !(1 == ~t11_pc~0); 27147#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27634#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27716#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26887#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 26888#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27928#L1213 assume !(1 == ~M_E~0); 27704#L1213-2 assume !(1 == ~T1_E~0); 27705#L1218-1 assume !(1 == ~T2_E~0); 26920#L1223-1 assume !(1 == ~T3_E~0); 26921#L1228-1 assume !(1 == ~T4_E~0); 27680#L1233-1 assume !(1 == ~T5_E~0); 28323#L1238-1 assume !(1 == ~T6_E~0); 28038#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28039#L1248-1 assume !(1 == ~T8_E~0); 28085#L1253-1 assume !(1 == ~T9_E~0); 28086#L1258-1 assume !(1 == ~T10_E~0); 28061#L1263-1 assume !(1 == ~T11_E~0); 28062#L1268-1 assume !(1 == ~E_1~0); 27882#L1273-1 assume !(1 == ~E_2~0); 27883#L1278-1 assume !(1 == ~E_3~0); 27453#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27454#L1288-1 assume !(1 == ~E_5~0); 28184#L1293-1 assume !(1 == ~E_6~0); 28144#L1298-1 assume !(1 == ~E_7~0); 27915#L1303-1 assume !(1 == ~E_8~0); 27463#L1308-1 assume !(1 == ~E_9~0); 27355#L1313-1 assume !(1 == ~E_10~0); 27356#L1318-1 assume !(1 == ~E_11~0); 27363#L1323-1 assume { :end_inline_reset_delta_events } true; 27364#L1644-2 [2024-11-20 22:59:11,977 INFO L747 eck$LassoCheckResult]: Loop: 27364#L1644-2 assume !false; 27977#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27271#L1065-1 assume !false; 27272#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28319#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27002#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27579#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27468#L906 assume !(0 != eval_~tmp~0#1); 27470#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27790#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27791#L1090-3 assume !(0 == ~M_E~0); 28199#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28256#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28221#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28222#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27244#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27245#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27521#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27522#L1125-3 assume !(0 == ~T8_E~0); 28037#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28294#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27443#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26952#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26953#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27078#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27079#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27426#L1165-3 assume !(0 == ~E_5~0); 27427#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27826#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27340#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27101#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27102#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28282#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28283#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27661#L525-36 assume !(1 == ~m_pc~0); 27662#L525-38 is_master_triggered_~__retres1~0#1 := 0; 27202#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27203#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27478#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27479#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27392#L544-36 assume 1 == ~t1_pc~0; 27393#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27949#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27950#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28289#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28270#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28174#L563-36 assume 1 == ~t2_pc~0; 27191#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26950#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26951#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28155#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27677#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27678#L582-36 assume 1 == ~t3_pc~0; 27510#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27511#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27609#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27610#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27715#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27655#L601-36 assume 1 == ~t4_pc~0; 27541#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27542#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27807#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27808#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28260#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28161#L620-36 assume 1 == ~t5_pc~0; 27596#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27597#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28024#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27568#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 27211#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26998#L639-36 assume 1 == ~t6_pc~0; 26999#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27039#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27040#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27261#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27262#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27867#L658-36 assume !(1 == ~t7_pc~0); 27011#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 27012#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28246#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26989#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26990#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28011#L677-36 assume !(1 == ~t8_pc~0); 27782#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 27783#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27912#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27913#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27809#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27810#L696-36 assume 1 == ~t9_pc~0; 27701#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27702#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27640#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27641#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27827#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27828#L715-36 assume 1 == ~t10_pc~0; 27972#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26885#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26886#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26863#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26864#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27251#L734-36 assume !(1 == ~t11_pc~0); 26961#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 26962#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27270#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26879#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26880#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27891#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27527#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27528#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27302#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27303#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27482#L1233-3 assume !(1 == ~T5_E~0); 27483#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27752#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27753#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28259#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28261#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 27284#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27285#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28234#L1273-3 assume !(1 == ~E_2~0); 28249#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28250#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27630#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27631#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27475#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27476#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27973#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27473#L1313-3 assume !(1 == ~E_10~0); 27474#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 27286#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27287#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27229#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27455#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 27456#L1663 assume !(0 == start_simulation_~tmp~3#1); 27120#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27865#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27073#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26956#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 26957#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27019#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27345#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 27811#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 27364#L1644-2 [2024-11-20 22:59:11,978 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:11,978 INFO L85 PathProgramCache]: Analyzing trace with hash -1778026138, now seen corresponding path program 1 times [2024-11-20 22:59:11,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:11,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896913029] [2024-11-20 22:59:11,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:11,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:11,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,016 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896913029] [2024-11-20 22:59:12,017 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [896913029] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,017 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,017 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:12,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284791592] [2024-11-20 22:59:12,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,017 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:12,018 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:12,018 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 3 times [2024-11-20 22:59:12,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:12,018 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435344822] [2024-11-20 22:59:12,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:12,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:12,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435344822] [2024-11-20 22:59:12,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435344822] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,068 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,068 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:12,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503344558] [2024-11-20 22:59:12,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,068 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:12,068 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:12,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:12,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:12,069 INFO L87 Difference]: Start difference. First operand 1488 states and 2197 transitions. cyclomatic complexity: 710 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:12,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:12,093 INFO L93 Difference]: Finished difference Result 1488 states and 2196 transitions. [2024-11-20 22:59:12,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2196 transitions. [2024-11-20 22:59:12,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:12,102 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2196 transitions. [2024-11-20 22:59:12,103 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:12,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:12,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2196 transitions. [2024-11-20 22:59:12,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:12,105 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2024-11-20 22:59:12,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2196 transitions. [2024-11-20 22:59:12,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:12,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4758064516129032) internal successors, (2196), 1487 states have internal predecessors, (2196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:12,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2196 transitions. [2024-11-20 22:59:12,123 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2024-11-20 22:59:12,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:12,125 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2024-11-20 22:59:12,125 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-20 22:59:12,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2196 transitions. [2024-11-20 22:59:12,128 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:12,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:12,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:12,130 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:12,130 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:12,130 INFO L745 eck$LassoCheckResult]: Stem: 30288#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 30289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 31271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31272#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30738#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 30739#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30610#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30503#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30232#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29880#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29881#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29925#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29926#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30872#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30873#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 30920#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30329#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30330#L1090 assume !(0 == ~M_E~0); 30376#L1090-2 assume !(0 == ~T1_E~0); 30377#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31061#L1100-1 assume !(0 == ~T3_E~0); 31062#L1105-1 assume !(0 == ~T4_E~0); 30153#L1110-1 assume !(0 == ~T5_E~0); 30154#L1115-1 assume !(0 == ~T6_E~0); 30542#L1120-1 assume !(0 == ~T7_E~0); 30847#L1125-1 assume !(0 == ~T8_E~0); 31319#L1130-1 assume !(0 == ~T9_E~0); 31082#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30334#L1140-1 assume !(0 == ~T11_E~0); 30335#L1145-1 assume !(0 == ~E_1~0); 31016#L1150-1 assume !(0 == ~E_2~0); 30516#L1155-1 assume !(0 == ~E_3~0); 30517#L1160-1 assume !(0 == ~E_4~0); 30615#L1165-1 assume !(0 == ~E_5~0); 30616#L1170-1 assume !(0 == ~E_6~0); 31254#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 30696#L1180-1 assume !(0 == ~E_8~0); 30697#L1185-1 assume !(0 == ~E_9~0); 30331#L1190-1 assume !(0 == ~E_10~0); 30332#L1195-1 assume !(0 == ~E_11~0); 30712#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30536#L525 assume !(1 == ~m_pc~0); 29970#L525-2 is_master_triggered_~__retres1~0#1 := 0; 29971#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31156#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31131#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30321#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30322#L544 assume 1 == ~t1_pc~0; 30591#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30538#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29949#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29950#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 30176#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30816#L563 assume !(1 == ~t2_pc~0); 31004#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29989#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29990#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30403#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 30404#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30894#L582 assume 1 == ~t3_pc~0; 30122#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30123#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29872#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29873#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 30058#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30059#L601 assume !(1 == ~t4_pc~0); 31028#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30543#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30072#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30073#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 31023#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31295#L620 assume 1 == ~t5_pc~0; 30021#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30022#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30910#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31162#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 31304#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31305#L639 assume !(1 == ~t6_pc~0); 30845#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30440#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30441#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30489#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 30548#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30549#L658 assume 1 == ~t7_pc~0; 30846#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30763#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31310#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30963#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 30324#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30325#L677 assume 1 == ~t8_pc~0; 30554#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30138#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30139#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30396#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 30397#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31123#L696 assume !(1 == ~t9_pc~0); 30831#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 30832#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30601#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30602#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30854#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31066#L715 assume 1 == ~t10_pc~0; 31072#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30944#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30750#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30751#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 30690#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30129#L734 assume !(1 == ~t11_pc~0); 30130#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 30617#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30701#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29870#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 29871#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30911#L1213 assume !(1 == ~M_E~0); 30688#L1213-2 assume !(1 == ~T1_E~0); 30689#L1218-1 assume !(1 == ~T2_E~0); 29903#L1223-1 assume !(1 == ~T3_E~0); 29904#L1228-1 assume !(1 == ~T4_E~0); 30663#L1233-1 assume !(1 == ~T5_E~0); 31306#L1238-1 assume !(1 == ~T6_E~0); 31021#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31022#L1248-1 assume !(1 == ~T8_E~0); 31068#L1253-1 assume !(1 == ~T9_E~0); 31069#L1258-1 assume !(1 == ~T10_E~0); 31044#L1263-1 assume !(1 == ~T11_E~0); 31045#L1268-1 assume !(1 == ~E_1~0); 30865#L1273-1 assume !(1 == ~E_2~0); 30866#L1278-1 assume !(1 == ~E_3~0); 30436#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30437#L1288-1 assume !(1 == ~E_5~0); 31167#L1293-1 assume !(1 == ~E_6~0); 31127#L1298-1 assume !(1 == ~E_7~0); 30898#L1303-1 assume !(1 == ~E_8~0); 30446#L1308-1 assume !(1 == ~E_9~0); 30338#L1313-1 assume !(1 == ~E_10~0); 30339#L1318-1 assume !(1 == ~E_11~0); 30349#L1323-1 assume { :end_inline_reset_delta_events } true; 30350#L1644-2 [2024-11-20 22:59:12,130 INFO L747 eck$LassoCheckResult]: Loop: 30350#L1644-2 assume !false; 30960#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30254#L1065-1 assume !false; 30255#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31302#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29985#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30562#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30451#L906 assume !(0 != eval_~tmp~0#1); 30453#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30773#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30774#L1090-3 assume !(0 == ~M_E~0); 31182#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31239#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31204#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31205#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30227#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30228#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30504#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30505#L1125-3 assume !(0 == ~T8_E~0); 31020#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31277#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30426#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29935#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29936#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30060#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30061#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30409#L1165-3 assume !(0 == ~E_5~0); 30410#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30809#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30323#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30084#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30085#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31265#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31266#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30641#L525-36 assume !(1 == ~m_pc~0); 30642#L525-38 is_master_triggered_~__retres1~0#1 := 0; 30185#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30186#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30461#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30462#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30373#L544-36 assume 1 == ~t1_pc~0; 30374#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30932#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30933#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31270#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31252#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31157#L563-36 assume 1 == ~t2_pc~0; 30174#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29933#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29934#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31138#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30660#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30661#L582-36 assume 1 == ~t3_pc~0; 30493#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30494#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30592#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30593#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30698#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30638#L601-36 assume 1 == ~t4_pc~0; 30524#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30525#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30790#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30791#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31243#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31144#L620-36 assume 1 == ~t5_pc~0; 30577#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30578#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31005#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30551#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 30194#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29981#L639-36 assume 1 == ~t6_pc~0; 29982#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30019#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30020#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30244#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30245#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30850#L658-36 assume !(1 == ~t7_pc~0); 29994#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 29995#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31229#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29972#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29973#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30994#L677-36 assume 1 == ~t8_pc~0; 31171#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30766#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30895#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30896#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30792#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30793#L696-36 assume 1 == ~t9_pc~0; 30684#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30685#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30626#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30627#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30810#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30811#L715-36 assume !(1 == ~t10_pc~0); 30772#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 29868#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29869#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29846#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29847#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30237#L734-36 assume !(1 == ~t11_pc~0); 29947#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 29948#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30253#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29862#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29863#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30874#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30510#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30511#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30285#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30286#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30465#L1233-3 assume !(1 == ~T5_E~0); 30466#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30735#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30736#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31242#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31244#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30267#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30268#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31217#L1273-3 assume !(1 == ~E_2~0); 31232#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31234#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30613#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30614#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30459#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30460#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30956#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30456#L1313-3 assume !(1 == ~E_10~0); 30457#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30269#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30270#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 30212#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30438#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30439#L1663 assume !(0 == start_simulation_~tmp~3#1); 30110#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30848#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 30056#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29939#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 29940#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30005#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30328#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 30794#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 30350#L1644-2 [2024-11-20 22:59:12,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:12,131 INFO L85 PathProgramCache]: Analyzing trace with hash 1655107556, now seen corresponding path program 1 times [2024-11-20 22:59:12,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:12,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897141941] [2024-11-20 22:59:12,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:12,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:12,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [897141941] [2024-11-20 22:59:12,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [897141941] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,158 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,158 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:12,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220793075] [2024-11-20 22:59:12,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,158 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:12,158 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:12,159 INFO L85 PathProgramCache]: Analyzing trace with hash -658480883, now seen corresponding path program 2 times [2024-11-20 22:59:12,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:12,159 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564573154] [2024-11-20 22:59:12,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:12,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:12,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,194 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [564573154] [2024-11-20 22:59:12,195 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [564573154] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,195 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,195 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:12,195 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382890809] [2024-11-20 22:59:12,195 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,195 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:12,195 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:12,196 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:12,196 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:12,196 INFO L87 Difference]: Start difference. First operand 1488 states and 2196 transitions. cyclomatic complexity: 709 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:12,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:12,220 INFO L93 Difference]: Finished difference Result 1488 states and 2195 transitions. [2024-11-20 22:59:12,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2195 transitions. [2024-11-20 22:59:12,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:12,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2195 transitions. [2024-11-20 22:59:12,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:12,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:12,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2195 transitions. [2024-11-20 22:59:12,232 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:12,232 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2024-11-20 22:59:12,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2195 transitions. [2024-11-20 22:59:12,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:12,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4751344086021505) internal successors, (2195), 1487 states have internal predecessors, (2195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:12,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2195 transitions. [2024-11-20 22:59:12,249 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2024-11-20 22:59:12,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:12,250 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2024-11-20 22:59:12,250 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-20 22:59:12,250 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2195 transitions. [2024-11-20 22:59:12,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:12,254 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:12,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:12,255 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:12,255 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:12,255 INFO L745 eck$LassoCheckResult]: Stem: 33271#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 33272#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 34253#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34254#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33721#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 33722#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33593#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33486#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33215#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32863#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32864#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32908#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32909#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33851#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33852#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33896#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 33312#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33313#L1090 assume !(0 == ~M_E~0); 33355#L1090-2 assume !(0 == ~T1_E~0); 33356#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34043#L1100-1 assume !(0 == ~T3_E~0); 34044#L1105-1 assume !(0 == ~T4_E~0); 33135#L1110-1 assume !(0 == ~T5_E~0); 33136#L1115-1 assume !(0 == ~T6_E~0); 33522#L1120-1 assume !(0 == ~T7_E~0); 33830#L1125-1 assume !(0 == ~T8_E~0); 34302#L1130-1 assume !(0 == ~T9_E~0); 34065#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33317#L1140-1 assume !(0 == ~T11_E~0); 33318#L1145-1 assume !(0 == ~E_1~0); 33999#L1150-1 assume !(0 == ~E_2~0); 33499#L1155-1 assume !(0 == ~E_3~0); 33500#L1160-1 assume !(0 == ~E_4~0); 33598#L1165-1 assume !(0 == ~E_5~0); 33599#L1170-1 assume !(0 == ~E_6~0); 34237#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 33679#L1180-1 assume !(0 == ~E_8~0); 33680#L1185-1 assume !(0 == ~E_9~0); 33314#L1190-1 assume !(0 == ~E_10~0); 33315#L1195-1 assume !(0 == ~E_11~0); 33695#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33514#L525 assume !(1 == ~m_pc~0); 32953#L525-2 is_master_triggered_~__retres1~0#1 := 0; 32954#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34139#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34112#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33304#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33305#L544 assume 1 == ~t1_pc~0; 33574#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33521#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32927#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32928#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 33159#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33799#L563 assume !(1 == ~t2_pc~0); 33985#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32972#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32973#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33383#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 33384#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33877#L582 assume 1 == ~t3_pc~0; 33103#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33104#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32855#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32856#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 33041#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33042#L601 assume !(1 == ~t4_pc~0); 34011#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33523#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33053#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33054#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 34006#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34278#L620 assume 1 == ~t5_pc~0; 33000#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33001#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33893#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34144#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 34287#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34288#L639 assume !(1 == ~t6_pc~0); 33828#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33421#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33422#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33472#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 33529#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33530#L658 assume 1 == ~t7_pc~0; 33829#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33745#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34293#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33945#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 33307#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33308#L677 assume 1 == ~t8_pc~0; 33535#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33118#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33119#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33379#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 33380#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34106#L696 assume !(1 == ~t9_pc~0); 33811#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 33812#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33584#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33585#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33835#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34048#L715 assume 1 == ~t10_pc~0; 34055#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33927#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33733#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33734#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 33673#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33112#L734 assume !(1 == ~t11_pc~0); 33113#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 33600#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33682#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32851#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 32852#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33894#L1213 assume !(1 == ~M_E~0); 33670#L1213-2 assume !(1 == ~T1_E~0); 33671#L1218-1 assume !(1 == ~T2_E~0); 32886#L1223-1 assume !(1 == ~T3_E~0); 32887#L1228-1 assume !(1 == ~T4_E~0); 33646#L1233-1 assume !(1 == ~T5_E~0); 34289#L1238-1 assume !(1 == ~T6_E~0); 34004#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34005#L1248-1 assume !(1 == ~T8_E~0); 34051#L1253-1 assume !(1 == ~T9_E~0); 34052#L1258-1 assume !(1 == ~T10_E~0); 34027#L1263-1 assume !(1 == ~T11_E~0); 34028#L1268-1 assume !(1 == ~E_1~0); 33848#L1273-1 assume !(1 == ~E_2~0); 33849#L1278-1 assume !(1 == ~E_3~0); 33419#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33420#L1288-1 assume !(1 == ~E_5~0); 34150#L1293-1 assume !(1 == ~E_6~0); 34110#L1298-1 assume !(1 == ~E_7~0); 33881#L1303-1 assume !(1 == ~E_8~0); 33429#L1308-1 assume !(1 == ~E_9~0); 33321#L1313-1 assume !(1 == ~E_10~0); 33322#L1318-1 assume !(1 == ~E_11~0); 33329#L1323-1 assume { :end_inline_reset_delta_events } true; 33330#L1644-2 [2024-11-20 22:59:12,256 INFO L747 eck$LassoCheckResult]: Loop: 33330#L1644-2 assume !false; 33943#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33236#L1065-1 assume !false; 33237#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34285#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32968#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33545#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33434#L906 assume !(0 != eval_~tmp~0#1); 33436#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33755#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33756#L1090-3 assume !(0 == ~M_E~0); 34165#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34222#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34187#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34188#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33210#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33211#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33487#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33488#L1125-3 assume !(0 == ~T8_E~0); 34003#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34260#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33409#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32918#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32919#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33043#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33044#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33392#L1165-3 assume !(0 == ~E_5~0); 33393#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33792#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33306#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33067#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33068#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34248#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34249#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33627#L525-36 assume !(1 == ~m_pc~0); 33628#L525-38 is_master_triggered_~__retres1~0#1 := 0; 33168#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33169#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33444#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33445#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33358#L544-36 assume !(1 == ~t1_pc~0); 33360#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 33915#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33916#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34255#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34235#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34140#L563-36 assume 1 == ~t2_pc~0; 33157#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32916#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32917#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34121#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33643#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33644#L582-36 assume 1 == ~t3_pc~0; 33476#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33477#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33575#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33576#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33681#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33621#L601-36 assume 1 == ~t4_pc~0; 33507#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33508#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33773#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33774#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34226#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34127#L620-36 assume 1 == ~t5_pc~0; 33560#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33561#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33988#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33534#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 33177#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32964#L639-36 assume 1 == ~t6_pc~0; 32965#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33005#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33006#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33227#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33228#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33833#L658-36 assume !(1 == ~t7_pc~0); 32977#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 32978#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34212#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32955#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32956#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33977#L677-36 assume !(1 == ~t8_pc~0); 33748#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 33749#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33878#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33879#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33775#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33776#L696-36 assume 1 == ~t9_pc~0; 33667#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33668#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33609#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33610#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33793#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33794#L715-36 assume 1 == ~t10_pc~0; 33938#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32853#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32854#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32829#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32830#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33220#L734-36 assume !(1 == ~t11_pc~0); 32932#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 32933#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33238#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32845#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32846#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33857#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33495#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33496#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33268#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33269#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33448#L1233-3 assume !(1 == ~T5_E~0); 33449#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33718#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33719#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34225#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34227#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33251#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33252#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34200#L1273-3 assume !(1 == ~E_2~0); 34215#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34217#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33596#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33597#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33442#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33443#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33939#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33439#L1313-3 assume !(1 == ~E_10~0); 33440#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33253#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33254#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 33195#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33423#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 33424#L1663 assume !(0 == start_simulation_~tmp~3#1); 33086#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33831#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 33039#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32925#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 32926#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32988#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33311#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 33777#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 33330#L1644-2 [2024-11-20 22:59:12,256 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:12,256 INFO L85 PathProgramCache]: Analyzing trace with hash -589450842, now seen corresponding path program 1 times [2024-11-20 22:59:12,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:12,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698731984] [2024-11-20 22:59:12,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:12,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:12,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698731984] [2024-11-20 22:59:12,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [698731984] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,304 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,304 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-20 22:59:12,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763953809] [2024-11-20 22:59:12,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,305 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:12,305 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:12,305 INFO L85 PathProgramCache]: Analyzing trace with hash -1567805460, now seen corresponding path program 1 times [2024-11-20 22:59:12,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:12,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384992759] [2024-11-20 22:59:12,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:12,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:12,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,341 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [384992759] [2024-11-20 22:59:12,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [384992759] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,341 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,341 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:12,341 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1365261246] [2024-11-20 22:59:12,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,342 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:12,342 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:12,342 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:12,342 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:12,343 INFO L87 Difference]: Start difference. First operand 1488 states and 2195 transitions. cyclomatic complexity: 708 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:12,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:12,391 INFO L93 Difference]: Finished difference Result 1488 states and 2190 transitions. [2024-11-20 22:59:12,391 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2190 transitions. [2024-11-20 22:59:12,395 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:12,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2190 transitions. [2024-11-20 22:59:12,399 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:12,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:12,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2190 transitions. [2024-11-20 22:59:12,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:12,401 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2024-11-20 22:59:12,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2190 transitions. [2024-11-20 22:59:12,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:12,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.471774193548387) internal successors, (2190), 1487 states have internal predecessors, (2190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:12,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2190 transitions. [2024-11-20 22:59:12,417 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2024-11-20 22:59:12,418 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:12,418 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2024-11-20 22:59:12,418 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-20 22:59:12,418 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2190 transitions. [2024-11-20 22:59:12,421 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:12,422 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:12,422 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:12,423 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:12,423 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:12,423 INFO L745 eck$LassoCheckResult]: Stem: 36254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 36255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 37237#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37238#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36704#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 36705#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36576#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36469#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36198#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35846#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35847#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35891#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35892#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36836#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36837#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36882#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36295#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36296#L1090 assume !(0 == ~M_E~0); 36341#L1090-2 assume !(0 == ~T1_E~0); 36342#L1095-1 assume !(0 == ~T2_E~0); 37027#L1100-1 assume !(0 == ~T3_E~0); 37028#L1105-1 assume !(0 == ~T4_E~0); 36119#L1110-1 assume !(0 == ~T5_E~0); 36120#L1115-1 assume !(0 == ~T6_E~0); 36505#L1120-1 assume !(0 == ~T7_E~0); 36813#L1125-1 assume !(0 == ~T8_E~0); 37285#L1130-1 assume !(0 == ~T9_E~0); 37048#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36300#L1140-1 assume !(0 == ~T11_E~0); 36301#L1145-1 assume !(0 == ~E_1~0); 36982#L1150-1 assume !(0 == ~E_2~0); 36482#L1155-1 assume !(0 == ~E_3~0); 36483#L1160-1 assume !(0 == ~E_4~0); 36581#L1165-1 assume !(0 == ~E_5~0); 36582#L1170-1 assume !(0 == ~E_6~0); 37220#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 36662#L1180-1 assume !(0 == ~E_8~0); 36663#L1185-1 assume !(0 == ~E_9~0); 36297#L1190-1 assume !(0 == ~E_10~0); 36298#L1195-1 assume !(0 == ~E_11~0); 36678#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36502#L525 assume !(1 == ~m_pc~0); 35936#L525-2 is_master_triggered_~__retres1~0#1 := 0; 35937#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37122#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37097#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36287#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36288#L544 assume 1 == ~t1_pc~0; 36557#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36504#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35915#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35916#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 36142#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36782#L563 assume !(1 == ~t2_pc~0); 36968#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35955#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36369#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 36370#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36860#L582 assume 1 == ~t3_pc~0; 36088#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36089#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35838#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35839#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 36024#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36025#L601 assume !(1 == ~t4_pc~0); 36994#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36506#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36038#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36039#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 36989#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37261#L620 assume 1 == ~t5_pc~0; 35987#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35988#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36876#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37128#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 37270#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37271#L639 assume !(1 == ~t6_pc~0); 36811#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36406#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36407#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36455#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 36512#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36513#L658 assume 1 == ~t7_pc~0; 36812#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36729#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37276#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36929#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 36290#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36291#L677 assume 1 == ~t8_pc~0; 36520#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36101#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36102#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36362#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 36363#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37089#L696 assume !(1 == ~t9_pc~0); 36796#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 36797#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36567#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36568#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36820#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37031#L715 assume 1 == ~t10_pc~0; 37038#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36910#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36716#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36717#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 36656#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36095#L734 assume !(1 == ~t11_pc~0); 36096#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 36583#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36667#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35836#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 35837#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36877#L1213 assume !(1 == ~M_E~0); 36654#L1213-2 assume !(1 == ~T1_E~0); 36655#L1218-1 assume !(1 == ~T2_E~0); 35869#L1223-1 assume !(1 == ~T3_E~0); 35870#L1228-1 assume !(1 == ~T4_E~0); 36629#L1233-1 assume !(1 == ~T5_E~0); 37272#L1238-1 assume !(1 == ~T6_E~0); 36987#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36988#L1248-1 assume !(1 == ~T8_E~0); 37034#L1253-1 assume !(1 == ~T9_E~0); 37035#L1258-1 assume !(1 == ~T10_E~0); 37010#L1263-1 assume !(1 == ~T11_E~0); 37011#L1268-1 assume !(1 == ~E_1~0); 36831#L1273-1 assume !(1 == ~E_2~0); 36832#L1278-1 assume !(1 == ~E_3~0); 36402#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 36403#L1288-1 assume !(1 == ~E_5~0); 37133#L1293-1 assume !(1 == ~E_6~0); 37093#L1298-1 assume !(1 == ~E_7~0); 36864#L1303-1 assume !(1 == ~E_8~0); 36412#L1308-1 assume !(1 == ~E_9~0); 36304#L1313-1 assume !(1 == ~E_10~0); 36305#L1318-1 assume !(1 == ~E_11~0); 36315#L1323-1 assume { :end_inline_reset_delta_events } true; 36316#L1644-2 [2024-11-20 22:59:12,424 INFO L747 eck$LassoCheckResult]: Loop: 36316#L1644-2 assume !false; 36926#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36220#L1065-1 assume !false; 36221#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 37268#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35951#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36528#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36417#L906 assume !(0 != eval_~tmp~0#1); 36419#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36739#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36740#L1090-3 assume !(0 == ~M_E~0); 37148#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37205#L1095-3 assume !(0 == ~T2_E~0); 37170#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37171#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36193#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36194#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36470#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36471#L1125-3 assume !(0 == ~T8_E~0); 36986#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37243#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36394#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35903#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35904#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36027#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36028#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36375#L1165-3 assume !(0 == ~E_5~0); 36376#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36775#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36289#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36053#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36054#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37231#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 37232#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36605#L525-36 assume !(1 == ~m_pc~0); 36606#L525-38 is_master_triggered_~__retres1~0#1 := 0; 36151#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36152#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36427#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36428#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36338#L544-36 assume 1 == ~t1_pc~0; 36339#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36898#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36899#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37236#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37218#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37123#L563-36 assume 1 == ~t2_pc~0; 36140#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35899#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35900#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37104#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36626#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36627#L582-36 assume 1 == ~t3_pc~0; 36459#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36460#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36558#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36559#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36664#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36604#L601-36 assume 1 == ~t4_pc~0; 36490#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36491#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36756#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36757#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37209#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37110#L620-36 assume 1 == ~t5_pc~0; 36541#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36542#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36971#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36517#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 36160#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35947#L639-36 assume 1 == ~t6_pc~0; 35948#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35985#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35986#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36210#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36211#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36816#L658-36 assume !(1 == ~t7_pc~0); 35960#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 35961#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37195#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35938#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35939#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36960#L677-36 assume 1 == ~t8_pc~0; 37137#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36732#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36861#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36862#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36758#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36759#L696-36 assume 1 == ~t9_pc~0; 36650#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36651#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36592#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36593#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36776#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36777#L715-36 assume !(1 == ~t10_pc~0); 36738#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 35834#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35835#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35812#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35813#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36203#L734-36 assume !(1 == ~t11_pc~0); 35913#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 35914#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36219#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35828#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35829#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36840#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36476#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36477#L1218-3 assume !(1 == ~T2_E~0); 36251#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36252#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36431#L1233-3 assume !(1 == ~T5_E~0); 36432#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36701#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36702#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37208#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37210#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36233#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36234#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37183#L1273-3 assume !(1 == ~E_2~0); 37198#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37200#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36579#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36580#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36425#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36426#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36922#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36422#L1313-3 assume !(1 == ~E_10~0); 36423#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36235#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36236#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 36178#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 36405#L1663 assume !(0 == start_simulation_~tmp~3#1); 36076#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36814#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 36022#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35905#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 35906#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35971#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36294#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 36760#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 36316#L1644-2 [2024-11-20 22:59:12,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:12,424 INFO L85 PathProgramCache]: Analyzing trace with hash 1863040740, now seen corresponding path program 1 times [2024-11-20 22:59:12,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:12,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691076638] [2024-11-20 22:59:12,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:12,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:12,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [691076638] [2024-11-20 22:59:12,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [691076638] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,471 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:12,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777814376] [2024-11-20 22:59:12,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,471 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:12,472 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:12,472 INFO L85 PathProgramCache]: Analyzing trace with hash 2067663241, now seen corresponding path program 1 times [2024-11-20 22:59:12,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:12,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044970122] [2024-11-20 22:59:12,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:12,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:12,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,521 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,521 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2044970122] [2024-11-20 22:59:12,521 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2044970122] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,521 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,521 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:12,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1618012307] [2024-11-20 22:59:12,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,521 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:12,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:12,521 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-20 22:59:12,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-20 22:59:12,522 INFO L87 Difference]: Start difference. First operand 1488 states and 2190 transitions. cyclomatic complexity: 703 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:12,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:12,609 INFO L93 Difference]: Finished difference Result 2840 states and 4171 transitions. [2024-11-20 22:59:12,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2840 states and 4171 transitions. [2024-11-20 22:59:12,618 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2678 [2024-11-20 22:59:12,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2840 states to 2840 states and 4171 transitions. [2024-11-20 22:59:12,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2840 [2024-11-20 22:59:12,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2840 [2024-11-20 22:59:12,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2840 states and 4171 transitions. [2024-11-20 22:59:12,638 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:12,638 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2840 states and 4171 transitions. [2024-11-20 22:59:12,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2840 states and 4171 transitions. [2024-11-20 22:59:12,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2840 to 1488. [2024-11-20 22:59:12,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4704301075268817) internal successors, (2188), 1487 states have internal predecessors, (2188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:12,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2188 transitions. [2024-11-20 22:59:12,662 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2188 transitions. [2024-11-20 22:59:12,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-20 22:59:12,663 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2188 transitions. [2024-11-20 22:59:12,663 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-20 22:59:12,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2188 transitions. [2024-11-20 22:59:12,669 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:12,669 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:12,669 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:12,670 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:12,670 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:12,671 INFO L745 eck$LassoCheckResult]: Stem: 40592#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 40593#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 41574#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41575#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41042#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 41043#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40914#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40807#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40536#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40184#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40185#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40229#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40230#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41172#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41173#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41217#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40633#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40634#L1090 assume !(0 == ~M_E~0); 40676#L1090-2 assume !(0 == ~T1_E~0); 40677#L1095-1 assume !(0 == ~T2_E~0); 41364#L1100-1 assume !(0 == ~T3_E~0); 41365#L1105-1 assume !(0 == ~T4_E~0); 40456#L1110-1 assume !(0 == ~T5_E~0); 40457#L1115-1 assume !(0 == ~T6_E~0); 40843#L1120-1 assume !(0 == ~T7_E~0); 41151#L1125-1 assume !(0 == ~T8_E~0); 41623#L1130-1 assume !(0 == ~T9_E~0); 41386#L1135-1 assume !(0 == ~T10_E~0); 40638#L1140-1 assume !(0 == ~T11_E~0); 40639#L1145-1 assume !(0 == ~E_1~0); 41320#L1150-1 assume !(0 == ~E_2~0); 40820#L1155-1 assume !(0 == ~E_3~0); 40821#L1160-1 assume !(0 == ~E_4~0); 40919#L1165-1 assume !(0 == ~E_5~0); 40920#L1170-1 assume !(0 == ~E_6~0); 41558#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 41000#L1180-1 assume !(0 == ~E_8~0); 41001#L1185-1 assume !(0 == ~E_9~0); 40635#L1190-1 assume !(0 == ~E_10~0); 40636#L1195-1 assume !(0 == ~E_11~0); 41016#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40835#L525 assume !(1 == ~m_pc~0); 40274#L525-2 is_master_triggered_~__retres1~0#1 := 0; 40275#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41460#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41433#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40625#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40626#L544 assume 1 == ~t1_pc~0; 40895#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40842#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40248#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40249#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 40480#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41120#L563 assume !(1 == ~t2_pc~0); 41306#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40293#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40294#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40704#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 40705#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41198#L582 assume 1 == ~t3_pc~0; 40424#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40425#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40176#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40177#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 40362#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40363#L601 assume !(1 == ~t4_pc~0); 41332#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40844#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40372#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40373#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 41327#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41599#L620 assume 1 == ~t5_pc~0; 40321#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40322#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41214#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41465#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 41608#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41609#L639 assume !(1 == ~t6_pc~0); 41149#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40742#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40743#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40793#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 40850#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40851#L658 assume 1 == ~t7_pc~0; 41150#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41066#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41614#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41266#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 40628#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40629#L677 assume 1 == ~t8_pc~0; 40856#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40439#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40440#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40700#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 40701#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41427#L696 assume !(1 == ~t9_pc~0); 41132#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 41133#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40905#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40906#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41156#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41369#L715 assume 1 == ~t10_pc~0; 41376#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41248#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41054#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41055#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 40994#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40433#L734 assume !(1 == ~t11_pc~0); 40434#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 40921#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41003#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40172#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 40173#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41215#L1213 assume !(1 == ~M_E~0); 40991#L1213-2 assume !(1 == ~T1_E~0); 40992#L1218-1 assume !(1 == ~T2_E~0); 40207#L1223-1 assume !(1 == ~T3_E~0); 40208#L1228-1 assume !(1 == ~T4_E~0); 40967#L1233-1 assume !(1 == ~T5_E~0); 41610#L1238-1 assume !(1 == ~T6_E~0); 41325#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41326#L1248-1 assume !(1 == ~T8_E~0); 41372#L1253-1 assume !(1 == ~T9_E~0); 41373#L1258-1 assume !(1 == ~T10_E~0); 41348#L1263-1 assume !(1 == ~T11_E~0); 41349#L1268-1 assume !(1 == ~E_1~0); 41169#L1273-1 assume !(1 == ~E_2~0); 41170#L1278-1 assume !(1 == ~E_3~0); 40740#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 40741#L1288-1 assume !(1 == ~E_5~0); 41471#L1293-1 assume !(1 == ~E_6~0); 41431#L1298-1 assume !(1 == ~E_7~0); 41202#L1303-1 assume !(1 == ~E_8~0); 40750#L1308-1 assume !(1 == ~E_9~0); 40642#L1313-1 assume !(1 == ~E_10~0); 40643#L1318-1 assume !(1 == ~E_11~0); 40650#L1323-1 assume { :end_inline_reset_delta_events } true; 40651#L1644-2 [2024-11-20 22:59:12,671 INFO L747 eck$LassoCheckResult]: Loop: 40651#L1644-2 assume !false; 41264#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40557#L1065-1 assume !false; 40558#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41606#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40289#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40866#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40755#L906 assume !(0 != eval_~tmp~0#1); 40757#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41076#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41077#L1090-3 assume !(0 == ~M_E~0); 41486#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41543#L1095-3 assume !(0 == ~T2_E~0); 41508#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41509#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40531#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40532#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40808#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40809#L1125-3 assume !(0 == ~T8_E~0); 41324#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41581#L1135-3 assume !(0 == ~T10_E~0); 40730#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40239#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40240#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40364#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40365#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40713#L1165-3 assume !(0 == ~E_5~0); 40714#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41113#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40627#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40388#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40389#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41569#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41570#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40948#L525-36 assume !(1 == ~m_pc~0); 40949#L525-38 is_master_triggered_~__retres1~0#1 := 0; 40489#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40490#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40765#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40766#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40679#L544-36 assume 1 == ~t1_pc~0; 40680#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41236#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41237#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41576#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41556#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41461#L563-36 assume 1 == ~t2_pc~0; 40478#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40237#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40238#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41442#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40964#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40965#L582-36 assume 1 == ~t3_pc~0; 40797#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40798#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40896#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40897#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41002#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40942#L601-36 assume 1 == ~t4_pc~0; 40828#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40829#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41094#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41095#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41547#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41448#L620-36 assume 1 == ~t5_pc~0; 40881#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40882#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41309#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40855#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 40498#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40285#L639-36 assume 1 == ~t6_pc~0; 40286#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40326#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40327#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40548#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40549#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41154#L658-36 assume !(1 == ~t7_pc~0); 40298#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 40299#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41533#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40276#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40277#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41298#L677-36 assume 1 == ~t8_pc~0; 41475#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41070#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41199#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41200#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41096#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41097#L696-36 assume 1 == ~t9_pc~0; 40988#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40989#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40930#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40931#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41114#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41115#L715-36 assume !(1 == ~t10_pc~0); 41078#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 40174#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40175#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40150#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40151#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40541#L734-36 assume !(1 == ~t11_pc~0); 40253#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 40254#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40559#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40166#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40167#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41178#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40816#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40817#L1218-3 assume !(1 == ~T2_E~0); 40589#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40590#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40769#L1233-3 assume !(1 == ~T5_E~0); 40770#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41039#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41040#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41546#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41548#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40572#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40573#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41521#L1273-3 assume !(1 == ~E_2~0); 41536#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41538#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40917#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40918#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40763#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40764#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41260#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40760#L1313-3 assume !(1 == ~E_10~0); 40761#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40574#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40575#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40516#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40744#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 40745#L1663 assume !(0 == start_simulation_~tmp~3#1); 40414#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41152#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40360#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40246#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 40247#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40309#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40632#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41098#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 40651#L1644-2 [2024-11-20 22:59:12,671 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:12,672 INFO L85 PathProgramCache]: Analyzing trace with hash -268309982, now seen corresponding path program 1 times [2024-11-20 22:59:12,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:12,672 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522206112] [2024-11-20 22:59:12,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:12,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:12,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,718 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,718 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522206112] [2024-11-20 22:59:12,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522206112] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,718 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-20 22:59:12,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245248976] [2024-11-20 22:59:12,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,718 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:12,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:12,719 INFO L85 PathProgramCache]: Analyzing trace with hash 17254343, now seen corresponding path program 1 times [2024-11-20 22:59:12,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:12,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188617647] [2024-11-20 22:59:12,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:12,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:12,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,756 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1188617647] [2024-11-20 22:59:12,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1188617647] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,756 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:12,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996574724] [2024-11-20 22:59:12,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,757 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:12,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:12,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:12,757 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:12,757 INFO L87 Difference]: Start difference. First operand 1488 states and 2188 transitions. cyclomatic complexity: 701 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:12,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:12,807 INFO L93 Difference]: Finished difference Result 1488 states and 2170 transitions. [2024-11-20 22:59:12,807 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2170 transitions. [2024-11-20 22:59:12,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:12,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2170 transitions. [2024-11-20 22:59:12,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-20 22:59:12,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-20 22:59:12,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2170 transitions. [2024-11-20 22:59:12,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:12,817 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2024-11-20 22:59:12,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2170 transitions. [2024-11-20 22:59:12,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2024-11-20 22:59:12,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4583333333333333) internal successors, (2170), 1487 states have internal predecessors, (2170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:12,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2170 transitions. [2024-11-20 22:59:12,834 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2024-11-20 22:59:12,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:12,835 INFO L425 stractBuchiCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2024-11-20 22:59:12,835 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-20 22:59:12,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2170 transitions. [2024-11-20 22:59:12,838 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2024-11-20 22:59:12,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:12,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:12,839 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:12,839 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:12,840 INFO L745 eck$LassoCheckResult]: Stem: 43575#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 43576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 44557#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44558#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44024#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 44025#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43897#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43790#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43519#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43167#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43168#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43212#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43213#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44155#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44156#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44200#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43616#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43617#L1090 assume !(0 == ~M_E~0); 43659#L1090-2 assume !(0 == ~T1_E~0); 43660#L1095-1 assume !(0 == ~T2_E~0); 44347#L1100-1 assume !(0 == ~T3_E~0); 44348#L1105-1 assume !(0 == ~T4_E~0); 43439#L1110-1 assume !(0 == ~T5_E~0); 43440#L1115-1 assume !(0 == ~T6_E~0); 43826#L1120-1 assume !(0 == ~T7_E~0); 44133#L1125-1 assume !(0 == ~T8_E~0); 44606#L1130-1 assume !(0 == ~T9_E~0); 44369#L1135-1 assume !(0 == ~T10_E~0); 43621#L1140-1 assume !(0 == ~T11_E~0); 43622#L1145-1 assume !(0 == ~E_1~0); 44303#L1150-1 assume !(0 == ~E_2~0); 43803#L1155-1 assume !(0 == ~E_3~0); 43804#L1160-1 assume !(0 == ~E_4~0); 43902#L1165-1 assume !(0 == ~E_5~0); 43903#L1170-1 assume !(0 == ~E_6~0); 44541#L1175-1 assume !(0 == ~E_7~0); 43982#L1180-1 assume !(0 == ~E_8~0); 43983#L1185-1 assume !(0 == ~E_9~0); 43618#L1190-1 assume !(0 == ~E_10~0); 43619#L1195-1 assume !(0 == ~E_11~0); 43998#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43818#L525 assume !(1 == ~m_pc~0); 43257#L525-2 is_master_triggered_~__retres1~0#1 := 0; 43258#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44443#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44416#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43608#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43609#L544 assume 1 == ~t1_pc~0; 43878#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43825#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43231#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43232#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 43463#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44102#L563 assume !(1 == ~t2_pc~0); 44289#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43276#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43277#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43687#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 43688#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44181#L582 assume 1 == ~t3_pc~0; 43407#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43408#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43159#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43160#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 43345#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43346#L601 assume !(1 == ~t4_pc~0); 44315#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43827#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43357#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43358#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 44310#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44582#L620 assume 1 == ~t5_pc~0; 43304#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43305#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44197#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44448#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 44591#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44592#L639 assume !(1 == ~t6_pc~0); 44131#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 43725#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43726#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43776#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 43833#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43834#L658 assume !(1 == ~t7_pc~0); 44047#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 44048#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44597#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44249#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 43611#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43612#L677 assume 1 == ~t8_pc~0; 43839#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43422#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43423#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43683#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 43684#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44410#L696 assume !(1 == ~t9_pc~0); 44114#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 44115#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43888#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43889#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44138#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44352#L715 assume 1 == ~t10_pc~0; 44359#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44231#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44036#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44037#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 43976#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43416#L734 assume !(1 == ~t11_pc~0); 43417#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 43904#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43985#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43155#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 43156#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44198#L1213 assume !(1 == ~M_E~0); 43973#L1213-2 assume !(1 == ~T1_E~0); 43974#L1218-1 assume !(1 == ~T2_E~0); 43190#L1223-1 assume !(1 == ~T3_E~0); 43191#L1228-1 assume !(1 == ~T4_E~0); 43949#L1233-1 assume !(1 == ~T5_E~0); 44593#L1238-1 assume !(1 == ~T6_E~0); 44308#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44309#L1248-1 assume !(1 == ~T8_E~0); 44355#L1253-1 assume !(1 == ~T9_E~0); 44356#L1258-1 assume !(1 == ~T10_E~0); 44331#L1263-1 assume !(1 == ~T11_E~0); 44332#L1268-1 assume !(1 == ~E_1~0); 44152#L1273-1 assume !(1 == ~E_2~0); 44153#L1278-1 assume !(1 == ~E_3~0); 43723#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43724#L1288-1 assume !(1 == ~E_5~0); 44454#L1293-1 assume !(1 == ~E_6~0); 44414#L1298-1 assume !(1 == ~E_7~0); 44185#L1303-1 assume !(1 == ~E_8~0); 43733#L1308-1 assume !(1 == ~E_9~0); 43625#L1313-1 assume !(1 == ~E_10~0); 43626#L1318-1 assume !(1 == ~E_11~0); 43633#L1323-1 assume { :end_inline_reset_delta_events } true; 43634#L1644-2 [2024-11-20 22:59:12,840 INFO L747 eck$LassoCheckResult]: Loop: 43634#L1644-2 assume !false; 44247#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43540#L1065-1 assume !false; 43541#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 44589#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43272#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43849#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43738#L906 assume !(0 != eval_~tmp~0#1); 43740#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44058#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44059#L1090-3 assume !(0 == ~M_E~0); 44469#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44526#L1095-3 assume !(0 == ~T2_E~0); 44491#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44492#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43514#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43515#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43791#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43792#L1125-3 assume !(0 == ~T8_E~0); 44307#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44564#L1135-3 assume !(0 == ~T10_E~0); 43713#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43222#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43223#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43348#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43349#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43696#L1165-3 assume !(0 == ~E_5~0); 43697#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44095#L1175-3 assume !(0 == ~E_7~0); 43610#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43371#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43372#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44552#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44553#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43930#L525-36 assume !(1 == ~m_pc~0); 43931#L525-38 is_master_triggered_~__retres1~0#1 := 0; 43472#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43473#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43748#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43749#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43662#L544-36 assume !(1 == ~t1_pc~0); 43664#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 44219#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44220#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44559#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44539#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44444#L563-36 assume 1 == ~t2_pc~0; 43461#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43220#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43221#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44425#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43946#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43947#L582-36 assume 1 == ~t3_pc~0; 43780#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43781#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43879#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43880#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43984#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43924#L601-36 assume 1 == ~t4_pc~0; 43811#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43812#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44076#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44077#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44530#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44431#L620-36 assume 1 == ~t5_pc~0; 43864#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43865#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44292#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43838#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 43481#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43268#L639-36 assume 1 == ~t6_pc~0; 43269#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43309#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43310#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43531#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43532#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44136#L658-36 assume !(1 == ~t7_pc~0); 43281#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 43282#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44516#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43259#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43260#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44281#L677-36 assume !(1 == ~t8_pc~0); 44051#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 44052#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44182#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44183#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44078#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44079#L696-36 assume 1 == ~t9_pc~0; 43970#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43971#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43913#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43914#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44096#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44097#L715-36 assume 1 == ~t10_pc~0; 44242#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43157#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43158#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43135#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43136#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43524#L734-36 assume !(1 == ~t11_pc~0); 43236#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 43237#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43542#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43149#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43150#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44161#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43799#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43800#L1218-3 assume !(1 == ~T2_E~0); 43572#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43573#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43752#L1233-3 assume !(1 == ~T5_E~0); 43753#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44021#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44022#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44529#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44531#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43555#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43556#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44504#L1273-3 assume !(1 == ~E_2~0); 44519#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44521#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43900#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43901#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43746#L1298-3 assume !(1 == ~E_7~0); 43747#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44243#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43743#L1313-3 assume !(1 == ~E_10~0); 43744#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43557#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 43558#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43499#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43727#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 43728#L1663 assume !(0 == start_simulation_~tmp~3#1); 43390#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 44134#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43343#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43226#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 43227#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43289#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43615#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 44080#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 43634#L1644-2 [2024-11-20 22:59:12,840 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:12,840 INFO L85 PathProgramCache]: Analyzing trace with hash -2032217409, now seen corresponding path program 1 times [2024-11-20 22:59:12,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:12,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094730571] [2024-11-20 22:59:12,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:12,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:12,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094730571] [2024-11-20 22:59:12,889 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094730571] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,889 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,889 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-20 22:59:12,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2115546479] [2024-11-20 22:59:12,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,889 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:12,889 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:12,890 INFO L85 PathProgramCache]: Analyzing trace with hash -884328670, now seen corresponding path program 1 times [2024-11-20 22:59:12,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:12,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077516294] [2024-11-20 22:59:12,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:12,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:12,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:12,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:12,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:12,958 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077516294] [2024-11-20 22:59:12,958 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077516294] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:12,958 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:12,958 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:12,958 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032606477] [2024-11-20 22:59:12,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:12,958 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:12,958 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:12,958 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-20 22:59:12,958 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-20 22:59:12,959 INFO L87 Difference]: Start difference. First operand 1488 states and 2170 transitions. cyclomatic complexity: 683 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:13,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:13,174 INFO L93 Difference]: Finished difference Result 1530 states and 2212 transitions. [2024-11-20 22:59:13,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1530 states and 2212 transitions. [2024-11-20 22:59:13,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1378 [2024-11-20 22:59:13,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1530 states to 1530 states and 2212 transitions. [2024-11-20 22:59:13,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1530 [2024-11-20 22:59:13,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1530 [2024-11-20 22:59:13,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1530 states and 2212 transitions. [2024-11-20 22:59:13,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:13,184 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1530 states and 2212 transitions. [2024-11-20 22:59:13,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1530 states and 2212 transitions. [2024-11-20 22:59:13,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1530 to 1530. [2024-11-20 22:59:13,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1530 states, 1530 states have (on average 1.445751633986928) internal successors, (2212), 1529 states have internal predecessors, (2212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:13,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1530 states to 1530 states and 2212 transitions. [2024-11-20 22:59:13,202 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1530 states and 2212 transitions. [2024-11-20 22:59:13,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-20 22:59:13,203 INFO L425 stractBuchiCegarLoop]: Abstraction has 1530 states and 2212 transitions. [2024-11-20 22:59:13,203 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-20 22:59:13,203 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1530 states and 2212 transitions. [2024-11-20 22:59:13,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1378 [2024-11-20 22:59:13,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:13,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:13,207 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:13,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:13,207 INFO L745 eck$LassoCheckResult]: Stem: 46602#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 46603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 47595#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47596#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47054#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 47055#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46927#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46819#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46546#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46194#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46195#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46239#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46240#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47190#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47191#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47235#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 46644#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46645#L1090 assume !(0 == ~M_E~0); 46690#L1090-2 assume !(0 == ~T1_E~0); 46691#L1095-1 assume !(0 == ~T2_E~0); 47382#L1100-1 assume !(0 == ~T3_E~0); 47383#L1105-1 assume !(0 == ~T4_E~0); 46467#L1110-1 assume !(0 == ~T5_E~0); 46468#L1115-1 assume !(0 == ~T6_E~0); 46858#L1120-1 assume !(0 == ~T7_E~0); 47164#L1125-1 assume !(0 == ~T8_E~0); 47647#L1130-1 assume !(0 == ~T9_E~0); 47403#L1135-1 assume !(0 == ~T10_E~0); 46649#L1140-1 assume !(0 == ~T11_E~0); 46650#L1145-1 assume !(0 == ~E_1~0); 47337#L1150-1 assume !(0 == ~E_2~0); 46832#L1155-1 assume !(0 == ~E_3~0); 46833#L1160-1 assume !(0 == ~E_4~0); 46932#L1165-1 assume !(0 == ~E_5~0); 46933#L1170-1 assume !(0 == ~E_6~0); 47577#L1175-1 assume !(0 == ~E_7~0); 47012#L1180-1 assume !(0 == ~E_8~0); 47013#L1185-1 assume !(0 == ~E_9~0); 46646#L1190-1 assume !(0 == ~E_10~0); 46647#L1195-1 assume !(0 == ~E_11~0); 47028#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46852#L525 assume !(1 == ~m_pc~0); 46284#L525-2 is_master_triggered_~__retres1~0#1 := 0; 46285#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47477#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47452#L1350 assume !(0 != activate_threads_~tmp~1#1); 46636#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46637#L544 assume 1 == ~t1_pc~0; 46907#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46854#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46263#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46264#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 46490#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47133#L563 assume !(1 == ~t2_pc~0); 47325#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46303#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46304#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46718#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 46719#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47212#L582 assume 1 == ~t3_pc~0; 46436#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46437#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46186#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46187#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 46372#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46373#L601 assume !(1 == ~t4_pc~0); 47349#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46859#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46386#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46387#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 47344#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47620#L620 assume 1 == ~t5_pc~0; 46335#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46336#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47228#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47483#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 47631#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47632#L639 assume !(1 == ~t6_pc~0); 47162#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46756#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46757#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46805#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 46862#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46863#L658 assume !(1 == ~t7_pc~0); 47078#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 47079#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47637#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47283#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 46639#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46640#L677 assume 1 == ~t8_pc~0; 46870#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46452#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46453#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46711#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 46712#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47444#L696 assume !(1 == ~t9_pc~0); 47148#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 47149#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46917#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46918#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47171#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47386#L715 assume 1 == ~t10_pc~0; 47393#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47262#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47066#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47067#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 47006#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46443#L734 assume !(1 == ~t11_pc~0); 46444#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 46934#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47017#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46184#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 46185#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47229#L1213 assume !(1 == ~M_E~0); 47004#L1213-2 assume !(1 == ~T1_E~0); 47005#L1218-1 assume !(1 == ~T2_E~0); 46217#L1223-1 assume !(1 == ~T3_E~0); 46218#L1228-1 assume !(1 == ~T4_E~0); 46979#L1233-1 assume !(1 == ~T5_E~0); 47633#L1238-1 assume !(1 == ~T6_E~0); 47342#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47343#L1248-1 assume !(1 == ~T8_E~0); 47389#L1253-1 assume !(1 == ~T9_E~0); 47390#L1258-1 assume !(1 == ~T10_E~0); 47365#L1263-1 assume !(1 == ~T11_E~0); 47366#L1268-1 assume !(1 == ~E_1~0); 47183#L1273-1 assume !(1 == ~E_2~0); 47184#L1278-1 assume !(1 == ~E_3~0); 46752#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 46753#L1288-1 assume !(1 == ~E_5~0); 47488#L1293-1 assume !(1 == ~E_6~0); 47448#L1298-1 assume !(1 == ~E_7~0); 47216#L1303-1 assume !(1 == ~E_8~0); 46762#L1308-1 assume !(1 == ~E_9~0); 46653#L1313-1 assume !(1 == ~E_10~0); 46654#L1318-1 assume !(1 == ~E_11~0); 46664#L1323-1 assume { :end_inline_reset_delta_events } true; 46665#L1644-2 [2024-11-20 22:59:13,208 INFO L747 eck$LassoCheckResult]: Loop: 46665#L1644-2 assume !false; 47280#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46568#L1065-1 assume !false; 46569#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 47629#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 46299#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46878#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46767#L906 assume !(0 != eval_~tmp~0#1); 46769#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47089#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47090#L1090-3 assume !(0 == ~M_E~0); 47504#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47561#L1095-3 assume !(0 == ~T2_E~0); 47526#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47527#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46541#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46542#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46820#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46821#L1125-3 assume !(0 == ~T8_E~0); 47341#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47601#L1135-3 assume !(0 == ~T10_E~0); 46743#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46251#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46252#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46375#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46376#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46724#L1165-3 assume !(0 == ~E_5~0); 46725#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47126#L1175-3 assume !(0 == ~E_7~0); 46638#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46398#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46399#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47588#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47589#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46955#L525-36 assume !(1 == ~m_pc~0); 46956#L525-38 is_master_triggered_~__retres1~0#1 := 0; 46499#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46500#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46777#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 46778#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46687#L544-36 assume 1 == ~t1_pc~0; 46688#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47250#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47251#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47594#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47575#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47478#L563-36 assume 1 == ~t2_pc~0; 46488#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46247#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46248#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47459#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46976#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46977#L582-36 assume 1 == ~t3_pc~0; 46809#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46810#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46908#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46909#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47014#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46954#L601-36 assume 1 == ~t4_pc~0; 46840#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46841#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47106#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47107#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47565#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47465#L620-36 assume 1 == ~t5_pc~0; 46891#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46892#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47326#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46867#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 46508#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46295#L639-36 assume 1 == ~t6_pc~0; 46296#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46333#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46334#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46558#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46559#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47167#L658-36 assume !(1 == ~t7_pc~0); 46308#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 46309#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47551#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46286#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46287#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47315#L677-36 assume 1 == ~t8_pc~0; 47492#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47082#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47213#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47214#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47108#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47109#L696-36 assume 1 == ~t9_pc~0; 47000#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47001#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46943#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46944#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47127#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47128#L715-36 assume !(1 == ~t10_pc~0); 47088#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 46182#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46183#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46160#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46161#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46551#L734-36 assume !(1 == ~t11_pc~0); 46261#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 46262#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46567#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46176#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46177#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47192#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46826#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46827#L1218-3 assume !(1 == ~T2_E~0); 46599#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46600#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46781#L1233-3 assume !(1 == ~T5_E~0); 46782#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47051#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47052#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47564#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47566#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46581#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46582#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47539#L1273-3 assume !(1 == ~E_2~0); 47554#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47556#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46930#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46931#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46775#L1298-3 assume !(1 == ~E_7~0); 46776#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47275#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46772#L1313-3 assume !(1 == ~E_10~0); 46773#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 46583#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 46584#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 46526#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46754#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 46755#L1663 assume !(0 == start_simulation_~tmp~3#1); 46424#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 47165#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 46370#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46253#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 46254#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46319#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46643#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 47111#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 46665#L1644-2 [2024-11-20 22:59:13,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:13,208 INFO L85 PathProgramCache]: Analyzing trace with hash -2060717699, now seen corresponding path program 1 times [2024-11-20 22:59:13,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:13,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150363781] [2024-11-20 22:59:13,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:13,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:13,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:13,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:13,246 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:13,246 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150363781] [2024-11-20 22:59:13,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [150363781] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:13,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:13,247 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-20 22:59:13,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [307826467] [2024-11-20 22:59:13,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:13,247 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:13,247 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:13,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1414289921, now seen corresponding path program 1 times [2024-11-20 22:59:13,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:13,247 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1602547236] [2024-11-20 22:59:13,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:13,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:13,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:13,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:13,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:13,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1602547236] [2024-11-20 22:59:13,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1602547236] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:13,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:13,313 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:13,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [356195008] [2024-11-20 22:59:13,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:13,313 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:13,313 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:13,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:13,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:13,314 INFO L87 Difference]: Start difference. First operand 1530 states and 2212 transitions. cyclomatic complexity: 683 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:13,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:13,397 INFO L93 Difference]: Finished difference Result 2805 states and 4029 transitions. [2024-11-20 22:59:13,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2805 states and 4029 transitions. [2024-11-20 22:59:13,406 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2652 [2024-11-20 22:59:13,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2805 states to 2805 states and 4029 transitions. [2024-11-20 22:59:13,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2805 [2024-11-20 22:59:13,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2805 [2024-11-20 22:59:13,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2805 states and 4029 transitions. [2024-11-20 22:59:13,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:13,416 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2805 states and 4029 transitions. [2024-11-20 22:59:13,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2805 states and 4029 transitions. [2024-11-20 22:59:13,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2805 to 2803. [2024-11-20 22:59:13,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2803 states, 2803 states have (on average 1.4366749910809846) internal successors, (4027), 2802 states have internal predecessors, (4027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:13,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2803 states to 2803 states and 4027 transitions. [2024-11-20 22:59:13,453 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2803 states and 4027 transitions. [2024-11-20 22:59:13,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:13,454 INFO L425 stractBuchiCegarLoop]: Abstraction has 2803 states and 4027 transitions. [2024-11-20 22:59:13,454 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-20 22:59:13,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2803 states and 4027 transitions. [2024-11-20 22:59:13,460 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2650 [2024-11-20 22:59:13,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:13,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:13,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:13,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:13,461 INFO L745 eck$LassoCheckResult]: Stem: 50946#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 50947#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 52006#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52007#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51407#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 51408#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51275#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51167#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50889#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50536#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50537#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50581#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50582#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 51546#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 51547#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51591#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 50989#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50990#L1090 assume !(0 == ~M_E~0); 51035#L1090-2 assume !(0 == ~T1_E~0); 51036#L1095-1 assume !(0 == ~T2_E~0); 51752#L1100-1 assume !(0 == ~T3_E~0); 51753#L1105-1 assume !(0 == ~T4_E~0); 50809#L1110-1 assume !(0 == ~T5_E~0); 50810#L1115-1 assume !(0 == ~T6_E~0); 51205#L1120-1 assume !(0 == ~T7_E~0); 51523#L1125-1 assume !(0 == ~T8_E~0); 52088#L1130-1 assume !(0 == ~T9_E~0); 51778#L1135-1 assume !(0 == ~T10_E~0); 50994#L1140-1 assume !(0 == ~T11_E~0); 50995#L1145-1 assume !(0 == ~E_1~0); 51703#L1150-1 assume !(0 == ~E_2~0); 51180#L1155-1 assume !(0 == ~E_3~0); 51181#L1160-1 assume !(0 == ~E_4~0); 51282#L1165-1 assume !(0 == ~E_5~0); 51283#L1170-1 assume !(0 == ~E_6~0); 51984#L1175-1 assume !(0 == ~E_7~0); 51364#L1180-1 assume !(0 == ~E_8~0); 51365#L1185-1 assume !(0 == ~E_9~0); 50991#L1190-1 assume !(0 == ~E_10~0); 50992#L1195-1 assume !(0 == ~E_11~0); 51380#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51202#L525 assume !(1 == ~m_pc~0); 50626#L525-2 is_master_triggered_~__retres1~0#1 := 0; 50627#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51864#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 51834#L1350 assume !(0 != activate_threads_~tmp~1#1); 50980#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50981#L544 assume !(1 == ~t1_pc~0); 51203#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 51204#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50605#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50606#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 50832#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51490#L563 assume !(1 == ~t2_pc~0); 51689#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50645#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50646#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51062#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 51063#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51572#L582 assume 1 == ~t3_pc~0; 50778#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50779#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50528#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50529#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 50714#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50715#L601 assume !(1 == ~t4_pc~0); 51718#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51206#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50728#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50729#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 51712#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52052#L620 assume 1 == ~t5_pc~0; 50675#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50676#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51588#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51872#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 52070#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52071#L639 assume !(1 == ~t6_pc~0); 51521#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 51103#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51104#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51153#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 51211#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51212#L658 assume !(1 == ~t7_pc~0); 51431#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 51432#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52076#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51644#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 50984#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50985#L677 assume 1 == ~t8_pc~0; 51220#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50791#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50792#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51058#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 51059#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51825#L696 assume !(1 == ~t9_pc~0); 51505#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 51506#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51266#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51267#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51528#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51757#L715 assume 1 == ~t10_pc~0; 51768#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51624#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51419#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51420#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 51357#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50785#L734 assume !(1 == ~t11_pc~0); 50786#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 51284#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51369#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50526#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 50527#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51589#L1213 assume !(1 == ~M_E~0); 51355#L1213-2 assume !(1 == ~T1_E~0); 51356#L1218-1 assume !(1 == ~T2_E~0); 50559#L1223-1 assume !(1 == ~T3_E~0); 50560#L1228-1 assume !(1 == ~T4_E~0); 51330#L1233-1 assume !(1 == ~T5_E~0); 52072#L1238-1 assume !(1 == ~T6_E~0); 51710#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51711#L1248-1 assume !(1 == ~T8_E~0); 51764#L1253-1 assume !(1 == ~T9_E~0); 51765#L1258-1 assume !(1 == ~T10_E~0); 51734#L1263-1 assume !(1 == ~T11_E~0); 51735#L1268-1 assume !(1 == ~E_1~0); 51543#L1273-1 assume !(1 == ~E_2~0); 51544#L1278-1 assume !(1 == ~E_3~0); 51099#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 51100#L1288-1 assume !(1 == ~E_5~0); 51879#L1293-1 assume !(1 == ~E_6~0); 51829#L1298-1 assume !(1 == ~E_7~0); 51576#L1303-1 assume !(1 == ~E_8~0); 51110#L1308-1 assume !(1 == ~E_9~0); 50998#L1313-1 assume !(1 == ~E_10~0); 50999#L1318-1 assume !(1 == ~E_11~0); 51009#L1323-1 assume { :end_inline_reset_delta_events } true; 51010#L1644-2 [2024-11-20 22:59:13,462 INFO L747 eck$LassoCheckResult]: Loop: 51010#L1644-2 assume !false; 51641#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50912#L1065-1 assume !false; 50913#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 52068#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 50641#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 52372#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 52370#L906 assume !(0 != eval_~tmp~0#1); 51802#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51442#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51443#L1090-3 assume !(0 == ~M_E~0); 51899#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51963#L1095-3 assume !(0 == ~T2_E~0); 51921#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51922#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50884#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50885#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51168#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51169#L1125-3 assume !(0 == ~T8_E~0); 51708#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 52016#L1135-3 assume !(0 == ~T10_E~0); 51090#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50593#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50594#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50717#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50718#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51071#L1165-3 assume !(0 == ~E_5~0); 51072#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51483#L1175-3 assume !(0 == ~E_7~0); 50982#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50983#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52802#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52801#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52800#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52799#L525-36 assume 1 == ~m_pc~0; 52798#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 52797#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52796#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52795#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52794#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51033#L544-36 assume !(1 == ~t1_pc~0); 51034#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 51610#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51611#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 52005#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51981#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51865#L563-36 assume !(1 == ~t2_pc~0); 51866#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 52759#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52758#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52757#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52756#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52755#L582-36 assume 1 == ~t3_pc~0; 51157#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51158#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51257#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51258#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51366#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51302#L601-36 assume 1 == ~t4_pc~0; 51190#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51191#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51459#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51460#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51968#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51846#L620-36 assume 1 == ~t5_pc~0; 51241#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51242#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51692#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51217#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 50850#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50637#L639-36 assume 1 == ~t6_pc~0; 50638#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52735#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52734#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52733#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 52732#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52731#L658-36 assume !(1 == ~t7_pc~0); 52729#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 52728#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52727#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52726#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52725#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52724#L677-36 assume 1 == ~t8_pc~0; 51993#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51435#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51573#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51574#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51461#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51462#L696-36 assume 1 == ~t9_pc~0; 51351#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51352#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52716#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52715#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52714#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52713#L715-36 assume 1 == ~t10_pc~0; 52711#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52710#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51109#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50502#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50503#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50895#L734-36 assume 1 == ~t11_pc~0; 50896#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50604#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50911#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50518#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50519#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51552#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 52700#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52699#L1218-3 assume !(1 == ~T2_E~0); 52698#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52697#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51129#L1233-3 assume !(1 == ~T5_E~0); 51130#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51404#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51405#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52694#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 51970#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50925#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50926#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51934#L1273-3 assume !(1 == ~E_2~0); 52691#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 52690#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51280#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51281#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51123#L1298-3 assume !(1 == ~E_7~0); 51124#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52032#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 52686#L1313-3 assume !(1 == ~E_10~0); 51969#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50927#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 50928#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 52673#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 51101#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 51102#L1663 assume !(0 == start_simulation_~tmp~3#1); 52643#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 51524#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 50712#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 50595#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 50596#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50658#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50988#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 51464#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 51010#L1644-2 [2024-11-20 22:59:13,462 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:13,462 INFO L85 PathProgramCache]: Analyzing trace with hash -2098164388, now seen corresponding path program 1 times [2024-11-20 22:59:13,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:13,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414165509] [2024-11-20 22:59:13,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:13,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:13,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:13,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:13,503 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:13,503 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414165509] [2024-11-20 22:59:13,503 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [414165509] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:13,503 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:13,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-20 22:59:13,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [628063093] [2024-11-20 22:59:13,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:13,503 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:13,503 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:13,504 INFO L85 PathProgramCache]: Analyzing trace with hash -314942556, now seen corresponding path program 1 times [2024-11-20 22:59:13,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:13,504 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781149425] [2024-11-20 22:59:13,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:13,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:13,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:13,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:13,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:13,538 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781149425] [2024-11-20 22:59:13,538 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781149425] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:13,539 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:13,539 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:13,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051442317] [2024-11-20 22:59:13,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:13,539 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:13,539 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:13,539 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:13,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:13,540 INFO L87 Difference]: Start difference. First operand 2803 states and 4027 transitions. cyclomatic complexity: 1226 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:13,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:13,629 INFO L93 Difference]: Finished difference Result 5250 states and 7502 transitions. [2024-11-20 22:59:13,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5250 states and 7502 transitions. [2024-11-20 22:59:13,647 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5094 [2024-11-20 22:59:13,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5250 states to 5250 states and 7502 transitions. [2024-11-20 22:59:13,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5250 [2024-11-20 22:59:13,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5250 [2024-11-20 22:59:13,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5250 states and 7502 transitions. [2024-11-20 22:59:13,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:13,737 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5250 states and 7502 transitions. [2024-11-20 22:59:13,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5250 states and 7502 transitions. [2024-11-20 22:59:13,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5250 to 5246. [2024-11-20 22:59:13,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5246 states, 5246 states have (on average 1.4292794510102935) internal successors, (7498), 5245 states have internal predecessors, (7498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:13,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5246 states to 5246 states and 7498 transitions. [2024-11-20 22:59:13,811 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5246 states and 7498 transitions. [2024-11-20 22:59:13,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:13,812 INFO L425 stractBuchiCegarLoop]: Abstraction has 5246 states and 7498 transitions. [2024-11-20 22:59:13,812 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-20 22:59:13,812 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5246 states and 7498 transitions. [2024-11-20 22:59:13,826 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5090 [2024-11-20 22:59:13,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:13,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:13,828 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:13,828 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:13,828 INFO L745 eck$LassoCheckResult]: Stem: 59002#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 59003#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 60040#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60041#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59463#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 59464#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59333#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59224#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58945#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58596#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58597#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58641#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 58642#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59599#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59600#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59645#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59047#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59048#L1090 assume !(0 == ~M_E~0); 59090#L1090-2 assume !(0 == ~T1_E~0); 59091#L1095-1 assume !(0 == ~T2_E~0); 59800#L1100-1 assume !(0 == ~T3_E~0); 59801#L1105-1 assume !(0 == ~T4_E~0); 58865#L1110-1 assume !(0 == ~T5_E~0); 58866#L1115-1 assume !(0 == ~T6_E~0); 59262#L1120-1 assume !(0 == ~T7_E~0); 59576#L1125-1 assume !(0 == ~T8_E~0); 60118#L1130-1 assume !(0 == ~T9_E~0); 59821#L1135-1 assume !(0 == ~T10_E~0); 59052#L1140-1 assume !(0 == ~T11_E~0); 59053#L1145-1 assume !(0 == ~E_1~0); 59752#L1150-1 assume !(0 == ~E_2~0); 59238#L1155-1 assume !(0 == ~E_3~0); 59239#L1160-1 assume !(0 == ~E_4~0); 59338#L1165-1 assume !(0 == ~E_5~0); 59339#L1170-1 assume !(0 == ~E_6~0); 60022#L1175-1 assume !(0 == ~E_7~0); 59420#L1180-1 assume !(0 == ~E_8~0); 59421#L1185-1 assume !(0 == ~E_9~0); 59049#L1190-1 assume !(0 == ~E_10~0); 59050#L1195-1 assume !(0 == ~E_11~0); 59436#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59259#L525 assume !(1 == ~m_pc~0); 58685#L525-2 is_master_triggered_~__retres1~0#1 := 0; 58686#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59908#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 59879#L1350 assume !(0 != activate_threads_~tmp~1#1); 59038#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59039#L544 assume !(1 == ~t1_pc~0); 59260#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 59261#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58665#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 58666#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 58888#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59544#L563 assume !(1 == ~t2_pc~0); 59737#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 58704#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58705#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59118#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 59119#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59626#L582 assume !(1 == ~t3_pc~0); 59751#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60086#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58588#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58589#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 58773#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58774#L601 assume !(1 == ~t4_pc~0); 59765#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 59263#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58787#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58788#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 59759#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60080#L620 assume 1 == ~t5_pc~0; 58734#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58735#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59642#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59914#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 60094#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60095#L639 assume !(1 == ~t6_pc~0); 59574#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 59159#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59160#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59208#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 59268#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59269#L658 assume !(1 == ~t7_pc~0); 59487#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59488#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60100#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59695#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 59042#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59043#L677 assume 1 == ~t8_pc~0; 59274#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58847#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58848#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59114#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 59115#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59869#L696 assume !(1 == ~t9_pc~0); 59559#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 59560#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59323#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59324#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59581#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59804#L715 assume 1 == ~t10_pc~0; 59811#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59675#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59475#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59476#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 59413#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58841#L734 assume !(1 == ~t11_pc~0); 58842#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 59340#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59423#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58586#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 58587#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59643#L1213 assume !(1 == ~M_E~0); 59411#L1213-2 assume !(1 == ~T1_E~0); 59412#L1218-1 assume !(1 == ~T2_E~0); 58619#L1223-1 assume !(1 == ~T3_E~0); 58620#L1228-1 assume !(1 == ~T4_E~0); 59387#L1233-1 assume !(1 == ~T5_E~0); 60096#L1238-1 assume !(1 == ~T6_E~0); 59757#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 59758#L1248-1 assume !(1 == ~T8_E~0); 59807#L1253-1 assume !(1 == ~T9_E~0); 59808#L1258-1 assume !(1 == ~T10_E~0); 59783#L1263-1 assume !(1 == ~T11_E~0); 59784#L1268-1 assume !(1 == ~E_1~0); 59596#L1273-1 assume !(1 == ~E_2~0); 59597#L1278-1 assume !(1 == ~E_3~0); 59155#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 59156#L1288-1 assume !(1 == ~E_5~0); 59921#L1293-1 assume !(1 == ~E_6~0); 59874#L1298-1 assume !(1 == ~E_7~0); 59630#L1303-1 assume !(1 == ~E_8~0); 59165#L1308-1 assume !(1 == ~E_9~0); 59056#L1313-1 assume !(1 == ~E_10~0); 59057#L1318-1 assume !(1 == ~E_11~0); 59064#L1323-1 assume { :end_inline_reset_delta_events } true; 59065#L1644-2 [2024-11-20 22:59:13,829 INFO L747 eck$LassoCheckResult]: Loop: 59065#L1644-2 assume !false; 59693#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 58968#L1065-1 assume !false; 58969#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 60092#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 58700#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 59285#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 59170#L906 assume !(0 != eval_~tmp~0#1); 59172#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63757#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63756#L1090-3 assume !(0 == ~M_E~0); 63755#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 63754#L1095-3 assume !(0 == ~T2_E~0); 63753#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 63752#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63751#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 63750#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 63749#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 63748#L1125-3 assume !(0 == ~T8_E~0); 63747#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 63746#L1135-3 assume !(0 == ~T10_E~0); 63745#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 63744#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 63743#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 63742#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 63741#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 63740#L1165-3 assume !(0 == ~E_5~0); 63739#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 63738#L1175-3 assume !(0 == ~E_7~0); 63737#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 63736#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 63735#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 63734#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 63733#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63732#L525-36 assume !(1 == ~m_pc~0); 63730#L525-38 is_master_triggered_~__retres1~0#1 := 0; 63728#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63726#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63725#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 63723#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63722#L544-36 assume !(1 == ~t1_pc~0); 63721#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 63720#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63719#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63718#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 63717#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63716#L563-36 assume !(1 == ~t2_pc~0); 63714#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 63713#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63712#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63711#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 63710#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63709#L582-36 assume !(1 == ~t3_pc~0); 63708#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 63707#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63706#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63705#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 63704#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63703#L601-36 assume !(1 == ~t4_pc~0); 63701#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 63700#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63699#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63697#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 63695#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63693#L620-36 assume 1 == ~t5_pc~0; 63690#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63687#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63685#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63683#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 63681#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63679#L639-36 assume 1 == ~t6_pc~0; 63676#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63673#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63671#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63669#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 63667#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63665#L658-36 assume !(1 == ~t7_pc~0); 63662#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 63659#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63657#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63656#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 63655#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63653#L677-36 assume 1 == ~t8_pc~0; 63650#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 63648#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63473#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63472#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63471#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63470#L696-36 assume !(1 == ~t9_pc~0); 63468#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 59838#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59349#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59350#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59539#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59540#L715-36 assume 1 == ~t10_pc~0; 59687#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59498#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63461#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63460#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 63459#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63458#L734-36 assume !(1 == ~t11_pc~0); 63456#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 58966#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58967#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58578#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58579#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59605#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 60035#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63451#L1218-3 assume !(1 == ~T2_E~0); 63450#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59763#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59184#L1233-3 assume !(1 == ~T5_E~0); 59185#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 63448#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60006#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60007#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60009#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60010#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 63445#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59993#L1273-3 assume !(1 == ~E_2~0); 59994#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60141#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63443#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63442#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63441#L1298-3 assume !(1 == ~E_7~0); 63440#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 63439#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59175#L1313-3 assume !(1 == ~E_10~0); 59176#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58983#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 58984#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 58924#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 59157#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 59158#L1663 assume !(0 == start_simulation_~tmp~3#1); 58818#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 59577#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 58771#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 58655#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 58656#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 58717#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59046#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 59521#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 59065#L1644-2 [2024-11-20 22:59:13,830 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:13,830 INFO L85 PathProgramCache]: Analyzing trace with hash 919650235, now seen corresponding path program 1 times [2024-11-20 22:59:13,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:13,830 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632256135] [2024-11-20 22:59:13,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:13,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:13,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:13,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:13,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:13,871 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1632256135] [2024-11-20 22:59:13,871 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1632256135] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:13,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:13,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-20 22:59:13,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380307911] [2024-11-20 22:59:13,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:13,872 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:13,872 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:13,872 INFO L85 PathProgramCache]: Analyzing trace with hash -1917472835, now seen corresponding path program 1 times [2024-11-20 22:59:13,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:13,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691641301] [2024-11-20 22:59:13,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:13,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:13,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:13,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:13,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:13,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [691641301] [2024-11-20 22:59:13,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [691641301] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:13,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:13,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:13,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165285277] [2024-11-20 22:59:13,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:13,908 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:13,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:13,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:13,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:13,909 INFO L87 Difference]: Start difference. First operand 5246 states and 7498 transitions. cyclomatic complexity: 2256 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:14,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:14,015 INFO L93 Difference]: Finished difference Result 9941 states and 14145 transitions. [2024-11-20 22:59:14,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9941 states and 14145 transitions. [2024-11-20 22:59:14,056 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9772 [2024-11-20 22:59:14,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9941 states to 9941 states and 14145 transitions. [2024-11-20 22:59:14,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9941 [2024-11-20 22:59:14,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9941 [2024-11-20 22:59:14,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9941 states and 14145 transitions. [2024-11-20 22:59:14,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:14,099 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9941 states and 14145 transitions. [2024-11-20 22:59:14,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9941 states and 14145 transitions. [2024-11-20 22:59:14,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9941 to 9933. [2024-11-20 22:59:14,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9933 states, 9933 states have (on average 1.4232356790496326) internal successors, (14137), 9932 states have internal predecessors, (14137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:14,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9933 states to 9933 states and 14137 transitions. [2024-11-20 22:59:14,222 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9933 states and 14137 transitions. [2024-11-20 22:59:14,223 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:14,223 INFO L425 stractBuchiCegarLoop]: Abstraction has 9933 states and 14137 transitions. [2024-11-20 22:59:14,223 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-20 22:59:14,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9933 states and 14137 transitions. [2024-11-20 22:59:14,329 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9764 [2024-11-20 22:59:14,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:14,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:14,331 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:14,331 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:14,331 INFO L745 eck$LassoCheckResult]: Stem: 74194#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 74195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 75238#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75239#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74650#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 74651#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74519#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74412#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74137#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73790#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 73791#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 73835#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 73836#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 74789#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 74790#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 74842#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 74235#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74236#L1090 assume !(0 == ~M_E~0); 74284#L1090-2 assume !(0 == ~T1_E~0); 74285#L1095-1 assume !(0 == ~T2_E~0); 74994#L1100-1 assume !(0 == ~T3_E~0); 74995#L1105-1 assume !(0 == ~T4_E~0); 74058#L1110-1 assume !(0 == ~T5_E~0); 74059#L1115-1 assume !(0 == ~T6_E~0); 74450#L1120-1 assume !(0 == ~T7_E~0); 74761#L1125-1 assume !(0 == ~T8_E~0); 75339#L1130-1 assume !(0 == ~T9_E~0); 75018#L1135-1 assume !(0 == ~T10_E~0); 74240#L1140-1 assume !(0 == ~T11_E~0); 74241#L1145-1 assume !(0 == ~E_1~0); 74945#L1150-1 assume !(0 == ~E_2~0); 74426#L1155-1 assume !(0 == ~E_3~0); 74427#L1160-1 assume !(0 == ~E_4~0); 74524#L1165-1 assume !(0 == ~E_5~0); 74525#L1170-1 assume !(0 == ~E_6~0); 75218#L1175-1 assume !(0 == ~E_7~0); 74607#L1180-1 assume !(0 == ~E_8~0); 74608#L1185-1 assume !(0 == ~E_9~0); 74237#L1190-1 assume !(0 == ~E_10~0); 74238#L1195-1 assume !(0 == ~E_11~0); 74623#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74445#L525 assume !(1 == ~m_pc~0); 73879#L525-2 is_master_triggered_~__retres1~0#1 := 0; 73880#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75103#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75076#L1350 assume !(0 != activate_threads_~tmp~1#1); 74227#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74228#L544 assume !(1 == ~t1_pc~0); 74446#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74447#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73858#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 73859#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 74080#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74729#L563 assume !(1 == ~t2_pc~0); 74931#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 73901#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73902#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 74309#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 74310#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74814#L582 assume !(1 == ~t3_pc~0); 74944#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 75299#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73782#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73783#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 73966#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73967#L601 assume !(1 == ~t4_pc~0); 74959#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74451#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73980#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73981#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 74953#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75290#L620 assume !(1 == ~t5_pc~0); 74775#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 74776#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74833#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75109#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 75308#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75309#L639 assume !(1 == ~t6_pc~0); 74759#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 74347#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74348#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74397#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 74456#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74457#L658 assume !(1 == ~t7_pc~0); 74674#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 74675#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75316#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74888#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 74230#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 74231#L677 assume 1 == ~t8_pc~0; 74463#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 74046#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74047#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 74302#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 74303#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75064#L696 assume !(1 == ~t9_pc~0); 74745#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 74746#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74509#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 74510#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 74768#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74999#L715 assume 1 == ~t10_pc~0; 75008#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 74867#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74662#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74663#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 74601#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74034#L734 assume !(1 == ~t11_pc~0); 74035#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 74526#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 74612#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 73780#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 73781#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74834#L1213 assume !(1 == ~M_E~0); 74599#L1213-2 assume !(1 == ~T1_E~0); 74600#L1218-1 assume !(1 == ~T2_E~0); 73813#L1223-1 assume !(1 == ~T3_E~0); 73814#L1228-1 assume !(1 == ~T4_E~0); 74574#L1233-1 assume !(1 == ~T5_E~0); 75310#L1238-1 assume !(1 == ~T6_E~0); 74951#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 74952#L1248-1 assume !(1 == ~T8_E~0); 75004#L1253-1 assume !(1 == ~T9_E~0); 75005#L1258-1 assume !(1 == ~T10_E~0); 74976#L1263-1 assume !(1 == ~T11_E~0); 74977#L1268-1 assume !(1 == ~E_1~0); 74782#L1273-1 assume !(1 == ~E_2~0); 74783#L1278-1 assume !(1 == ~E_3~0); 74343#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 74344#L1288-1 assume !(1 == ~E_5~0); 75116#L1293-1 assume !(1 == ~E_6~0); 75072#L1298-1 assume !(1 == ~E_7~0); 74818#L1303-1 assume !(1 == ~E_8~0); 74353#L1308-1 assume !(1 == ~E_9~0); 74244#L1313-1 assume !(1 == ~E_10~0); 74245#L1318-1 assume !(1 == ~E_11~0); 74255#L1323-1 assume { :end_inline_reset_delta_events } true; 74256#L1644-2 [2024-11-20 22:59:14,332 INFO L747 eck$LassoCheckResult]: Loop: 74256#L1644-2 assume !false; 74885#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74160#L1065-1 assume !false; 74161#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 75306#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 73894#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 74473#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 74358#L906 assume !(0 != eval_~tmp~0#1); 74360#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83640#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83639#L1090-3 assume !(0 == ~M_E~0); 83638#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 83637#L1095-3 assume !(0 == ~T2_E~0); 83636#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 83635#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 83634#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 83633#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 74413#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 74414#L1125-3 assume !(0 == ~T8_E~0); 74949#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 75246#L1135-3 assume !(0 == ~T10_E~0); 74332#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 73844#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 73845#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 73968#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 73969#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 74317#L1165-3 assume !(0 == ~E_5~0); 74318#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 74723#L1175-3 assume !(0 == ~E_7~0); 74229#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 73994#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 73995#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 75230#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 75231#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74553#L525-36 assume 1 == ~m_pc~0; 74555#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 75234#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83459#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 83458#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 74369#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74279#L544-36 assume !(1 == ~t1_pc~0); 74280#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 74854#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74855#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75237#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75215#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75104#L563-36 assume !(1 == ~t2_pc~0); 74079#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 73842#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73843#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75084#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 75312#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75348#L582-36 assume !(1 == ~t3_pc~0); 75349#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 83477#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83475#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83472#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 83470#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83467#L601-36 assume 1 == ~t4_pc~0; 83465#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 83463#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74701#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74702#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75203#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75087#L620-36 assume !(1 == ~t5_pc~0); 75088#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 74932#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74933#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74460#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 74098#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73890#L639-36 assume 1 == ~t6_pc~0; 73891#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73928#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73929#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74148#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 74149#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74764#L658-36 assume !(1 == ~t7_pc~0); 73906#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 73907#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75188#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 73881#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 73882#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 74920#L677-36 assume 1 == ~t8_pc~0; 75122#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 74678#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74815#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 74816#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 74703#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74704#L696-36 assume 1 == ~t9_pc~0; 74595#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 74596#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74536#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 74537#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 74724#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74725#L715-36 assume 1 == ~t10_pc~0; 74879#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 73778#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 73779#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 73756#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 73757#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74143#L734-36 assume 1 == ~t11_pc~0; 74144#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 73857#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 74159#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 73772#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 73773#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74791#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 74420#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 74421#L1218-3 assume !(1 == ~T2_E~0); 74191#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 74192#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 74372#L1233-3 assume !(1 == ~T5_E~0); 74373#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 74647#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 74648#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 75202#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 75204#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 75205#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 75175#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 75176#L1273-3 assume !(1 == ~E_2~0); 75191#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 75193#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 74522#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 74523#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 74366#L1298-3 assume !(1 == ~E_7~0); 74367#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 74880#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 74363#L1313-3 assume !(1 == ~E_10~0); 74364#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 74175#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 74176#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 74116#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 74345#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 74346#L1663 assume !(0 == start_simulation_~tmp~3#1); 74018#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 74762#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 73964#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 73848#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 73849#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 73916#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 74234#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 74706#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 74256#L1644-2 [2024-11-20 22:59:14,332 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:14,332 INFO L85 PathProgramCache]: Analyzing trace with hash -258324326, now seen corresponding path program 1 times [2024-11-20 22:59:14,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:14,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757004945] [2024-11-20 22:59:14,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:14,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:14,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:14,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:14,383 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:14,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757004945] [2024-11-20 22:59:14,384 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757004945] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:14,384 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:14,384 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-20 22:59:14,384 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334070059] [2024-11-20 22:59:14,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:14,385 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:14,385 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:14,385 INFO L85 PathProgramCache]: Analyzing trace with hash -1629541918, now seen corresponding path program 1 times [2024-11-20 22:59:14,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:14,385 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1664841063] [2024-11-20 22:59:14,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:14,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:14,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:14,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:14,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:14,433 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1664841063] [2024-11-20 22:59:14,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1664841063] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:14,434 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:14,434 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:14,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784792603] [2024-11-20 22:59:14,434 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:14,434 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:14,435 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:14,435 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:14,435 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:14,435 INFO L87 Difference]: Start difference. First operand 9933 states and 14137 transitions. cyclomatic complexity: 4212 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:14,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:14,584 INFO L93 Difference]: Finished difference Result 18924 states and 26826 transitions. [2024-11-20 22:59:14,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18924 states and 26826 transitions. [2024-11-20 22:59:14,674 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18720 [2024-11-20 22:59:14,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18924 states to 18924 states and 26826 transitions. [2024-11-20 22:59:14,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18924 [2024-11-20 22:59:14,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18924 [2024-11-20 22:59:14,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18924 states and 26826 transitions. [2024-11-20 22:59:14,776 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:14,776 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18924 states and 26826 transitions. [2024-11-20 22:59:14,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18924 states and 26826 transitions. [2024-11-20 22:59:14,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18924 to 18908. [2024-11-20 22:59:15,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18908 states, 18908 states have (on average 1.4179183414427756) internal successors, (26810), 18907 states have internal predecessors, (26810), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:15,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18908 states to 18908 states and 26810 transitions. [2024-11-20 22:59:15,046 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18908 states and 26810 transitions. [2024-11-20 22:59:15,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:15,047 INFO L425 stractBuchiCegarLoop]: Abstraction has 18908 states and 26810 transitions. [2024-11-20 22:59:15,047 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-20 22:59:15,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18908 states and 26810 transitions. [2024-11-20 22:59:15,098 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18704 [2024-11-20 22:59:15,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:15,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:15,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:15,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:15,100 INFO L745 eck$LassoCheckResult]: Stem: 103059#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 103060#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 104148#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 104149#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103521#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 103522#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 103387#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 103279#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 103003#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102654#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 102655#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 102699#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 102700#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 103668#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 103669#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 103718#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 103101#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 103102#L1090 assume !(0 == ~M_E~0); 103146#L1090-2 assume !(0 == ~T1_E~0); 103147#L1095-1 assume !(0 == ~T2_E~0); 103881#L1100-1 assume !(0 == ~T3_E~0); 103882#L1105-1 assume !(0 == ~T4_E~0); 102924#L1110-1 assume !(0 == ~T5_E~0); 102925#L1115-1 assume !(0 == ~T6_E~0); 103316#L1120-1 assume !(0 == ~T7_E~0); 103642#L1125-1 assume !(0 == ~T8_E~0); 104255#L1130-1 assume !(0 == ~T9_E~0); 103909#L1135-1 assume !(0 == ~T10_E~0); 103107#L1140-1 assume !(0 == ~T11_E~0); 103108#L1145-1 assume !(0 == ~E_1~0); 103832#L1150-1 assume !(0 == ~E_2~0); 103292#L1155-1 assume !(0 == ~E_3~0); 103293#L1160-1 assume !(0 == ~E_4~0); 103392#L1165-1 assume !(0 == ~E_5~0); 103393#L1170-1 assume !(0 == ~E_6~0); 104125#L1175-1 assume !(0 == ~E_7~0); 103479#L1180-1 assume !(0 == ~E_8~0); 103480#L1185-1 assume !(0 == ~E_9~0); 103103#L1190-1 assume !(0 == ~E_10~0); 103104#L1195-1 assume !(0 == ~E_11~0); 103495#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103311#L525 assume !(1 == ~m_pc~0); 102743#L525-2 is_master_triggered_~__retres1~0#1 := 0; 102744#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104004#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 103971#L1350 assume !(0 != activate_threads_~tmp~1#1); 103093#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103094#L544 assume !(1 == ~t1_pc~0); 103314#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 103315#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102722#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 102723#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 102946#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103608#L563 assume !(1 == ~t2_pc~0); 103816#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 102765#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102766#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 103174#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 103175#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103697#L582 assume !(1 == ~t3_pc~0); 103831#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 104209#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102646#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 102647#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 102832#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102833#L601 assume !(1 == ~t4_pc~0); 103846#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 103317#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102846#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102847#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 103841#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104194#L620 assume !(1 == ~t5_pc~0); 103658#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 103659#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103714#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 104010#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 104224#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 104225#L639 assume !(1 == ~t6_pc~0); 103640#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 103215#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103216#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103264#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 103322#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103323#L658 assume !(1 == ~t7_pc~0); 103544#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 103545#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 104232#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 103771#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 103096#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 103097#L677 assume !(1 == ~t8_pc~0); 103118#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 102906#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 102907#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 103169#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 103170#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 103961#L696 assume !(1 == ~t9_pc~0); 103624#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 103625#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 103377#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 103378#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 103647#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 103885#L715 assume 1 == ~t10_pc~0; 103896#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 103752#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 103533#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 103534#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 103472#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 102900#L734 assume !(1 == ~t11_pc~0); 102901#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 103394#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 103482#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 102644#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 102645#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103715#L1213 assume !(1 == ~M_E~0); 103470#L1213-2 assume !(1 == ~T1_E~0); 103471#L1218-1 assume !(1 == ~T2_E~0); 102677#L1223-1 assume !(1 == ~T3_E~0); 102678#L1228-1 assume !(1 == ~T4_E~0); 103443#L1233-1 assume !(1 == ~T5_E~0); 104226#L1238-1 assume !(1 == ~T6_E~0); 103839#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 103840#L1248-1 assume !(1 == ~T8_E~0); 103892#L1253-1 assume !(1 == ~T9_E~0); 103893#L1258-1 assume !(1 == ~T10_E~0); 103863#L1263-1 assume !(1 == ~T11_E~0); 103864#L1268-1 assume !(1 == ~E_1~0); 103665#L1273-1 assume !(1 == ~E_2~0); 103666#L1278-1 assume !(1 == ~E_3~0); 103211#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 103212#L1288-1 assume !(1 == ~E_5~0); 104015#L1293-1 assume !(1 == ~E_6~0); 103966#L1298-1 assume !(1 == ~E_7~0); 103701#L1303-1 assume !(1 == ~E_8~0); 103221#L1308-1 assume !(1 == ~E_9~0); 103111#L1313-1 assume !(1 == ~E_10~0); 103112#L1318-1 assume !(1 == ~E_11~0); 103119#L1323-1 assume { :end_inline_reset_delta_events } true; 103120#L1644-2 [2024-11-20 22:59:15,100 INFO L747 eck$LassoCheckResult]: Loop: 103120#L1644-2 assume !false; 116097#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 116091#L1065-1 assume !false; 116090#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 115311#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 115300#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 115299#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 115294#L906 assume !(0 != eval_~tmp~0#1); 115295#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117318#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 117313#L1090-3 assume !(0 == ~M_E~0); 117307#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 117302#L1095-3 assume !(0 == ~T2_E~0); 117297#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117291#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117284#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 117278#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117271#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 117266#L1125-3 assume !(0 == ~T8_E~0); 117260#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 117254#L1135-3 assume !(0 == ~T10_E~0); 117247#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 117241#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117237#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 117233#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117227#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 117220#L1165-3 assume !(0 == ~E_5~0); 117213#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 117207#L1175-3 assume !(0 == ~E_7~0); 117201#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 117196#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 117190#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 117185#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 117181#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117177#L525-36 assume 1 == ~m_pc~0; 117171#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 117164#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117157#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 117148#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 117142#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117137#L544-36 assume !(1 == ~t1_pc~0); 117132#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 117126#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117120#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 117115#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 117110#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117105#L563-36 assume !(1 == ~t2_pc~0); 117099#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 117093#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117088#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 117081#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117076#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117071#L582-36 assume !(1 == ~t3_pc~0); 117066#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 117061#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117054#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 117049#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 117044#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117040#L601-36 assume !(1 == ~t4_pc~0); 117035#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 117029#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117025#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117020#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 117016#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117012#L620-36 assume !(1 == ~t5_pc~0); 117008#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 117004#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117000#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 116995#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 116990#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116984#L639-36 assume 1 == ~t6_pc~0; 116977#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 116970#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116963#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 116959#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 116955#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 116950#L658-36 assume !(1 == ~t7_pc~0); 116944#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 116940#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 116934#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 116928#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 116922#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 116915#L677-36 assume !(1 == ~t8_pc~0); 116909#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 116904#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 116898#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 116892#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 116887#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 116883#L696-36 assume 1 == ~t9_pc~0; 116879#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 116874#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 116870#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 116864#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 116859#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 116854#L715-36 assume 1 == ~t10_pc~0; 116849#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 116845#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 116841#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 116836#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 116830#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 116824#L734-36 assume !(1 == ~t11_pc~0); 116817#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 116811#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 116807#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 116802#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 116797#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116793#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 116789#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116785#L1218-3 assume !(1 == ~T2_E~0); 116781#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 116777#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116772#L1233-3 assume !(1 == ~T5_E~0); 116769#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 116765#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 116764#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 116763#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 116762#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 116761#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 116760#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 116759#L1273-3 assume !(1 == ~E_2~0); 116758#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 116757#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116756#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116755#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 116754#L1298-3 assume !(1 == ~E_7~0); 116753#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 116752#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 116751#L1313-3 assume !(1 == ~E_10~0); 116750#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 116749#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 116731#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 116724#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 116722#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 116549#L1663 assume !(0 == start_simulation_~tmp~3#1); 116546#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 116539#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 116529#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 116525#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 116523#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 116521#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 116128#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 116117#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 103120#L1644-2 [2024-11-20 22:59:15,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:15,101 INFO L85 PathProgramCache]: Analyzing trace with hash 1174510393, now seen corresponding path program 1 times [2024-11-20 22:59:15,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:15,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317428213] [2024-11-20 22:59:15,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:15,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:15,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:15,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:15,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:15,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317428213] [2024-11-20 22:59:15,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317428213] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:15,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:15,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-20 22:59:15,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137283991] [2024-11-20 22:59:15,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:15,151 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:15,151 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:15,151 INFO L85 PathProgramCache]: Analyzing trace with hash -1851479297, now seen corresponding path program 1 times [2024-11-20 22:59:15,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:15,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228572534] [2024-11-20 22:59:15,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:15,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:15,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:15,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:15,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:15,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228572534] [2024-11-20 22:59:15,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [228572534] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:15,185 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:15,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:15,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260687569] [2024-11-20 22:59:15,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:15,186 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:15,186 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:15,186 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-20 22:59:15,186 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-20 22:59:15,186 INFO L87 Difference]: Start difference. First operand 18908 states and 26810 transitions. cyclomatic complexity: 7918 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:15,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:15,543 INFO L93 Difference]: Finished difference Result 19439 states and 27341 transitions. [2024-11-20 22:59:15,544 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19439 states and 27341 transitions. [2024-11-20 22:59:15,609 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19232 [2024-11-20 22:59:15,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19439 states to 19439 states and 27341 transitions. [2024-11-20 22:59:15,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19439 [2024-11-20 22:59:15,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19439 [2024-11-20 22:59:15,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19439 states and 27341 transitions. [2024-11-20 22:59:15,682 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:15,682 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19439 states and 27341 transitions. [2024-11-20 22:59:15,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19439 states and 27341 transitions. [2024-11-20 22:59:15,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19439 to 19439. [2024-11-20 22:59:15,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19439 states, 19439 states have (on average 1.406502392098359) internal successors, (27341), 19438 states have internal predecessors, (27341), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:15,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19439 states to 19439 states and 27341 transitions. [2024-11-20 22:59:15,879 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19439 states and 27341 transitions. [2024-11-20 22:59:15,879 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-20 22:59:15,879 INFO L425 stractBuchiCegarLoop]: Abstraction has 19439 states and 27341 transitions. [2024-11-20 22:59:15,879 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-20 22:59:15,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19439 states and 27341 transitions. [2024-11-20 22:59:15,927 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19232 [2024-11-20 22:59:15,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:15,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:15,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:15,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:15,929 INFO L745 eck$LassoCheckResult]: Stem: 141420#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 141421#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 142528#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 142529#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 141894#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 141895#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 141757#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 141648#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 141360#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 141010#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 141011#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 141055#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 141056#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 142042#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 142043#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 142091#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 141465#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 141466#L1090 assume !(0 == ~M_E~0); 141512#L1090-2 assume !(0 == ~T1_E~0); 141513#L1095-1 assume !(0 == ~T2_E~0); 142255#L1100-1 assume !(0 == ~T3_E~0); 142256#L1105-1 assume !(0 == ~T4_E~0); 141279#L1110-1 assume !(0 == ~T5_E~0); 141280#L1115-1 assume !(0 == ~T6_E~0); 141686#L1120-1 assume !(0 == ~T7_E~0); 142015#L1125-1 assume !(0 == ~T8_E~0); 142657#L1130-1 assume !(0 == ~T9_E~0); 142280#L1135-1 assume !(0 == ~T10_E~0); 141471#L1140-1 assume !(0 == ~T11_E~0); 141472#L1145-1 assume !(0 == ~E_1~0); 142206#L1150-1 assume !(0 == ~E_2~0); 141662#L1155-1 assume !(0 == ~E_3~0); 141663#L1160-1 assume !(0 == ~E_4~0); 141764#L1165-1 assume !(0 == ~E_5~0); 141765#L1170-1 assume !(0 == ~E_6~0); 142506#L1175-1 assume !(0 == ~E_7~0); 141850#L1180-1 assume !(0 == ~E_8~0); 141851#L1185-1 assume !(0 == ~E_9~0); 141467#L1190-1 assume !(0 == ~E_10~0); 141468#L1195-1 assume !(0 == ~E_11~0); 141866#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 141683#L525 assume !(1 == ~m_pc~0); 141098#L525-2 is_master_triggered_~__retres1~0#1 := 0; 141099#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 142471#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 142342#L1350 assume !(0 != activate_threads_~tmp~1#1); 141457#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 141458#L544 assume !(1 == ~t1_pc~0); 141684#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 141685#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 141078#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 141079#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 141303#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 141982#L563 assume !(1 == ~t2_pc~0); 142190#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 141120#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 141121#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 141542#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 141543#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 142070#L582 assume !(1 == ~t3_pc~0); 142205#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 142594#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 141002#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 141003#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 141185#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141186#L601 assume !(1 == ~t4_pc~0); 142220#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 141687#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 141199#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 141200#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 142215#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 142575#L620 assume !(1 == ~t5_pc~0); 142029#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 142030#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 142088#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 142381#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 142613#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 142614#L639 assume !(1 == ~t6_pc~0); 142013#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 141580#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 141581#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 141634#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 141693#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 141694#L658 assume !(1 == ~t7_pc~0); 141922#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 141923#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 142626#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 142145#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 141460#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 141461#L677 assume !(1 == ~t8_pc~0); 141484#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 141260#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 141261#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 141535#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 141536#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 142332#L696 assume !(1 == ~t9_pc~0); 141996#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 141997#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 141747#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 141748#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 142020#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 142259#L715 assume 1 == ~t10_pc~0; 142269#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 142123#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 141908#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 141909#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 141843#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 141254#L734 assume !(1 == ~t11_pc~0); 141255#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 141766#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 141855#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 141000#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 141001#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 142089#L1213 assume !(1 == ~M_E~0); 141841#L1213-2 assume !(1 == ~T1_E~0); 141842#L1218-1 assume !(1 == ~T2_E~0); 141033#L1223-1 assume !(1 == ~T3_E~0); 141034#L1228-1 assume !(1 == ~T4_E~0); 141816#L1233-1 assume !(1 == ~T5_E~0); 142615#L1238-1 assume !(1 == ~T6_E~0); 142213#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 142214#L1248-1 assume !(1 == ~T8_E~0); 142265#L1253-1 assume !(1 == ~T9_E~0); 142266#L1258-1 assume !(1 == ~T10_E~0); 142237#L1263-1 assume !(1 == ~T11_E~0); 142238#L1268-1 assume !(1 == ~E_1~0); 142037#L1273-1 assume !(1 == ~E_2~0); 142038#L1278-1 assume !(1 == ~E_3~0); 141576#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 141577#L1288-1 assume !(1 == ~E_5~0); 142386#L1293-1 assume !(1 == ~E_6~0); 142337#L1298-1 assume !(1 == ~E_7~0); 142074#L1303-1 assume !(1 == ~E_8~0); 141588#L1308-1 assume !(1 == ~E_9~0); 141475#L1313-1 assume !(1 == ~E_10~0); 141476#L1318-1 assume !(1 == ~E_11~0); 141485#L1323-1 assume { :end_inline_reset_delta_events } true; 141486#L1644-2 [2024-11-20 22:59:15,929 INFO L747 eck$LassoCheckResult]: Loop: 141486#L1644-2 assume !false; 147219#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 147214#L1065-1 assume !false; 147212#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 147204#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 147193#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 147191#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 147188#L906 assume !(0 != eval_~tmp~0#1); 147189#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 148866#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 148865#L1090-3 assume !(0 == ~M_E~0); 148864#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 148862#L1095-3 assume !(0 == ~T2_E~0); 148861#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 148860#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 148859#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 148855#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 148853#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 148851#L1125-3 assume !(0 == ~T8_E~0); 148849#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 148846#L1135-3 assume !(0 == ~T10_E~0); 148844#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 148842#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 148839#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 148837#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 148835#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 148833#L1165-3 assume !(0 == ~E_5~0); 148831#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 148829#L1175-3 assume !(0 == ~E_7~0); 148826#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 148824#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 148822#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 148820#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 148818#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 148816#L525-36 assume 1 == ~m_pc~0; 148814#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 148815#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148867#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 148805#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 148803#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 148801#L544-36 assume !(1 == ~t1_pc~0); 148798#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 148796#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 148794#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 148792#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 148790#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 148788#L563-36 assume !(1 == ~t2_pc~0); 148784#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 148782#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 148780#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 148778#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 148776#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148774#L582-36 assume !(1 == ~t3_pc~0); 148771#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 148769#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 148767#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 148765#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 148763#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 148760#L601-36 assume 1 == ~t4_pc~0; 148758#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 148755#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 148753#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 148751#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 148749#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 148747#L620-36 assume !(1 == ~t5_pc~0); 148745#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 148743#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 148741#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 148739#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 148737#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 148733#L639-36 assume 1 == ~t6_pc~0; 148730#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 148728#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 148726#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 148723#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 148721#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 148719#L658-36 assume !(1 == ~t7_pc~0); 148717#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 148716#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 148715#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 148714#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 148713#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 148712#L677-36 assume !(1 == ~t8_pc~0); 148711#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 148710#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 148709#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 148707#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 148706#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 148705#L696-36 assume !(1 == ~t9_pc~0); 148704#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 154007#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 153999#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 148533#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 148530#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 148528#L715-36 assume !(1 == ~t10_pc~0); 148526#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 148523#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 148521#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 148519#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 148517#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 148514#L734-36 assume 1 == ~t11_pc~0; 148512#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 148509#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 148507#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 148505#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 148503#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 148500#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 148498#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 148496#L1218-3 assume !(1 == ~T2_E~0); 148494#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 148492#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 148490#L1233-3 assume !(1 == ~T5_E~0); 148488#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 148486#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 148484#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 148482#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 148480#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 148476#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 148474#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 148472#L1273-3 assume !(1 == ~E_2~0); 148470#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 148467#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 148465#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 148463#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 148460#L1298-3 assume !(1 == ~E_7~0); 148458#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 148456#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 148454#L1313-3 assume !(1 == ~E_10~0); 148452#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 148450#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 148431#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 148424#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 148421#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 148282#L1663 assume !(0 == start_simulation_~tmp~3#1); 148280#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 147248#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 147235#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 147231#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 147227#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 147226#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 147225#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 147224#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 141486#L1644-2 [2024-11-20 22:59:15,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:15,930 INFO L85 PathProgramCache]: Analyzing trace with hash 145151095, now seen corresponding path program 1 times [2024-11-20 22:59:15,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:15,930 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820643874] [2024-11-20 22:59:15,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:15,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:15,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:15,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:15,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:15,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820643874] [2024-11-20 22:59:15,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1820643874] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:15,966 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:15,967 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-20 22:59:15,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221830282] [2024-11-20 22:59:15,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:15,967 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:15,967 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:15,967 INFO L85 PathProgramCache]: Analyzing trace with hash 1813496893, now seen corresponding path program 1 times [2024-11-20 22:59:15,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:15,968 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178786179] [2024-11-20 22:59:15,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:15,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:15,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:15,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:16,000 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:16,000 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178786179] [2024-11-20 22:59:16,000 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1178786179] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:16,000 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:16,000 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:16,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [622094363] [2024-11-20 22:59:16,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:16,001 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:16,001 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:16,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:16,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:16,002 INFO L87 Difference]: Start difference. First operand 19439 states and 27341 transitions. cyclomatic complexity: 7918 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:16,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:16,354 INFO L93 Difference]: Finished difference Result 37110 states and 52010 transitions. [2024-11-20 22:59:16,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37110 states and 52010 transitions. [2024-11-20 22:59:16,471 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36816 [2024-11-20 22:59:16,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37110 states to 37110 states and 52010 transitions. [2024-11-20 22:59:16,557 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37110 [2024-11-20 22:59:16,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37110 [2024-11-20 22:59:16,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37110 states and 52010 transitions. [2024-11-20 22:59:16,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:16,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37110 states and 52010 transitions. [2024-11-20 22:59:16,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37110 states and 52010 transitions. [2024-11-20 22:59:16,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37110 to 37078. [2024-11-20 22:59:16,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.4018555477641728) internal successors, (51978), 37077 states have internal predecessors, (51978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:16,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 51978 transitions. [2024-11-20 22:59:16,994 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51978 transitions. [2024-11-20 22:59:16,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:16,995 INFO L425 stractBuchiCegarLoop]: Abstraction has 37078 states and 51978 transitions. [2024-11-20 22:59:16,995 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-20 22:59:16,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 51978 transitions. [2024-11-20 22:59:17,284 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2024-11-20 22:59:17,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:17,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:17,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:17,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:17,287 INFO L745 eck$LassoCheckResult]: Stem: 197969#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 197970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 199041#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 199042#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 198432#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 198433#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 198301#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 198191#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 197913#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 197566#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 197567#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 197612#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 197613#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 198577#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 198578#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 198625#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 198013#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 198014#L1090 assume !(0 == ~M_E~0); 198057#L1090-2 assume !(0 == ~T1_E~0); 198058#L1095-1 assume !(0 == ~T2_E~0); 198790#L1100-1 assume !(0 == ~T3_E~0); 198791#L1105-1 assume !(0 == ~T4_E~0); 197833#L1110-1 assume !(0 == ~T5_E~0); 197834#L1115-1 assume !(0 == ~T6_E~0); 198228#L1120-1 assume !(0 == ~T7_E~0); 198551#L1125-1 assume !(0 == ~T8_E~0); 199143#L1130-1 assume !(0 == ~T9_E~0); 198811#L1135-1 assume !(0 == ~T10_E~0); 198019#L1140-1 assume !(0 == ~T11_E~0); 198020#L1145-1 assume !(0 == ~E_1~0); 198737#L1150-1 assume !(0 == ~E_2~0); 198206#L1155-1 assume !(0 == ~E_3~0); 198207#L1160-1 assume !(0 == ~E_4~0); 198306#L1165-1 assume !(0 == ~E_5~0); 198307#L1170-1 assume !(0 == ~E_6~0); 199019#L1175-1 assume !(0 == ~E_7~0); 198391#L1180-1 assume !(0 == ~E_8~0); 198392#L1185-1 assume !(0 == ~E_9~0); 198015#L1190-1 assume !(0 == ~E_10~0); 198016#L1195-1 assume !(0 == ~E_11~0); 198407#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 198220#L525 assume !(1 == ~m_pc~0); 197656#L525-2 is_master_triggered_~__retres1~0#1 := 0; 197657#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 198982#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 198871#L1350 assume !(0 != activate_threads_~tmp~1#1); 198005#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 198006#L544 assume !(1 == ~t1_pc~0); 198226#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 198227#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 197631#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 197632#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 197858#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 198516#L563 assume !(1 == ~t2_pc~0); 198723#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 197675#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 197676#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 198083#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 198084#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 198603#L582 assume !(1 == ~t3_pc~0); 198736#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 199091#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 197558#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 197559#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 197741#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 197742#L601 assume !(1 == ~t4_pc~0); 198754#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 198229#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 197753#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 197754#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 198747#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 199082#L620 assume !(1 == ~t5_pc~0); 198567#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 198568#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 198622#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 198905#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 199100#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 199101#L639 assume !(1 == ~t6_pc~0); 198549#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 198125#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198126#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 198176#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 198235#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 198236#L658 assume !(1 == ~t7_pc~0); 198456#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 198457#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 199113#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 198677#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 198008#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 198009#L677 assume !(1 == ~t8_pc~0); 198030#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 197816#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 197817#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 198079#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 198080#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 198862#L696 assume !(1 == ~t9_pc~0); 198529#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 198530#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 198289#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 198290#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 198556#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 198795#L715 assume !(1 == ~t10_pc~0); 199060#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 198655#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 198444#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 198445#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 198385#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 197810#L734 assume !(1 == ~t11_pc~0); 197811#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 198308#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 198394#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 197554#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 197555#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198623#L1213 assume !(1 == ~M_E~0); 198382#L1213-2 assume !(1 == ~T1_E~0); 198383#L1218-1 assume !(1 == ~T2_E~0); 197589#L1223-1 assume !(1 == ~T3_E~0); 197590#L1228-1 assume !(1 == ~T4_E~0); 198355#L1233-1 assume !(1 == ~T5_E~0); 199102#L1238-1 assume !(1 == ~T6_E~0); 198745#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 198746#L1248-1 assume !(1 == ~T8_E~0); 198799#L1253-1 assume !(1 == ~T9_E~0); 198800#L1258-1 assume !(1 == ~T10_E~0); 198773#L1263-1 assume !(1 == ~T11_E~0); 198774#L1268-1 assume !(1 == ~E_1~0); 198574#L1273-1 assume !(1 == ~E_2~0); 198575#L1278-1 assume !(1 == ~E_3~0); 198123#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 198124#L1288-1 assume !(1 == ~E_5~0); 198910#L1293-1 assume !(1 == ~E_6~0); 198866#L1298-1 assume !(1 == ~E_7~0); 198607#L1303-1 assume !(1 == ~E_8~0); 198133#L1308-1 assume !(1 == ~E_9~0); 198023#L1313-1 assume !(1 == ~E_10~0); 198024#L1318-1 assume !(1 == ~E_11~0); 198031#L1323-1 assume { :end_inline_reset_delta_events } true; 198032#L1644-2 [2024-11-20 22:59:17,287 INFO L747 eck$LassoCheckResult]: Loop: 198032#L1644-2 assume !false; 221137#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 221132#L1065-1 assume !false; 221129#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 221118#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 221107#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 221104#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 221102#L906 assume !(0 != eval_~tmp~0#1); 221103#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 221513#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 221511#L1090-3 assume !(0 == ~M_E~0); 221508#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 221506#L1095-3 assume !(0 == ~T2_E~0); 221504#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 221502#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 221500#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 221499#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 221495#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 221493#L1125-3 assume !(0 == ~T8_E~0); 221491#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 221488#L1135-3 assume !(0 == ~T10_E~0); 221487#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 221486#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 221483#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 221479#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 221478#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 221477#L1165-3 assume !(0 == ~E_5~0); 221475#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 221474#L1175-3 assume !(0 == ~E_7~0); 221473#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 221472#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 221471#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 221470#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 221469#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221468#L525-36 assume !(1 == ~m_pc~0); 221467#L525-38 is_master_triggered_~__retres1~0#1 := 0; 221465#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221462#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 221458#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 221454#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 221451#L544-36 assume !(1 == ~t1_pc~0); 221448#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 221446#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221444#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 221442#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 221440#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 221438#L563-36 assume !(1 == ~t2_pc~0); 221435#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 221433#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 221431#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 221428#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 221426#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221424#L582-36 assume !(1 == ~t3_pc~0); 221422#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 221420#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 221418#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 221416#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 221414#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221412#L601-36 assume 1 == ~t4_pc~0; 221410#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 221407#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221405#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 221402#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 221400#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221398#L620-36 assume !(1 == ~t5_pc~0); 221396#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 221394#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221392#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 221390#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 221388#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 221386#L639-36 assume 1 == ~t6_pc~0; 221383#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 221381#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 221379#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 221376#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 221374#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 221372#L658-36 assume !(1 == ~t7_pc~0); 221369#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 221367#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221363#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 221360#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 221356#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 221352#L677-36 assume !(1 == ~t8_pc~0); 221348#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 221344#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 221341#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 221338#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 221335#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 221332#L696-36 assume !(1 == ~t9_pc~0); 221329#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 221325#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 221321#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 221316#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 221310#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 221306#L715-36 assume !(1 == ~t10_pc~0); 221302#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 221299#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 221296#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 221293#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 221290#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 221287#L734-36 assume !(1 == ~t11_pc~0); 221283#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 221280#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 221277#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 221273#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 221269#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221266#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 221263#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 221260#L1218-3 assume !(1 == ~T2_E~0); 221257#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 221254#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 221251#L1233-3 assume !(1 == ~T5_E~0); 221248#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 221245#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 221242#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 221239#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 221236#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 221232#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 221229#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 221226#L1273-3 assume !(1 == ~E_2~0); 221223#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 221220#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 221216#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 221213#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 221210#L1298-3 assume !(1 == ~E_7~0); 221207#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 221204#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 221201#L1313-3 assume !(1 == ~E_10~0); 221198#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 221196#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 221185#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 221177#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 221172#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 221168#L1663 assume !(0 == start_simulation_~tmp~3#1); 221166#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 221162#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 221150#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 221148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 221146#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 221144#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 221142#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 221140#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 198032#L1644-2 [2024-11-20 22:59:17,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:17,288 INFO L85 PathProgramCache]: Analyzing trace with hash -1619665514, now seen corresponding path program 1 times [2024-11-20 22:59:17,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:17,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102156008] [2024-11-20 22:59:17,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:17,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:17,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:17,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:17,338 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:17,340 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102156008] [2024-11-20 22:59:17,340 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102156008] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:17,340 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:17,340 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:17,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1975433688] [2024-11-20 22:59:17,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:17,340 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:17,340 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:17,340 INFO L85 PathProgramCache]: Analyzing trace with hash 600518137, now seen corresponding path program 1 times [2024-11-20 22:59:17,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:17,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627033946] [2024-11-20 22:59:17,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:17,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:17,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:17,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:17,375 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:17,375 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627033946] [2024-11-20 22:59:17,375 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627033946] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:17,375 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:17,375 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:17,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [432701459] [2024-11-20 22:59:17,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:17,376 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:17,376 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:17,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-20 22:59:17,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-20 22:59:17,376 INFO L87 Difference]: Start difference. First operand 37078 states and 51978 transitions. cyclomatic complexity: 14932 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:17,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:17,821 INFO L93 Difference]: Finished difference Result 77699 states and 108961 transitions. [2024-11-20 22:59:17,821 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77699 states and 108961 transitions. [2024-11-20 22:59:18,367 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 77136 [2024-11-20 22:59:18,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77699 states to 77699 states and 108961 transitions. [2024-11-20 22:59:18,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77699 [2024-11-20 22:59:18,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77699 [2024-11-20 22:59:18,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77699 states and 108961 transitions. [2024-11-20 22:59:18,826 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:18,826 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77699 states and 108961 transitions. [2024-11-20 22:59:18,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77699 states and 108961 transitions. [2024-11-20 22:59:19,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77699 to 40755. [2024-11-20 22:59:19,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40755 states, 40755 states have (on average 1.404367562262299) internal successors, (57235), 40754 states have internal predecessors, (57235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:19,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40755 states to 40755 states and 57235 transitions. [2024-11-20 22:59:19,734 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40755 states and 57235 transitions. [2024-11-20 22:59:19,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-20 22:59:19,739 INFO L425 stractBuchiCegarLoop]: Abstraction has 40755 states and 57235 transitions. [2024-11-20 22:59:19,739 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-20 22:59:19,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40755 states and 57235 transitions. [2024-11-20 22:59:19,875 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40352 [2024-11-20 22:59:19,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:19,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:19,878 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:19,878 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:19,878 INFO L745 eck$LassoCheckResult]: Stem: 312763#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 312764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 313869#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 313870#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 313228#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 313229#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 313099#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 312990#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 312703#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 312353#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 312354#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 312398#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 312399#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 313387#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 313388#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 313437#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 312806#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 312807#L1090 assume !(0 == ~M_E~0); 312857#L1090-2 assume !(0 == ~T1_E~0); 312858#L1095-1 assume !(0 == ~T2_E~0); 313610#L1100-1 assume !(0 == ~T3_E~0); 313611#L1105-1 assume !(0 == ~T4_E~0); 312621#L1110-1 assume !(0 == ~T5_E~0); 312622#L1115-1 assume !(0 == ~T6_E~0); 313032#L1120-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 313354#L1125-1 assume !(0 == ~T8_E~0); 313995#L1130-1 assume !(0 == ~T9_E~0); 313631#L1135-1 assume !(0 == ~T10_E~0); 312812#L1140-1 assume !(0 == ~T11_E~0); 312813#L1145-1 assume !(0 == ~E_1~0); 314108#L1150-1 assume !(0 == ~E_2~0); 313007#L1155-1 assume !(0 == ~E_3~0); 313008#L1160-1 assume !(0 == ~E_4~0); 314107#L1165-1 assume !(0 == ~E_5~0); 313844#L1170-1 assume !(0 == ~E_6~0); 313845#L1175-1 assume !(0 == ~E_7~0); 314106#L1180-1 assume !(0 == ~E_8~0); 314105#L1185-1 assume !(0 == ~E_9~0); 314104#L1190-1 assume !(0 == ~E_10~0); 314103#L1195-1 assume !(0 == ~E_11~0); 313813#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 313814#L525 assume !(1 == ~m_pc~0); 314101#L525-2 is_master_triggered_~__retres1~0#1 := 0; 314099#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 314097#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 314095#L1350 assume !(0 != activate_threads_~tmp~1#1); 314094#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 313256#L544 assume !(1 == ~t1_pc~0); 313257#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 313554#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 312421#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 312422#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 313316#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 313317#L563 assume !(1 == ~t2_pc~0); 313539#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 313540#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 313003#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 313004#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 313410#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 313411#L582 assume !(1 == ~t3_pc~0); 313996#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 313997#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 314089#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 313856#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 312529#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 312530#L601 assume !(1 == ~t4_pc~0); 314086#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 314085#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 314084#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 314083#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 314022#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 314023#L620 assume !(1 == ~t5_pc~0); 313372#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 313373#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 314082#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 314053#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 314054#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 313999#L639 assume !(1 == ~t6_pc~0); 314000#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 312922#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 312923#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 313950#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 313036#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 313037#L658 assume !(1 == ~t7_pc~0); 313353#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 313965#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 313966#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 313488#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 312801#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 312802#L677 assume !(1 == ~t8_pc~0); 313044#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 312606#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 312607#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 313649#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 314075#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 314074#L696 assume !(1 == ~t9_pc~0); 313335#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 313336#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 314111#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 313364#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 313365#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 313614#L715 assume !(1 == ~t10_pc~0); 313982#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 313983#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 313241#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 313242#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 313178#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 313179#L734 assume !(1 == ~t11_pc~0); 314063#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 314062#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 313501#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 313502#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 313431#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 313432#L1213 assume !(1 == ~M_E~0); 314061#L1213-2 assume !(1 == ~T1_E~0); 314060#L1218-1 assume !(1 == ~T2_E~0); 314059#L1223-1 assume !(1 == ~T3_E~0); 314058#L1228-1 assume !(1 == ~T4_E~0); 313955#L1233-1 assume !(1 == ~T5_E~0); 313956#L1238-1 assume !(1 == ~T6_E~0); 314057#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 313567#L1248-1 assume !(1 == ~T8_E~0); 313617#L1253-1 assume !(1 == ~T9_E~0); 313618#L1258-1 assume !(1 == ~T10_E~0); 313591#L1263-1 assume !(1 == ~T11_E~0); 313592#L1268-1 assume !(1 == ~E_1~0); 313380#L1273-1 assume !(1 == ~E_2~0); 313381#L1278-1 assume !(1 == ~E_3~0); 312918#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 312919#L1288-1 assume !(1 == ~E_5~0); 313730#L1293-1 assume !(1 == ~E_6~0); 313685#L1298-1 assume !(1 == ~E_7~0); 313415#L1303-1 assume !(1 == ~E_8~0); 312929#L1308-1 assume !(1 == ~E_9~0); 312816#L1313-1 assume !(1 == ~E_10~0); 312817#L1318-1 assume !(1 == ~E_11~0); 312829#L1323-1 assume { :end_inline_reset_delta_events } true; 312830#L1644-2 [2024-11-20 22:59:19,879 INFO L747 eck$LassoCheckResult]: Loop: 312830#L1644-2 assume !false; 325752#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 325747#L1065-1 assume !false; 325745#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 325738#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 325722#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 325717#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 325712#L906 assume !(0 != eval_~tmp~0#1); 325713#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 326095#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 326094#L1090-3 assume !(0 == ~M_E~0); 326093#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 326092#L1095-3 assume !(0 == ~T2_E~0); 326091#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 326090#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 326089#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 326088#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 326086#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 326085#L1125-3 assume !(0 == ~T8_E~0); 326084#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 326083#L1135-3 assume !(0 == ~T10_E~0); 326082#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 326081#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 326080#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 326079#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 326078#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 326077#L1165-3 assume !(0 == ~E_5~0); 326076#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 326075#L1175-3 assume !(0 == ~E_7~0); 326074#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 326073#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 326072#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 326071#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 326070#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 326069#L525-36 assume !(1 == ~m_pc~0); 326068#L525-38 is_master_triggered_~__retres1~0#1 := 0; 326066#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 326064#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 326062#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 326060#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 326059#L544-36 assume !(1 == ~t1_pc~0); 326058#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 326057#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 326056#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 326055#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 326054#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 326053#L563-36 assume 1 == ~t2_pc~0; 326052#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 326050#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 326049#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 326048#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 326047#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326046#L582-36 assume !(1 == ~t3_pc~0); 326045#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 326044#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 326043#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 326042#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 326041#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 326040#L601-36 assume !(1 == ~t4_pc~0); 326038#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 326037#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 326036#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 326035#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 326034#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 326033#L620-36 assume !(1 == ~t5_pc~0); 326032#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 326031#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 326030#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 326029#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 326028#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 326027#L639-36 assume 1 == ~t6_pc~0; 326025#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 326024#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 326023#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 326022#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 326021#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 326020#L658-36 assume !(1 == ~t7_pc~0); 326018#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 326017#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 326016#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 326015#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 326014#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 326013#L677-36 assume !(1 == ~t8_pc~0); 326012#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 326011#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 326010#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 326009#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 326008#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 326007#L696-36 assume 1 == ~t9_pc~0; 326005#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 326003#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 326001#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 325999#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 325998#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 325997#L715-36 assume !(1 == ~t10_pc~0); 325996#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 325995#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 325994#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 325993#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 325992#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 325991#L734-36 assume !(1 == ~t11_pc~0); 325989#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 325988#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 325987#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 325986#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 325985#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 325984#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 325983#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 325982#L1218-3 assume !(1 == ~T2_E~0); 325981#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 325980#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 325979#L1233-3 assume !(1 == ~T5_E~0); 325978#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 325976#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 325974#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 325972#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 325970#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 325968#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 325966#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 325964#L1273-3 assume !(1 == ~E_2~0); 325962#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 325960#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 325957#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 325955#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 325953#L1298-3 assume !(1 == ~E_7~0); 325951#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 325949#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 325947#L1313-3 assume !(1 == ~E_10~0); 325945#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 325943#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 325926#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 325919#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 325917#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 325789#L1663 assume !(0 == start_simulation_~tmp~3#1); 325787#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 325779#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 325768#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 325764#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 325762#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 325760#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 325758#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 325755#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 312830#L1644-2 [2024-11-20 22:59:19,879 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:19,879 INFO L85 PathProgramCache]: Analyzing trace with hash 948156820, now seen corresponding path program 1 times [2024-11-20 22:59:19,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:19,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1190519940] [2024-11-20 22:59:19,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:19,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:19,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:19,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:19,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:19,946 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1190519940] [2024-11-20 22:59:19,946 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1190519940] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:19,947 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:19,947 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:19,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818813110] [2024-11-20 22:59:19,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:19,947 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:19,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:19,948 INFO L85 PathProgramCache]: Analyzing trace with hash 168294620, now seen corresponding path program 1 times [2024-11-20 22:59:19,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:19,948 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564403835] [2024-11-20 22:59:19,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:19,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:19,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:20,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:20,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:20,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1564403835] [2024-11-20 22:59:20,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1564403835] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:20,030 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:20,030 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:20,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137473728] [2024-11-20 22:59:20,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:20,031 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:20,031 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:20,031 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-20 22:59:20,031 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-20 22:59:20,031 INFO L87 Difference]: Start difference. First operand 40755 states and 57235 transitions. cyclomatic complexity: 16512 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:20,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:20,153 INFO L93 Difference]: Finished difference Result 37078 states and 51880 transitions. [2024-11-20 22:59:20,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37078 states and 51880 transitions. [2024-11-20 22:59:20,517 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2024-11-20 22:59:20,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37078 states to 37078 states and 51880 transitions. [2024-11-20 22:59:20,600 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37078 [2024-11-20 22:59:20,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37078 [2024-11-20 22:59:20,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37078 states and 51880 transitions. [2024-11-20 22:59:20,649 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:20,649 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51880 transitions. [2024-11-20 22:59:20,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37078 states and 51880 transitions. [2024-11-20 22:59:21,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37078 to 37078. [2024-11-20 22:59:21,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.3992124710070661) internal successors, (51880), 37077 states have internal predecessors, (51880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:21,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 51880 transitions. [2024-11-20 22:59:21,124 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51880 transitions. [2024-11-20 22:59:21,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:21,125 INFO L425 stractBuchiCegarLoop]: Abstraction has 37078 states and 51880 transitions. [2024-11-20 22:59:21,125 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-20 22:59:21,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 51880 transitions. [2024-11-20 22:59:21,208 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2024-11-20 22:59:21,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:21,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:21,210 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:21,210 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:21,211 INFO L745 eck$LassoCheckResult]: Stem: 390602#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 390603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 391674#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 391675#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 391066#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 391067#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 390933#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 390828#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 390545#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 390196#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 390197#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 390241#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 390242#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 391211#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 391212#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 391256#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 390647#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 390648#L1090 assume !(0 == ~M_E~0); 390692#L1090-2 assume !(0 == ~T1_E~0); 390693#L1095-1 assume !(0 == ~T2_E~0); 391425#L1100-1 assume !(0 == ~T3_E~0); 391426#L1105-1 assume !(0 == ~T4_E~0); 390462#L1110-1 assume !(0 == ~T5_E~0); 390463#L1115-1 assume !(0 == ~T6_E~0); 390863#L1120-1 assume !(0 == ~T7_E~0); 391185#L1125-1 assume !(0 == ~T8_E~0); 391783#L1130-1 assume !(0 == ~T9_E~0); 391448#L1135-1 assume !(0 == ~T10_E~0); 390653#L1140-1 assume !(0 == ~T11_E~0); 390654#L1145-1 assume !(0 == ~E_1~0); 391371#L1150-1 assume !(0 == ~E_2~0); 390841#L1155-1 assume !(0 == ~E_3~0); 390842#L1160-1 assume !(0 == ~E_4~0); 390938#L1165-1 assume !(0 == ~E_5~0); 390939#L1170-1 assume !(0 == ~E_6~0); 391655#L1175-1 assume !(0 == ~E_7~0); 391020#L1180-1 assume !(0 == ~E_8~0); 391021#L1185-1 assume !(0 == ~E_9~0); 390649#L1190-1 assume !(0 == ~E_10~0); 390650#L1195-1 assume !(0 == ~E_11~0); 391036#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 390855#L525 assume !(1 == ~m_pc~0); 390285#L525-2 is_master_triggered_~__retres1~0#1 := 0; 390286#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 391622#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 391507#L1350 assume !(0 != activate_threads_~tmp~1#1); 390639#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 390640#L544 assume !(1 == ~t1_pc~0); 390861#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 390862#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 390259#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 390260#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 390486#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 391151#L563 assume !(1 == ~t2_pc~0); 391356#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 390305#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 390306#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 390719#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 390720#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 391237#L582 assume !(1 == ~t3_pc~0); 391370#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 391734#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 390188#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 390189#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 390371#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 390372#L601 assume !(1 == ~t4_pc~0); 391389#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 390864#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 390381#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 390382#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 391383#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 391721#L620 assume !(1 == ~t5_pc~0); 391200#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 391201#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 391253#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 391542#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 391743#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 391744#L639 assume !(1 == ~t6_pc~0); 391184#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 390759#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 390760#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 390811#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 390870#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 390871#L658 assume !(1 == ~t7_pc~0); 391095#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 391096#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 391756#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 391309#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 390642#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 390643#L677 assume !(1 == ~t8_pc~0); 390664#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 390445#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 390446#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 390715#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 390716#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 391499#L696 assume !(1 == ~t9_pc~0); 391164#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 391165#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 390923#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 390924#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 391190#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 391430#L715 assume !(1 == ~t10_pc~0); 391694#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 391289#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 391082#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 391083#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 391014#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 390439#L734 assume !(1 == ~t11_pc~0); 390440#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 390940#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 391023#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 390184#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 390185#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 391254#L1213 assume !(1 == ~M_E~0); 391011#L1213-2 assume !(1 == ~T1_E~0); 391012#L1218-1 assume !(1 == ~T2_E~0); 390219#L1223-1 assume !(1 == ~T3_E~0); 390220#L1228-1 assume !(1 == ~T4_E~0); 390987#L1233-1 assume !(1 == ~T5_E~0); 391745#L1238-1 assume !(1 == ~T6_E~0); 391381#L1243-1 assume !(1 == ~T7_E~0); 391382#L1248-1 assume !(1 == ~T8_E~0); 391435#L1253-1 assume !(1 == ~T9_E~0); 391436#L1258-1 assume !(1 == ~T10_E~0); 391407#L1263-1 assume !(1 == ~T11_E~0); 391408#L1268-1 assume !(1 == ~E_1~0); 391208#L1273-1 assume !(1 == ~E_2~0); 391209#L1278-1 assume !(1 == ~E_3~0); 390757#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 390758#L1288-1 assume !(1 == ~E_5~0); 391548#L1293-1 assume !(1 == ~E_6~0); 391503#L1298-1 assume !(1 == ~E_7~0); 391241#L1303-1 assume !(1 == ~E_8~0); 390767#L1308-1 assume !(1 == ~E_9~0); 390657#L1313-1 assume !(1 == ~E_10~0); 390658#L1318-1 assume !(1 == ~E_11~0); 390665#L1323-1 assume { :end_inline_reset_delta_events } true; 390666#L1644-2 [2024-11-20 22:59:21,211 INFO L747 eck$LassoCheckResult]: Loop: 390666#L1644-2 assume !false; 401140#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 401135#L1065-1 assume !false; 401133#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 400120#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 400110#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 400109#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 400107#L906 assume !(0 != eval_~tmp~0#1); 400108#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 401432#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 401430#L1090-3 assume !(0 == ~M_E~0); 401429#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 401428#L1095-3 assume !(0 == ~T2_E~0); 401427#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 401426#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 401425#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 401424#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 401423#L1120-3 assume !(0 == ~T7_E~0); 401422#L1125-3 assume !(0 == ~T8_E~0); 401421#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 401420#L1135-3 assume !(0 == ~T10_E~0); 401419#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 401418#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 401417#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 401416#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 401414#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 401413#L1165-3 assume !(0 == ~E_5~0); 401412#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 401411#L1175-3 assume !(0 == ~E_7~0); 401410#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 401408#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 401407#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 401406#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 401405#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 401404#L525-36 assume !(1 == ~m_pc~0); 401402#L525-38 is_master_triggered_~__retres1~0#1 := 0; 401400#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 401398#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 401397#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 401395#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 401394#L544-36 assume !(1 == ~t1_pc~0); 401393#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 401392#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 401390#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 401389#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 401388#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 401387#L563-36 assume 1 == ~t2_pc~0; 401386#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 401381#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 401379#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 401377#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 401375#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 401372#L582-36 assume !(1 == ~t3_pc~0); 401370#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 401368#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 401366#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 401364#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 401362#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 401360#L601-36 assume 1 == ~t4_pc~0; 401358#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 401355#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 401352#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 401350#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 401348#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 401346#L620-36 assume !(1 == ~t5_pc~0); 401344#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 401342#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 401340#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 401338#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 401336#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 401334#L639-36 assume !(1 == ~t6_pc~0); 401332#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 401329#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 401326#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 401324#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 401322#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 401320#L658-36 assume !(1 == ~t7_pc~0); 401317#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 401315#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 401313#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 401311#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 401309#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 401307#L677-36 assume !(1 == ~t8_pc~0); 401305#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 401303#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 401300#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 401298#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 401296#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 401289#L696-36 assume !(1 == ~t9_pc~0); 401287#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 401285#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 401283#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 401281#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 401278#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 401276#L715-36 assume !(1 == ~t10_pc~0); 401274#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 401272#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 401270#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 401268#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 401266#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 401262#L734-36 assume 1 == ~t11_pc~0; 401260#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 401257#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 401255#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 401252#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 401250#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 401248#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 401246#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 401244#L1218-3 assume !(1 == ~T2_E~0); 401242#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 401240#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 401238#L1233-3 assume !(1 == ~T5_E~0); 401236#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 401233#L1243-3 assume !(1 == ~T7_E~0); 401231#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 401229#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 401227#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 401225#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 401223#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 401221#L1273-3 assume !(1 == ~E_2~0); 401219#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 401217#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 401215#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 401213#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 401211#L1298-3 assume !(1 == ~E_7~0); 401209#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 401207#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 401205#L1313-3 assume !(1 == ~E_10~0); 401203#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 401201#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 401186#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 401179#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 401177#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 401173#L1663 assume !(0 == start_simulation_~tmp~3#1); 401172#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 401167#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 401154#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 401152#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 401150#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 401148#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 401145#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 401143#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 390666#L1644-2 [2024-11-20 22:59:21,211 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:21,211 INFO L85 PathProgramCache]: Analyzing trace with hash 1086953880, now seen corresponding path program 1 times [2024-11-20 22:59:21,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:21,211 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1302520643] [2024-11-20 22:59:21,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:21,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:21,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:21,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:21,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:21,262 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1302520643] [2024-11-20 22:59:21,262 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1302520643] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:21,262 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:21,262 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:21,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81199657] [2024-11-20 22:59:21,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:21,263 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:21,263 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:21,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1700339938, now seen corresponding path program 1 times [2024-11-20 22:59:21,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:21,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984002227] [2024-11-20 22:59:21,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:21,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:21,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:21,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:21,524 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:21,525 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984002227] [2024-11-20 22:59:21,525 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [984002227] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:21,525 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:21,525 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:21,525 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [931810349] [2024-11-20 22:59:21,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:21,525 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:21,525 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:21,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-20 22:59:21,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-20 22:59:21,525 INFO L87 Difference]: Start difference. First operand 37078 states and 51880 transitions. cyclomatic complexity: 14834 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:22,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:22,021 INFO L93 Difference]: Finished difference Result 77241 states and 107480 transitions. [2024-11-20 22:59:22,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77241 states and 107480 transitions. [2024-11-20 22:59:22,897 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 76600 [2024-11-20 22:59:23,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77241 states to 77241 states and 107480 transitions. [2024-11-20 22:59:23,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77241 [2024-11-20 22:59:23,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77241 [2024-11-20 22:59:23,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77241 states and 107480 transitions. [2024-11-20 22:59:23,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:23,344 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77241 states and 107480 transitions. [2024-11-20 22:59:23,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77241 states and 107480 transitions. [2024-11-20 22:59:23,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77241 to 40755. [2024-11-20 22:59:23,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40755 states, 40755 states have (on average 1.3940866151392468) internal successors, (56816), 40754 states have internal predecessors, (56816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:24,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40755 states to 40755 states and 56816 transitions. [2024-11-20 22:59:24,057 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40755 states and 56816 transitions. [2024-11-20 22:59:24,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-20 22:59:24,058 INFO L425 stractBuchiCegarLoop]: Abstraction has 40755 states and 56816 transitions. [2024-11-20 22:59:24,058 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-20 22:59:24,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40755 states and 56816 transitions. [2024-11-20 22:59:24,362 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40352 [2024-11-20 22:59:24,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:24,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:24,368 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:24,369 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:24,369 INFO L745 eck$LassoCheckResult]: Stem: 504933#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 504934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 506022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 506023#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 505398#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 505399#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 505267#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 505160#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 504875#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 504525#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 504526#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 504570#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 504571#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 505546#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 505547#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 505596#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 504980#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 504981#L1090 assume !(0 == ~M_E~0); 505025#L1090-2 assume !(0 == ~T1_E~0); 505026#L1095-1 assume !(0 == ~T2_E~0); 505763#L1100-1 assume !(0 == ~T3_E~0); 505764#L1105-1 assume !(0 == ~T4_E~0); 504792#L1110-1 assume !(0 == ~T5_E~0); 504793#L1115-1 assume !(0 == ~T6_E~0); 505198#L1120-1 assume !(0 == ~T7_E~0); 505520#L1125-1 assume !(0 == ~T8_E~0); 506134#L1130-1 assume !(0 == ~T9_E~0); 505790#L1135-1 assume !(0 == ~T10_E~0); 504986#L1140-1 assume !(0 == ~T11_E~0); 504987#L1145-1 assume !(0 == ~E_1~0); 505716#L1150-1 assume !(0 == ~E_2~0); 505176#L1155-1 assume !(0 == ~E_3~0); 505177#L1160-1 assume 0 == ~E_4~0;~E_4~0 := 1; 505272#L1165-1 assume !(0 == ~E_5~0); 505273#L1170-1 assume !(0 == ~E_6~0); 506103#L1175-1 assume !(0 == ~E_7~0); 505358#L1180-1 assume !(0 == ~E_8~0); 505359#L1185-1 assume !(0 == ~E_9~0); 504982#L1190-1 assume !(0 == ~E_10~0); 504983#L1195-1 assume !(0 == ~E_11~0); 505374#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 505190#L525 assume !(1 == ~m_pc~0); 504613#L525-2 is_master_triggered_~__retres1~0#1 := 0; 504614#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 505878#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 505848#L1350 assume !(0 != activate_threads_~tmp~1#1); 504971#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 504972#L544 assume !(1 == ~t1_pc~0); 505196#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 505197#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 504588#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 504589#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 505486#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505487#L563 assume !(1 == ~t2_pc~0); 505697#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 505698#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 505172#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 505173#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 505572#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 505573#L582 assume !(1 == ~t3_pc~0); 505715#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 506086#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 506087#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 506008#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 504699#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 504700#L601 assume !(1 == ~t4_pc~0); 506254#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 506253#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 506252#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 506251#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 506250#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 506249#L620 assume !(1 == ~t5_pc~0); 506248#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 506247#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 506246#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 506245#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 506244#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 506243#L639 assume !(1 == ~t6_pc~0); 506241#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 506240#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 506239#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 506238#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 506237#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 506236#L658 assume !(1 == ~t7_pc~0); 506234#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 506233#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 506232#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 506231#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 506230#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 506229#L677 assume !(1 == ~t8_pc~0); 506228#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 506227#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 506226#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 506225#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 506224#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 506223#L696 assume !(1 == ~t9_pc~0); 506221#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 506219#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 506217#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 506215#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 506214#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 506213#L715 assume !(1 == ~t10_pc~0); 506212#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 506211#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 506210#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 506209#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 506208#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 506207#L734 assume !(1 == ~t11_pc~0); 506205#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 506204#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 506203#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 506202#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 506201#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 506200#L1213 assume !(1 == ~M_E~0); 506199#L1213-2 assume !(1 == ~T1_E~0); 506198#L1218-1 assume !(1 == ~T2_E~0); 506197#L1223-1 assume !(1 == ~T3_E~0); 506196#L1228-1 assume !(1 == ~T4_E~0); 506195#L1233-1 assume !(1 == ~T5_E~0); 506194#L1238-1 assume !(1 == ~T6_E~0); 506193#L1243-1 assume !(1 == ~T7_E~0); 506192#L1248-1 assume !(1 == ~T8_E~0); 506191#L1253-1 assume !(1 == ~T9_E~0); 506190#L1258-1 assume !(1 == ~T10_E~0); 506189#L1263-1 assume !(1 == ~T11_E~0); 506188#L1268-1 assume !(1 == ~E_1~0); 506187#L1273-1 assume !(1 == ~E_2~0); 506186#L1278-1 assume !(1 == ~E_3~0); 506185#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 505093#L1288-1 assume !(1 == ~E_5~0); 505888#L1293-1 assume !(1 == ~E_6~0); 505843#L1298-1 assume !(1 == ~E_7~0); 505577#L1303-1 assume !(1 == ~E_8~0); 505102#L1308-1 assume !(1 == ~E_9~0); 504990#L1313-1 assume !(1 == ~E_10~0); 504991#L1318-1 assume !(1 == ~E_11~0); 504998#L1323-1 assume { :end_inline_reset_delta_events } true; 504999#L1644-2 [2024-11-20 22:59:24,369 INFO L747 eck$LassoCheckResult]: Loop: 504999#L1644-2 assume !false; 518930#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 518926#L1065-1 assume !false; 518925#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 518919#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 518908#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 518906#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 518903#L906 assume !(0 != eval_~tmp~0#1); 518904#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 519324#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 519322#L1090-3 assume !(0 == ~M_E~0); 519320#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 519318#L1095-3 assume !(0 == ~T2_E~0); 519316#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 519314#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 519312#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 519310#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 519308#L1120-3 assume !(0 == ~T7_E~0); 519306#L1125-3 assume !(0 == ~T8_E~0); 519304#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 519302#L1135-3 assume !(0 == ~T10_E~0); 519300#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 519298#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 519296#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 519294#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 519291#L1160-3 assume !(0 == ~E_4~0); 519292#L1165-3 assume !(0 == ~E_5~0); 519474#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 519472#L1175-3 assume !(0 == ~E_7~0); 519470#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 519468#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 519466#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 519464#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 519462#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 519460#L525-36 assume 1 == ~m_pc~0; 519458#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 519459#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 519480#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 519448#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 519446#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 519443#L544-36 assume !(1 == ~t1_pc~0); 519441#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 519439#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 519437#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 519435#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 519433#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 519431#L563-36 assume 1 == ~t2_pc~0; 519429#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 519426#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 519424#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 519422#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 519420#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 519416#L582-36 assume !(1 == ~t3_pc~0); 519414#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 519412#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 519410#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 519407#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 519405#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 519403#L601-36 assume !(1 == ~t4_pc~0); 519252#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 519399#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 519397#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 519395#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 519393#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 519391#L620-36 assume !(1 == ~t5_pc~0); 519388#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 519386#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 519384#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 519382#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 519380#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 519376#L639-36 assume !(1 == ~t6_pc~0); 519374#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 519371#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 519368#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 519367#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 519366#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 519365#L658-36 assume !(1 == ~t7_pc~0); 519363#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 519362#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 519361#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 519360#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 519359#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 519358#L677-36 assume !(1 == ~t8_pc~0); 519357#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 519355#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 519353#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 519351#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 519348#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 519346#L696-36 assume 1 == ~t9_pc~0; 519347#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 519345#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 519343#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 519338#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 519337#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 519336#L715-36 assume !(1 == ~t10_pc~0); 519335#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 519334#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 519333#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 519332#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 519331#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 519330#L734-36 assume 1 == ~t11_pc~0; 519329#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 519327#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 519326#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 519325#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 519323#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 519321#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 519319#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 519317#L1218-3 assume !(1 == ~T2_E~0); 519315#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 519313#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 519311#L1233-3 assume !(1 == ~T5_E~0); 519309#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 519307#L1243-3 assume !(1 == ~T7_E~0); 519305#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 519303#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 519301#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 519299#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 519297#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 519295#L1273-3 assume !(1 == ~E_2~0); 519293#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 519181#L1283-3 assume !(1 == ~E_4~0); 519179#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 519178#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 519177#L1298-3 assume !(1 == ~E_7~0); 519175#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 519174#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 519173#L1313-3 assume !(1 == ~E_10~0); 519172#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 519171#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 519159#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 519152#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 519149#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 518968#L1663 assume !(0 == start_simulation_~tmp~3#1); 518965#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 518955#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 518944#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 518942#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 518939#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 518938#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 518937#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 518934#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 504999#L1644-2 [2024-11-20 22:59:24,369 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:24,370 INFO L85 PathProgramCache]: Analyzing trace with hash 968512406, now seen corresponding path program 1 times [2024-11-20 22:59:24,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:24,370 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039779177] [2024-11-20 22:59:24,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:24,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:24,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:24,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:24,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:24,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039779177] [2024-11-20 22:59:24,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1039779177] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:24,440 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:24,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:24,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524493240] [2024-11-20 22:59:24,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:24,440 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:24,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:24,440 INFO L85 PathProgramCache]: Analyzing trace with hash 276163783, now seen corresponding path program 1 times [2024-11-20 22:59:24,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:24,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662126079] [2024-11-20 22:59:24,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:24,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:24,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:24,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:24,503 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:24,503 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662126079] [2024-11-20 22:59:24,503 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1662126079] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:24,503 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:24,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:24,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [741015175] [2024-11-20 22:59:24,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:24,504 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:24,504 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:24,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-20 22:59:24,504 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-20 22:59:24,504 INFO L87 Difference]: Start difference. First operand 40755 states and 56816 transitions. cyclomatic complexity: 16093 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:24,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:24,909 INFO L93 Difference]: Finished difference Result 54950 states and 76421 transitions. [2024-11-20 22:59:24,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54950 states and 76421 transitions. [2024-11-20 22:59:25,130 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 54576 [2024-11-20 22:59:25,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54950 states to 54950 states and 76421 transitions. [2024-11-20 22:59:25,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54950 [2024-11-20 22:59:25,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54950 [2024-11-20 22:59:25,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54950 states and 76421 transitions. [2024-11-20 22:59:25,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:25,326 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54950 states and 76421 transitions. [2024-11-20 22:59:25,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54950 states and 76421 transitions. [2024-11-20 22:59:25,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54950 to 37078. [2024-11-20 22:59:25,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.3879119693618858) internal successors, (51461), 37077 states have internal predecessors, (51461), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:26,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 51461 transitions. [2024-11-20 22:59:26,006 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51461 transitions. [2024-11-20 22:59:26,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-20 22:59:26,007 INFO L425 stractBuchiCegarLoop]: Abstraction has 37078 states and 51461 transitions. [2024-11-20 22:59:26,007 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-20 22:59:26,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 51461 transitions. [2024-11-20 22:59:26,092 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2024-11-20 22:59:26,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:26,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:26,093 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:26,093 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:26,094 INFO L745 eck$LassoCheckResult]: Stem: 600643#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 600644#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 601712#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 601713#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 601107#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 601108#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 600976#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 600867#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 600587#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 600240#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 600241#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 600284#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 600285#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 601251#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 601252#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 601300#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 600686#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 600687#L1090 assume !(0 == ~M_E~0); 600732#L1090-2 assume !(0 == ~T1_E~0); 600733#L1095-1 assume !(0 == ~T2_E~0); 601463#L1100-1 assume !(0 == ~T3_E~0); 601464#L1105-1 assume !(0 == ~T4_E~0); 600506#L1110-1 assume !(0 == ~T5_E~0); 600507#L1115-1 assume !(0 == ~T6_E~0); 600906#L1120-1 assume !(0 == ~T7_E~0); 601226#L1125-1 assume !(0 == ~T8_E~0); 601822#L1130-1 assume !(0 == ~T9_E~0); 601485#L1135-1 assume !(0 == ~T10_E~0); 600692#L1140-1 assume !(0 == ~T11_E~0); 600693#L1145-1 assume !(0 == ~E_1~0); 601415#L1150-1 assume !(0 == ~E_2~0); 600882#L1155-1 assume !(0 == ~E_3~0); 600883#L1160-1 assume !(0 == ~E_4~0); 600982#L1165-1 assume !(0 == ~E_5~0); 600983#L1170-1 assume !(0 == ~E_6~0); 601690#L1175-1 assume !(0 == ~E_7~0); 601062#L1180-1 assume !(0 == ~E_8~0); 601063#L1185-1 assume !(0 == ~E_9~0); 600688#L1190-1 assume !(0 == ~E_10~0); 600689#L1195-1 assume !(0 == ~E_11~0); 601078#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 600898#L525 assume !(1 == ~m_pc~0); 600330#L525-2 is_master_triggered_~__retres1~0#1 := 0; 600331#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 601658#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 601543#L1350 assume !(0 != activate_threads_~tmp~1#1); 600677#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 600678#L544 assume !(1 == ~t1_pc~0); 600904#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 600905#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600303#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 600304#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 600530#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 601191#L563 assume !(1 == ~t2_pc~0); 601399#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 600349#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 600350#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 600761#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 600762#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 601279#L582 assume !(1 == ~t3_pc~0); 601414#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 601771#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 600232#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 600233#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 600414#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 600415#L601 assume !(1 == ~t4_pc~0); 601429#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 600907#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 600424#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 600425#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 601424#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 601764#L620 assume !(1 == ~t5_pc~0); 601240#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 601241#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 601297#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 601578#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 601784#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 601785#L639 assume !(1 == ~t6_pc~0); 601224#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 600800#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 600801#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 600852#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 600912#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 600913#L658 assume !(1 == ~t7_pc~0); 601136#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 601137#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 601798#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 601352#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 600681#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 600682#L677 assume !(1 == ~t8_pc~0); 600703#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 600489#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 600490#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 600757#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 600758#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 601533#L696 assume !(1 == ~t9_pc~0); 601203#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 601204#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 600966#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 600967#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 601231#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 601469#L715 assume !(1 == ~t10_pc~0); 601732#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 601333#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 601123#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 601124#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 601055#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 600483#L734 assume !(1 == ~t11_pc~0); 600484#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 600984#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 601065#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 600228#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 600229#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 601298#L1213 assume !(1 == ~M_E~0); 601052#L1213-2 assume !(1 == ~T1_E~0); 601053#L1218-1 assume !(1 == ~T2_E~0); 600263#L1223-1 assume !(1 == ~T3_E~0); 600264#L1228-1 assume !(1 == ~T4_E~0); 601027#L1233-1 assume !(1 == ~T5_E~0); 601786#L1238-1 assume !(1 == ~T6_E~0); 601422#L1243-1 assume !(1 == ~T7_E~0); 601423#L1248-1 assume !(1 == ~T8_E~0); 601472#L1253-1 assume !(1 == ~T9_E~0); 601473#L1258-1 assume !(1 == ~T10_E~0); 601446#L1263-1 assume !(1 == ~T11_E~0); 601447#L1268-1 assume !(1 == ~E_1~0); 601248#L1273-1 assume !(1 == ~E_2~0); 601249#L1278-1 assume !(1 == ~E_3~0); 600798#L1283-1 assume !(1 == ~E_4~0); 600799#L1288-1 assume !(1 == ~E_5~0); 601585#L1293-1 assume !(1 == ~E_6~0); 601538#L1298-1 assume !(1 == ~E_7~0); 601283#L1303-1 assume !(1 == ~E_8~0); 600809#L1308-1 assume !(1 == ~E_9~0); 600696#L1313-1 assume !(1 == ~E_10~0); 600697#L1318-1 assume !(1 == ~E_11~0); 600704#L1323-1 assume { :end_inline_reset_delta_events } true; 600705#L1644-2 [2024-11-20 22:59:26,094 INFO L747 eck$LassoCheckResult]: Loop: 600705#L1644-2 assume !false; 611147#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 611138#L1065-1 assume !false; 611133#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 610926#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 610908#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 610902#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 610893#L906 assume !(0 != eval_~tmp~0#1); 610894#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 612841#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 612835#L1090-3 assume !(0 == ~M_E~0); 612828#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 612821#L1095-3 assume !(0 == ~T2_E~0); 612813#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 612806#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 612799#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 612791#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 612783#L1120-3 assume !(0 == ~T7_E~0); 612774#L1125-3 assume !(0 == ~T8_E~0); 612768#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 612762#L1135-3 assume !(0 == ~T10_E~0); 612755#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 612749#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 612742#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 612736#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 612730#L1160-3 assume !(0 == ~E_4~0); 612724#L1165-3 assume !(0 == ~E_5~0); 612717#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 611935#L1175-3 assume !(0 == ~E_7~0); 611931#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 611929#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 611927#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 611925#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 611922#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 611920#L525-36 assume 1 == ~m_pc~0; 611917#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 611914#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 611912#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 611908#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 611906#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 611904#L544-36 assume !(1 == ~t1_pc~0); 611901#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 611899#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 611897#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 611895#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 611893#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 611892#L563-36 assume 1 == ~t2_pc~0; 611885#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 611882#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 611880#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 611878#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 611876#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 611874#L582-36 assume !(1 == ~t3_pc~0); 611872#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 611870#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 611868#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 611866#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 611864#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 611862#L601-36 assume !(1 == ~t4_pc~0); 611859#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 611857#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 611855#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 611853#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 611851#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 611849#L620-36 assume !(1 == ~t5_pc~0); 611847#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 611845#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 611843#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 611841#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 611838#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 611836#L639-36 assume 1 == ~t6_pc~0; 611833#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 611832#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 611829#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 611827#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 611825#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 611823#L658-36 assume !(1 == ~t7_pc~0); 611820#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 611818#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 611816#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 611814#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 611812#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 611809#L677-36 assume !(1 == ~t8_pc~0); 611807#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 611805#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 611803#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 611801#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 611799#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 611797#L696-36 assume !(1 == ~t9_pc~0); 611795#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 612695#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 612691#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 611787#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 611784#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 611782#L715-36 assume !(1 == ~t10_pc~0); 611779#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 611777#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 611775#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 611773#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 611771#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 611769#L734-36 assume 1 == ~t11_pc~0; 611767#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 611764#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 611762#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 611760#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 611758#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 611756#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 611754#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 611751#L1218-3 assume !(1 == ~T2_E~0); 611749#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 611747#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 611733#L1233-3 assume !(1 == ~T5_E~0); 611724#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 611715#L1243-3 assume !(1 == ~T7_E~0); 611705#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 611697#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 611690#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 611683#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 611679#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 611675#L1273-3 assume !(1 == ~E_2~0); 611670#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 611666#L1283-3 assume !(1 == ~E_4~0); 611661#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 611655#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 611648#L1298-3 assume !(1 == ~E_7~0); 611642#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 611635#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 611630#L1313-3 assume !(1 == ~E_10~0); 611626#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 611624#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 611520#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 611509#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 611503#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 611495#L1663 assume !(0 == start_simulation_~tmp~3#1); 611491#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 611236#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 611217#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 611206#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 611195#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 611186#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 611177#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 611168#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 600705#L1644-2 [2024-11-20 22:59:26,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:26,095 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 1 times [2024-11-20 22:59:26,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:26,095 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927610789] [2024-11-20 22:59:26,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:26,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:26,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:26,104 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-20 22:59:26,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:26,190 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-20 22:59:26,193 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:26,194 INFO L85 PathProgramCache]: Analyzing trace with hash 383300293, now seen corresponding path program 1 times [2024-11-20 22:59:26,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:26,194 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252230790] [2024-11-20 22:59:26,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:26,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:26,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:26,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:26,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:26,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [252230790] [2024-11-20 22:59:26,254 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [252230790] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:26,254 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:26,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:26,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [363454689] [2024-11-20 22:59:26,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:26,255 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:26,255 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:26,255 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:26,255 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:26,255 INFO L87 Difference]: Start difference. First operand 37078 states and 51461 transitions. cyclomatic complexity: 14415 Second operand has 3 states, 3 states have (on average 47.333333333333336) internal successors, (142), 3 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:26,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:26,456 INFO L93 Difference]: Finished difference Result 40755 states and 56651 transitions. [2024-11-20 22:59:26,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40755 states and 56651 transitions. [2024-11-20 22:59:26,741 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40352 [2024-11-20 22:59:27,112 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40755 states to 40755 states and 56651 transitions. [2024-11-20 22:59:27,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40755 [2024-11-20 22:59:27,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40755 [2024-11-20 22:59:27,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40755 states and 56651 transitions. [2024-11-20 22:59:27,135 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:27,135 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40755 states and 56651 transitions. [2024-11-20 22:59:27,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40755 states and 56651 transitions. [2024-11-20 22:59:27,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40755 to 40755. [2024-11-20 22:59:27,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40755 states, 40755 states have (on average 1.3900380321432952) internal successors, (56651), 40754 states have internal predecessors, (56651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:27,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40755 states to 40755 states and 56651 transitions. [2024-11-20 22:59:27,448 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40755 states and 56651 transitions. [2024-11-20 22:59:27,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:27,449 INFO L425 stractBuchiCegarLoop]: Abstraction has 40755 states and 56651 transitions. [2024-11-20 22:59:27,449 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-20 22:59:27,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40755 states and 56651 transitions. [2024-11-20 22:59:27,541 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40352 [2024-11-20 22:59:27,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:27,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:27,543 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:27,543 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:27,543 INFO L745 eck$LassoCheckResult]: Stem: 678490#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 678491#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 679634#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 679635#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 678964#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 678965#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 678832#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 678720#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 678434#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 678079#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 678080#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 678124#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 678125#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 679134#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 679135#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 679194#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 678535#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 678536#L1090 assume !(0 == ~M_E~0); 678585#L1090-2 assume !(0 == ~T1_E~0); 678586#L1095-1 assume !(0 == ~T2_E~0); 679364#L1100-1 assume !(0 == ~T3_E~0); 679365#L1105-1 assume !(0 == ~T4_E~0); 678351#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 678352#L1115-1 assume !(0 == ~T6_E~0); 678762#L1120-1 assume !(0 == ~T7_E~0); 679795#L1125-1 assume !(0 == ~T8_E~0); 679796#L1130-1 assume !(0 == ~T9_E~0); 679925#L1135-1 assume !(0 == ~T10_E~0); 679924#L1140-1 assume !(0 == ~T11_E~0); 679310#L1145-1 assume !(0 == ~E_1~0); 679311#L1150-1 assume !(0 == ~E_2~0); 679357#L1155-1 assume !(0 == ~E_3~0); 679778#L1160-1 assume !(0 == ~E_4~0); 678837#L1165-1 assume !(0 == ~E_5~0); 678838#L1170-1 assume !(0 == ~E_6~0); 679744#L1175-1 assume !(0 == ~E_7~0); 678923#L1180-1 assume !(0 == ~E_8~0); 678924#L1185-1 assume !(0 == ~E_9~0); 678537#L1190-1 assume !(0 == ~E_10~0); 678538#L1195-1 assume !(0 == ~E_11~0); 678939#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 678759#L525 assume !(1 == ~m_pc~0); 678170#L525-2 is_master_triggered_~__retres1~0#1 := 0; 678171#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 679478#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 679448#L1350 assume !(0 != activate_threads_~tmp~1#1); 678527#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 678528#L544 assume !(1 == ~t1_pc~0); 678760#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 678761#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 679908#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 678375#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 678376#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 679907#L563 assume !(1 == ~t2_pc~0); 679906#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 678190#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 678191#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 678614#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 678615#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 679308#L582 assume !(1 == ~t3_pc~0); 679309#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 679717#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 678071#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 678072#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 679903#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 679816#L601 assume !(1 == ~t4_pc~0); 679328#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 678763#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 678270#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 678271#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 679320#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 679702#L620 assume !(1 == ~t5_pc~0); 679703#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 679187#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 679188#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 679485#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 679735#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 679736#L639 assume !(1 == ~t6_pc~0); 679100#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 679101#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 678705#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 678706#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 679896#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 679895#L658 assume !(1 == ~t7_pc~0); 678992#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 678993#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 679810#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 679811#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 679893#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 679892#L677 assume !(1 == ~t8_pc~0); 679891#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 678332#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 678333#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 679405#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 679889#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 679888#L696 assume !(1 == ~t9_pc~0); 679084#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 679085#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 679926#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 679111#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 679112#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 679368#L715 assume !(1 == ~t10_pc~0); 679766#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 679767#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 679880#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 679879#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 679878#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 678326#L734 assume !(1 == ~t11_pc~0); 678327#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 678839#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 678928#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 678069#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 678070#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 679189#L1213 assume !(1 == ~M_E~0); 678913#L1213-2 assume !(1 == ~T1_E~0); 678914#L1218-1 assume !(1 == ~T2_E~0); 678102#L1223-1 assume !(1 == ~T3_E~0); 678103#L1228-1 assume !(1 == ~T4_E~0); 678884#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 679737#L1238-1 assume !(1 == ~T6_E~0); 679318#L1243-1 assume !(1 == ~T7_E~0); 679319#L1248-1 assume !(1 == ~T8_E~0); 679373#L1253-1 assume !(1 == ~T9_E~0); 679374#L1258-1 assume !(1 == ~T10_E~0); 679345#L1263-1 assume !(1 == ~T11_E~0); 679346#L1268-1 assume !(1 == ~E_1~0); 679128#L1273-1 assume !(1 == ~E_2~0); 679129#L1278-1 assume !(1 == ~E_3~0); 678651#L1283-1 assume !(1 == ~E_4~0); 678652#L1288-1 assume !(1 == ~E_5~0); 679489#L1293-1 assume !(1 == ~E_6~0); 679441#L1298-1 assume !(1 == ~E_7~0); 679170#L1303-1 assume !(1 == ~E_8~0); 678662#L1308-1 assume !(1 == ~E_9~0); 678545#L1313-1 assume !(1 == ~E_10~0); 678546#L1318-1 assume !(1 == ~E_11~0); 678557#L1323-1 assume { :end_inline_reset_delta_events } true; 678558#L1644-2 [2024-11-20 22:59:27,543 INFO L747 eck$LassoCheckResult]: Loop: 678558#L1644-2 assume !false; 686934#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 686929#L1065-1 assume !false; 686926#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 686915#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 686904#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 686901#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 686899#L906 assume !(0 != eval_~tmp~0#1); 686900#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 687324#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 687322#L1090-3 assume !(0 == ~M_E~0); 687320#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 687318#L1095-3 assume !(0 == ~T2_E~0); 687316#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 687314#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 687311#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 687309#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 687307#L1120-3 assume !(0 == ~T7_E~0); 687305#L1125-3 assume !(0 == ~T8_E~0); 687303#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 687302#L1135-3 assume !(0 == ~T10_E~0); 687298#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 687296#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 687294#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 687292#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 687289#L1160-3 assume !(0 == ~E_4~0); 687287#L1165-3 assume !(0 == ~E_5~0); 687285#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 687283#L1175-3 assume !(0 == ~E_7~0); 687281#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 687279#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 687277#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 687275#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 687273#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 687270#L525-36 assume !(1 == ~m_pc~0); 687266#L525-38 is_master_triggered_~__retres1~0#1 := 0; 687264#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 687262#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 687260#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 687257#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 687255#L544-36 assume !(1 == ~t1_pc~0); 687253#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 687251#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 687249#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 687248#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 687247#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 687246#L563-36 assume !(1 == ~t2_pc~0); 687244#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 687243#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 687242#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 687240#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 687239#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 687238#L582-36 assume !(1 == ~t3_pc~0); 687237#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 687236#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 687235#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 687234#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 687233#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 687231#L601-36 assume !(1 == ~t4_pc~0); 687229#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 687228#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 687227#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 687225#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 687221#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 687219#L620-36 assume !(1 == ~t5_pc~0); 687217#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 687215#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 687212#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 687210#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 687208#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 687206#L639-36 assume 1 == ~t6_pc~0; 687203#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 687201#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 687199#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 687197#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 687195#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 687192#L658-36 assume !(1 == ~t7_pc~0); 687189#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 687187#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 687185#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 687183#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 687181#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 687179#L677-36 assume !(1 == ~t8_pc~0); 687177#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 687175#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 687173#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 687171#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 687168#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 687163#L696-36 assume !(1 == ~t9_pc~0); 687161#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 687159#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 687157#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 687155#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 687152#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 687150#L715-36 assume !(1 == ~t10_pc~0); 687148#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 687146#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 687144#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 687142#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 687139#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 687137#L734-36 assume !(1 == ~t11_pc~0); 687134#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 687132#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 687130#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 687127#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 687125#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 687123#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 687121#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 687119#L1218-3 assume !(1 == ~T2_E~0); 687117#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 687115#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 687113#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 687110#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 687108#L1243-3 assume !(1 == ~T7_E~0); 687106#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 687104#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 687102#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 687099#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 687097#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 687095#L1273-3 assume !(1 == ~E_2~0); 687094#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 687093#L1283-3 assume !(1 == ~E_4~0); 687092#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 687091#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 687090#L1298-3 assume !(1 == ~E_7~0); 687089#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 687088#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 687087#L1313-3 assume !(1 == ~E_10~0); 687086#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 687085#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 686979#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 686972#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 686970#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 686966#L1663 assume !(0 == start_simulation_~tmp~3#1); 686965#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 686959#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 686947#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 686945#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 686943#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 686941#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 686939#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 686937#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 678558#L1644-2 [2024-11-20 22:59:27,544 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:27,544 INFO L85 PathProgramCache]: Analyzing trace with hash 1527023766, now seen corresponding path program 1 times [2024-11-20 22:59:27,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:27,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553133941] [2024-11-20 22:59:27,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:27,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:27,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:27,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:27,628 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:27,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553133941] [2024-11-20 22:59:27,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553133941] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:27,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:27,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-20 22:59:27,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1961799412] [2024-11-20 22:59:27,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:27,629 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:27,629 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:27,629 INFO L85 PathProgramCache]: Analyzing trace with hash -1175681890, now seen corresponding path program 1 times [2024-11-20 22:59:27,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:27,629 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215860510] [2024-11-20 22:59:27,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:27,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:27,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:27,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:27,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:27,673 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215860510] [2024-11-20 22:59:27,673 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215860510] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:27,673 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:27,673 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:27,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335817387] [2024-11-20 22:59:27,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:27,673 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:27,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:27,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:27,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:27,674 INFO L87 Difference]: Start difference. First operand 40755 states and 56651 transitions. cyclomatic complexity: 15928 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:27,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:27,758 INFO L93 Difference]: Finished difference Result 37078 states and 51363 transitions. [2024-11-20 22:59:27,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37078 states and 51363 transitions. [2024-11-20 22:59:28,422 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2024-11-20 22:59:28,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37078 states to 37078 states and 51363 transitions. [2024-11-20 22:59:28,548 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37078 [2024-11-20 22:59:28,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37078 [2024-11-20 22:59:28,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37078 states and 51363 transitions. [2024-11-20 22:59:28,598 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:28,598 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51363 transitions. [2024-11-20 22:59:28,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37078 states and 51363 transitions. [2024-11-20 22:59:28,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37078 to 37078. [2024-11-20 22:59:28,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.3852688926047791) internal successors, (51363), 37077 states have internal predecessors, (51363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:29,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 51363 transitions. [2024-11-20 22:59:29,005 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51363 transitions. [2024-11-20 22:59:29,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:29,005 INFO L425 stractBuchiCegarLoop]: Abstraction has 37078 states and 51363 transitions. [2024-11-20 22:59:29,005 INFO L332 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-20 22:59:29,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 51363 transitions. [2024-11-20 22:59:29,114 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2024-11-20 22:59:29,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:29,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:29,117 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:29,117 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:29,118 INFO L745 eck$LassoCheckResult]: Stem: 756324#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 756325#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 757405#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 757406#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 756779#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 756780#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 756651#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 756546#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 756268#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 755919#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 755920#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 755963#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 755964#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 756934#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 756935#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 756987#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 756366#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 756367#L1090 assume !(0 == ~M_E~0); 756417#L1090-2 assume !(0 == ~T1_E~0); 756418#L1095-1 assume !(0 == ~T2_E~0); 757141#L1100-1 assume !(0 == ~T3_E~0); 757142#L1105-1 assume !(0 == ~T4_E~0); 756188#L1110-1 assume !(0 == ~T5_E~0); 756189#L1115-1 assume !(0 == ~T6_E~0); 756585#L1120-1 assume !(0 == ~T7_E~0); 756903#L1125-1 assume !(0 == ~T8_E~0); 757514#L1130-1 assume !(0 == ~T9_E~0); 757164#L1135-1 assume !(0 == ~T10_E~0); 756372#L1140-1 assume !(0 == ~T11_E~0); 756373#L1145-1 assume !(0 == ~E_1~0); 757093#L1150-1 assume !(0 == ~E_2~0); 756562#L1155-1 assume !(0 == ~E_3~0); 756563#L1160-1 assume !(0 == ~E_4~0); 756656#L1165-1 assume !(0 == ~E_5~0); 756657#L1170-1 assume !(0 == ~E_6~0); 757381#L1175-1 assume !(0 == ~E_7~0); 756739#L1180-1 assume !(0 == ~E_8~0); 756740#L1185-1 assume !(0 == ~E_9~0); 756368#L1190-1 assume !(0 == ~E_10~0); 756369#L1195-1 assume !(0 == ~E_11~0); 756755#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 756580#L525 assume !(1 == ~m_pc~0); 756007#L525-2 is_master_triggered_~__retres1~0#1 := 0; 756008#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 757347#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 757224#L1350 assume !(0 != activate_threads_~tmp~1#1); 756358#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 756359#L544 assume !(1 == ~t1_pc~0); 756581#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 756582#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 755986#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 755987#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 756212#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 756869#L563 assume !(1 == ~t2_pc~0); 757080#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 756029#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 756030#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 756443#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 756444#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 756957#L582 assume !(1 == ~t3_pc~0); 757092#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 757459#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 755911#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 755912#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 756094#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 756095#L601 assume !(1 == ~t4_pc~0); 757107#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 756586#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 756108#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 756109#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 757102#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 757452#L620 assume !(1 == ~t5_pc~0); 756922#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 756923#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 756977#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 757260#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 757469#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 757470#L639 assume !(1 == ~t6_pc~0); 756901#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 756483#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 756484#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 756532#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 756591#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 756592#L658 assume !(1 == ~t7_pc~0); 756805#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 756806#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 757482#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 757035#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 756361#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 756362#L677 assume !(1 == ~t8_pc~0); 756385#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 756175#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 756176#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 756436#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 756437#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 757212#L696 assume !(1 == ~t9_pc~0); 756886#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 756887#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 756641#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 756642#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 756912#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 757146#L715 assume !(1 == ~t10_pc~0); 757422#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 757013#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 756791#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 756792#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 756732#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 756163#L734 assume !(1 == ~t11_pc~0); 756164#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 756659#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 756744#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 755909#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 755910#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 756978#L1213 assume !(1 == ~M_E~0); 756730#L1213-2 assume !(1 == ~T1_E~0); 756731#L1218-1 assume !(1 == ~T2_E~0); 755942#L1223-1 assume !(1 == ~T3_E~0); 755943#L1228-1 assume !(1 == ~T4_E~0); 756701#L1233-1 assume !(1 == ~T5_E~0); 757471#L1238-1 assume !(1 == ~T6_E~0); 757100#L1243-1 assume !(1 == ~T7_E~0); 757101#L1248-1 assume !(1 == ~T8_E~0); 757151#L1253-1 assume !(1 == ~T9_E~0); 757152#L1258-1 assume !(1 == ~T10_E~0); 757124#L1263-1 assume !(1 == ~T11_E~0); 757125#L1268-1 assume !(1 == ~E_1~0); 756927#L1273-1 assume !(1 == ~E_2~0); 756928#L1278-1 assume !(1 == ~E_3~0); 756479#L1283-1 assume !(1 == ~E_4~0); 756480#L1288-1 assume !(1 == ~E_5~0); 757266#L1293-1 assume !(1 == ~E_6~0); 757220#L1298-1 assume !(1 == ~E_7~0); 756961#L1303-1 assume !(1 == ~E_8~0); 756489#L1308-1 assume !(1 == ~E_9~0); 756376#L1313-1 assume !(1 == ~E_10~0); 756377#L1318-1 assume !(1 == ~E_11~0); 756386#L1323-1 assume { :end_inline_reset_delta_events } true; 756387#L1644-2 [2024-11-20 22:59:29,118 INFO L747 eck$LassoCheckResult]: Loop: 756387#L1644-2 assume !false; 777240#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 777235#L1065-1 assume !false; 777233#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 777226#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 777215#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 777213#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 777210#L906 assume !(0 != eval_~tmp~0#1); 777211#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 777532#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 777528#L1090-3 assume !(0 == ~M_E~0); 777524#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 777523#L1095-3 assume !(0 == ~T2_E~0); 777522#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 777521#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 777520#L1110-3 assume !(0 == ~T5_E~0); 777519#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 777518#L1120-3 assume !(0 == ~T7_E~0); 777517#L1125-3 assume !(0 == ~T8_E~0); 777516#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 777515#L1135-3 assume !(0 == ~T10_E~0); 777514#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 777513#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 777512#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 777511#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 777509#L1160-3 assume !(0 == ~E_4~0); 777508#L1165-3 assume !(0 == ~E_5~0); 777507#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 777506#L1175-3 assume !(0 == ~E_7~0); 777505#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 777503#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 777502#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 777501#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 777500#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 777499#L525-36 assume 1 == ~m_pc~0; 777498#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 777496#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 777494#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 777491#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 777490#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 777489#L544-36 assume !(1 == ~t1_pc~0); 777488#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 777487#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 777485#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 777484#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 777483#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 777482#L563-36 assume 1 == ~t2_pc~0; 777481#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 777476#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 777474#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 777472#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 777470#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 777467#L582-36 assume !(1 == ~t3_pc~0); 777465#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 777463#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 777461#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 777459#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 777457#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 777455#L601-36 assume !(1 == ~t4_pc~0); 777452#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 777450#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 777447#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 777445#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 777443#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 777441#L620-36 assume !(1 == ~t5_pc~0); 777439#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 777437#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 777435#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 777433#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 777431#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 777429#L639-36 assume !(1 == ~t6_pc~0); 777427#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 777423#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 777421#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 777419#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 777417#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 777415#L658-36 assume !(1 == ~t7_pc~0); 777412#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 777410#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 777408#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 777406#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 777404#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 777402#L677-36 assume !(1 == ~t8_pc~0); 777400#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 777398#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 777395#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 777393#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 777391#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 777384#L696-36 assume 1 == ~t9_pc~0; 777385#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 777386#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 777504#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 777375#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 777373#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 777371#L715-36 assume !(1 == ~t10_pc~0); 777369#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 777367#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 777365#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 777363#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 777361#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 777357#L734-36 assume 1 == ~t11_pc~0; 777355#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 777352#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 777350#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 777347#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 777345#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 777343#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 777341#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 777339#L1218-3 assume !(1 == ~T2_E~0); 777337#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 777335#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 777333#L1233-3 assume !(1 == ~T5_E~0); 777331#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 777328#L1243-3 assume !(1 == ~T7_E~0); 777326#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 777324#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 777322#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 777320#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 777318#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 777316#L1273-3 assume !(1 == ~E_2~0); 777314#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 777312#L1283-3 assume !(1 == ~E_4~0); 777310#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 777308#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 777306#L1298-3 assume !(1 == ~E_7~0); 777304#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 777302#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 777300#L1313-3 assume !(1 == ~E_10~0); 777298#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 777296#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 777281#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 777274#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 777272#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 777268#L1663 assume !(0 == start_simulation_~tmp~3#1); 777267#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 777264#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 777253#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 777251#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 777249#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 777247#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 777245#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 777243#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 756387#L1644-2 [2024-11-20 22:59:29,119 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:29,119 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 2 times [2024-11-20 22:59:29,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:29,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080414118] [2024-11-20 22:59:29,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:29,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:29,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:29,133 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-20 22:59:29,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:29,189 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-20 22:59:29,189 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:29,190 INFO L85 PathProgramCache]: Analyzing trace with hash -158341815, now seen corresponding path program 1 times [2024-11-20 22:59:29,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:29,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281809522] [2024-11-20 22:59:29,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:29,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:29,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:29,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:29,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:29,232 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281809522] [2024-11-20 22:59:29,232 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281809522] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:29,232 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:29,233 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:29,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1824311805] [2024-11-20 22:59:29,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:29,233 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:29,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:29,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:29,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:29,234 INFO L87 Difference]: Start difference. First operand 37078 states and 51363 transitions. cyclomatic complexity: 14317 Second operand has 3 states, 3 states have (on average 47.333333333333336) internal successors, (142), 3 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:29,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:29,485 INFO L93 Difference]: Finished difference Result 70243 states and 96408 transitions. [2024-11-20 22:59:29,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70243 states and 96408 transitions. [2024-11-20 22:59:30,160 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 69696 [2024-11-20 22:59:30,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70243 states to 70243 states and 96408 transitions. [2024-11-20 22:59:30,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70243 [2024-11-20 22:59:30,403 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70243 [2024-11-20 22:59:30,404 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70243 states and 96408 transitions. [2024-11-20 22:59:30,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:30,447 INFO L218 hiAutomatonCegarLoop]: Abstraction has 70243 states and 96408 transitions. [2024-11-20 22:59:30,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70243 states and 96408 transitions. [2024-11-20 22:59:30,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70243 to 70227. [2024-11-20 22:59:30,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70227 states, 70227 states have (on average 1.3725774986828427) internal successors, (96392), 70226 states have internal predecessors, (96392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:31,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70227 states to 70227 states and 96392 transitions. [2024-11-20 22:59:31,086 INFO L240 hiAutomatonCegarLoop]: Abstraction has 70227 states and 96392 transitions. [2024-11-20 22:59:31,087 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:31,087 INFO L425 stractBuchiCegarLoop]: Abstraction has 70227 states and 96392 transitions. [2024-11-20 22:59:31,087 INFO L332 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-20 22:59:31,087 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70227 states and 96392 transitions. [2024-11-20 22:59:31,565 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 69680 [2024-11-20 22:59:31,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:31,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:31,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:31,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:31,574 INFO L745 eck$LassoCheckResult]: Stem: 863651#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 863652#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 864757#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 864758#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 864122#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 864123#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 863991#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 863880#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 863595#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 863246#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 863247#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 863290#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 863291#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 864268#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 864269#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 864320#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 863695#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 863696#L1090 assume !(0 == ~M_E~0); 863741#L1090-2 assume !(0 == ~T1_E~0); 863742#L1095-1 assume !(0 == ~T2_E~0); 864486#L1100-1 assume !(0 == ~T3_E~0); 864487#L1105-1 assume !(0 == ~T4_E~0); 863511#L1110-1 assume !(0 == ~T5_E~0); 863512#L1115-1 assume !(0 == ~T6_E~0); 863919#L1120-1 assume !(0 == ~T7_E~0); 864242#L1125-1 assume !(0 == ~T8_E~0); 864887#L1130-1 assume !(0 == ~T9_E~0); 864510#L1135-1 assume !(0 == ~T10_E~0); 863701#L1140-1 assume !(0 == ~T11_E~0); 863702#L1145-1 assume !(0 == ~E_1~0); 864437#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 864481#L1155-1 assume !(0 == ~E_3~0); 864881#L1160-1 assume !(0 == ~E_4~0); 863996#L1165-1 assume !(0 == ~E_5~0); 863997#L1170-1 assume !(0 == ~E_6~0); 864845#L1175-1 assume !(0 == ~E_7~0); 864078#L1180-1 assume !(0 == ~E_8~0); 864079#L1185-1 assume !(0 == ~E_9~0); 863697#L1190-1 assume !(0 == ~E_10~0); 863698#L1195-1 assume !(0 == ~E_11~0); 864094#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 863911#L525 assume !(1 == ~m_pc~0); 863336#L525-2 is_master_triggered_~__retres1~0#1 := 0; 863337#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 864602#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 864571#L1350 assume !(0 != activate_threads_~tmp~1#1); 863687#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 863688#L544 assume !(1 == ~t1_pc~0); 864998#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 864997#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 863308#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 863309#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 864203#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 864204#L563 assume !(1 == ~t2_pc~0); 864419#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 864420#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 864991#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 863770#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 863771#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 864990#L582 assume !(1 == ~t3_pc~0); 864888#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 864889#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 864989#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 864745#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 863420#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 863421#L601 assume !(1 == ~t4_pc~0); 864986#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 864985#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 864984#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 864983#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 864911#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 864912#L620 assume !(1 == ~t5_pc~0); 864257#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 864258#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 864982#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 864981#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 864840#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 864841#L639 assume !(1 == ~t6_pc~0); 864238#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 864239#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 863865#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 863866#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 864980#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 864979#L658 assume !(1 == ~t7_pc~0); 864147#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 864148#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 864902#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 864903#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 864977#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 864976#L677 assume !(1 == ~t8_pc~0); 863712#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 863713#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 864975#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 863766#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 863767#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 864563#L696 assume !(1 == ~t9_pc~0); 864667#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 864971#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 864969#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 864967#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 864966#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 864965#L715 assume !(1 == ~t10_pc~0); 864870#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 864871#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 864135#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 864136#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 864071#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 863489#L734 assume !(1 == ~t11_pc~0); 863490#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 863998#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 864081#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 863234#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 863235#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 864318#L1213 assume !(1 == ~M_E~0); 864067#L1213-2 assume !(1 == ~T1_E~0); 864068#L1218-1 assume !(1 == ~T2_E~0); 863269#L1223-1 assume !(1 == ~T3_E~0); 863270#L1228-1 assume !(1 == ~T4_E~0); 864043#L1233-1 assume !(1 == ~T5_E~0); 864842#L1238-1 assume !(1 == ~T6_E~0); 864443#L1243-1 assume !(1 == ~T7_E~0); 864444#L1248-1 assume !(1 == ~T8_E~0); 864498#L1253-1 assume !(1 == ~T9_E~0); 864499#L1258-1 assume !(1 == ~T10_E~0); 864469#L1263-1 assume !(1 == ~T11_E~0); 864470#L1268-1 assume !(1 == ~E_1~0); 864264#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 864265#L1278-1 assume !(1 == ~E_3~0); 863807#L1283-1 assume !(1 == ~E_4~0); 863808#L1288-1 assume !(1 == ~E_5~0); 864617#L1293-1 assume !(1 == ~E_6~0); 864569#L1298-1 assume !(1 == ~E_7~0); 864301#L1303-1 assume !(1 == ~E_8~0); 863818#L1308-1 assume !(1 == ~E_9~0); 863705#L1313-1 assume !(1 == ~E_10~0); 863706#L1318-1 assume !(1 == ~E_11~0); 863714#L1323-1 assume { :end_inline_reset_delta_events } true; 863715#L1644-2 [2024-11-20 22:59:31,575 INFO L747 eck$LassoCheckResult]: Loop: 863715#L1644-2 assume !false; 882030#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 882025#L1065-1 assume !false; 882024#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 880400#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 880390#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 880386#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 880383#L906 assume !(0 != eval_~tmp~0#1); 880384#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 890210#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 890204#L1090-3 assume !(0 == ~M_E~0); 890199#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 890193#L1095-3 assume !(0 == ~T2_E~0); 890187#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 890181#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 890174#L1110-3 assume !(0 == ~T5_E~0); 890168#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 890162#L1120-3 assume !(0 == ~T7_E~0); 890156#L1125-3 assume !(0 == ~T8_E~0); 890149#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 890142#L1135-3 assume !(0 == ~T10_E~0); 890135#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 890128#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 890120#L1150-3 assume !(0 == ~E_2~0); 890121#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 890151#L1160-3 assume !(0 == ~E_4~0); 890144#L1165-3 assume !(0 == ~E_5~0); 890137#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 890130#L1175-3 assume !(0 == ~E_7~0); 890123#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 890115#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 890109#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 890100#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 890093#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 890085#L525-36 assume !(1 == ~m_pc~0); 890077#L525-38 is_master_triggered_~__retres1~0#1 := 0; 890069#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 890061#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 890054#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 890047#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 890042#L544-36 assume !(1 == ~t1_pc~0); 890037#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 890031#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 890025#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 890018#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 890011#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 889967#L563-36 assume !(1 == ~t2_pc~0); 889961#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 889955#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 889948#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 889900#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 889893#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 889887#L582-36 assume !(1 == ~t3_pc~0); 889881#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 889873#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 889866#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 889859#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 889852#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 889846#L601-36 assume !(1 == ~t4_pc~0); 889838#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 889832#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 889827#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 889822#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 889818#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 889814#L620-36 assume !(1 == ~t5_pc~0); 889811#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 889809#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 889807#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 889805#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 889803#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 889801#L639-36 assume !(1 == ~t6_pc~0); 889799#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 889796#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 889794#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 889792#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 889790#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 889788#L658-36 assume !(1 == ~t7_pc~0); 889785#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 889782#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 889780#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 889778#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 889765#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 889758#L677-36 assume !(1 == ~t8_pc~0); 889752#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 889745#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 889738#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 889732#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 889726#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 889720#L696-36 assume 1 == ~t9_pc~0; 889711#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 889704#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 889697#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 889690#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 889687#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 889685#L715-36 assume !(1 == ~t10_pc~0); 889683#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 889681#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 889679#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 889677#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 889675#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 889673#L734-36 assume 1 == ~t11_pc~0; 889671#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 889667#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 889665#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 889663#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 889661#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 889659#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 889657#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 889655#L1218-3 assume !(1 == ~T2_E~0); 889653#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 889651#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 889649#L1233-3 assume !(1 == ~T5_E~0); 889647#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 889645#L1243-3 assume !(1 == ~T7_E~0); 889643#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 889641#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 889639#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 889637#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 889635#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 889632#L1273-3 assume !(1 == ~E_2~0); 889631#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 889630#L1283-3 assume !(1 == ~E_4~0); 889628#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 889626#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 889624#L1298-3 assume !(1 == ~E_7~0); 889621#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 889620#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 889619#L1313-3 assume !(1 == ~E_10~0); 889618#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 889617#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 889610#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 889604#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 889603#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 889386#L1663 assume !(0 == start_simulation_~tmp~3#1); 889384#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 889377#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 889364#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 889362#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 889359#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 889356#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 889352#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 889348#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 863715#L1644-2 [2024-11-20 22:59:31,575 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:31,575 INFO L85 PathProgramCache]: Analyzing trace with hash -1087159146, now seen corresponding path program 1 times [2024-11-20 22:59:31,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:31,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263346738] [2024-11-20 22:59:31,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:31,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:31,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:31,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:31,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:31,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1263346738] [2024-11-20 22:59:31,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1263346738] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:31,621 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:31,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-20 22:59:31,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1305016934] [2024-11-20 22:59:31,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:31,621 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:31,622 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:31,622 INFO L85 PathProgramCache]: Analyzing trace with hash -142382009, now seen corresponding path program 1 times [2024-11-20 22:59:31,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:31,622 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334103188] [2024-11-20 22:59:31,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:31,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:31,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:31,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:31,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:31,656 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334103188] [2024-11-20 22:59:31,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334103188] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:31,657 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:31,657 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:31,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893959145] [2024-11-20 22:59:31,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:31,657 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:31,657 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:31,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:31,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:31,658 INFO L87 Difference]: Start difference. First operand 70227 states and 96392 transitions. cyclomatic complexity: 26197 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:31,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:31,780 INFO L93 Difference]: Finished difference Result 37078 states and 50928 transitions. [2024-11-20 22:59:31,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37078 states and 50928 transitions. [2024-11-20 22:59:31,908 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2024-11-20 22:59:31,991 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37078 states to 37078 states and 50928 transitions. [2024-11-20 22:59:31,991 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37078 [2024-11-20 22:59:32,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37078 [2024-11-20 22:59:32,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37078 states and 50928 transitions. [2024-11-20 22:59:32,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:32,041 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37078 states and 50928 transitions. [2024-11-20 22:59:32,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37078 states and 50928 transitions. [2024-11-20 22:59:32,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37078 to 37078. [2024-11-20 22:59:32,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.3735368682237445) internal successors, (50928), 37077 states have internal predecessors, (50928), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:32,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 50928 transitions. [2024-11-20 22:59:32,351 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 50928 transitions. [2024-11-20 22:59:32,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:32,352 INFO L425 stractBuchiCegarLoop]: Abstraction has 37078 states and 50928 transitions. [2024-11-20 22:59:32,352 INFO L332 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-20 22:59:32,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 50928 transitions. [2024-11-20 22:59:32,437 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2024-11-20 22:59:32,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:32,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:32,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:32,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:32,438 INFO L745 eck$LassoCheckResult]: Stem: 970963#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 970964#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 972081#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 972082#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 971434#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 971435#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 971298#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 971189#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 970905#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 970558#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 970559#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 970602#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 970603#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 971584#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 971585#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 971634#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 971008#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 971009#L1090 assume !(0 == ~M_E~0); 971051#L1090-2 assume !(0 == ~T1_E~0); 971052#L1095-1 assume !(0 == ~T2_E~0); 971797#L1100-1 assume !(0 == ~T3_E~0); 971798#L1105-1 assume !(0 == ~T4_E~0); 970821#L1110-1 assume !(0 == ~T5_E~0); 970822#L1115-1 assume !(0 == ~T6_E~0); 971226#L1120-1 assume !(0 == ~T7_E~0); 971556#L1125-1 assume !(0 == ~T8_E~0); 972187#L1130-1 assume !(0 == ~T9_E~0); 971821#L1135-1 assume !(0 == ~T10_E~0); 971014#L1140-1 assume !(0 == ~T11_E~0); 971015#L1145-1 assume !(0 == ~E_1~0); 971747#L1150-1 assume !(0 == ~E_2~0); 971205#L1155-1 assume !(0 == ~E_3~0); 971206#L1160-1 assume !(0 == ~E_4~0); 971305#L1165-1 assume !(0 == ~E_5~0); 971306#L1170-1 assume !(0 == ~E_6~0); 972057#L1175-1 assume !(0 == ~E_7~0); 971390#L1180-1 assume !(0 == ~E_8~0); 971391#L1185-1 assume !(0 == ~E_9~0); 971010#L1190-1 assume !(0 == ~E_10~0); 971011#L1195-1 assume !(0 == ~E_11~0); 971407#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 971218#L525 assume !(1 == ~m_pc~0); 970646#L525-2 is_master_triggered_~__retres1~0#1 := 0; 970647#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 972011#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 971889#L1350 assume !(0 != activate_threads_~tmp~1#1); 970999#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 971000#L544 assume !(1 == ~t1_pc~0); 971224#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 971225#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 970621#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 970622#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 970847#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 971520#L563 assume !(1 == ~t2_pc~0); 971732#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 970665#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 970666#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 971077#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 971078#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 971613#L582 assume !(1 == ~t3_pc~0); 971746#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 972141#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 970550#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 970551#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 970729#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 970730#L601 assume !(1 == ~t4_pc~0); 971762#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 971227#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 970739#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 970740#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 971756#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 972133#L620 assume !(1 == ~t5_pc~0); 971571#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 971572#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 971631#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 971927#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 972150#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 972151#L639 assume !(1 == ~t6_pc~0); 971554#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 971118#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 971119#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 971173#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 971233#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 971234#L658 assume !(1 == ~t7_pc~0); 971458#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 971459#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 972161#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 971687#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 971002#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 971003#L677 assume !(1 == ~t8_pc~0); 971025#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 970805#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 970806#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 971073#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 971074#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 971879#L696 assume !(1 == ~t9_pc~0); 971533#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 971534#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 971287#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 971288#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 971561#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 971802#L715 assume !(1 == ~t10_pc~0); 972099#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 971667#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 971446#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 971447#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 971383#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 970799#L734 assume !(1 == ~t11_pc~0); 970800#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 971307#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 971393#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 970546#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 970547#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 971632#L1213 assume !(1 == ~M_E~0); 971380#L1213-2 assume !(1 == ~T1_E~0); 971381#L1218-1 assume !(1 == ~T2_E~0); 970581#L1223-1 assume !(1 == ~T3_E~0); 970582#L1228-1 assume !(1 == ~T4_E~0); 971354#L1233-1 assume !(1 == ~T5_E~0); 972152#L1238-1 assume !(1 == ~T6_E~0); 971754#L1243-1 assume !(1 == ~T7_E~0); 971755#L1248-1 assume !(1 == ~T8_E~0); 971808#L1253-1 assume !(1 == ~T9_E~0); 971809#L1258-1 assume !(1 == ~T10_E~0); 971780#L1263-1 assume !(1 == ~T11_E~0); 971781#L1268-1 assume !(1 == ~E_1~0); 971579#L1273-1 assume !(1 == ~E_2~0); 971580#L1278-1 assume !(1 == ~E_3~0); 971116#L1283-1 assume !(1 == ~E_4~0); 971117#L1288-1 assume !(1 == ~E_5~0); 971936#L1293-1 assume !(1 == ~E_6~0); 971885#L1298-1 assume !(1 == ~E_7~0); 971617#L1303-1 assume !(1 == ~E_8~0); 971129#L1308-1 assume !(1 == ~E_9~0); 971018#L1313-1 assume !(1 == ~E_10~0); 971019#L1318-1 assume !(1 == ~E_11~0); 971026#L1323-1 assume { :end_inline_reset_delta_events } true; 971027#L1644-2 [2024-11-20 22:59:32,439 INFO L747 eck$LassoCheckResult]: Loop: 971027#L1644-2 assume !false; 979279#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 979274#L1065-1 assume !false; 979272#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 979263#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 979252#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 979250#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 978345#L906 assume !(0 != eval_~tmp~0#1); 978346#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 979925#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 979923#L1090-3 assume !(0 == ~M_E~0); 979921#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 979919#L1095-3 assume !(0 == ~T2_E~0); 979916#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 979914#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 979912#L1110-3 assume !(0 == ~T5_E~0); 979910#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 979908#L1120-3 assume !(0 == ~T7_E~0); 979905#L1125-3 assume !(0 == ~T8_E~0); 979903#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 979901#L1135-3 assume !(0 == ~T10_E~0); 979899#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 979897#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 979895#L1150-3 assume !(0 == ~E_2~0); 979893#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 979891#L1160-3 assume !(0 == ~E_4~0); 979889#L1165-3 assume !(0 == ~E_5~0); 979887#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 979885#L1175-3 assume !(0 == ~E_7~0); 979883#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 979879#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 979877#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 979875#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 979873#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 979870#L525-36 assume 1 == ~m_pc~0; 979868#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 979869#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 979938#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 979859#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 979857#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 979855#L544-36 assume !(1 == ~t1_pc~0); 979853#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 979851#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 979848#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 979846#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 979844#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 979837#L563-36 assume !(1 == ~t2_pc~0); 979835#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 979833#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 979830#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 979829#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 979828#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 979825#L582-36 assume !(1 == ~t3_pc~0); 979821#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 979817#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 979813#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 979809#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 979805#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 979801#L601-36 assume !(1 == ~t4_pc~0); 979796#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 979792#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 979791#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 979790#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 979788#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 979787#L620-36 assume !(1 == ~t5_pc~0); 979786#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 979785#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 979784#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 979783#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 979782#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 979781#L639-36 assume !(1 == ~t6_pc~0); 979780#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 979778#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 979777#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 979776#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 979775#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 979773#L658-36 assume !(1 == ~t7_pc~0); 979771#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 979770#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 979769#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 979767#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 979766#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 979765#L677-36 assume !(1 == ~t8_pc~0); 979764#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 979760#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 979758#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 979756#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 979754#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 979748#L696-36 assume 1 == ~t9_pc~0; 979749#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 979750#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 979774#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 979738#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 979736#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 979734#L715-36 assume !(1 == ~t10_pc~0); 979731#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 979729#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 979728#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 979727#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 979726#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 979725#L734-36 assume 1 == ~t11_pc~0; 979724#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 979722#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 979721#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 979720#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 979719#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 979718#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 979716#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 979715#L1218-3 assume !(1 == ~T2_E~0); 979714#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 979713#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 979709#L1233-3 assume !(1 == ~T5_E~0); 979707#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 979705#L1243-3 assume !(1 == ~T7_E~0); 979703#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 979700#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 979698#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 979696#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 979694#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 979692#L1273-3 assume !(1 == ~E_2~0); 979690#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 979688#L1283-3 assume !(1 == ~E_4~0); 979686#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 979683#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 979681#L1298-3 assume !(1 == ~E_7~0); 979679#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 979677#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 979675#L1313-3 assume !(1 == ~E_10~0); 979673#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 979671#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 979654#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 979647#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 979645#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 979514#L1663 assume !(0 == start_simulation_~tmp~3#1); 979512#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 979306#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 979295#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 979291#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 979289#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 979287#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 979285#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 979282#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 971027#L1644-2 [2024-11-20 22:59:32,439 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:32,439 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 3 times [2024-11-20 22:59:32,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:32,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336833934] [2024-11-20 22:59:32,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:32,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:32,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:32,449 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-20 22:59:32,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:32,480 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-20 22:59:32,481 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:32,481 INFO L85 PathProgramCache]: Analyzing trace with hash -1084917654, now seen corresponding path program 1 times [2024-11-20 22:59:32,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:32,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422242319] [2024-11-20 22:59:32,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:32,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:32,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:32,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:32,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:32,508 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [422242319] [2024-11-20 22:59:32,508 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [422242319] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:32,508 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:32,508 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:32,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172312676] [2024-11-20 22:59:32,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:32,508 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:32,508 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:32,509 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:32,509 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:32,509 INFO L87 Difference]: Start difference. First operand 37078 states and 50928 transitions. cyclomatic complexity: 13882 Second operand has 3 states, 3 states have (on average 47.333333333333336) internal successors, (142), 3 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:32,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:32,898 INFO L93 Difference]: Finished difference Result 54939 states and 75292 transitions. [2024-11-20 22:59:32,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54939 states and 75292 transitions. [2024-11-20 22:59:33,075 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 54480 [2024-11-20 22:59:33,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54939 states to 54939 states and 75292 transitions. [2024-11-20 22:59:33,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54939 [2024-11-20 22:59:33,227 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54939 [2024-11-20 22:59:33,227 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54939 states and 75292 transitions. [2024-11-20 22:59:33,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:33,258 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54939 states and 75292 transitions. [2024-11-20 22:59:33,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54939 states and 75292 transitions. [2024-11-20 22:59:33,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54939 to 54923. [2024-11-20 22:59:33,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54923 states, 54923 states have (on average 1.3705733481419442) internal successors, (75276), 54922 states have internal predecessors, (75276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:33,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54923 states to 54923 states and 75276 transitions. [2024-11-20 22:59:33,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54923 states and 75276 transitions. [2024-11-20 22:59:33,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:33,730 INFO L425 stractBuchiCegarLoop]: Abstraction has 54923 states and 75276 transitions. [2024-11-20 22:59:33,730 INFO L332 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2024-11-20 22:59:33,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54923 states and 75276 transitions. [2024-11-20 22:59:34,030 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 54464 [2024-11-20 22:59:34,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:34,031 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:34,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:34,033 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:34,033 INFO L745 eck$LassoCheckResult]: Stem: 1062988#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1062989#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1064149#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1064150#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1063462#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1063463#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1063329#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1063217#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1062929#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1062581#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1062582#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1062626#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1062627#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1063624#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1063625#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1063679#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1063036#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1063037#L1090 assume !(0 == ~M_E~0); 1063086#L1090-2 assume !(0 == ~T1_E~0); 1063087#L1095-1 assume !(0 == ~T2_E~0); 1063851#L1100-1 assume !(0 == ~T3_E~0); 1063852#L1105-1 assume !(0 == ~T4_E~0); 1062848#L1110-1 assume !(0 == ~T5_E~0); 1062849#L1115-1 assume !(0 == ~T6_E~0); 1063258#L1120-1 assume !(0 == ~T7_E~0); 1063592#L1125-1 assume !(0 == ~T8_E~0); 1064274#L1130-1 assume !(0 == ~T9_E~0); 1063877#L1135-1 assume !(0 == ~T10_E~0); 1063043#L1140-1 assume !(0 == ~T11_E~0); 1063044#L1145-1 assume !(0 == ~E_1~0); 1063797#L1150-1 assume !(0 == ~E_2~0); 1063233#L1155-1 assume !(0 == ~E_3~0); 1063234#L1160-1 assume !(0 == ~E_4~0); 1063334#L1165-1 assume !(0 == ~E_5~0); 1063335#L1170-1 assume !(0 == ~E_6~0); 1064122#L1175-1 assume !(0 == ~E_7~0); 1063420#L1180-1 assume !(0 == ~E_8~0); 1063421#L1185-1 assume !(0 == ~E_9~0); 1063038#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 1063039#L1195-1 assume !(0 == ~E_11~0); 1064086#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1064087#L525 assume !(1 == ~m_pc~0); 1064401#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1064399#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1064397#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1064394#L1350 assume !(0 != activate_threads_~tmp~1#1); 1064393#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1063495#L544 assume !(1 == ~t1_pc~0); 1063496#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1063793#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1063794#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1062870#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1062871#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1064392#L563 assume !(1 == ~t2_pc~0); 1063779#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1063780#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1063229#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1063230#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1063647#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1063648#L582 assume !(1 == ~t3_pc~0); 1064276#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1064277#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1064390#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1064133#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1062755#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1062756#L601 assume !(1 == ~t4_pc~0); 1064387#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1063259#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1062767#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1062768#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1063808#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1064207#L620 assume !(1 == ~t5_pc~0); 1064208#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1063669#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1063670#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1063988#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1064232#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1064233#L639 assume !(1 == ~t6_pc~0); 1063588#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1063589#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1063201#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1063202#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1064383#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1064382#L658 assume !(1 == ~t7_pc~0); 1063493#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1063494#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1064290#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1064291#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1064380#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1064379#L677 assume !(1 == ~t8_pc~0); 1063054#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1063055#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1064378#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1063106#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1063107#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1063937#L696 assume !(1 == ~t9_pc~0); 1063572#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1063573#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1064396#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1063601#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1063602#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1063858#L715 assume !(1 == ~t10_pc~0); 1064168#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1063705#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1063478#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1063479#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1064362#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1062824#L734 assume !(1 == ~t11_pc~0); 1062825#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1063336#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1063425#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1062569#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1062570#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1063671#L1213 assume !(1 == ~M_E~0); 1064355#L1213-2 assume !(1 == ~T1_E~0); 1064354#L1218-1 assume !(1 == ~T2_E~0); 1064353#L1223-1 assume !(1 == ~T3_E~0); 1064352#L1228-1 assume !(1 == ~T4_E~0); 1064234#L1233-1 assume !(1 == ~T5_E~0); 1064235#L1238-1 assume !(1 == ~T6_E~0); 1063806#L1243-1 assume !(1 == ~T7_E~0); 1063807#L1248-1 assume !(1 == ~T8_E~0); 1064349#L1253-1 assume !(1 == ~T9_E~0); 1064137#L1258-1 assume !(1 == ~T10_E~0); 1063833#L1263-1 assume !(1 == ~T11_E~0); 1063834#L1268-1 assume !(1 == ~E_1~0); 1063617#L1273-1 assume !(1 == ~E_2~0); 1063618#L1278-1 assume !(1 == ~E_3~0); 1063147#L1283-1 assume !(1 == ~E_4~0); 1063148#L1288-1 assume !(1 == ~E_5~0); 1064347#L1293-1 assume !(1 == ~E_6~0); 1064346#L1298-1 assume !(1 == ~E_7~0); 1063652#L1303-1 assume !(1 == ~E_8~0); 1063157#L1308-1 assume !(1 == ~E_9~0); 1063047#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1063048#L1318-1 assume !(1 == ~E_11~0); 1063056#L1323-1 assume { :end_inline_reset_delta_events } true; 1063057#L1644-2 [2024-11-20 22:59:34,033 INFO L747 eck$LassoCheckResult]: Loop: 1063057#L1644-2 assume !false; 1069745#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1069734#L1065-1 assume !false; 1069727#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1069694#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1069683#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1069681#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1069678#L906 assume !(0 != eval_~tmp~0#1); 1069679#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1070913#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1070912#L1090-3 assume !(0 == ~M_E~0); 1070911#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1070910#L1095-3 assume !(0 == ~T2_E~0); 1070909#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1070908#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1070907#L1110-3 assume !(0 == ~T5_E~0); 1070906#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1070904#L1120-3 assume !(0 == ~T7_E~0); 1070901#L1125-3 assume !(0 == ~T8_E~0); 1070898#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1070895#L1135-3 assume !(0 == ~T10_E~0); 1070891#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1070887#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1070883#L1150-3 assume !(0 == ~E_2~0); 1070878#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1070873#L1160-3 assume !(0 == ~E_4~0); 1070870#L1165-3 assume !(0 == ~E_5~0); 1070865#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1070859#L1175-3 assume !(0 == ~E_7~0); 1070852#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1070846#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1070839#L1190-3 assume !(0 == ~E_10~0); 1070834#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1070827#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1070820#L525-36 assume 1 == ~m_pc~0; 1070813#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1070806#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1070800#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1070793#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1070787#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1070782#L544-36 assume !(1 == ~t1_pc~0); 1070778#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1070773#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1070768#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1070762#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1070758#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1070753#L563-36 assume !(1 == ~t2_pc~0); 1070749#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1070744#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1070740#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1070735#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1070729#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1070723#L582-36 assume !(1 == ~t3_pc~0); 1070717#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1070711#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1070705#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1070699#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1070693#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1070686#L601-36 assume !(1 == ~t4_pc~0); 1070680#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1070675#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1070670#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1070665#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1070658#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1070652#L620-36 assume !(1 == ~t5_pc~0); 1070647#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1070642#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1070638#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1070635#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1070631#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1070626#L639-36 assume 1 == ~t6_pc~0; 1070620#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1070613#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1070605#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1070597#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1070590#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1070584#L658-36 assume !(1 == ~t7_pc~0); 1070578#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1070573#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1070568#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1070563#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1070557#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1070553#L677-36 assume !(1 == ~t8_pc~0); 1070548#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1070543#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1070539#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1070535#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1070529#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1070522#L696-36 assume 1 == ~t9_pc~0; 1070514#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1070506#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1070499#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1070493#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1070488#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1070483#L715-36 assume !(1 == ~t10_pc~0); 1070477#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1070471#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1070466#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1070461#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1070454#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1070449#L734-36 assume !(1 == ~t11_pc~0); 1070443#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1070438#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1070433#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1070428#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1070423#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1070418#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1070413#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1070407#L1218-3 assume !(1 == ~T2_E~0); 1070401#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1070396#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1070392#L1233-3 assume !(1 == ~T5_E~0); 1070388#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1070383#L1243-3 assume !(1 == ~T7_E~0); 1070377#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1070371#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1070365#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1070359#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1070353#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1070348#L1273-3 assume !(1 == ~E_2~0); 1070343#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1070339#L1283-3 assume !(1 == ~E_4~0); 1070335#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1070318#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1070309#L1298-3 assume !(1 == ~E_7~0); 1070294#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1070287#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1070281#L1313-3 assume !(1 == ~E_10~0); 1070277#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1070274#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1070077#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1070064#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1070057#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1070049#L1663 assume !(0 == start_simulation_~tmp~3#1); 1070044#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1069867#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1069852#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1069843#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1069834#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1069824#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1069823#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1069760#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1063057#L1644-2 [2024-11-20 22:59:34,034 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:34,034 INFO L85 PathProgramCache]: Analyzing trace with hash 735969430, now seen corresponding path program 1 times [2024-11-20 22:59:34,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:34,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552852354] [2024-11-20 22:59:34,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:34,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:34,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:34,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:34,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:34,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552852354] [2024-11-20 22:59:34,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552852354] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:34,083 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:34,083 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:34,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039686026] [2024-11-20 22:59:34,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:34,084 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-20 22:59:34,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:34,084 INFO L85 PathProgramCache]: Analyzing trace with hash -107412180, now seen corresponding path program 1 times [2024-11-20 22:59:34,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:34,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255949477] [2024-11-20 22:59:34,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:34,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:34,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:34,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:34,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:34,133 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1255949477] [2024-11-20 22:59:34,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1255949477] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:34,134 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:34,134 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-20 22:59:34,134 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455585165] [2024-11-20 22:59:34,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:34,134 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:34,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:34,135 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-20 22:59:34,135 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-20 22:59:34,135 INFO L87 Difference]: Start difference. First operand 54923 states and 75276 transitions. cyclomatic complexity: 20385 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:34,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:34,517 INFO L93 Difference]: Finished difference Result 103096 states and 141346 transitions. [2024-11-20 22:59:34,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103096 states and 141346 transitions. [2024-11-20 22:59:34,979 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 99808 [2024-11-20 22:59:35,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103096 states to 103096 states and 141346 transitions. [2024-11-20 22:59:35,290 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 103096 [2024-11-20 22:59:35,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 103096 [2024-11-20 22:59:35,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 103096 states and 141346 transitions. [2024-11-20 22:59:35,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:35,456 INFO L218 hiAutomatonCegarLoop]: Abstraction has 103096 states and 141346 transitions. [2024-11-20 22:59:35,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103096 states and 141346 transitions. [2024-11-20 22:59:36,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103096 to 53038. [2024-11-20 22:59:36,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53038 states, 53038 states have (on average 1.3694143821411064) internal successors, (72631), 53037 states have internal predecessors, (72631), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:36,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53038 states to 53038 states and 72631 transitions. [2024-11-20 22:59:36,694 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53038 states and 72631 transitions. [2024-11-20 22:59:36,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-20 22:59:36,695 INFO L425 stractBuchiCegarLoop]: Abstraction has 53038 states and 72631 transitions. [2024-11-20 22:59:36,695 INFO L332 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2024-11-20 22:59:36,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53038 states and 72631 transitions. [2024-11-20 22:59:36,823 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52688 [2024-11-20 22:59:36,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:36,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:36,825 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:36,825 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:36,825 INFO L745 eck$LassoCheckResult]: Stem: 1221021#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1221022#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1222131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1222132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1221485#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1221486#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1221354#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1221249#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1220964#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1220612#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1220613#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1220657#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1220658#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1221635#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1221636#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1221685#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1221066#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1221067#L1090 assume !(0 == ~M_E~0); 1221113#L1090-2 assume !(0 == ~T1_E~0); 1221114#L1095-1 assume !(0 == ~T2_E~0); 1221850#L1100-1 assume !(0 == ~T3_E~0); 1221851#L1105-1 assume !(0 == ~T4_E~0); 1220881#L1110-1 assume !(0 == ~T5_E~0); 1220882#L1115-1 assume !(0 == ~T6_E~0); 1221284#L1120-1 assume !(0 == ~T7_E~0); 1221610#L1125-1 assume !(0 == ~T8_E~0); 1222257#L1130-1 assume !(0 == ~T9_E~0); 1221873#L1135-1 assume !(0 == ~T10_E~0); 1221072#L1140-1 assume !(0 == ~T11_E~0); 1221073#L1145-1 assume !(0 == ~E_1~0); 1221801#L1150-1 assume !(0 == ~E_2~0); 1221264#L1155-1 assume !(0 == ~E_3~0); 1221265#L1160-1 assume !(0 == ~E_4~0); 1221361#L1165-1 assume !(0 == ~E_5~0); 1221362#L1170-1 assume !(0 == ~E_6~0); 1222108#L1175-1 assume !(0 == ~E_7~0); 1221444#L1180-1 assume !(0 == ~E_8~0); 1221445#L1185-1 assume !(0 == ~E_9~0); 1221068#L1190-1 assume !(0 == ~E_10~0); 1221069#L1195-1 assume !(0 == ~E_11~0); 1221460#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1221277#L525 assume !(1 == ~m_pc~0); 1220700#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1220701#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1222066#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1221930#L1350 assume !(0 != activate_threads_~tmp~1#1); 1221057#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1221058#L544 assume !(1 == ~t1_pc~0); 1221282#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1221283#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1220675#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1220676#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1220905#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1221577#L563 assume !(1 == ~t2_pc~0); 1221785#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1220722#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1220723#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1221139#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1221140#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1221662#L582 assume !(1 == ~t3_pc~0); 1221800#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1222197#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1220604#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1220605#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1220787#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1220788#L601 assume !(1 == ~t4_pc~0); 1221815#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1221285#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1220797#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1220798#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1221810#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1222184#L620 assume !(1 == ~t5_pc~0); 1221624#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1221625#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1221682#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1221969#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1222210#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1222211#L639 assume !(1 == ~t6_pc~0); 1221608#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1221180#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1221181#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1221232#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1221291#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1221292#L658 assume !(1 == ~t7_pc~0); 1221509#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1221510#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1222225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1221736#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1221061#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1221062#L677 assume !(1 == ~t8_pc~0); 1221085#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1220864#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1220865#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1221135#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1221136#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1221921#L696 assume !(1 == ~t9_pc~0); 1221590#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1221591#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1221344#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1221345#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1221615#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1221855#L715 assume !(1 == ~t10_pc~0); 1222152#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1221716#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1221497#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1221498#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1221437#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1220858#L734 assume !(1 == ~t11_pc~0); 1220859#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1221363#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1221447#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1220600#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1220601#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1221683#L1213 assume !(1 == ~M_E~0); 1221433#L1213-2 assume !(1 == ~T1_E~0); 1221434#L1218-1 assume !(1 == ~T2_E~0); 1220635#L1223-1 assume !(1 == ~T3_E~0); 1220636#L1228-1 assume !(1 == ~T4_E~0); 1221407#L1233-1 assume !(1 == ~T5_E~0); 1222212#L1238-1 assume !(1 == ~T6_E~0); 1221808#L1243-1 assume !(1 == ~T7_E~0); 1221809#L1248-1 assume !(1 == ~T8_E~0); 1221860#L1253-1 assume !(1 == ~T9_E~0); 1221861#L1258-1 assume !(1 == ~T10_E~0); 1221834#L1263-1 assume !(1 == ~T11_E~0); 1221835#L1268-1 assume !(1 == ~E_1~0); 1221632#L1273-1 assume !(1 == ~E_2~0); 1221633#L1278-1 assume !(1 == ~E_3~0); 1221178#L1283-1 assume !(1 == ~E_4~0); 1221179#L1288-1 assume !(1 == ~E_5~0); 1221976#L1293-1 assume !(1 == ~E_6~0); 1221925#L1298-1 assume !(1 == ~E_7~0); 1221667#L1303-1 assume !(1 == ~E_8~0); 1221189#L1308-1 assume !(1 == ~E_9~0); 1221076#L1313-1 assume !(1 == ~E_10~0); 1221077#L1318-1 assume !(1 == ~E_11~0); 1221086#L1323-1 assume { :end_inline_reset_delta_events } true; 1221087#L1644-2 [2024-11-20 22:59:36,825 INFO L747 eck$LassoCheckResult]: Loop: 1221087#L1644-2 assume !false; 1233605#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1233600#L1065-1 assume !false; 1233597#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1233590#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1233579#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1233577#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1233574#L906 assume !(0 != eval_~tmp~0#1); 1233575#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1234040#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1234038#L1090-3 assume !(0 == ~M_E~0); 1234035#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1234033#L1095-3 assume !(0 == ~T2_E~0); 1234031#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1234029#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1234027#L1110-3 assume !(0 == ~T5_E~0); 1234025#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1234023#L1120-3 assume !(0 == ~T7_E~0); 1234021#L1125-3 assume !(0 == ~T8_E~0); 1234019#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1234017#L1135-3 assume !(0 == ~T10_E~0); 1234015#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1234013#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1234010#L1150-3 assume !(0 == ~E_2~0); 1234008#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1234006#L1160-3 assume !(0 == ~E_4~0); 1234004#L1165-3 assume !(0 == ~E_5~0); 1234002#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1234000#L1175-3 assume !(0 == ~E_7~0); 1233998#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1233996#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1233994#L1190-3 assume !(0 == ~E_10~0); 1233992#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1233990#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1233988#L525-36 assume 1 == ~m_pc~0; 1233986#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1233987#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1234049#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1233976#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1233974#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1233972#L544-36 assume !(1 == ~t1_pc~0); 1233970#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1233967#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1233965#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1233963#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1233961#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1233957#L563-36 assume !(1 == ~t2_pc~0); 1233955#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1233953#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1233951#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1233949#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1233947#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1233943#L582-36 assume !(1 == ~t3_pc~0); 1233941#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1233939#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1233937#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1233934#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1233932#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1233930#L601-36 assume !(1 == ~t4_pc~0); 1233927#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1233925#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1233923#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1233921#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1233919#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1233917#L620-36 assume !(1 == ~t5_pc~0); 1233914#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1233912#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1233910#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1233908#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1233906#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1233905#L639-36 assume 1 == ~t6_pc~0; 1233900#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1233898#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1233896#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1233893#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1233892#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1233891#L658-36 assume !(1 == ~t7_pc~0); 1233889#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1233886#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1233882#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1233878#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1233874#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1233870#L677-36 assume !(1 == ~t8_pc~0); 1233869#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1233868#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1233867#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1233866#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1233865#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1233864#L696-36 assume !(1 == ~t9_pc~0); 1233862#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1233860#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1233858#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1233857#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1233855#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1233854#L715-36 assume !(1 == ~t10_pc~0); 1233853#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1233852#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1233851#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1233850#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1233849#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1233848#L734-36 assume !(1 == ~t11_pc~0); 1233846#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1233845#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1233844#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1233842#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1233841#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1233840#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1233839#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1233835#L1218-3 assume !(1 == ~T2_E~0); 1233833#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1233831#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1233829#L1233-3 assume !(1 == ~T5_E~0); 1233826#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1233824#L1243-3 assume !(1 == ~T7_E~0); 1233822#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1233820#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1233818#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1233816#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1233814#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1233812#L1273-3 assume !(1 == ~E_2~0); 1233809#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1233807#L1283-3 assume !(1 == ~E_4~0); 1233805#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1233803#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1233801#L1298-3 assume !(1 == ~E_7~0); 1233799#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1233797#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1233795#L1313-3 assume !(1 == ~E_10~0); 1233793#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1233791#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1233774#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1233767#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1233765#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1233640#L1663 assume !(0 == start_simulation_~tmp~3#1); 1233638#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1233631#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1233620#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1233618#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1233616#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1233614#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1233612#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1233608#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1221087#L1644-2 [2024-11-20 22:59:36,826 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:36,826 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 4 times [2024-11-20 22:59:36,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:36,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406057550] [2024-11-20 22:59:36,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:36,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:36,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:36,838 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-20 22:59:36,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:36,874 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-20 22:59:36,874 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:36,874 INFO L85 PathProgramCache]: Analyzing trace with hash -485691191, now seen corresponding path program 1 times [2024-11-20 22:59:36,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:36,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656382793] [2024-11-20 22:59:36,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:36,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:36,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:36,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:36,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:36,912 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1656382793] [2024-11-20 22:59:36,912 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1656382793] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:36,912 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:36,912 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-20 22:59:36,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1471799501] [2024-11-20 22:59:36,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:36,913 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:36,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:36,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-20 22:59:36,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-20 22:59:36,914 INFO L87 Difference]: Start difference. First operand 53038 states and 72631 transitions. cyclomatic complexity: 19625 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:37,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:37,098 INFO L93 Difference]: Finished difference Result 53310 states and 72903 transitions. [2024-11-20 22:59:37,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53310 states and 72903 transitions. [2024-11-20 22:59:37,314 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52960 [2024-11-20 22:59:37,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53310 states to 53310 states and 72903 transitions. [2024-11-20 22:59:37,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53310 [2024-11-20 22:59:37,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53310 [2024-11-20 22:59:37,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53310 states and 72903 transitions. [2024-11-20 22:59:38,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:38,082 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53310 states and 72903 transitions. [2024-11-20 22:59:38,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53310 states and 72903 transitions. [2024-11-20 22:59:38,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53310 to 53182. [2024-11-20 22:59:38,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53182 states, 53182 states have (on average 1.3684141250799142) internal successors, (72775), 53181 states have internal predecessors, (72775), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:38,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53182 states to 53182 states and 72775 transitions. [2024-11-20 22:59:38,578 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53182 states and 72775 transitions. [2024-11-20 22:59:38,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-20 22:59:38,579 INFO L425 stractBuchiCegarLoop]: Abstraction has 53182 states and 72775 transitions. [2024-11-20 22:59:38,579 INFO L332 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2024-11-20 22:59:38,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53182 states and 72775 transitions. [2024-11-20 22:59:38,705 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52832 [2024-11-20 22:59:38,705 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:38,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:38,707 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:38,707 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:38,707 INFO L745 eck$LassoCheckResult]: Stem: 1327371#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1327372#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1328464#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1328465#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1327832#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1327833#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1327701#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1327593#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1327314#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1326968#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1326969#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1327013#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1327014#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1327989#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1327990#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1328043#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1327415#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1327416#L1090 assume !(0 == ~M_E~0); 1327462#L1090-2 assume !(0 == ~T1_E~0); 1327463#L1095-1 assume !(0 == ~T2_E~0); 1328207#L1100-1 assume !(0 == ~T3_E~0); 1328208#L1105-1 assume !(0 == ~T4_E~0); 1327235#L1110-1 assume !(0 == ~T5_E~0); 1327236#L1115-1 assume !(0 == ~T6_E~0); 1327632#L1120-1 assume !(0 == ~T7_E~0); 1327958#L1125-1 assume !(0 == ~T8_E~0); 1328586#L1130-1 assume !(0 == ~T9_E~0); 1328232#L1135-1 assume !(0 == ~T10_E~0); 1327419#L1140-1 assume !(0 == ~T11_E~0); 1327420#L1145-1 assume !(0 == ~E_1~0); 1328157#L1150-1 assume !(0 == ~E_2~0); 1327608#L1155-1 assume !(0 == ~E_3~0); 1327609#L1160-1 assume !(0 == ~E_4~0); 1327706#L1165-1 assume !(0 == ~E_5~0); 1327707#L1170-1 assume !(0 == ~E_6~0); 1328442#L1175-1 assume !(0 == ~E_7~0); 1327789#L1180-1 assume !(0 == ~E_8~0); 1327790#L1185-1 assume !(0 == ~E_9~0); 1327413#L1190-1 assume !(0 == ~E_10~0); 1327414#L1195-1 assume !(0 == ~E_11~0); 1327805#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1327627#L525 assume !(1 == ~m_pc~0); 1327058#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1327059#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1328406#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1328290#L1350 assume !(0 != activate_threads_~tmp~1#1); 1327405#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1327406#L544 assume !(1 == ~t1_pc~0); 1327628#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1327629#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1327034#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1327035#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1327257#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1327922#L563 assume !(1 == ~t2_pc~0); 1328143#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1327077#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1327078#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1327488#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1327489#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1328012#L582 assume !(1 == ~t3_pc~0); 1328155#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1328532#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1326960#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1326961#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1327142#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1327143#L601 assume !(1 == ~t4_pc~0); 1328172#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1327633#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1327154#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1327155#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1328165#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1328526#L620 assume !(1 == ~t5_pc~0); 1327975#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1327976#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1328033#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1328328#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1328542#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1328543#L639 assume !(1 == ~t6_pc~0); 1327957#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1327527#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1327528#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1327577#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1327636#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1327637#L658 assume !(1 == ~t7_pc~0); 1327858#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1327859#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1328554#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1328091#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1327408#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1327409#L677 assume !(1 == ~t8_pc~0); 1327430#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1327220#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1327221#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1327480#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1327481#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1328281#L696 assume !(1 == ~t9_pc~0); 1327937#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1327938#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1327692#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1327693#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1327966#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1328213#L715 assume !(1 == ~t10_pc~0); 1328484#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1328069#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1327844#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1327845#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1327782#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1327212#L734 assume !(1 == ~t11_pc~0); 1327213#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1327708#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1327794#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1326958#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1326959#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1328034#L1213 assume !(1 == ~M_E~0); 1327779#L1213-2 assume !(1 == ~T1_E~0); 1327780#L1218-1 assume !(1 == ~T2_E~0); 1326991#L1223-1 assume !(1 == ~T3_E~0); 1326992#L1228-1 assume !(1 == ~T4_E~0); 1327752#L1233-1 assume !(1 == ~T5_E~0); 1328544#L1238-1 assume !(1 == ~T6_E~0); 1328163#L1243-1 assume !(1 == ~T7_E~0); 1328164#L1248-1 assume !(1 == ~T8_E~0); 1328218#L1253-1 assume !(1 == ~T9_E~0); 1328219#L1258-1 assume !(1 == ~T10_E~0); 1328190#L1263-1 assume !(1 == ~T11_E~0); 1328191#L1268-1 assume !(1 == ~E_1~0); 1327982#L1273-1 assume !(1 == ~E_2~0); 1327983#L1278-1 assume !(1 == ~E_3~0); 1327523#L1283-1 assume !(1 == ~E_4~0); 1327524#L1288-1 assume !(1 == ~E_5~0); 1328332#L1293-1 assume !(1 == ~E_6~0); 1328286#L1298-1 assume !(1 == ~E_7~0); 1328016#L1303-1 assume !(1 == ~E_8~0); 1327535#L1308-1 assume !(1 == ~E_9~0); 1327423#L1313-1 assume !(1 == ~E_10~0); 1327424#L1318-1 assume !(1 == ~E_11~0); 1327431#L1323-1 assume { :end_inline_reset_delta_events } true; 1327432#L1644-2 [2024-11-20 22:59:38,707 INFO L747 eck$LassoCheckResult]: Loop: 1327432#L1644-2 assume !false; 1349691#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1349688#L1065-1 assume !false; 1349684#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1349550#L829 assume !(0 == ~m_st~0); 1349551#L833 assume !(0 == ~t1_st~0); 1349540#L837 assume !(0 == ~t2_st~0); 1349541#L841 assume !(0 == ~t3_st~0); 1349544#L845 assume !(0 == ~t4_st~0); 1349546#L849 assume !(0 == ~t5_st~0); 1349548#L853 assume !(0 == ~t6_st~0); 1349549#L857 assume !(0 == ~t7_st~0); 1349552#L861 assume !(0 == ~t8_st~0); 1349542#L865 assume !(0 == ~t9_st~0); 1349543#L869 assume !(0 == ~t10_st~0); 1349545#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 1349547#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1348622#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1348623#L906 assume !(0 != eval_~tmp~0#1); 1351475#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1351474#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1351473#L1090-3 assume !(0 == ~M_E~0); 1351472#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1351471#L1095-3 assume !(0 == ~T2_E~0); 1351470#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1351469#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1351468#L1110-3 assume !(0 == ~T5_E~0); 1351467#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1351466#L1120-3 assume !(0 == ~T7_E~0); 1351465#L1125-3 assume !(0 == ~T8_E~0); 1351464#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1351463#L1135-3 assume !(0 == ~T10_E~0); 1351462#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1351461#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1351460#L1150-3 assume !(0 == ~E_2~0); 1351459#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1351458#L1160-3 assume !(0 == ~E_4~0); 1351457#L1165-3 assume !(0 == ~E_5~0); 1351456#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1351455#L1175-3 assume !(0 == ~E_7~0); 1351454#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1351453#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1351452#L1190-3 assume !(0 == ~E_10~0); 1351451#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1351450#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1351449#L525-36 assume 1 == ~m_pc~0; 1351447#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1351445#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1351443#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1351441#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1351440#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1351439#L544-36 assume !(1 == ~t1_pc~0); 1351438#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1351437#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1351436#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1351435#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1351434#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1351432#L563-36 assume !(1 == ~t2_pc~0); 1351431#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1351430#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1351429#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1351428#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1351427#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1351426#L582-36 assume !(1 == ~t3_pc~0); 1351425#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1351424#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1351423#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1351422#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1351421#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1351420#L601-36 assume !(1 == ~t4_pc~0); 1351418#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1351417#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1351416#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1351415#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1351414#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1351413#L620-36 assume !(1 == ~t5_pc~0); 1351412#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1351411#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1351410#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1351409#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1351408#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1351407#L639-36 assume 1 == ~t6_pc~0; 1351405#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1351404#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1351403#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1351402#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1351401#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1351400#L658-36 assume !(1 == ~t7_pc~0); 1351398#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1351397#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1351396#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1351395#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1351394#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1351393#L677-36 assume !(1 == ~t8_pc~0); 1351392#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1351391#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1351390#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1351389#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1351388#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1351387#L696-36 assume 1 == ~t9_pc~0; 1351385#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1351383#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1351381#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1351379#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1351378#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1351377#L715-36 assume !(1 == ~t10_pc~0); 1351376#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1351375#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1351374#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1351373#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1351372#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1351371#L734-36 assume !(1 == ~t11_pc~0); 1351369#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1351368#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1351367#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1351366#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1351365#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1351364#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1351363#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1351362#L1218-3 assume !(1 == ~T2_E~0); 1351361#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1351360#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1351359#L1233-3 assume !(1 == ~T5_E~0); 1351358#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1351357#L1243-3 assume !(1 == ~T7_E~0); 1351356#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1351355#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1351354#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1351353#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1351352#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1351351#L1273-3 assume !(1 == ~E_2~0); 1351350#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1351349#L1283-3 assume !(1 == ~E_4~0); 1351348#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1351347#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1351346#L1298-3 assume !(1 == ~E_7~0); 1351345#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1351344#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1351343#L1313-3 assume !(1 == ~E_10~0); 1351342#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1351341#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1351334#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1351327#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1351091#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1351088#L1663 assume !(0 == start_simulation_~tmp~3#1); 1351087#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1351084#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1350455#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1349720#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1349718#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1349716#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1349714#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1349711#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1327432#L1644-2 [2024-11-20 22:59:38,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:38,708 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 5 times [2024-11-20 22:59:38,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:38,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354218258] [2024-11-20 22:59:38,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:38,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:38,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:38,716 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-20 22:59:38,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:38,747 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-20 22:59:38,747 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:38,747 INFO L85 PathProgramCache]: Analyzing trace with hash 900696634, now seen corresponding path program 1 times [2024-11-20 22:59:38,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:38,748 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804866055] [2024-11-20 22:59:38,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:38,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:38,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:38,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:38,798 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:38,798 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [804866055] [2024-11-20 22:59:38,798 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [804866055] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:38,798 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:38,799 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-20 22:59:38,799 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [668246153] [2024-11-20 22:59:38,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:38,799 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:38,799 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:38,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-20 22:59:38,799 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-20 22:59:38,799 INFO L87 Difference]: Start difference. First operand 53182 states and 72775 transitions. cyclomatic complexity: 19625 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:39,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:39,108 INFO L93 Difference]: Finished difference Result 53938 states and 73302 transitions. [2024-11-20 22:59:39,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53938 states and 73302 transitions. [2024-11-20 22:59:39,299 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 53588 [2024-11-20 22:59:39,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53938 states to 53938 states and 73302 transitions. [2024-11-20 22:59:39,903 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53938 [2024-11-20 22:59:39,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53938 [2024-11-20 22:59:39,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53938 states and 73302 transitions. [2024-11-20 22:59:39,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:39,952 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53938 states and 73302 transitions. [2024-11-20 22:59:39,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53938 states and 73302 transitions. [2024-11-20 22:59:40,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53938 to 53938. [2024-11-20 22:59:40,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53938 states, 53938 states have (on average 1.35900478326968) internal successors, (73302), 53937 states have internal predecessors, (73302), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:40,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53938 states to 53938 states and 73302 transitions. [2024-11-20 22:59:40,424 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53938 states and 73302 transitions. [2024-11-20 22:59:40,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-20 22:59:40,424 INFO L425 stractBuchiCegarLoop]: Abstraction has 53938 states and 73302 transitions. [2024-11-20 22:59:40,425 INFO L332 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2024-11-20 22:59:40,425 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53938 states and 73302 transitions. [2024-11-20 22:59:40,556 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 53588 [2024-11-20 22:59:40,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:40,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:40,558 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:40,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:40,558 INFO L745 eck$LassoCheckResult]: Stem: 1434502#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1434503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1435594#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1435595#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1434965#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1434966#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1434834#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1434726#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1434445#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1434096#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1434097#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1434141#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1434142#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1435110#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1435111#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1435158#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1434545#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1434546#L1090 assume !(0 == ~M_E~0); 1434590#L1090-2 assume !(0 == ~T1_E~0); 1434591#L1095-1 assume !(0 == ~T2_E~0); 1435329#L1100-1 assume !(0 == ~T3_E~0); 1435330#L1105-1 assume !(0 == ~T4_E~0); 1434361#L1110-1 assume !(0 == ~T5_E~0); 1434362#L1115-1 assume !(0 == ~T6_E~0); 1434761#L1120-1 assume !(0 == ~T7_E~0); 1435085#L1125-1 assume !(0 == ~T8_E~0); 1435718#L1130-1 assume !(0 == ~T9_E~0); 1435353#L1135-1 assume !(0 == ~T10_E~0); 1434551#L1140-1 assume !(0 == ~T11_E~0); 1434552#L1145-1 assume !(0 == ~E_1~0); 1435276#L1150-1 assume !(0 == ~E_2~0); 1434740#L1155-1 assume !(0 == ~E_3~0); 1434741#L1160-1 assume !(0 == ~E_4~0); 1434839#L1165-1 assume !(0 == ~E_5~0); 1434840#L1170-1 assume !(0 == ~E_6~0); 1435576#L1175-1 assume !(0 == ~E_7~0); 1434923#L1180-1 assume !(0 == ~E_8~0); 1434924#L1185-1 assume !(0 == ~E_9~0); 1434547#L1190-1 assume !(0 == ~E_10~0); 1434548#L1195-1 assume !(0 == ~E_11~0); 1434939#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1434754#L525 assume !(1 == ~m_pc~0); 1434186#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1434187#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1435540#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1435416#L1350 assume !(0 != activate_threads_~tmp~1#1); 1434537#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1434538#L544 assume !(1 == ~t1_pc~0); 1434759#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1434760#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1434160#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1434161#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1434386#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1435050#L563 assume !(1 == ~t2_pc~0); 1435262#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1434205#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1434206#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1434619#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1434620#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1435136#L582 assume !(1 == ~t3_pc~0); 1435275#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1435663#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1434088#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1434089#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1434269#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1434270#L601 assume !(1 == ~t4_pc~0); 1435294#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1434762#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1434279#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1434280#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1435286#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1435652#L620 assume !(1 == ~t5_pc~0); 1435100#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1435101#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1435155#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1435454#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1435677#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1435678#L639 assume !(1 == ~t6_pc~0); 1435084#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1434659#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1434660#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1434712#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1434767#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1434768#L658 assume !(1 == ~t7_pc~0); 1434990#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1434991#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1435688#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1435210#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1434540#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1434541#L677 assume !(1 == ~t8_pc~0); 1434562#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1434345#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1434346#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1434615#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1434616#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1435406#L696 assume !(1 == ~t9_pc~0); 1435063#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1435064#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1434824#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1434825#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1435090#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1435334#L715 assume !(1 == ~t10_pc~0); 1435612#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1435190#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1434977#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1434978#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1434916#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1434339#L734 assume !(1 == ~t11_pc~0); 1434340#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1434841#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1434926#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1434084#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1434085#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1435156#L1213 assume !(1 == ~M_E~0); 1434913#L1213-2 assume !(1 == ~T1_E~0); 1434914#L1218-1 assume !(1 == ~T2_E~0); 1434119#L1223-1 assume !(1 == ~T3_E~0); 1434120#L1228-1 assume !(1 == ~T4_E~0); 1434886#L1233-1 assume !(1 == ~T5_E~0); 1435679#L1238-1 assume !(1 == ~T6_E~0); 1435284#L1243-1 assume !(1 == ~T7_E~0); 1435285#L1248-1 assume !(1 == ~T8_E~0); 1435338#L1253-1 assume !(1 == ~T9_E~0); 1435339#L1258-1 assume !(1 == ~T10_E~0); 1435311#L1263-1 assume !(1 == ~T11_E~0); 1435312#L1268-1 assume !(1 == ~E_1~0); 1435107#L1273-1 assume !(1 == ~E_2~0); 1435108#L1278-1 assume !(1 == ~E_3~0); 1434657#L1283-1 assume !(1 == ~E_4~0); 1434658#L1288-1 assume !(1 == ~E_5~0); 1435461#L1293-1 assume !(1 == ~E_6~0); 1435412#L1298-1 assume !(1 == ~E_7~0); 1435140#L1303-1 assume !(1 == ~E_8~0); 1434667#L1308-1 assume !(1 == ~E_9~0); 1434555#L1313-1 assume !(1 == ~E_10~0); 1434556#L1318-1 assume !(1 == ~E_11~0); 1434563#L1323-1 assume { :end_inline_reset_delta_events } true; 1434564#L1644-2 [2024-11-20 22:59:40,558 INFO L747 eck$LassoCheckResult]: Loop: 1434564#L1644-2 assume !false; 1460561#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1460555#L1065-1 assume !false; 1460554#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1460551#L829 assume !(0 == ~m_st~0); 1460552#L833 assume !(0 == ~t1_st~0); 1460541#L837 assume !(0 == ~t2_st~0); 1460542#L841 assume !(0 == ~t3_st~0); 1460545#L845 assume !(0 == ~t4_st~0); 1460547#L849 assume !(0 == ~t5_st~0); 1460549#L853 assume !(0 == ~t6_st~0); 1460550#L857 assume !(0 == ~t7_st~0); 1460553#L861 assume !(0 == ~t8_st~0); 1460543#L865 assume !(0 == ~t9_st~0); 1460544#L869 assume !(0 == ~t10_st~0); 1460546#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 1460548#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1459796#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1459797#L906 assume !(0 != eval_~tmp~0#1); 1460845#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1460844#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1460843#L1090-3 assume !(0 == ~M_E~0); 1460842#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1460841#L1095-3 assume !(0 == ~T2_E~0); 1460840#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1460839#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1460838#L1110-3 assume !(0 == ~T5_E~0); 1460837#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1460836#L1120-3 assume !(0 == ~T7_E~0); 1460835#L1125-3 assume !(0 == ~T8_E~0); 1460834#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1460833#L1135-3 assume !(0 == ~T10_E~0); 1460832#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1460831#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1460830#L1150-3 assume !(0 == ~E_2~0); 1460829#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1460828#L1160-3 assume !(0 == ~E_4~0); 1460827#L1165-3 assume !(0 == ~E_5~0); 1460826#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1460825#L1175-3 assume !(0 == ~E_7~0); 1460824#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1460823#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1460822#L1190-3 assume !(0 == ~E_10~0); 1460821#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1460820#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1460819#L525-36 assume !(1 == ~m_pc~0); 1460818#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1460816#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1460814#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1460812#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1460809#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1460806#L544-36 assume !(1 == ~t1_pc~0); 1460803#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1460800#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1460797#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1460795#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 1460793#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1460790#L563-36 assume !(1 == ~t2_pc~0); 1460788#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1460786#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1460784#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1460782#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1460779#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1460777#L582-36 assume !(1 == ~t3_pc~0); 1460775#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1460773#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1460771#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1460769#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1460767#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1460765#L601-36 assume !(1 == ~t4_pc~0); 1460762#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1460760#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1460758#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1460756#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1460753#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1460751#L620-36 assume !(1 == ~t5_pc~0); 1460749#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1460747#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1460745#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1460743#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1460741#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1460739#L639-36 assume 1 == ~t6_pc~0; 1460736#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1460734#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1460732#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1460730#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1460728#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1460725#L658-36 assume !(1 == ~t7_pc~0); 1460722#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1460720#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1460718#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1460716#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1460713#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1460711#L677-36 assume !(1 == ~t8_pc~0); 1460709#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1460707#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1460705#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1460703#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1460701#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1460699#L696-36 assume 1 == ~t9_pc~0; 1460696#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1460693#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1460690#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1460687#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1460685#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1460682#L715-36 assume !(1 == ~t10_pc~0); 1460679#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1460676#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1460673#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1460671#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1460669#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1460667#L734-36 assume !(1 == ~t11_pc~0); 1460664#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1460662#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1460660#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1460658#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1460656#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1460653#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1460651#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1460649#L1218-3 assume !(1 == ~T2_E~0); 1460647#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1460645#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1460643#L1233-3 assume !(1 == ~T5_E~0); 1460641#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1460639#L1243-3 assume !(1 == ~T7_E~0); 1460637#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1460635#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1460633#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1460631#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1460629#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1460627#L1273-3 assume !(1 == ~E_2~0); 1460625#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1460623#L1283-3 assume !(1 == ~E_4~0); 1460621#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1460619#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1460617#L1298-3 assume !(1 == ~E_7~0); 1460615#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1460613#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1460611#L1313-3 assume !(1 == ~E_10~0); 1460609#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1460607#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1460598#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1460591#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1460589#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1460586#L1663 assume !(0 == start_simulation_~tmp~3#1); 1460585#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1460582#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1460572#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1460571#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1460570#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1460569#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1460567#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1460565#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1434564#L1644-2 [2024-11-20 22:59:40,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:40,559 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 6 times [2024-11-20 22:59:40,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:40,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107179789] [2024-11-20 22:59:40,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:40,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:40,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:40,575 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-20 22:59:40,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:40,614 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-20 22:59:40,614 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:40,614 INFO L85 PathProgramCache]: Analyzing trace with hash -63170987, now seen corresponding path program 1 times [2024-11-20 22:59:40,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:40,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830092838] [2024-11-20 22:59:40,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:40,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:40,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:40,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:40,643 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:40,643 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830092838] [2024-11-20 22:59:40,643 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1830092838] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:40,643 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:40,644 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-20 22:59:40,644 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [251000081] [2024-11-20 22:59:40,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:40,644 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:40,644 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:40,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-20 22:59:40,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-20 22:59:40,645 INFO L87 Difference]: Start difference. First operand 53938 states and 73302 transitions. cyclomatic complexity: 19396 Second operand has 3 states, 3 states have (on average 51.0) internal successors, (153), 3 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:40,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:40,894 INFO L93 Difference]: Finished difference Result 103950 states and 140030 transitions. [2024-11-20 22:59:40,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103950 states and 140030 transitions. [2024-11-20 22:59:41,675 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 103400 [2024-11-20 22:59:41,961 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103950 states to 103950 states and 140030 transitions. [2024-11-20 22:59:41,962 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 103950 [2024-11-20 22:59:42,031 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 103950 [2024-11-20 22:59:42,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 103950 states and 140030 transitions. [2024-11-20 22:59:42,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:42,101 INFO L218 hiAutomatonCegarLoop]: Abstraction has 103950 states and 140030 transitions. [2024-11-20 22:59:42,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103950 states and 140030 transitions. [2024-11-20 22:59:43,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103950 to 99958. [2024-11-20 22:59:43,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99958 states, 99958 states have (on average 1.3491866583965266) internal successors, (134862), 99957 states have internal predecessors, (134862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:43,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99958 states to 99958 states and 134862 transitions. [2024-11-20 22:59:43,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99958 states and 134862 transitions. [2024-11-20 22:59:43,735 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-20 22:59:43,736 INFO L425 stractBuchiCegarLoop]: Abstraction has 99958 states and 134862 transitions. [2024-11-20 22:59:43,736 INFO L332 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2024-11-20 22:59:43,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99958 states and 134862 transitions. [2024-11-20 22:59:43,984 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99408 [2024-11-20 22:59:43,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:43,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:43,986 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:43,986 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:43,986 INFO L745 eck$LassoCheckResult]: Stem: 1592396#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1592397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1593578#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1593579#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1592863#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1592864#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1592732#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1592622#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1592339#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1591990#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1591991#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1592035#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1592036#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1593027#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1593028#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1593082#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1592440#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1592441#L1090 assume !(0 == ~M_E~0); 1592489#L1090-2 assume !(0 == ~T1_E~0); 1592490#L1095-1 assume !(0 == ~T2_E~0); 1593273#L1100-1 assume !(0 == ~T3_E~0); 1593274#L1105-1 assume !(0 == ~T4_E~0); 1592257#L1110-1 assume !(0 == ~T5_E~0); 1592258#L1115-1 assume !(0 == ~T6_E~0); 1592659#L1120-1 assume !(0 == ~T7_E~0); 1592999#L1125-1 assume !(0 == ~T8_E~0); 1593738#L1130-1 assume !(0 == ~T9_E~0); 1593298#L1135-1 assume !(0 == ~T10_E~0); 1592446#L1140-1 assume !(0 == ~T11_E~0); 1592447#L1145-1 assume !(0 == ~E_1~0); 1593219#L1150-1 assume !(0 == ~E_2~0); 1592637#L1155-1 assume !(0 == ~E_3~0); 1592638#L1160-1 assume !(0 == ~E_4~0); 1592737#L1165-1 assume !(0 == ~E_5~0); 1592738#L1170-1 assume !(0 == ~E_6~0); 1593548#L1175-1 assume !(0 == ~E_7~0); 1592821#L1180-1 assume !(0 == ~E_8~0); 1592822#L1185-1 assume !(0 == ~E_9~0); 1592442#L1190-1 assume !(0 == ~E_10~0); 1592443#L1195-1 assume !(0 == ~E_11~0); 1592837#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1592656#L525 assume !(1 == ~m_pc~0); 1592080#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1592081#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1593505#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1593361#L1350 assume !(0 != activate_threads_~tmp~1#1); 1592432#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1592433#L544 assume !(1 == ~t1_pc~0); 1592657#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1592658#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1592054#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1592055#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1592281#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1592962#L563 assume !(1 == ~t2_pc~0); 1593202#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1592099#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1592100#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1592515#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1592516#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1593054#L582 assume !(1 == ~t3_pc~0); 1593218#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1593666#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1591982#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1591983#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1592163#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1592164#L601 assume !(1 == ~t4_pc~0); 1593236#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1592660#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1592175#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1592176#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1593229#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1593655#L620 assume !(1 == ~t5_pc~0); 1593016#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1593017#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1593078#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1593402#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1593688#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1593689#L639 assume !(1 == ~t6_pc~0); 1592997#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1592557#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1592558#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1592608#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1592665#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1592666#L658 assume !(1 == ~t7_pc~0); 1592891#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1592892#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1593703#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1593144#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1592435#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1592436#L677 assume !(1 == ~t8_pc~0); 1592458#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1592240#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1592241#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1592510#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1592511#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1593349#L696 assume !(1 == ~t9_pc~0); 1592977#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1592978#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1592721#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1592722#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1593005#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1593278#L715 assume !(1 == ~t10_pc~0); 1593602#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1593120#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1592875#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1592876#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1592814#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1592234#L734 assume !(1 == ~t11_pc~0); 1592235#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1592739#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1592826#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1591978#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1591979#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1593079#L1213 assume !(1 == ~M_E~0); 1592811#L1213-2 assume !(1 == ~T1_E~0); 1592812#L1218-1 assume !(1 == ~T2_E~0); 1592013#L1223-1 assume !(1 == ~T3_E~0); 1592014#L1228-1 assume !(1 == ~T4_E~0); 1592786#L1233-1 assume !(1 == ~T5_E~0); 1593690#L1238-1 assume !(1 == ~T6_E~0); 1593227#L1243-1 assume !(1 == ~T7_E~0); 1593228#L1248-1 assume !(1 == ~T8_E~0); 1593284#L1253-1 assume !(1 == ~T9_E~0); 1593285#L1258-1 assume !(1 == ~T10_E~0); 1593255#L1263-1 assume !(1 == ~T11_E~0); 1593256#L1268-1 assume !(1 == ~E_1~0); 1593024#L1273-1 assume !(1 == ~E_2~0); 1593025#L1278-1 assume !(1 == ~E_3~0); 1592553#L1283-1 assume !(1 == ~E_4~0); 1592554#L1288-1 assume !(1 == ~E_5~0); 1593411#L1293-1 assume !(1 == ~E_6~0); 1593354#L1298-1 assume !(1 == ~E_7~0); 1593060#L1303-1 assume !(1 == ~E_8~0); 1592563#L1308-1 assume !(1 == ~E_9~0); 1592450#L1313-1 assume !(1 == ~E_10~0); 1592451#L1318-1 assume !(1 == ~E_11~0); 1592459#L1323-1 assume { :end_inline_reset_delta_events } true; 1592460#L1644-2 [2024-11-20 22:59:43,986 INFO L747 eck$LassoCheckResult]: Loop: 1592460#L1644-2 assume !false; 1610629#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1610624#L1065-1 assume !false; 1610622#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1610619#L829 assume !(0 == ~m_st~0); 1610620#L833 assume !(0 == ~t1_st~0); 1610970#L837 assume !(0 == ~t2_st~0); 1610967#L841 assume !(0 == ~t3_st~0); 1610965#L845 assume !(0 == ~t4_st~0); 1610963#L849 assume !(0 == ~t5_st~0); 1610961#L853 assume !(0 == ~t6_st~0); 1610959#L857 assume !(0 == ~t7_st~0); 1610957#L861 assume !(0 == ~t8_st~0); 1610955#L865 assume !(0 == ~t9_st~0); 1610953#L869 assume !(0 == ~t10_st~0); 1610950#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 1610948#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1610946#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1610943#L906 assume !(0 != eval_~tmp~0#1); 1610941#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1610939#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1610937#L1090-3 assume !(0 == ~M_E~0); 1610935#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1610933#L1095-3 assume !(0 == ~T2_E~0); 1610931#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1610929#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1610927#L1110-3 assume !(0 == ~T5_E~0); 1610925#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1610923#L1120-3 assume !(0 == ~T7_E~0); 1610921#L1125-3 assume !(0 == ~T8_E~0); 1610919#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1610917#L1135-3 assume !(0 == ~T10_E~0); 1610915#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1610913#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1610911#L1150-3 assume !(0 == ~E_2~0); 1610909#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1610907#L1160-3 assume !(0 == ~E_4~0); 1610906#L1165-3 assume !(0 == ~E_5~0); 1610905#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1610904#L1175-3 assume !(0 == ~E_7~0); 1610903#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1610902#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1610901#L1190-3 assume !(0 == ~E_10~0); 1610900#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1610899#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1610898#L525-36 assume 1 == ~m_pc~0; 1610886#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1610884#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1610882#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1610878#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1610876#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1610874#L544-36 assume !(1 == ~t1_pc~0); 1610871#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1610869#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1610867#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1610866#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 1610865#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1610861#L563-36 assume !(1 == ~t2_pc~0); 1610860#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1610859#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1610857#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1610854#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1610852#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1610850#L582-36 assume !(1 == ~t3_pc~0); 1610845#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1610843#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1610841#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1610839#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1610837#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1610835#L601-36 assume !(1 == ~t4_pc~0); 1610832#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1610830#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1610827#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1610825#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1610823#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1610821#L620-36 assume !(1 == ~t5_pc~0); 1610819#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1610817#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1610815#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1610813#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1610811#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1610809#L639-36 assume 1 == ~t6_pc~0; 1610806#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1610804#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1610801#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1610799#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1610797#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1610795#L658-36 assume !(1 == ~t7_pc~0); 1610792#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1610790#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1610788#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1610786#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1610784#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1610782#L677-36 assume !(1 == ~t8_pc~0); 1610780#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1610778#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1610776#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1610773#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1610771#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1610766#L696-36 assume !(1 == ~t9_pc~0); 1610764#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1610761#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1610759#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1610757#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1610754#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1610752#L715-36 assume !(1 == ~t10_pc~0); 1610750#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1610748#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1610746#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1610744#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1610742#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1610740#L734-36 assume !(1 == ~t11_pc~0); 1610737#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1610733#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1610731#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1610729#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1610727#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1610724#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1610722#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1610720#L1218-3 assume !(1 == ~T2_E~0); 1610718#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1610716#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1610714#L1233-3 assume !(1 == ~T5_E~0); 1610712#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1610710#L1243-3 assume !(1 == ~T7_E~0); 1610708#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1610705#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1610703#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1610701#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1610699#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1610697#L1273-3 assume !(1 == ~E_2~0); 1610695#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1610693#L1283-3 assume !(1 == ~E_4~0); 1610691#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1610689#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1610687#L1298-3 assume !(1 == ~E_7~0); 1610685#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1610683#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1610681#L1313-3 assume !(1 == ~E_10~0); 1610679#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1610677#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1610674#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1610672#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1610670#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1610650#L1663 assume !(0 == start_simulation_~tmp~3#1); 1610648#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1610645#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1610642#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1610640#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1610638#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1610636#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1610634#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1610632#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1592460#L1644-2 [2024-11-20 22:59:43,991 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:43,991 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 7 times [2024-11-20 22:59:43,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:43,992 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058216859] [2024-11-20 22:59:43,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:43,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:44,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:44,005 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-20 22:59:44,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:44,037 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-20 22:59:44,037 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:44,037 INFO L85 PathProgramCache]: Analyzing trace with hash -1383985643, now seen corresponding path program 1 times [2024-11-20 22:59:44,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:44,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769884872] [2024-11-20 22:59:44,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:44,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:44,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:44,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:44,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:44,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769884872] [2024-11-20 22:59:44,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1769884872] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:44,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:44,088 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-20 22:59:44,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320417526] [2024-11-20 22:59:44,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:44,088 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:44,088 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:44,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-20 22:59:44,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-20 22:59:44,089 INFO L87 Difference]: Start difference. First operand 99958 states and 134862 transitions. cyclomatic complexity: 34936 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:44,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:44,470 INFO L93 Difference]: Finished difference Result 100102 states and 134141 transitions. [2024-11-20 22:59:44,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100102 states and 134141 transitions. [2024-11-20 22:59:45,451 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99552 [2024-11-20 22:59:45,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100102 states to 100102 states and 134141 transitions. [2024-11-20 22:59:45,765 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100102 [2024-11-20 22:59:45,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100102 [2024-11-20 22:59:45,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100102 states and 134141 transitions. [2024-11-20 22:59:45,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:45,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100102 states and 134141 transitions. [2024-11-20 22:59:45,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100102 states and 134141 transitions. [2024-11-20 22:59:46,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100102 to 100102. [2024-11-20 22:59:46,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100102 states, 100102 states have (on average 1.3400431559808994) internal successors, (134141), 100101 states have internal predecessors, (134141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:46,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100102 states to 100102 states and 134141 transitions. [2024-11-20 22:59:46,814 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100102 states and 134141 transitions. [2024-11-20 22:59:46,815 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-20 22:59:46,815 INFO L425 stractBuchiCegarLoop]: Abstraction has 100102 states and 134141 transitions. [2024-11-20 22:59:46,815 INFO L332 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2024-11-20 22:59:46,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100102 states and 134141 transitions. [2024-11-20 22:59:47,673 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99552 [2024-11-20 22:59:47,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:47,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:47,674 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:47,674 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:47,675 INFO L745 eck$LassoCheckResult]: Stem: 1792464#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1792465#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1793598#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1793599#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1792928#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1792929#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1792794#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1792684#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1792405#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1792058#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1792059#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1792102#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1792103#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1793083#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1793084#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1793137#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1792510#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1792511#L1090 assume !(0 == ~M_E~0); 1792553#L1090-2 assume !(0 == ~T1_E~0); 1792554#L1095-1 assume !(0 == ~T2_E~0); 1793306#L1100-1 assume !(0 == ~T3_E~0); 1793307#L1105-1 assume !(0 == ~T4_E~0); 1792324#L1110-1 assume !(0 == ~T5_E~0); 1792325#L1115-1 assume !(0 == ~T6_E~0); 1792722#L1120-1 assume !(0 == ~T7_E~0); 1793057#L1125-1 assume !(0 == ~T8_E~0); 1793731#L1130-1 assume !(0 == ~T9_E~0); 1793333#L1135-1 assume !(0 == ~T10_E~0); 1792514#L1140-1 assume !(0 == ~T11_E~0); 1792515#L1145-1 assume !(0 == ~E_1~0); 1793255#L1150-1 assume !(0 == ~E_2~0); 1792700#L1155-1 assume !(0 == ~E_3~0); 1792701#L1160-1 assume !(0 == ~E_4~0); 1792800#L1165-1 assume !(0 == ~E_5~0); 1792801#L1170-1 assume !(0 == ~E_6~0); 1793573#L1175-1 assume !(0 == ~E_7~0); 1792887#L1180-1 assume !(0 == ~E_8~0); 1792888#L1185-1 assume !(0 == ~E_9~0); 1792508#L1190-1 assume !(0 == ~E_10~0); 1792509#L1195-1 assume !(0 == ~E_11~0); 1792903#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1792715#L525 assume !(1 == ~m_pc~0); 1792146#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1792147#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1793530#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1793399#L1350 assume !(0 != activate_threads_~tmp~1#1); 1792499#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1792500#L544 assume !(1 == ~t1_pc~0); 1792720#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1792721#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1792120#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1792121#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1792349#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1793021#L563 assume !(1 == ~t2_pc~0); 1793239#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1792168#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1792169#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1792578#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1792579#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1793111#L582 assume !(1 == ~t3_pc~0); 1793254#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1793671#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1792050#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1792051#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1792232#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1792233#L601 assume !(1 == ~t4_pc~0); 1793271#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1792723#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1792242#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1792243#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1793264#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1793662#L620 assume !(1 == ~t5_pc~0); 1793072#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1793073#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1793134#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1793438#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1793688#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1793689#L639 assume !(1 == ~t6_pc~0); 1793056#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1792618#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1792619#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1792670#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1792728#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1792729#L658 assume !(1 == ~t7_pc~0); 1792955#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1792956#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1793699#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1793188#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1792503#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1792504#L677 assume !(1 == ~t8_pc~0); 1792525#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1792308#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1792309#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1792574#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1792575#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1793387#L696 assume !(1 == ~t9_pc~0); 1793035#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1793036#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1792783#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1792784#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1793062#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1793312#L715 assume !(1 == ~t10_pc~0); 1793623#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1793168#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1792942#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1792943#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1792880#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1792302#L734 assume !(1 == ~t11_pc~0); 1792303#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1792802#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1792890#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1792046#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1792047#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1793135#L1213 assume !(1 == ~M_E~0); 1792877#L1213-2 assume !(1 == ~T1_E~0); 1792878#L1218-1 assume !(1 == ~T2_E~0); 1792081#L1223-1 assume !(1 == ~T3_E~0); 1792082#L1228-1 assume !(1 == ~T4_E~0); 1792849#L1233-1 assume !(1 == ~T5_E~0); 1793690#L1238-1 assume !(1 == ~T6_E~0); 1793262#L1243-1 assume !(1 == ~T7_E~0); 1793263#L1248-1 assume !(1 == ~T8_E~0); 1793318#L1253-1 assume !(1 == ~T9_E~0); 1793319#L1258-1 assume !(1 == ~T10_E~0); 1793290#L1263-1 assume !(1 == ~T11_E~0); 1793291#L1268-1 assume !(1 == ~E_1~0); 1793080#L1273-1 assume !(1 == ~E_2~0); 1793081#L1278-1 assume !(1 == ~E_3~0); 1792616#L1283-1 assume !(1 == ~E_4~0); 1792617#L1288-1 assume !(1 == ~E_5~0); 1793445#L1293-1 assume !(1 == ~E_6~0); 1793391#L1298-1 assume !(1 == ~E_7~0); 1793116#L1303-1 assume !(1 == ~E_8~0); 1792626#L1308-1 assume !(1 == ~E_9~0); 1792518#L1313-1 assume !(1 == ~E_10~0); 1792519#L1318-1 assume !(1 == ~E_11~0); 1792526#L1323-1 assume { :end_inline_reset_delta_events } true; 1792527#L1644-2 [2024-11-20 22:59:47,675 INFO L747 eck$LassoCheckResult]: Loop: 1792527#L1644-2 assume !false; 1809664#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1809658#L1065-1 assume !false; 1809656#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1809653#L829 assume !(0 == ~m_st~0); 1809654#L833 assume !(0 == ~t1_st~0); 1857467#L837 assume !(0 == ~t2_st~0); 1857461#L841 assume !(0 == ~t3_st~0); 1857455#L845 assume !(0 == ~t4_st~0); 1857448#L849 assume !(0 == ~t5_st~0); 1857440#L853 assume !(0 == ~t6_st~0); 1857144#L857 assume !(0 == ~t7_st~0); 1857141#L861 assume !(0 == ~t8_st~0); 1857139#L865 assume !(0 == ~t9_st~0); 1857137#L869 assume !(0 == ~t10_st~0); 1857134#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 1857132#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1857130#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1857128#L906 assume !(0 != eval_~tmp~0#1); 1857126#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1857124#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1857122#L1090-3 assume !(0 == ~M_E~0); 1857120#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1857118#L1095-3 assume !(0 == ~T2_E~0); 1857115#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1857113#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1857111#L1110-3 assume !(0 == ~T5_E~0); 1857109#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1857107#L1120-3 assume !(0 == ~T7_E~0); 1857105#L1125-3 assume !(0 == ~T8_E~0); 1857103#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1857100#L1135-3 assume !(0 == ~T10_E~0); 1857098#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1857096#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1857094#L1150-3 assume !(0 == ~E_2~0); 1857092#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1857090#L1160-3 assume !(0 == ~E_4~0); 1856995#L1165-3 assume !(0 == ~E_5~0); 1856989#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1856981#L1175-3 assume !(0 == ~E_7~0); 1856974#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1855244#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1855240#L1190-3 assume !(0 == ~E_10~0); 1855236#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1855235#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1855232#L525-36 assume 1 == ~m_pc~0; 1855229#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1855227#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1855224#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1853344#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1853339#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1853335#L544-36 assume !(1 == ~t1_pc~0); 1853330#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1853326#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1853321#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1853318#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 1853315#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1853312#L563-36 assume !(1 == ~t2_pc~0); 1853310#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1820958#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1820957#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1820956#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 1820955#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1820953#L582-36 assume !(1 == ~t3_pc~0); 1820951#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1820949#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1820946#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1820945#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1820944#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1820943#L601-36 assume !(1 == ~t4_pc~0); 1820941#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1820940#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1820938#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1820936#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1820935#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1820934#L620-36 assume !(1 == ~t5_pc~0); 1820923#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1820921#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1820919#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1820916#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1820914#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1820912#L639-36 assume !(1 == ~t6_pc~0); 1820909#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1820906#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1820904#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1820903#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1820902#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1820901#L658-36 assume !(1 == ~t7_pc~0); 1820899#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1820895#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1820893#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1820891#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1820889#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1820888#L677-36 assume !(1 == ~t8_pc~0); 1820883#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1809874#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1809870#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1809868#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1809866#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1809864#L696-36 assume !(1 == ~t9_pc~0); 1809861#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1820227#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1820225#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1809852#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1809849#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1809847#L715-36 assume !(1 == ~t10_pc~0); 1809845#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1809843#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1809841#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1809839#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1809837#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1809835#L734-36 assume 1 == ~t11_pc~0; 1809833#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1809829#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1809827#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1809825#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1809823#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1809821#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1809819#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1809817#L1218-3 assume !(1 == ~T2_E~0); 1809814#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1809812#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1809810#L1233-3 assume !(1 == ~T5_E~0); 1809808#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1809806#L1243-3 assume !(1 == ~T7_E~0); 1809804#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1809801#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1809799#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1809797#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1809795#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1809793#L1273-3 assume !(1 == ~E_2~0); 1809790#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1809788#L1283-3 assume !(1 == ~E_4~0); 1809786#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1809784#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1809782#L1298-3 assume !(1 == ~E_7~0); 1809780#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1809778#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1809776#L1313-3 assume !(1 == ~E_10~0); 1809774#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1809772#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1809769#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1809767#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1809765#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1809687#L1663 assume !(0 == start_simulation_~tmp~3#1); 1809685#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1809682#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1809680#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1809678#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1809676#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1809674#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1809671#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1809669#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1792527#L1644-2 [2024-11-20 22:59:47,675 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:47,675 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 8 times [2024-11-20 22:59:47,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:47,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999931384] [2024-11-20 22:59:47,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:47,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:47,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:47,683 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-20 22:59:47,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:47,713 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-20 22:59:47,714 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:47,714 INFO L85 PathProgramCache]: Analyzing trace with hash 257612947, now seen corresponding path program 1 times [2024-11-20 22:59:47,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:47,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334006134] [2024-11-20 22:59:47,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:47,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:47,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:47,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:47,760 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:47,760 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [334006134] [2024-11-20 22:59:47,760 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [334006134] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:47,760 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:47,760 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-20 22:59:47,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [860827488] [2024-11-20 22:59:47,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:47,760 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:47,761 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:47,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-20 22:59:47,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-20 22:59:47,761 INFO L87 Difference]: Start difference. First operand 100102 states and 134141 transitions. cyclomatic complexity: 34071 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:48,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:48,170 INFO L93 Difference]: Finished difference Result 101542 states and 135148 transitions. [2024-11-20 22:59:48,170 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101542 states and 135148 transitions. [2024-11-20 22:59:48,542 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 100992 [2024-11-20 22:59:48,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101542 states to 101542 states and 135148 transitions. [2024-11-20 22:59:48,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101542 [2024-11-20 22:59:48,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101542 [2024-11-20 22:59:48,869 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101542 states and 135148 transitions. [2024-11-20 22:59:48,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:48,931 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101542 states and 135148 transitions. [2024-11-20 22:59:48,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101542 states and 135148 transitions. [2024-11-20 22:59:50,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101542 to 101542. [2024-11-20 22:59:50,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101542 states, 101542 states have (on average 1.3309566484804318) internal successors, (135148), 101541 states have internal predecessors, (135148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:50,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101542 states to 101542 states and 135148 transitions. [2024-11-20 22:59:50,632 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101542 states and 135148 transitions. [2024-11-20 22:59:50,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-20 22:59:50,633 INFO L425 stractBuchiCegarLoop]: Abstraction has 101542 states and 135148 transitions. [2024-11-20 22:59:50,633 INFO L332 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2024-11-20 22:59:50,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101542 states and 135148 transitions. [2024-11-20 22:59:50,940 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 100992 [2024-11-20 22:59:50,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:50,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:50,942 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:50,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:50,943 INFO L745 eck$LassoCheckResult]: Stem: 1994118#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1994119#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1995255#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1995256#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1994578#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1994579#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1994446#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1994338#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1994059#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1993710#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1993711#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1993755#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1993756#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1994730#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1994731#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1994783#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1994162#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1994163#L1090 assume !(0 == ~M_E~0); 1994208#L1090-2 assume !(0 == ~T1_E~0); 1994209#L1095-1 assume !(0 == ~T2_E~0); 1994958#L1100-1 assume !(0 == ~T3_E~0); 1994959#L1105-1 assume !(0 == ~T4_E~0); 1993978#L1110-1 assume !(0 == ~T5_E~0); 1993979#L1115-1 assume !(0 == ~T6_E~0); 1994374#L1120-1 assume !(0 == ~T7_E~0); 1994704#L1125-1 assume !(0 == ~T8_E~0); 1995394#L1130-1 assume !(0 == ~T9_E~0); 1994986#L1135-1 assume !(0 == ~T10_E~0); 1994168#L1140-1 assume !(0 == ~T11_E~0); 1994169#L1145-1 assume !(0 == ~E_1~0); 1994904#L1150-1 assume !(0 == ~E_2~0); 1994353#L1155-1 assume !(0 == ~E_3~0); 1994354#L1160-1 assume !(0 == ~E_4~0); 1994451#L1165-1 assume !(0 == ~E_5~0); 1994452#L1170-1 assume !(0 == ~E_6~0); 1995232#L1175-1 assume !(0 == ~E_7~0); 1994536#L1180-1 assume !(0 == ~E_8~0); 1994537#L1185-1 assume !(0 == ~E_9~0); 1994164#L1190-1 assume !(0 == ~E_10~0); 1994165#L1195-1 assume !(0 == ~E_11~0); 1994552#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1994367#L525 assume !(1 == ~m_pc~0); 1993800#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1993801#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1995187#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1995050#L1350 assume !(0 != activate_threads_~tmp~1#1); 1994153#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1994154#L544 assume !(1 == ~t1_pc~0); 1994372#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1994373#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1993774#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1993775#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1994003#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1994669#L563 assume !(1 == ~t2_pc~0); 1994888#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1993819#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1993820#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1994233#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1994234#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1994759#L582 assume !(1 == ~t3_pc~0); 1994903#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1995332#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1993702#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1993703#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1993884#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1993885#L601 assume !(1 == ~t4_pc~0); 1994921#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1994375#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1993894#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1993895#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1994914#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1995322#L620 assume !(1 == ~t5_pc~0); 1994719#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1994720#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1994780#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1995090#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1995349#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1995350#L639 assume !(1 == ~t6_pc~0); 1994702#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1994272#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1994273#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1994325#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1994380#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1994381#L658 assume !(1 == ~t7_pc~0); 1994604#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1994605#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1995362#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1994840#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1994157#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1994158#L677 assume !(1 == ~t8_pc~0); 1994179#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1993962#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1993963#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1994229#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1994230#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1995039#L696 assume !(1 == ~t9_pc~0); 1994683#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1994684#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1994436#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1994437#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1994709#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1994963#L715 assume !(1 == ~t10_pc~0); 1995277#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1994819#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1994591#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1994592#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1994529#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1993956#L734 assume !(1 == ~t11_pc~0); 1993957#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1994453#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1994539#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1993698#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1993699#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1994781#L1213 assume !(1 == ~M_E~0); 1994526#L1213-2 assume !(1 == ~T1_E~0); 1994527#L1218-1 assume !(1 == ~T2_E~0); 1993733#L1223-1 assume !(1 == ~T3_E~0); 1993734#L1228-1 assume !(1 == ~T4_E~0); 1994500#L1233-1 assume !(1 == ~T5_E~0); 1995351#L1238-1 assume !(1 == ~T6_E~0); 1994912#L1243-1 assume !(1 == ~T7_E~0); 1994913#L1248-1 assume !(1 == ~T8_E~0); 1994971#L1253-1 assume !(1 == ~T9_E~0); 1994972#L1258-1 assume !(1 == ~T10_E~0); 1994941#L1263-1 assume !(1 == ~T11_E~0); 1994942#L1268-1 assume !(1 == ~E_1~0); 1994726#L1273-1 assume !(1 == ~E_2~0); 1994727#L1278-1 assume !(1 == ~E_3~0); 1994270#L1283-1 assume !(1 == ~E_4~0); 1994271#L1288-1 assume !(1 == ~E_5~0); 1995098#L1293-1 assume !(1 == ~E_6~0); 1995044#L1298-1 assume !(1 == ~E_7~0); 1994764#L1303-1 assume !(1 == ~E_8~0); 1994282#L1308-1 assume !(1 == ~E_9~0); 1994172#L1313-1 assume !(1 == ~E_10~0); 1994173#L1318-1 assume !(1 == ~E_11~0); 1994180#L1323-1 assume { :end_inline_reset_delta_events } true; 1994181#L1644-2 [2024-11-20 22:59:50,944 INFO L747 eck$LassoCheckResult]: Loop: 1994181#L1644-2 assume !false; 2015803#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2015798#L1065-1 assume !false; 2015797#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2015795#L829 assume !(0 == ~m_st~0); 2015796#L833 assume !(0 == ~t1_st~0); 2016362#L837 assume !(0 == ~t2_st~0); 2016360#L841 assume !(0 == ~t3_st~0); 2016358#L845 assume !(0 == ~t4_st~0); 2016354#L849 assume !(0 == ~t5_st~0); 2016352#L853 assume !(0 == ~t6_st~0); 2016350#L857 assume !(0 == ~t7_st~0); 2016348#L861 assume !(0 == ~t8_st~0); 2016345#L865 assume !(0 == ~t9_st~0); 2016343#L869 assume !(0 == ~t10_st~0); 2016340#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 2016338#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2016336#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2016334#L906 assume !(0 != eval_~tmp~0#1); 2016332#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2016330#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2016328#L1090-3 assume !(0 == ~M_E~0); 2016325#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2016323#L1095-3 assume !(0 == ~T2_E~0); 2016321#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2016319#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2016317#L1110-3 assume !(0 == ~T5_E~0); 2016316#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2016312#L1120-3 assume !(0 == ~T7_E~0); 2016310#L1125-3 assume !(0 == ~T8_E~0); 2016308#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2016305#L1135-3 assume !(0 == ~T10_E~0); 2016304#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2016302#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2016301#L1150-3 assume !(0 == ~E_2~0); 2016300#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2016299#L1160-3 assume !(0 == ~E_4~0); 2016298#L1165-3 assume !(0 == ~E_5~0); 2016297#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2016295#L1175-3 assume !(0 == ~E_7~0); 2016294#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2016293#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2016292#L1190-3 assume !(0 == ~E_10~0); 2016291#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2016290#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2016288#L525-36 assume 1 == ~m_pc~0; 2016286#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2016285#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2016284#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2016282#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2016281#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2016280#L544-36 assume !(1 == ~t1_pc~0); 2016279#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 2016277#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2016274#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2016272#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 2016270#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2016265#L563-36 assume !(1 == ~t2_pc~0); 2016263#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2016262#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2016261#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2016259#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 2016258#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2016257#L582-36 assume !(1 == ~t3_pc~0); 2016256#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2016255#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2016251#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2016249#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 2016247#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2016245#L601-36 assume !(1 == ~t4_pc~0); 2016239#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2016237#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2016235#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2016233#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2016231#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2016229#L620-36 assume !(1 == ~t5_pc~0); 2016227#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2016225#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2016222#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2016220#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 2016218#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2016216#L639-36 assume !(1 == ~t6_pc~0); 2016214#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2016211#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2016209#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2016207#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2016205#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2016203#L658-36 assume !(1 == ~t7_pc~0); 2016200#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2016198#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2016195#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2016193#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2016191#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2016189#L677-36 assume !(1 == ~t8_pc~0); 2016187#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2016185#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2016183#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2016181#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2016179#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2016174#L696-36 assume 1 == ~t9_pc~0; 2016175#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2016176#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2016289#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2016164#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2016162#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2016160#L715-36 assume !(1 == ~t10_pc~0); 2016158#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2016155#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2016153#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2016151#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2016149#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2016147#L734-36 assume !(1 == ~t11_pc~0); 2016144#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 2016142#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2016140#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2016138#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2016136#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2016134#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2016132#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2016128#L1218-3 assume !(1 == ~T2_E~0); 2016126#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2016124#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2016122#L1233-3 assume !(1 == ~T5_E~0); 2016119#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2016117#L1243-3 assume !(1 == ~T7_E~0); 2016115#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2016113#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2016111#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2016109#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2016107#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2016105#L1273-3 assume !(1 == ~E_2~0); 2016103#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2016100#L1283-3 assume !(1 == ~E_4~0); 2016098#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2016096#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2016094#L1298-3 assume !(1 == ~E_7~0); 2016092#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2016091#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2016087#L1313-3 assume !(1 == ~E_10~0); 2016085#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2016083#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2016080#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2016079#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2016077#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2015837#L1663 assume !(0 == start_simulation_~tmp~3#1); 2015833#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2015828#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2015824#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2015820#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2015816#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2015812#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2015808#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2015804#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1994181#L1644-2 [2024-11-20 22:59:50,944 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:50,944 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 9 times [2024-11-20 22:59:50,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:50,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132522463] [2024-11-20 22:59:50,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:50,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:50,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:50,956 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-20 22:59:50,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:50,979 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-20 22:59:50,980 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:50,980 INFO L85 PathProgramCache]: Analyzing trace with hash 816770067, now seen corresponding path program 1 times [2024-11-20 22:59:50,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:50,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083938219] [2024-11-20 22:59:50,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:50,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:50,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:51,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:51,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:51,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083938219] [2024-11-20 22:59:51,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083938219] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:51,056 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:51,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-20 22:59:51,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440465378] [2024-11-20 22:59:51,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:51,056 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:51,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:51,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-20 22:59:51,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-20 22:59:51,057 INFO L87 Difference]: Start difference. First operand 101542 states and 135148 transitions. cyclomatic complexity: 33638 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:52,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:52,049 INFO L93 Difference]: Finished difference Result 101686 states and 134427 transitions. [2024-11-20 22:59:52,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101686 states and 134427 transitions. [2024-11-20 22:59:52,422 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101136 [2024-11-20 22:59:52,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101686 states to 101686 states and 134427 transitions. [2024-11-20 22:59:52,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101686 [2024-11-20 22:59:52,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101686 [2024-11-20 22:59:52,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101686 states and 134427 transitions. [2024-11-20 22:59:52,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:52,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101686 states and 134427 transitions. [2024-11-20 22:59:52,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101686 states and 134427 transitions. [2024-11-20 22:59:53,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101686 to 101686. [2024-11-20 22:59:53,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101686 states, 101686 states have (on average 1.3219813937021812) internal successors, (134427), 101685 states have internal predecessors, (134427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:54,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101686 states to 101686 states and 134427 transitions. [2024-11-20 22:59:54,150 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101686 states and 134427 transitions. [2024-11-20 22:59:54,151 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-20 22:59:54,151 INFO L425 stractBuchiCegarLoop]: Abstraction has 101686 states and 134427 transitions. [2024-11-20 22:59:54,151 INFO L332 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2024-11-20 22:59:54,151 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101686 states and 134427 transitions. [2024-11-20 22:59:54,410 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101136 [2024-11-20 22:59:54,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:54,411 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:54,412 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:54,412 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:54,412 INFO L745 eck$LassoCheckResult]: Stem: 2197351#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 2197352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2198502#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2198503#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2197823#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 2197824#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2197686#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2197576#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2197294#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2196946#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2196947#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2196990#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2196991#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2197977#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2197978#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2198029#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2197394#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2197395#L1090 assume !(0 == ~M_E~0); 2197445#L1090-2 assume !(0 == ~T1_E~0); 2197446#L1095-1 assume !(0 == ~T2_E~0); 2198210#L1100-1 assume !(0 == ~T3_E~0); 2198211#L1105-1 assume !(0 == ~T4_E~0); 2197213#L1110-1 assume !(0 == ~T5_E~0); 2197214#L1115-1 assume !(0 == ~T6_E~0); 2197614#L1120-1 assume !(0 == ~T7_E~0); 2197947#L1125-1 assume !(0 == ~T8_E~0); 2198648#L1130-1 assume !(0 == ~T9_E~0); 2198237#L1135-1 assume !(0 == ~T10_E~0); 2197400#L1140-1 assume !(0 == ~T11_E~0); 2197401#L1145-1 assume !(0 == ~E_1~0); 2198153#L1150-1 assume !(0 == ~E_2~0); 2197591#L1155-1 assume !(0 == ~E_3~0); 2197592#L1160-1 assume !(0 == ~E_4~0); 2197691#L1165-1 assume !(0 == ~E_5~0); 2197692#L1170-1 assume !(0 == ~E_6~0); 2198479#L1175-1 assume !(0 == ~E_7~0); 2197777#L1180-1 assume !(0 == ~E_8~0); 2197778#L1185-1 assume !(0 == ~E_9~0); 2197396#L1190-1 assume !(0 == ~E_10~0); 2197397#L1195-1 assume !(0 == ~E_11~0); 2197793#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2197609#L525 assume !(1 == ~m_pc~0); 2197035#L525-2 is_master_triggered_~__retres1~0#1 := 0; 2197036#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2198437#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2198301#L1350 assume !(0 != activate_threads_~tmp~1#1); 2197386#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2197387#L544 assume !(1 == ~t1_pc~0); 2197610#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2197611#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2197013#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2197014#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 2197236#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2197914#L563 assume !(1 == ~t2_pc~0); 2198136#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2197057#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2197058#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2197470#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 2197471#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2198001#L582 assume !(1 == ~t3_pc~0); 2198151#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2198580#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2196938#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2196939#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 2197120#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2197121#L601 assume !(1 == ~t4_pc~0); 2198172#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2197615#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2197134#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2197135#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 2198165#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2198569#L620 assume !(1 == ~t5_pc~0); 2197964#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2197965#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2198020#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2198340#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 2198597#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2198598#L639 assume !(1 == ~t6_pc~0); 2197946#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2197509#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2197510#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2197559#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 2197620#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2197621#L658 assume !(1 == ~t7_pc~0); 2197852#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2197853#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2198615#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2198082#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 2197389#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2197390#L677 assume !(1 == ~t8_pc~0); 2197414#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2197200#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2197201#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2197463#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 2197464#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2198292#L696 assume !(1 == ~t9_pc~0); 2197930#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2197931#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2197677#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2197678#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 2197954#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2198217#L715 assume !(1 == ~t10_pc~0); 2198525#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2198058#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2197837#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2197838#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 2197771#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2197189#L734 assume !(1 == ~t11_pc~0); 2197190#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2197694#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2197782#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2196936#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 2196937#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2198021#L1213 assume !(1 == ~M_E~0); 2197769#L1213-2 assume !(1 == ~T1_E~0); 2197770#L1218-1 assume !(1 == ~T2_E~0); 2196969#L1223-1 assume !(1 == ~T3_E~0); 2196970#L1228-1 assume !(1 == ~T4_E~0); 2197741#L1233-1 assume !(1 == ~T5_E~0); 2198599#L1238-1 assume !(1 == ~T6_E~0); 2198163#L1243-1 assume !(1 == ~T7_E~0); 2198164#L1248-1 assume !(1 == ~T8_E~0); 2198222#L1253-1 assume !(1 == ~T9_E~0); 2198223#L1258-1 assume !(1 == ~T10_E~0); 2198191#L1263-1 assume !(1 == ~T11_E~0); 2198192#L1268-1 assume !(1 == ~E_1~0); 2197969#L1273-1 assume !(1 == ~E_2~0); 2197970#L1278-1 assume !(1 == ~E_3~0); 2197505#L1283-1 assume !(1 == ~E_4~0); 2197506#L1288-1 assume !(1 == ~E_5~0); 2198348#L1293-1 assume !(1 == ~E_6~0); 2198297#L1298-1 assume !(1 == ~E_7~0); 2198005#L1303-1 assume !(1 == ~E_8~0); 2197515#L1308-1 assume !(1 == ~E_9~0); 2197404#L1313-1 assume !(1 == ~E_10~0); 2197405#L1318-1 assume !(1 == ~E_11~0); 2197415#L1323-1 assume { :end_inline_reset_delta_events } true; 2197416#L1644-2 [2024-11-20 22:59:54,413 INFO L747 eck$LassoCheckResult]: Loop: 2197416#L1644-2 assume !false; 2204635#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2204630#L1065-1 assume !false; 2204628#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2204625#L829 assume !(0 == ~m_st~0); 2204626#L833 assume !(0 == ~t1_st~0); 2213863#L837 assume !(0 == ~t2_st~0); 2213864#L841 assume !(0 == ~t3_st~0); 2213869#L845 assume !(0 == ~t4_st~0); 2213872#L849 assume !(0 == ~t5_st~0); 2213867#L853 assume !(0 == ~t6_st~0); 2213868#L857 assume !(0 == ~t7_st~0); 2213871#L861 assume !(0 == ~t8_st~0); 2213865#L865 assume !(0 == ~t9_st~0); 2213866#L869 assume !(0 == ~t10_st~0); 2213870#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 2213873#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2227607#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2227605#L906 assume !(0 != eval_~tmp~0#1); 2227603#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2227601#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2227600#L1090-3 assume !(0 == ~M_E~0); 2227599#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2227597#L1095-3 assume !(0 == ~T2_E~0); 2227557#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2227527#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2227519#L1110-3 assume !(0 == ~T5_E~0); 2227510#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2227500#L1120-3 assume !(0 == ~T7_E~0); 2227491#L1125-3 assume !(0 == ~T8_E~0); 2227482#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2227473#L1135-3 assume !(0 == ~T10_E~0); 2227464#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2227455#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2227445#L1150-3 assume !(0 == ~E_2~0); 2227436#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2227429#L1160-3 assume !(0 == ~E_4~0); 2227423#L1165-3 assume !(0 == ~E_5~0); 2227415#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2227405#L1175-3 assume !(0 == ~E_7~0); 2227397#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2227389#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2227365#L1190-3 assume !(0 == ~E_10~0); 2227347#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2224980#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2224977#L525-36 assume 1 == ~m_pc~0; 2224974#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2224972#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2224970#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2224967#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2224965#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2224963#L544-36 assume !(1 == ~t1_pc~0); 2224960#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 2224958#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2224956#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2224954#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 2224952#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2224946#L563-36 assume !(1 == ~t2_pc~0); 2224944#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2224942#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2224939#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2224937#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 2224935#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2224933#L582-36 assume !(1 == ~t3_pc~0); 2224931#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2224929#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2224927#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2224925#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 2224923#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2224920#L601-36 assume !(1 == ~t4_pc~0); 2224917#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2224915#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2224913#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2224911#L1382-36 assume !(0 != activate_threads_~tmp___3~0#1); 2224909#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2224907#L620-36 assume !(1 == ~t5_pc~0); 2224905#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2224903#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2224900#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2224898#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 2224896#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2224894#L639-36 assume 1 == ~t6_pc~0; 2224891#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2224889#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2224887#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2224885#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2224883#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2224881#L658-36 assume !(1 == ~t7_pc~0); 2224878#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2224876#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2224873#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2224871#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2224869#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2224867#L677-36 assume !(1 == ~t8_pc~0); 2224865#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2224863#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2224861#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2224858#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2224856#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2224851#L696-36 assume !(1 == ~t9_pc~0); 2224849#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 2224847#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2224844#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2224842#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 2224839#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2224837#L715-36 assume !(1 == ~t10_pc~0); 2224835#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2224833#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2224830#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2224828#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2224826#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2224824#L734-36 assume !(1 == ~t11_pc~0); 2224821#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 2224819#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2224816#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2224814#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2224812#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2224810#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2224808#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2224804#L1218-3 assume !(1 == ~T2_E~0); 2224802#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2224800#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2224798#L1233-3 assume !(1 == ~T5_E~0); 2224795#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2224793#L1243-3 assume !(1 == ~T7_E~0); 2224791#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2224789#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2224787#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2224785#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2224783#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2224781#L1273-3 assume !(1 == ~E_2~0); 2224779#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2224776#L1283-3 assume !(1 == ~E_4~0); 2224774#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2224772#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2224770#L1298-3 assume !(1 == ~E_7~0); 2224768#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2224767#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2224763#L1313-3 assume !(1 == ~E_10~0); 2224761#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2224759#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2224756#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2224755#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2224754#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2224590#L1663 assume !(0 == start_simulation_~tmp~3#1); 2224588#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2215747#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2211335#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2211331#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2211329#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2211327#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2211325#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2211322#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 2197416#L1644-2 [2024-11-20 22:59:54,413 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:54,413 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 10 times [2024-11-20 22:59:54,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:54,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265562926] [2024-11-20 22:59:54,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:54,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:54,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:54,426 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-20 22:59:54,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:54,445 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-20 22:59:54,446 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:54,446 INFO L85 PathProgramCache]: Analyzing trace with hash -218595889, now seen corresponding path program 1 times [2024-11-20 22:59:54,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:54,446 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380898979] [2024-11-20 22:59:54,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:54,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:54,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:54,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:54,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:54,502 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380898979] [2024-11-20 22:59:54,502 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380898979] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:54,502 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:54,502 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-20 22:59:54,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [786096073] [2024-11-20 22:59:54,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:54,503 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:54,503 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:54,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-20 22:59:54,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-20 22:59:54,503 INFO L87 Difference]: Start difference. First operand 101686 states and 134427 transitions. cyclomatic complexity: 32773 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:54,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-20 22:59:54,896 INFO L93 Difference]: Finished difference Result 101974 states and 133898 transitions. [2024-11-20 22:59:54,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101974 states and 133898 transitions. [2024-11-20 22:59:55,928 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101424 [2024-11-20 22:59:56,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101974 states to 101974 states and 133898 transitions. [2024-11-20 22:59:56,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101974 [2024-11-20 22:59:56,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101974 [2024-11-20 22:59:56,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101974 states and 133898 transitions. [2024-11-20 22:59:56,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-20 22:59:56,192 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101974 states and 133898 transitions. [2024-11-20 22:59:56,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101974 states and 133898 transitions. [2024-11-20 22:59:56,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101974 to 101974. [2024-11-20 22:59:56,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101974 states, 101974 states have (on average 1.3130601918135996) internal successors, (133898), 101973 states have internal predecessors, (133898), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-20 22:59:57,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101974 states to 101974 states and 133898 transitions. [2024-11-20 22:59:57,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101974 states and 133898 transitions. [2024-11-20 22:59:57,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-20 22:59:57,608 INFO L425 stractBuchiCegarLoop]: Abstraction has 101974 states and 133898 transitions. [2024-11-20 22:59:57,608 INFO L332 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2024-11-20 22:59:57,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101974 states and 133898 transitions. [2024-11-20 22:59:57,862 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101424 [2024-11-20 22:59:57,863 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-20 22:59:57,863 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-20 22:59:57,864 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:57,864 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-20 22:59:57,864 INFO L745 eck$LassoCheckResult]: Stem: 2401026#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 2401027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2402164#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2402165#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2401493#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 2401494#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2401359#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2401248#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2400967#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2400614#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2400615#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2400659#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2400660#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2401650#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2401651#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2401702#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2401071#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2401072#L1090 assume !(0 == ~M_E~0); 2401121#L1090-2 assume !(0 == ~T1_E~0); 2401122#L1095-1 assume !(0 == ~T2_E~0); 2401868#L1100-1 assume !(0 == ~T3_E~0); 2401869#L1105-1 assume !(0 == ~T4_E~0); 2400884#L1110-1 assume !(0 == ~T5_E~0); 2400885#L1115-1 assume !(0 == ~T6_E~0); 2401288#L1120-1 assume !(0 == ~T7_E~0); 2401619#L1125-1 assume !(0 == ~T8_E~0); 2402307#L1130-1 assume !(0 == ~T9_E~0); 2401890#L1135-1 assume !(0 == ~T10_E~0); 2401077#L1140-1 assume !(0 == ~T11_E~0); 2401078#L1145-1 assume !(0 == ~E_1~0); 2401816#L1150-1 assume !(0 == ~E_2~0); 2401263#L1155-1 assume !(0 == ~E_3~0); 2401264#L1160-1 assume !(0 == ~E_4~0); 2401365#L1165-1 assume !(0 == ~E_5~0); 2401366#L1170-1 assume !(0 == ~E_6~0); 2402136#L1175-1 assume !(0 == ~E_7~0); 2401448#L1180-1 assume !(0 == ~E_8~0); 2401449#L1185-1 assume !(0 == ~E_9~0); 2401073#L1190-1 assume !(0 == ~E_10~0); 2401074#L1195-1 assume !(0 == ~E_11~0); 2401465#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2401281#L525 assume !(1 == ~m_pc~0); 2400704#L525-2 is_master_triggered_~__retres1~0#1 := 0; 2400705#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2402094#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2401955#L1350 assume !(0 != activate_threads_~tmp~1#1); 2401062#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2401063#L544 assume !(1 == ~t1_pc~0); 2401282#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2401283#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2400682#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2400683#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 2400908#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2401585#L563 assume !(1 == ~t2_pc~0); 2401802#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2400726#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2400727#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2401146#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 2401147#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2401674#L582 assume !(1 == ~t3_pc~0); 2401815#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2402243#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2400606#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2400607#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 2400790#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2400791#L601 assume !(1 == ~t4_pc~0); 2401832#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2401287#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2400804#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2400805#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 2401827#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2402228#L620 assume !(1 == ~t5_pc~0); 2401637#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2401638#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2401693#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2401992#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 2402258#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2402259#L639 assume !(1 == ~t6_pc~0); 2401617#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2401184#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2401185#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2401234#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 2401291#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2401292#L658 assume !(1 == ~t7_pc~0); 2401521#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2401522#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2402275#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2401752#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 2401065#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2401066#L677 assume !(1 == ~t8_pc~0); 2401088#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2400871#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2400872#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2401139#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 2401140#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2401943#L696 assume !(1 == ~t9_pc~0); 2401600#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2401601#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2401349#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2401350#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 2401627#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2401874#L715 assume !(1 == ~t10_pc~0); 2402186#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2401729#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2401507#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2401508#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 2401442#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2400860#L734 assume !(1 == ~t11_pc~0); 2400861#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2401369#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2401453#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2400604#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 2400605#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2401694#L1213 assume !(1 == ~M_E~0); 2401440#L1213-2 assume !(1 == ~T1_E~0); 2401441#L1218-1 assume !(1 == ~T2_E~0); 2400637#L1223-1 assume !(1 == ~T3_E~0); 2400638#L1228-1 assume !(1 == ~T4_E~0); 2401414#L1233-1 assume !(1 == ~T5_E~0); 2402260#L1238-1 assume !(1 == ~T6_E~0); 2401825#L1243-1 assume !(1 == ~T7_E~0); 2401826#L1248-1 assume !(1 == ~T8_E~0); 2401877#L1253-1 assume !(1 == ~T9_E~0); 2401878#L1258-1 assume !(1 == ~T10_E~0); 2401850#L1263-1 assume !(1 == ~T11_E~0); 2401851#L1268-1 assume !(1 == ~E_1~0); 2401642#L1273-1 assume !(1 == ~E_2~0); 2401643#L1278-1 assume !(1 == ~E_3~0); 2401180#L1283-1 assume !(1 == ~E_4~0); 2401181#L1288-1 assume !(1 == ~E_5~0); 2401998#L1293-1 assume !(1 == ~E_6~0); 2401950#L1298-1 assume !(1 == ~E_7~0); 2401679#L1303-1 assume !(1 == ~E_8~0); 2401191#L1308-1 assume !(1 == ~E_9~0); 2401081#L1313-1 assume !(1 == ~E_10~0); 2401082#L1318-1 assume !(1 == ~E_11~0); 2401089#L1323-1 assume { :end_inline_reset_delta_events } true; 2401090#L1644-2 [2024-11-20 22:59:57,865 INFO L747 eck$LassoCheckResult]: Loop: 2401090#L1644-2 assume !false; 2416320#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2416315#L1065-1 assume !false; 2416313#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2416310#L829 assume !(0 == ~m_st~0); 2416311#L833 assume !(0 == ~t1_st~0); 2421840#L837 assume !(0 == ~t2_st~0); 2421838#L841 assume !(0 == ~t3_st~0); 2421836#L845 assume !(0 == ~t4_st~0); 2421834#L849 assume !(0 == ~t5_st~0); 2421832#L853 assume !(0 == ~t6_st~0); 2421830#L857 assume !(0 == ~t7_st~0); 2421828#L861 assume !(0 == ~t8_st~0); 2421826#L865 assume !(0 == ~t9_st~0); 2421824#L869 assume !(0 == ~t10_st~0); 2421821#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 2421819#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2421817#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2421813#L906 assume !(0 != eval_~tmp~0#1); 2421811#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2421809#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2421807#L1090-3 assume !(0 == ~M_E~0); 2421804#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2421802#L1095-3 assume !(0 == ~T2_E~0); 2421800#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2421798#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2421796#L1110-3 assume !(0 == ~T5_E~0); 2421794#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2421792#L1120-3 assume !(0 == ~T7_E~0); 2421790#L1125-3 assume !(0 == ~T8_E~0); 2421788#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2421785#L1135-3 assume !(0 == ~T10_E~0); 2421783#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2421781#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2421779#L1150-3 assume !(0 == ~E_2~0); 2421777#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2421773#L1160-3 assume !(0 == ~E_4~0); 2421771#L1165-3 assume !(0 == ~E_5~0); 2421769#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2421767#L1175-3 assume !(0 == ~E_7~0); 2421766#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2421765#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2421764#L1190-3 assume !(0 == ~E_10~0); 2421762#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2421760#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2421758#L525-36 assume 1 == ~m_pc~0; 2421754#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2421752#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2421749#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2421745#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2421742#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2421739#L544-36 assume !(1 == ~t1_pc~0); 2421737#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 2421734#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2421732#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2421730#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 2421727#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2421712#L563-36 assume !(1 == ~t2_pc~0); 2421710#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2421708#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2421706#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2421704#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 2421702#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2421700#L582-36 assume !(1 == ~t3_pc~0); 2421698#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2421695#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2421693#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2421691#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 2421689#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2421687#L601-36 assume !(1 == ~t4_pc~0); 2421684#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2421682#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2421680#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2421678#L1382-36 assume !(0 != activate_threads_~tmp___3~0#1); 2421676#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2421674#L620-36 assume !(1 == ~t5_pc~0); 2421672#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2421669#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2421667#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2421665#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 2421663#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2421661#L639-36 assume 1 == ~t6_pc~0; 2421658#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2421656#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2421654#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2421652#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2421650#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2421648#L658-36 assume !(1 == ~t7_pc~0); 2421645#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2421643#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2421640#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2421638#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 2421636#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2421634#L677-36 assume !(1 == ~t8_pc~0); 2421632#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2421629#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2421627#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2421625#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2421623#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2421618#L696-36 assume !(1 == ~t9_pc~0); 2421616#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 2421614#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2421612#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2421610#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 2421607#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2421605#L715-36 assume !(1 == ~t10_pc~0); 2421601#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2421599#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2421597#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2421595#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2421592#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2421590#L734-36 assume 1 == ~t11_pc~0; 2421588#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2421585#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2421583#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2421581#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2421579#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2421577#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2421575#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2421572#L1218-3 assume !(1 == ~T2_E~0); 2421570#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2421568#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2421566#L1233-3 assume !(1 == ~T5_E~0); 2421564#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2421563#L1243-3 assume !(1 == ~T7_E~0); 2421559#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2421557#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2421555#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2421552#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2421551#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2421550#L1273-3 assume !(1 == ~E_2~0); 2421547#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2421543#L1283-3 assume !(1 == ~E_4~0); 2421539#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2421535#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2421531#L1298-3 assume !(1 == ~E_7~0); 2421527#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2421523#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2421519#L1313-3 assume !(1 == ~E_10~0); 2421515#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2421514#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2421513#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2421511#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2421510#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2416343#L1663 assume !(0 == start_simulation_~tmp~3#1); 2416341#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2416338#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2416336#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2416334#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2416330#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2416328#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2416326#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2416324#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 2401090#L1644-2 [2024-11-20 22:59:57,865 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:57,865 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 11 times [2024-11-20 22:59:57,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:57,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679375441] [2024-11-20 22:59:57,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:57,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:57,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:57,876 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-20 22:59:57,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-20 22:59:57,898 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-20 22:59:57,899 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-20 22:59:57,899 INFO L85 PathProgramCache]: Analyzing trace with hash -1678776530, now seen corresponding path program 1 times [2024-11-20 22:59:57,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-20 22:59:57,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499343026] [2024-11-20 22:59:57,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-20 22:59:57,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-20 22:59:57,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-20 22:59:57,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-20 22:59:57,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-20 22:59:57,961 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [499343026] [2024-11-20 22:59:57,961 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [499343026] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-20 22:59:57,961 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-20 22:59:57,962 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-20 22:59:57,962 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1263024694] [2024-11-20 22:59:57,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-20 22:59:57,962 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-20 22:59:57,962 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-20 22:59:57,962 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-20 22:59:57,963 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-20 22:59:57,963 INFO L87 Difference]: Start difference. First operand 101974 states and 133898 transitions. cyclomatic complexity: 31956 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)