./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 803cd42f Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-assert-order-craig-803cd42-m [2024-11-23 02:53:24,831 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-23 02:53:24,892 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-23 02:53:24,897 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-23 02:53:24,899 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-23 02:53:24,935 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-23 02:53:24,935 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-23 02:53:24,936 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-23 02:53:24,936 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-23 02:53:24,938 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-23 02:53:24,938 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-23 02:53:24,939 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-23 02:53:24,939 INFO L153 SettingsManager]: * Use SBE=true [2024-11-23 02:53:24,939 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-23 02:53:24,940 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-23 02:53:24,940 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-23 02:53:24,940 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-23 02:53:24,940 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-23 02:53:24,941 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-23 02:53:24,941 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-23 02:53:24,941 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-23 02:53:24,945 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-23 02:53:24,946 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-23 02:53:24,946 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-23 02:53:24,946 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-23 02:53:24,946 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-23 02:53:24,947 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-23 02:53:24,947 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-23 02:53:24,947 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-23 02:53:24,947 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-23 02:53:24,947 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-23 02:53:24,948 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-23 02:53:24,948 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-23 02:53:24,948 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-23 02:53:24,948 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-23 02:53:24,948 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-23 02:53:24,949 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-23 02:53:24,949 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-23 02:53:24,950 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-23 02:53:24,951 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f [2024-11-23 02:53:25,199 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-23 02:53:25,225 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-23 02:53:25,228 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-23 02:53:25,230 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-23 02:53:25,231 INFO L274 PluginConnector]: CDTParser initialized [2024-11-23 02:53:25,232 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2024-11-23 02:53:26,763 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-23 02:53:26,949 INFO L384 CDTParser]: Found 1 translation units. [2024-11-23 02:53:26,949 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2024-11-23 02:53:26,958 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4b35f7cc6/6e9f7987c4e14cf6b60eb49b6d556c67/FLAG4f3e16a49 [2024-11-23 02:53:27,331 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4b35f7cc6/6e9f7987c4e14cf6b60eb49b6d556c67 [2024-11-23 02:53:27,334 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-23 02:53:27,335 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-23 02:53:27,336 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-23 02:53:27,336 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-23 02:53:27,342 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-23 02:53:27,343 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,344 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7d786ee8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27, skipping insertion in model container [2024-11-23 02:53:27,344 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,373 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-23 02:53:27,597 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-23 02:53:27,618 INFO L200 MainTranslator]: Completed pre-run [2024-11-23 02:53:27,647 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-23 02:53:27,664 INFO L204 MainTranslator]: Completed translation [2024-11-23 02:53:27,664 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27 WrapperNode [2024-11-23 02:53:27,665 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-23 02:53:27,665 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-23 02:53:27,666 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-23 02:53:27,666 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-23 02:53:27,672 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,680 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,712 INFO L138 Inliner]: procedures = 29, calls = 32, calls flagged for inlining = 27, calls inlined = 29, statements flattened = 307 [2024-11-23 02:53:27,716 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-23 02:53:27,717 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-23 02:53:27,717 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-23 02:53:27,717 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-23 02:53:27,729 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,730 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,735 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,765 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-23 02:53:27,765 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,766 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,774 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,787 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,789 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,794 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,801 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-23 02:53:27,802 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-23 02:53:27,805 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-23 02:53:27,805 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-23 02:53:27,806 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (1/1) ... [2024-11-23 02:53:27,816 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:53:27,830 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:53:27,850 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:53:27,854 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-23 02:53:27,901 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-23 02:53:27,901 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-23 02:53:27,901 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-23 02:53:27,901 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-23 02:53:27,981 INFO L238 CfgBuilder]: Building ICFG [2024-11-23 02:53:27,983 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-23 02:53:28,329 INFO L? ?]: Removed 41 outVars from TransFormulas that were not future-live. [2024-11-23 02:53:28,330 INFO L287 CfgBuilder]: Performing block encoding [2024-11-23 02:53:28,343 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-23 02:53:28,343 INFO L316 CfgBuilder]: Removed 4 assume(true) statements. [2024-11-23 02:53:28,344 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:53:28 BoogieIcfgContainer [2024-11-23 02:53:28,344 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-23 02:53:28,345 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-23 02:53:28,345 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-23 02:53:28,350 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-23 02:53:28,351 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:53:28,352 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 02:53:27" (1/3) ... [2024-11-23 02:53:28,354 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@b5a3705 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:53:28, skipping insertion in model container [2024-11-23 02:53:28,354 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:53:28,354 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:53:27" (2/3) ... [2024-11-23 02:53:28,354 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@b5a3705 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:53:28, skipping insertion in model container [2024-11-23 02:53:28,354 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:53:28,355 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:53:28" (3/3) ... [2024-11-23 02:53:28,356 INFO L332 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-1.c [2024-11-23 02:53:28,419 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-23 02:53:28,419 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-23 02:53:28,419 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-23 02:53:28,419 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-23 02:53:28,420 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-23 02:53:28,420 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-23 02:53:28,420 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-23 02:53:28,420 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-23 02:53:28,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:28,450 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2024-11-23 02:53:28,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:28,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:28,458 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:28,458 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:28,458 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-23 02:53:28,459 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:28,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2024-11-23 02:53:28,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:28,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:28,465 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:28,466 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:28,475 INFO L745 eck$LassoCheckResult]: Stem: 19#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 31#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 101#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64#L222true assume !(1 == ~q_req_up~0); 9#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 32#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 39#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L275true assume !(0 == ~q_read_ev~0); 93#L275-2true assume !(0 == ~q_write_ev~0); 23#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 106#L65true assume !(1 == ~p_dw_pc~0); 30#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 56#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 74#is_do_write_p_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 36#L315true assume !(0 != activate_threads_~tmp~1#1); 62#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 96#L84true assume 1 == ~c_dr_pc~0; 25#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 68#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 21#is_do_read_c_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4#L323true assume !(0 != activate_threads_~tmp___0~1#1); 47#L323-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97#L293true assume !(1 == ~q_read_ev~0); 2#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 37#L298-1true assume { :end_inline_reset_delta_events } true; 11#L419-2true [2024-11-23 02:53:28,477 INFO L747 eck$LassoCheckResult]: Loop: 11#L419-2true assume !false; 27#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 102#L364true assume !true; 65#eval_returnLabel#1true havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83#L222-3true assume !(1 == ~q_req_up~0); 33#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 41#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 54#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 61#L65-3true assume !(1 == ~p_dw_pc~0); 17#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 94#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 55#is_do_write_p_triggered_returnLabel#2true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 42#L315-3true assume !(0 != activate_threads_~tmp~1#1); 84#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 59#L84-3true assume 1 == ~c_dr_pc~0; 44#L85-1true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 78#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 29#is_do_read_c_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 104#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 77#L323-5true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 5#L293-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 53#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 75#exists_runnable_thread_returnLabel#2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 13#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 7#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28#L436true assume !(0 != start_simulation_~tmp~4#1); 11#L419-2true [2024-11-23 02:53:28,483 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:28,484 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2024-11-23 02:53:28,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:28,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534197044] [2024-11-23 02:53:28,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:28,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:28,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:28,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:28,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:28,722 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534197044] [2024-11-23 02:53:28,722 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534197044] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:28,722 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:28,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:53:28,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [757999027] [2024-11-23 02:53:28,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:28,727 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:53:28,728 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:28,728 INFO L85 PathProgramCache]: Analyzing trace with hash -573197680, now seen corresponding path program 1 times [2024-11-23 02:53:28,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:28,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468686066] [2024-11-23 02:53:28,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:28,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:28,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:28,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:28,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:28,758 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [468686066] [2024-11-23 02:53:28,758 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [468686066] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:28,758 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:28,759 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:53:28,759 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1312028169] [2024-11-23 02:53:28,759 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:28,760 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:53:28,761 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:53:28,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:53:28,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:53:28,790 INFO L87 Difference]: Start difference. First operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:28,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:53:28,816 INFO L93 Difference]: Finished difference Result 101 states and 144 transitions. [2024-11-23 02:53:28,818 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 144 transitions. [2024-11-23 02:53:28,821 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2024-11-23 02:53:28,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 95 states and 138 transitions. [2024-11-23 02:53:28,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2024-11-23 02:53:28,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2024-11-23 02:53:28,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 138 transitions. [2024-11-23 02:53:28,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:53:28,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2024-11-23 02:53:28,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 138 transitions. [2024-11-23 02:53:28,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2024-11-23 02:53:28,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4526315789473685) internal successors, (138), 94 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:28,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 138 transitions. [2024-11-23 02:53:28,908 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2024-11-23 02:53:28,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:53:28,913 INFO L425 stractBuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2024-11-23 02:53:28,914 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-23 02:53:28,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 138 transitions. [2024-11-23 02:53:28,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2024-11-23 02:53:28,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:28,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:28,919 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:28,919 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:28,920 INFO L745 eck$LassoCheckResult]: Stem: 272#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 297#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 250#L222 assume !(1 == ~q_req_up~0); 239#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 240#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 280#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 301#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 299#L275 assume !(0 == ~q_read_ev~0); 300#L275-2 assume !(0 == ~q_write_ev~0); 286#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 287#L65 assume !(1 == ~p_dw_pc~0); 283#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 282#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 267#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 268#L315 assume !(0 != activate_threads_~tmp~1#1); 245#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 246#L84 assume 1 == ~c_dr_pc~0; 292#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 259#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 260#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 222#L323 assume !(0 != activate_threads_~tmp___0~1#1); 223#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 308#L293 assume !(1 == ~q_read_ev~0); 215#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 216#L298-1 assume { :end_inline_reset_delta_events } true; 241#L419-2 [2024-11-23 02:53:28,920 INFO L747 eck$LassoCheckResult]: Loop: 241#L419-2 assume !false; 242#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 256#L364 assume !false; 288#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 252#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 218#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 237#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 238#L344 assume !(0 != eval_~tmp___1~0#1); 253#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 254#L222-3 assume !(1 == ~q_req_up~0); 285#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 278#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 279#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 306#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 228#L65-3 assume !(1 == ~p_dw_pc~0); 229#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 263#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 305#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 307#L315-3 assume !(0 != activate_threads_~tmp~1#1); 295#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 219#L84-3 assume 1 == ~c_dr_pc~0; 220#L85-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 276#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 277#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 294#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 274#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 275#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 226#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 227#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 289#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 290#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 269#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 247#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 233#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 234#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 293#L436 assume !(0 != start_simulation_~tmp~4#1); 241#L419-2 [2024-11-23 02:53:28,921 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:28,921 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2024-11-23 02:53:28,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:28,922 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103087875] [2024-11-23 02:53:28,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:28,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:28,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:29,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:29,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:29,095 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [103087875] [2024-11-23 02:53:29,095 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [103087875] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:29,095 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:29,095 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-23 02:53:29,096 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237464996] [2024-11-23 02:53:29,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:29,096 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:53:29,097 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:29,097 INFO L85 PathProgramCache]: Analyzing trace with hash -1808359021, now seen corresponding path program 1 times [2024-11-23 02:53:29,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:29,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381956451] [2024-11-23 02:53:29,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:29,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:29,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:29,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:29,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:29,200 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381956451] [2024-11-23 02:53:29,200 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381956451] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:29,201 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:29,201 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:53:29,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [557700152] [2024-11-23 02:53:29,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:29,202 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:53:29,203 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:53:29,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:53:29,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:53:29,205 INFO L87 Difference]: Start difference. First operand 95 states and 138 transitions. cyclomatic complexity: 44 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:29,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:53:29,326 INFO L93 Difference]: Finished difference Result 211 states and 299 transitions. [2024-11-23 02:53:29,327 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 211 states and 299 transitions. [2024-11-23 02:53:29,330 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 177 [2024-11-23 02:53:29,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 211 states to 211 states and 299 transitions. [2024-11-23 02:53:29,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 211 [2024-11-23 02:53:29,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 211 [2024-11-23 02:53:29,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 211 states and 299 transitions. [2024-11-23 02:53:29,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:53:29,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 211 states and 299 transitions. [2024-11-23 02:53:29,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states and 299 transitions. [2024-11-23 02:53:29,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 196. [2024-11-23 02:53:29,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.4285714285714286) internal successors, (280), 195 states have internal predecessors, (280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:29,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 280 transitions. [2024-11-23 02:53:29,349 INFO L240 hiAutomatonCegarLoop]: Abstraction has 196 states and 280 transitions. [2024-11-23 02:53:29,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:53:29,350 INFO L425 stractBuchiCegarLoop]: Abstraction has 196 states and 280 transitions. [2024-11-23 02:53:29,350 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-23 02:53:29,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 280 transitions. [2024-11-23 02:53:29,352 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 164 [2024-11-23 02:53:29,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:29,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:29,353 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:29,353 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:29,354 INFO L745 eck$LassoCheckResult]: Stem: 589#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 590#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 614#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 567#L222 assume !(1 == ~q_req_up~0); 554#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 555#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 600#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 619#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 617#L275 assume !(0 == ~q_read_ev~0); 618#L275-2 assume !(0 == ~q_write_ev~0); 603#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 604#L65 assume !(1 == ~p_dw_pc~0); 611#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 612#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 587#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 588#L315 assume !(0 != activate_threads_~tmp~1#1); 562#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 563#L84 assume !(1 == ~c_dr_pc~0); 582#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 577#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 578#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 540#L323 assume !(0 != activate_threads_~tmp___0~1#1); 541#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 627#L293 assume !(1 == ~q_read_ev~0); 534#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 535#L298-1 assume { :end_inline_reset_delta_events } true; 558#L419-2 [2024-11-23 02:53:29,354 INFO L747 eck$LassoCheckResult]: Loop: 558#L419-2 assume !false; 559#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 573#L364 assume !false; 605#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 569#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 537#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 556#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 557#L344 assume !(0 != eval_~tmp___1~0#1); 570#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 571#L222-3 assume !(1 == ~q_req_up~0); 602#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 598#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 599#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 625#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 546#L65-3 assume !(1 == ~p_dw_pc~0); 547#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 581#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 624#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 626#L315-3 assume !(0 != activate_threads_~tmp~1#1); 613#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 538#L84-3 assume !(1 == ~c_dr_pc~0); 539#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 596#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 597#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 610#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 594#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 595#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 623#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 635#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 636#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 719#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 718#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 564#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 548#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 549#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 609#L436 assume !(0 != start_simulation_~tmp~4#1); 558#L419-2 [2024-11-23 02:53:29,355 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:29,355 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2024-11-23 02:53:29,355 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:29,356 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1053598984] [2024-11-23 02:53:29,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:29,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:29,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:29,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:29,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:29,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1053598984] [2024-11-23 02:53:29,442 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1053598984] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:29,442 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:29,442 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-23 02:53:29,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1457641141] [2024-11-23 02:53:29,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:29,443 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:53:29,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:29,443 INFO L85 PathProgramCache]: Analyzing trace with hash -631754702, now seen corresponding path program 1 times [2024-11-23 02:53:29,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:29,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058189769] [2024-11-23 02:53:29,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:29,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:29,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:29,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:29,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:29,530 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1058189769] [2024-11-23 02:53:29,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1058189769] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:29,530 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:29,530 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:53:29,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473260662] [2024-11-23 02:53:29,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:29,531 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:53:29,531 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:53:29,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:53:29,532 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:53:29,532 INFO L87 Difference]: Start difference. First operand 196 states and 280 transitions. cyclomatic complexity: 86 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:29,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:53:29,657 INFO L93 Difference]: Finished difference Result 449 states and 621 transitions. [2024-11-23 02:53:29,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 621 transitions. [2024-11-23 02:53:29,661 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 375 [2024-11-23 02:53:29,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 621 transitions. [2024-11-23 02:53:29,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2024-11-23 02:53:29,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2024-11-23 02:53:29,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 621 transitions. [2024-11-23 02:53:29,667 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:53:29,668 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 621 transitions. [2024-11-23 02:53:29,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 621 transitions. [2024-11-23 02:53:29,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2024-11-23 02:53:29,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449 states, 449 states have (on average 1.3830734966592428) internal successors, (621), 448 states have internal predecessors, (621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:29,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 621 transitions. [2024-11-23 02:53:29,702 INFO L240 hiAutomatonCegarLoop]: Abstraction has 449 states and 621 transitions. [2024-11-23 02:53:29,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:53:29,704 INFO L425 stractBuchiCegarLoop]: Abstraction has 449 states and 621 transitions. [2024-11-23 02:53:29,704 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-23 02:53:29,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449 states and 621 transitions. [2024-11-23 02:53:29,706 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 375 [2024-11-23 02:53:29,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:29,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:29,709 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:29,709 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:29,709 INFO L745 eck$LassoCheckResult]: Stem: 1254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1283#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1227#L222 assume !(1 == ~q_req_up~0); 1229#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1266#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1267#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1295#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1296#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1287#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1299#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1344#L65 assume !(1 == ~p_dw_pc~0); 1343#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1342#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1341#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1340#L315 assume !(0 != activate_threads_~tmp~1#1); 1339#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1338#L84 assume !(1 == ~c_dr_pc~0); 1337#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1336#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1335#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1334#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1333#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1332#L293 assume !(1 == ~q_read_ev~0); 1331#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1193#L298-1 assume { :end_inline_reset_delta_events } true; 1219#L419-2 [2024-11-23 02:53:29,713 INFO L747 eck$LassoCheckResult]: Loop: 1219#L419-2 assume !false; 1220#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1382#L364 assume !false; 1377#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1230#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1197#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1215#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1216#L344 assume !(0 != eval_~tmp___1~0#1); 1257#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1552#L222-3 assume !(1 == ~q_req_up~0); 1549#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1548#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1543#L275-5 assume !(0 == ~q_write_ev~0); 1541#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1539#L65-3 assume !(1 == ~p_dw_pc~0); 1537#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 1535#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1533#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1531#L315-3 assume !(0 != activate_threads_~tmp~1#1); 1529#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1527#L84-3 assume !(1 == ~c_dr_pc~0); 1525#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 1523#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1521#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1519#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1518#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1517#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1516#L293-5 assume !(1 == ~q_write_ev~0); 1514#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1438#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1421#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1398#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1395#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1392#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1317#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1278#L436 assume !(0 != start_simulation_~tmp~4#1); 1219#L419-2 [2024-11-23 02:53:29,714 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:29,714 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2024-11-23 02:53:29,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:29,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598517932] [2024-11-23 02:53:29,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:29,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:29,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:29,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:29,768 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:29,768 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598517932] [2024-11-23 02:53:29,768 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598517932] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:29,769 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:29,770 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:53:29,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1650504710] [2024-11-23 02:53:29,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:29,770 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:53:29,772 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:29,772 INFO L85 PathProgramCache]: Analyzing trace with hash -85709838, now seen corresponding path program 1 times [2024-11-23 02:53:29,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:29,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651563286] [2024-11-23 02:53:29,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:29,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:29,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:29,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:29,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:29,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651563286] [2024-11-23 02:53:29,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [651563286] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:29,829 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:29,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:53:29,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897064801] [2024-11-23 02:53:29,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:29,830 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:53:29,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:53:29,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:53:29,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:53:29,832 INFO L87 Difference]: Start difference. First operand 449 states and 621 transitions. cyclomatic complexity: 176 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:29,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:53:29,871 INFO L93 Difference]: Finished difference Result 701 states and 951 transitions. [2024-11-23 02:53:29,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 701 states and 951 transitions. [2024-11-23 02:53:29,877 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 586 [2024-11-23 02:53:29,883 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 701 states to 701 states and 951 transitions. [2024-11-23 02:53:29,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 701 [2024-11-23 02:53:29,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 701 [2024-11-23 02:53:29,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 701 states and 951 transitions. [2024-11-23 02:53:29,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:53:29,891 INFO L218 hiAutomatonCegarLoop]: Abstraction has 701 states and 951 transitions. [2024-11-23 02:53:29,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 701 states and 951 transitions. [2024-11-23 02:53:29,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 701 to 510. [2024-11-23 02:53:29,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 510 states, 510 states have (on average 1.3588235294117648) internal successors, (693), 509 states have internal predecessors, (693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:29,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 510 states to 510 states and 693 transitions. [2024-11-23 02:53:29,912 INFO L240 hiAutomatonCegarLoop]: Abstraction has 510 states and 693 transitions. [2024-11-23 02:53:29,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:53:29,913 INFO L425 stractBuchiCegarLoop]: Abstraction has 510 states and 693 transitions. [2024-11-23 02:53:29,913 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-23 02:53:29,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 510 states and 693 transitions. [2024-11-23 02:53:29,916 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 422 [2024-11-23 02:53:29,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:29,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:29,917 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:29,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:29,918 INFO L745 eck$LassoCheckResult]: Stem: 2411#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 2412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2439#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2386#L222 assume !(1 == ~q_req_up~0); 2371#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2372#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2421#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2444#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2441#L275 assume !(0 == ~q_read_ev~0); 2442#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2452#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2493#L65 assume !(1 == ~p_dw_pc~0); 2491#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 2489#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2487#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2485#L315 assume !(0 != activate_threads_~tmp~1#1); 2483#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2481#L84 assume !(1 == ~c_dr_pc~0); 2479#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 2477#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2475#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2473#L323 assume !(0 != activate_threads_~tmp___0~1#1); 2471#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2469#L293 assume !(1 == ~q_read_ev~0); 2466#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2352#L298-1 assume { :end_inline_reset_delta_events } true; 2377#L419-2 [2024-11-23 02:53:29,918 INFO L747 eck$LassoCheckResult]: Loop: 2377#L419-2 assume !false; 2378#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2392#L364 assume !false; 2426#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2388#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2356#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2373#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2374#L344 assume !(0 != eval_~tmp___1~0#1); 2414#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2823#L222-3 assume !(1 == ~q_req_up~0); 2820#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2819#L275-3 assume !(0 == ~q_read_ev~0); 2817#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2816#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2815#L65-3 assume !(1 == ~p_dw_pc~0); 2814#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 2813#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2812#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2811#L315-3 assume !(0 != activate_threads_~tmp~1#1); 2810#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2809#L84-3 assume !(1 == ~c_dr_pc~0); 2808#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2807#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2806#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2805#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2804#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2803#L293-3 assume !(1 == ~q_read_ev~0); 2726#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2802#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2563#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2560#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2406#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2407#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2367#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2368#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2433#L436 assume !(0 != start_simulation_~tmp~4#1); 2377#L419-2 [2024-11-23 02:53:29,919 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:29,919 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2024-11-23 02:53:29,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:29,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580471822] [2024-11-23 02:53:29,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:29,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:29,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:29,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:29,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:29,968 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1580471822] [2024-11-23 02:53:29,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1580471822] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:29,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:29,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-23 02:53:29,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644539866] [2024-11-23 02:53:29,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:29,969 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:53:29,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:29,970 INFO L85 PathProgramCache]: Analyzing trace with hash -884233102, now seen corresponding path program 1 times [2024-11-23 02:53:29,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:29,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306035733] [2024-11-23 02:53:29,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:29,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:29,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:30,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:30,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:30,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [306035733] [2024-11-23 02:53:30,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [306035733] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:30,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:30,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:53:30,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [482535231] [2024-11-23 02:53:30,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:30,024 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:53:30,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:53:30,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:53:30,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:53:30,025 INFO L87 Difference]: Start difference. First operand 510 states and 693 transitions. cyclomatic complexity: 185 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:53:30,101 INFO L93 Difference]: Finished difference Result 745 states and 1002 transitions. [2024-11-23 02:53:30,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 745 states and 1002 transitions. [2024-11-23 02:53:30,129 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 622 [2024-11-23 02:53:30,135 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 745 states to 745 states and 1002 transitions. [2024-11-23 02:53:30,135 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 745 [2024-11-23 02:53:30,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 745 [2024-11-23 02:53:30,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 745 states and 1002 transitions. [2024-11-23 02:53:30,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:53:30,138 INFO L218 hiAutomatonCegarLoop]: Abstraction has 745 states and 1002 transitions. [2024-11-23 02:53:30,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 745 states and 1002 transitions. [2024-11-23 02:53:30,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 745 to 563. [2024-11-23 02:53:30,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 563 states, 563 states have (on average 1.3481349911190053) internal successors, (759), 562 states have internal predecessors, (759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 759 transitions. [2024-11-23 02:53:30,155 INFO L240 hiAutomatonCegarLoop]: Abstraction has 563 states and 759 transitions. [2024-11-23 02:53:30,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:53:30,156 INFO L425 stractBuchiCegarLoop]: Abstraction has 563 states and 759 transitions. [2024-11-23 02:53:30,157 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-23 02:53:30,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 563 states and 759 transitions. [2024-11-23 02:53:30,164 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 458 [2024-11-23 02:53:30,164 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:30,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:30,165 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,169 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,169 INFO L745 eck$LassoCheckResult]: Stem: 3680#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3705#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3653#L222 assume !(1 == ~q_req_up~0); 3641#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3642#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3781#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3719#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3707#L275 assume !(0 == ~q_read_ev~0); 3708#L275-2 assume !(0 == ~q_write_ev~0); 3693#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3694#L65 assume !(1 == ~p_dw_pc~0); 3701#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3702#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3675#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3676#L315 assume !(0 != activate_threads_~tmp~1#1); 3647#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3648#L84 assume !(1 == ~c_dr_pc~0); 3670#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3663#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3664#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3624#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3625#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3725#L293 assume !(1 == ~q_read_ev~0); 3618#L293-2 assume !(1 == ~q_write_ev~0); 3619#L298-1 assume { :end_inline_reset_delta_events } true; 3718#L419-2 [2024-11-23 02:53:30,170 INFO L747 eck$LassoCheckResult]: Loop: 3718#L419-2 assume !false; 3834#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3831#L364 assume !false; 3829#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3827#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3669#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3639#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3640#L344 assume !(0 != eval_~tmp___1~0#1); 3679#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4100#L222-3 assume !(1 == ~q_req_up~0); 4101#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4164#L275-3 assume !(0 == ~q_read_ev~0); 3721#L275-5 assume !(0 == ~q_write_ev~0); 3722#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3630#L65-3 assume !(1 == ~p_dw_pc~0); 3631#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 4176#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4175#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4174#L315-3 assume !(0 != activate_threads_~tmp~1#1); 4173#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4172#L84-3 assume !(1 == ~c_dr_pc~0); 4171#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 4170#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4169#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4168#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 4166#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4165#L293-3 assume !(1 == ~q_read_ev~0); 3628#L293-5 assume !(1 == ~q_write_ev~0); 3629#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3695#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3696#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3674#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3649#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3634#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3635#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3731#L436 assume !(0 != start_simulation_~tmp~4#1); 3718#L419-2 [2024-11-23 02:53:30,173 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,174 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2024-11-23 02:53:30,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,174 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92512329] [2024-11-23 02:53:30,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:30,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:30,217 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:53:30,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:30,251 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:53:30,251 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,251 INFO L85 PathProgramCache]: Analyzing trace with hash -338188238, now seen corresponding path program 1 times [2024-11-23 02:53:30,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459203713] [2024-11-23 02:53:30,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:30,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:30,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:30,303 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:30,303 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459203713] [2024-11-23 02:53:30,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [459203713] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:30,304 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:30,304 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:53:30,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636915541] [2024-11-23 02:53:30,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:30,305 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:53:30,305 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:53:30,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:53:30,306 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:53:30,307 INFO L87 Difference]: Start difference. First operand 563 states and 759 transitions. cyclomatic complexity: 198 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:53:30,340 INFO L93 Difference]: Finished difference Result 593 states and 789 transitions. [2024-11-23 02:53:30,340 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 593 states and 789 transitions. [2024-11-23 02:53:30,344 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2024-11-23 02:53:30,347 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 593 states to 593 states and 789 transitions. [2024-11-23 02:53:30,348 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 593 [2024-11-23 02:53:30,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 593 [2024-11-23 02:53:30,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 593 states and 789 transitions. [2024-11-23 02:53:30,349 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:53:30,349 INFO L218 hiAutomatonCegarLoop]: Abstraction has 593 states and 789 transitions. [2024-11-23 02:53:30,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 593 states and 789 transitions. [2024-11-23 02:53:30,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 593 to 581. [2024-11-23 02:53:30,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 581 states, 581 states have (on average 1.3373493975903614) internal successors, (777), 580 states have internal predecessors, (777), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 581 states to 581 states and 777 transitions. [2024-11-23 02:53:30,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 581 states and 777 transitions. [2024-11-23 02:53:30,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:53:30,361 INFO L425 stractBuchiCegarLoop]: Abstraction has 581 states and 777 transitions. [2024-11-23 02:53:30,361 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-23 02:53:30,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 581 states and 777 transitions. [2024-11-23 02:53:30,364 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 476 [2024-11-23 02:53:30,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:30,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:30,367 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,368 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,368 INFO L745 eck$LassoCheckResult]: Stem: 4842#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 4843#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4875#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4818#L222 assume !(1 == ~q_req_up~0); 4820#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4958#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4956#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4954#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4952#L275 assume !(0 == ~q_read_ev~0); 4890#L275-2 assume !(0 == ~q_write_ev~0); 4891#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4948#L65 assume !(1 == ~p_dw_pc~0); 4946#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 4944#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4942#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4940#L315 assume !(0 != activate_threads_~tmp~1#1); 4938#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4936#L84 assume !(1 == ~c_dr_pc~0); 4934#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 4932#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4930#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4928#L323 assume !(0 != activate_threads_~tmp___0~1#1); 4926#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4924#L293 assume !(1 == ~q_read_ev~0); 4782#L293-2 assume !(1 == ~q_write_ev~0); 4783#L298-1 assume { :end_inline_reset_delta_events } true; 4808#L419-2 [2024-11-23 02:53:30,369 INFO L747 eck$LassoCheckResult]: Loop: 4808#L419-2 assume !false; 4809#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 4823#L364 assume !false; 5297#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5296#L255 assume !(0 == ~p_dw_st~0); 5295#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 5294#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5290#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5284#L344 assume !(0 != eval_~tmp___1~0#1); 5285#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4867#L222-3 assume !(1 == ~q_req_up~0); 4868#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4852#L275-3 assume !(0 == ~q_read_ev~0); 4853#L275-5 assume !(0 == ~q_write_ev~0); 4893#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5329#L65-3 assume !(1 == ~p_dw_pc~0); 5327#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 5325#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5323#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5321#L315-3 assume !(0 != activate_threads_~tmp~1#1); 5319#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5317#L84-3 assume !(1 == ~c_dr_pc~0); 5315#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 5313#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5311#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5309#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5307#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5305#L293-3 assume !(1 == ~q_read_ev~0); 4793#L293-5 assume !(1 == ~q_write_ev~0); 4794#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4861#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4862#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5302#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5301#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5300#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5299#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5298#L436 assume !(0 != start_simulation_~tmp~4#1); 4808#L419-2 [2024-11-23 02:53:30,371 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,371 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2024-11-23 02:53:30,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [952646652] [2024-11-23 02:53:30,372 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:53:30,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,387 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:53:30,388 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:53:30,388 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:53:30,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:30,399 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:53:30,400 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,400 INFO L85 PathProgramCache]: Analyzing trace with hash 22665520, now seen corresponding path program 1 times [2024-11-23 02:53:30,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885264314] [2024-11-23 02:53:30,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:30,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:30,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:30,427 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:30,428 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885264314] [2024-11-23 02:53:30,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885264314] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:30,429 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:30,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:53:30,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378783897] [2024-11-23 02:53:30,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:30,430 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:53:30,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:53:30,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:53:30,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:53:30,431 INFO L87 Difference]: Start difference. First operand 581 states and 777 transitions. cyclomatic complexity: 198 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:53:30,456 INFO L93 Difference]: Finished difference Result 905 states and 1173 transitions. [2024-11-23 02:53:30,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 905 states and 1173 transitions. [2024-11-23 02:53:30,462 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 722 [2024-11-23 02:53:30,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 905 states to 905 states and 1173 transitions. [2024-11-23 02:53:30,467 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 905 [2024-11-23 02:53:30,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 905 [2024-11-23 02:53:30,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 905 states and 1173 transitions. [2024-11-23 02:53:30,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:53:30,469 INFO L218 hiAutomatonCegarLoop]: Abstraction has 905 states and 1173 transitions. [2024-11-23 02:53:30,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 905 states and 1173 transitions. [2024-11-23 02:53:30,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 905 to 905. [2024-11-23 02:53:30,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 905 states, 905 states have (on average 1.296132596685083) internal successors, (1173), 904 states have internal predecessors, (1173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 905 states to 905 states and 1173 transitions. [2024-11-23 02:53:30,484 INFO L240 hiAutomatonCegarLoop]: Abstraction has 905 states and 1173 transitions. [2024-11-23 02:53:30,485 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:53:30,486 INFO L425 stractBuchiCegarLoop]: Abstraction has 905 states and 1173 transitions. [2024-11-23 02:53:30,486 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-23 02:53:30,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 905 states and 1173 transitions. [2024-11-23 02:53:30,491 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 722 [2024-11-23 02:53:30,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:30,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:30,492 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,492 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,493 INFO L745 eck$LassoCheckResult]: Stem: 6337#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6338#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6369#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6311#L222 assume !(1 == ~q_req_up~0); 6313#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6349#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 6350#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6385#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6371#L275 assume !(0 == ~q_read_ev~0); 6372#L275-2 assume !(0 == ~q_write_ev~0); 6491#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6546#L65 assume !(1 == ~p_dw_pc~0); 6543#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6414#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6334#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6335#L315 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 6380#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6529#L84 assume !(1 == ~c_dr_pc~0); 6527#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6525#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6523#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6521#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6519#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6517#L293 assume !(1 == ~q_read_ev~0); 6440#L293-2 assume !(1 == ~q_write_ev~0); 6437#L298-1 assume { :end_inline_reset_delta_events } true; 6438#L419-2 [2024-11-23 02:53:30,493 INFO L747 eck$LassoCheckResult]: Loop: 6438#L419-2 assume !false; 6434#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6431#L364 assume !false; 6426#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6427#L255 assume !(0 == ~p_dw_st~0); 6639#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6635#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6631#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6625#L344 assume !(0 != eval_~tmp___1~0#1); 6621#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6615#L222-3 assume !(1 == ~q_req_up~0); 6616#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6674#L275-3 assume !(0 == ~q_read_ev~0); 6672#L275-5 assume !(0 == ~q_write_ev~0); 6595#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6670#L65-3 assume !(1 == ~p_dw_pc~0); 6668#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6658#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6654#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6649#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 6643#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6638#L84-3 assume !(1 == ~c_dr_pc~0); 6634#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6630#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6624#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6620#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6614#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6608#L293-3 assume !(1 == ~q_read_ev~0); 6560#L293-5 assume !(1 == ~q_write_ev~0); 6558#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6556#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6542#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6514#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6513#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6465#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6442#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6439#L436 assume !(0 != start_simulation_~tmp~4#1); 6438#L419-2 [2024-11-23 02:53:30,494 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,494 INFO L85 PathProgramCache]: Analyzing trace with hash -1896010065, now seen corresponding path program 1 times [2024-11-23 02:53:30,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,494 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486634930] [2024-11-23 02:53:30,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:30,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:30,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:30,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:30,532 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486634930] [2024-11-23 02:53:30,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1486634930] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:30,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:30,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:53:30,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [296746955] [2024-11-23 02:53:30,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:30,533 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:53:30,533 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,533 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 1 times [2024-11-23 02:53:30,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765839037] [2024-11-23 02:53:30,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:30,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:30,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:30,616 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:30,616 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765839037] [2024-11-23 02:53:30,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765839037] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:30,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:30,617 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:53:30,617 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2018340064] [2024-11-23 02:53:30,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:30,617 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:53:30,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:53:30,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:53:30,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:53:30,618 INFO L87 Difference]: Start difference. First operand 905 states and 1173 transitions. cyclomatic complexity: 270 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:53:30,630 INFO L93 Difference]: Finished difference Result 827 states and 1075 transitions. [2024-11-23 02:53:30,630 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 827 states and 1075 transitions. [2024-11-23 02:53:30,635 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 722 [2024-11-23 02:53:30,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 827 states to 827 states and 1075 transitions. [2024-11-23 02:53:30,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 827 [2024-11-23 02:53:30,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 827 [2024-11-23 02:53:30,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 827 states and 1075 transitions. [2024-11-23 02:53:30,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:53:30,641 INFO L218 hiAutomatonCegarLoop]: Abstraction has 827 states and 1075 transitions. [2024-11-23 02:53:30,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 827 states and 1075 transitions. [2024-11-23 02:53:30,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 827 to 827. [2024-11-23 02:53:30,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 827 states, 827 states have (on average 1.2998790810157195) internal successors, (1075), 826 states have internal predecessors, (1075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 827 states to 827 states and 1075 transitions. [2024-11-23 02:53:30,654 INFO L240 hiAutomatonCegarLoop]: Abstraction has 827 states and 1075 transitions. [2024-11-23 02:53:30,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:53:30,657 INFO L425 stractBuchiCegarLoop]: Abstraction has 827 states and 1075 transitions. [2024-11-23 02:53:30,657 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-23 02:53:30,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 827 states and 1075 transitions. [2024-11-23 02:53:30,661 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 722 [2024-11-23 02:53:30,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:30,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:30,663 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,663 INFO L745 eck$LassoCheckResult]: Stem: 8078#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 8079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8107#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8052#L222 assume !(1 == ~q_req_up~0); 8054#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8089#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 8090#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8115#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8211#L275 assume !(0 == ~q_read_ev~0); 8210#L275-2 assume !(0 == ~q_write_ev~0); 8185#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8152#L65 assume !(1 == ~p_dw_pc~0); 8103#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 8104#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8208#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8207#L315 assume !(0 != activate_threads_~tmp~1#1); 8206#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8205#L84 assume !(1 == ~c_dr_pc~0); 8204#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 8063#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8064#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8022#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8023#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8134#L293 assume !(1 == ~q_read_ev~0); 8135#L293-2 assume !(1 == ~q_write_ev~0); 8121#L298-1 assume { :end_inline_reset_delta_events } true; 8122#L419-2 [2024-11-23 02:53:30,663 INFO L747 eck$LassoCheckResult]: Loop: 8122#L419-2 assume !false; 8253#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8249#L364 assume !false; 8247#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8248#L255 assume !(0 == ~p_dw_st~0); 8349#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 8345#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8341#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8335#L344 assume !(0 != eval_~tmp___1~0#1); 8331#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8325#L222-3 assume !(1 == ~q_req_up~0); 8326#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8428#L275-3 assume !(0 == ~q_read_ev~0); 8426#L275-5 assume !(0 == ~q_write_ev~0); 8305#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8421#L65-3 assume !(1 == ~p_dw_pc~0); 8419#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 8416#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8413#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8401#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 8353#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8348#L84-3 assume !(1 == ~c_dr_pc~0); 8344#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 8340#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8334#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8330#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 8324#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8318#L293-3 assume !(1 == ~q_read_ev~0); 8270#L293-5 assume !(1 == ~q_write_ev~0); 8269#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8263#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8264#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8411#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 8410#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8409#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8408#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8256#L436 assume !(0 != start_simulation_~tmp~4#1); 8122#L419-2 [2024-11-23 02:53:30,664 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,664 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2024-11-23 02:53:30,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037961040] [2024-11-23 02:53:30,665 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-23 02:53:30,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,674 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-23 02:53:30,675 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:53:30,675 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:53:30,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:30,686 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:53:30,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,687 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 2 times [2024-11-23 02:53:30,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [419876350] [2024-11-23 02:53:30,687 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:53:30,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,694 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:53:30,694 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-23 02:53:30,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:30,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:30,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [419876350] [2024-11-23 02:53:30,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [419876350] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:30,736 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:30,736 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:53:30,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778245566] [2024-11-23 02:53:30,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:30,737 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:53:30,737 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:53:30,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:53:30,737 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:53:30,737 INFO L87 Difference]: Start difference. First operand 827 states and 1075 transitions. cyclomatic complexity: 250 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:53:30,773 INFO L93 Difference]: Finished difference Result 754 states and 971 transitions. [2024-11-23 02:53:30,773 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 754 states and 971 transitions. [2024-11-23 02:53:30,778 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2024-11-23 02:53:30,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 754 states to 754 states and 971 transitions. [2024-11-23 02:53:30,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 754 [2024-11-23 02:53:30,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 754 [2024-11-23 02:53:30,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 754 states and 971 transitions. [2024-11-23 02:53:30,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:53:30,783 INFO L218 hiAutomatonCegarLoop]: Abstraction has 754 states and 971 transitions. [2024-11-23 02:53:30,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 754 states and 971 transitions. [2024-11-23 02:53:30,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 754 to 754. [2024-11-23 02:53:30,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 754 states, 754 states have (on average 1.2877984084880636) internal successors, (971), 753 states have internal predecessors, (971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 754 states to 754 states and 971 transitions. [2024-11-23 02:53:30,795 INFO L240 hiAutomatonCegarLoop]: Abstraction has 754 states and 971 transitions. [2024-11-23 02:53:30,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:53:30,796 INFO L425 stractBuchiCegarLoop]: Abstraction has 754 states and 971 transitions. [2024-11-23 02:53:30,796 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-23 02:53:30,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 754 states and 971 transitions. [2024-11-23 02:53:30,800 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2024-11-23 02:53:30,800 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:30,800 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:30,801 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,801 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,802 INFO L745 eck$LassoCheckResult]: Stem: 9670#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 9671#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 9696#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9640#L222 assume !(1 == ~q_req_up~0); 9642#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9781#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 9778#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 9760#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9761#L275 assume !(0 == ~q_read_ev~0); 9711#L275-2 assume !(0 == ~q_write_ev~0); 9712#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9755#L65 assume !(1 == ~p_dw_pc~0); 9753#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 9751#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9749#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9747#L315 assume !(0 != activate_threads_~tmp~1#1); 9745#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9743#L84 assume !(1 == ~c_dr_pc~0); 9741#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 9739#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9737#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9735#L323 assume !(0 != activate_threads_~tmp___0~1#1); 9733#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9731#L293 assume !(1 == ~q_read_ev~0); 9604#L293-2 assume !(1 == ~q_write_ev~0); 9605#L298-1 assume { :end_inline_reset_delta_events } true; 9709#L419-2 assume !false; 9808#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 9805#L364 [2024-11-23 02:53:30,802 INFO L747 eck$LassoCheckResult]: Loop: 9805#L364 assume !false; 9804#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9803#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9802#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9801#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 9800#L344 assume 0 != eval_~tmp___1~0#1; 9799#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 9797#L353 assume !(0 != eval_~tmp~2#1); 9798#L349 assume !(0 == ~c_dr_st~0); 9805#L364 [2024-11-23 02:53:30,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,802 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 1 times [2024-11-23 02:53:30,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820037342] [2024-11-23 02:53:30,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:30,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:30,827 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:53:30,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:30,833 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:53:30,834 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,834 INFO L85 PathProgramCache]: Analyzing trace with hash -479000197, now seen corresponding path program 1 times [2024-11-23 02:53:30,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,834 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293942789] [2024-11-23 02:53:30,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:30,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:30,838 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:53:30,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:30,840 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:53:30,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,841 INFO L85 PathProgramCache]: Analyzing trace with hash 519639659, now seen corresponding path program 1 times [2024-11-23 02:53:30,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872170724] [2024-11-23 02:53:30,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:30,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:53:30,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:53:30,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:53:30,871 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1872170724] [2024-11-23 02:53:30,871 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1872170724] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:53:30,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:53:30,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:53:30,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583981710] [2024-11-23 02:53:30,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:53:30,922 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:53:30,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:53:30,923 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:53:30,923 INFO L87 Difference]: Start difference. First operand 754 states and 971 transitions. cyclomatic complexity: 221 Second operand has 3 states, 2 states have (on average 18.5) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:53:30,949 INFO L93 Difference]: Finished difference Result 844 states and 1081 transitions. [2024-11-23 02:53:30,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 844 states and 1081 transitions. [2024-11-23 02:53:30,956 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 735 [2024-11-23 02:53:30,959 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 844 states to 844 states and 1081 transitions. [2024-11-23 02:53:30,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 844 [2024-11-23 02:53:30,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 844 [2024-11-23 02:53:30,960 INFO L73 IsDeterministic]: Start isDeterministic. Operand 844 states and 1081 transitions. [2024-11-23 02:53:30,961 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:53:30,961 INFO L218 hiAutomatonCegarLoop]: Abstraction has 844 states and 1081 transitions. [2024-11-23 02:53:30,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 844 states and 1081 transitions. [2024-11-23 02:53:30,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 844 to 824. [2024-11-23 02:53:30,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 824 states, 824 states have (on average 1.2851941747572815) internal successors, (1059), 823 states have internal predecessors, (1059), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:53:30,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 824 states to 824 states and 1059 transitions. [2024-11-23 02:53:30,972 INFO L240 hiAutomatonCegarLoop]: Abstraction has 824 states and 1059 transitions. [2024-11-23 02:53:30,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:53:30,974 INFO L425 stractBuchiCegarLoop]: Abstraction has 824 states and 1059 transitions. [2024-11-23 02:53:30,974 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-23 02:53:30,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 824 states and 1059 transitions. [2024-11-23 02:53:30,977 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 715 [2024-11-23 02:53:30,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:53:30,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:53:30,978 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,978 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:53:30,978 INFO L745 eck$LassoCheckResult]: Stem: 11269#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 11270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 11297#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11246#L222 assume !(1 == ~q_req_up~0); 11248#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11384#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 11382#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 11310#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11302#L275 assume !(0 == ~q_read_ev~0); 11303#L275-2 assume !(0 == ~q_write_ev~0); 11311#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 11332#L65 assume !(1 == ~p_dw_pc~0); 11293#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 11294#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 11394#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11391#L315 assume !(0 != activate_threads_~tmp~1#1); 11390#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 11316#L84 assume !(1 == ~c_dr_pc~0); 11261#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 11256#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 11257#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11216#L323 assume !(0 != activate_threads_~tmp___0~1#1); 11217#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11318#L293 assume !(1 == ~q_read_ev~0); 11319#L293-2 assume !(1 == ~q_write_ev~0); 11848#L298-1 assume { :end_inline_reset_delta_events } true; 11846#L419-2 assume !false; 11844#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 11838#L364 [2024-11-23 02:53:30,978 INFO L747 eck$LassoCheckResult]: Loop: 11838#L364 assume !false; 11832#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11829#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11826#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11823#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 11820#L344 assume 0 != eval_~tmp___1~0#1; 11816#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 11770#L353 assume !(0 != eval_~tmp~2#1); 11658#L349 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 11659#L368 assume !(0 != eval_~tmp___0~2#1); 11838#L364 [2024-11-23 02:53:30,979 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:30,979 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 2 times [2024-11-23 02:53:30,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:30,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [366378810] [2024-11-23 02:53:30,980 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:53:30,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:30,988 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:53:30,988 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:53:30,988 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:53:30,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:31,000 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:53:31,001 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:31,001 INFO L85 PathProgramCache]: Analyzing trace with hash -1964105996, now seen corresponding path program 1 times [2024-11-23 02:53:31,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:31,002 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2356288] [2024-11-23 02:53:31,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:31,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:31,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:31,005 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:53:31,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:31,009 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:53:31,010 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:53:31,010 INFO L85 PathProgramCache]: Analyzing trace with hash -1071041532, now seen corresponding path program 1 times [2024-11-23 02:53:31,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:53:31,010 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940963109] [2024-11-23 02:53:31,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:53:31,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:53:31,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:31,022 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:53:31,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:31,032 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:53:31,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:31,719 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:53:31,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:53:31,834 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 23.11 02:53:31 BoogieIcfgContainer [2024-11-23 02:53:31,834 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-23 02:53:31,835 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-23 02:53:31,835 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-23 02:53:31,835 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-23 02:53:31,835 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:53:28" (3/4) ... [2024-11-23 02:53:31,837 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-23 02:53:31,912 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-23 02:53:31,912 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-23 02:53:31,913 INFO L158 Benchmark]: Toolchain (without parser) took 4577.98ms. Allocated memory was 151.0MB in the beginning and 224.4MB in the end (delta: 73.4MB). Free memory was 78.6MB in the beginning and 166.4MB in the end (delta: -87.8MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-23 02:53:31,913 INFO L158 Benchmark]: CDTParser took 0.21ms. Allocated memory is still 151.0MB. Free memory is still 102.5MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-23 02:53:31,913 INFO L158 Benchmark]: CACSL2BoogieTranslator took 328.82ms. Allocated memory was 151.0MB in the beginning and 186.6MB in the end (delta: 35.7MB). Free memory was 78.5MB in the beginning and 152.9MB in the end (delta: -74.5MB). Peak memory consumption was 14.8MB. Max. memory is 16.1GB. [2024-11-23 02:53:31,914 INFO L158 Benchmark]: Boogie Procedure Inliner took 51.09ms. Allocated memory is still 186.6MB. Free memory was 152.9MB in the beginning and 150.8MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-23 02:53:31,914 INFO L158 Benchmark]: Boogie Preprocessor took 83.66ms. Allocated memory is still 186.6MB. Free memory was 150.8MB in the beginning and 148.7MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-23 02:53:31,914 INFO L158 Benchmark]: RCFGBuilder took 542.70ms. Allocated memory is still 186.6MB. Free memory was 148.7MB in the beginning and 126.7MB in the end (delta: 22.0MB). Peak memory consumption was 23.1MB. Max. memory is 16.1GB. [2024-11-23 02:53:31,915 INFO L158 Benchmark]: BuchiAutomizer took 3488.73ms. Allocated memory was 186.6MB in the beginning and 224.4MB in the end (delta: 37.7MB). Free memory was 126.7MB in the beginning and 170.6MB in the end (delta: -43.9MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-23 02:53:31,915 INFO L158 Benchmark]: Witness Printer took 77.70ms. Allocated memory is still 224.4MB. Free memory was 170.6MB in the beginning and 166.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-23 02:53:31,916 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21ms. Allocated memory is still 151.0MB. Free memory is still 102.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 328.82ms. Allocated memory was 151.0MB in the beginning and 186.6MB in the end (delta: 35.7MB). Free memory was 78.5MB in the beginning and 152.9MB in the end (delta: -74.5MB). Peak memory consumption was 14.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 51.09ms. Allocated memory is still 186.6MB. Free memory was 152.9MB in the beginning and 150.8MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 83.66ms. Allocated memory is still 186.6MB. Free memory was 150.8MB in the beginning and 148.7MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 542.70ms. Allocated memory is still 186.6MB. Free memory was 148.7MB in the beginning and 126.7MB in the end (delta: 22.0MB). Peak memory consumption was 23.1MB. Max. memory is 16.1GB. * BuchiAutomizer took 3488.73ms. Allocated memory was 186.6MB in the beginning and 224.4MB in the end (delta: 37.7MB). Free memory was 126.7MB in the beginning and 170.6MB in the end (delta: -43.9MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 77.70ms. Allocated memory is still 224.4MB. Free memory was 170.6MB in the beginning and 166.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 824 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.3s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 2.2s. Construction of modules took 0.2s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 10 MinimizatonAttempts, 420 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1378 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1378 mSDsluCounter, 2929 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1470 mSDsCounter, 67 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 237 IncrementalHoareTripleChecker+Invalid, 304 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 67 mSolverCounterUnsat, 1459 mSDtfsCounter, 237 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 339]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 339]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-23 02:53:31,939 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)