./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.08.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 803cd42f Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.08.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-assert-order-craig-803cd42-m [2024-11-23 02:53:57,949 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-23 02:53:58,024 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-23 02:53:58,033 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-23 02:53:58,034 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-23 02:53:58,065 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-23 02:53:58,065 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-23 02:53:58,066 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-23 02:53:58,066 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-23 02:53:58,067 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-23 02:53:58,068 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-23 02:53:58,068 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-23 02:53:58,069 INFO L153 SettingsManager]: * Use SBE=true [2024-11-23 02:53:58,070 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-23 02:53:58,071 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-23 02:53:58,071 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-23 02:53:58,071 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-23 02:53:58,072 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-23 02:53:58,072 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-23 02:53:58,072 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-23 02:53:58,072 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-23 02:53:58,073 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-23 02:53:58,073 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-23 02:53:58,074 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-23 02:53:58,085 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-23 02:53:58,085 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-23 02:53:58,085 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-23 02:53:58,085 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-23 02:53:58,086 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-23 02:53:58,086 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-23 02:53:58,086 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-23 02:53:58,086 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-23 02:53:58,087 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-23 02:53:58,087 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-23 02:53:58,087 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-23 02:53:58,087 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-23 02:53:58,088 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-23 02:53:58,088 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-23 02:53:58,089 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-23 02:53:58,089 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 [2024-11-23 02:53:58,380 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-23 02:53:58,401 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-23 02:53:58,406 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-23 02:53:58,408 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-23 02:53:58,408 INFO L274 PluginConnector]: CDTParser initialized [2024-11-23 02:53:58,409 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2024-11-23 02:53:59,924 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-23 02:54:00,144 INFO L384 CDTParser]: Found 1 translation units. [2024-11-23 02:54:00,145 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2024-11-23 02:54:00,162 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ee29d127f/02f2236bb4be4b05b4ca8288d12b41b8/FLAGb03e54244 [2024-11-23 02:54:00,511 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ee29d127f/02f2236bb4be4b05b4ca8288d12b41b8 [2024-11-23 02:54:00,514 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-23 02:54:00,515 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-23 02:54:00,517 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-23 02:54:00,517 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-23 02:54:00,523 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-23 02:54:00,524 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:54:00" (1/1) ... [2024-11-23 02:54:00,525 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@14ad2c50 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:00, skipping insertion in model container [2024-11-23 02:54:00,525 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:54:00" (1/1) ... [2024-11-23 02:54:00,569 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-23 02:54:00,880 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-23 02:54:00,905 INFO L200 MainTranslator]: Completed pre-run [2024-11-23 02:54:00,974 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-23 02:54:01,010 INFO L204 MainTranslator]: Completed translation [2024-11-23 02:54:01,011 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01 WrapperNode [2024-11-23 02:54:01,011 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-23 02:54:01,013 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-23 02:54:01,013 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-23 02:54:01,013 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-23 02:54:01,018 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,029 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,104 INFO L138 Inliner]: procedures = 44, calls = 57, calls flagged for inlining = 52, calls inlined = 160, statements flattened = 2391 [2024-11-23 02:54:01,104 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-23 02:54:01,105 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-23 02:54:01,105 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-23 02:54:01,105 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-23 02:54:01,117 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,117 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,134 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,193 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-23 02:54:01,193 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,193 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,237 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,260 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,265 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,272 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,282 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-23 02:54:01,284 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-23 02:54:01,284 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-23 02:54:01,284 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-23 02:54:01,285 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (1/1) ... [2024-11-23 02:54:01,290 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:54:01,315 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:54:01,340 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:54:01,343 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-23 02:54:01,395 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-23 02:54:01,396 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-23 02:54:01,396 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-23 02:54:01,396 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-23 02:54:01,520 INFO L238 CfgBuilder]: Building ICFG [2024-11-23 02:54:01,525 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-23 02:54:03,271 INFO L? ?]: Removed 478 outVars from TransFormulas that were not future-live. [2024-11-23 02:54:03,273 INFO L287 CfgBuilder]: Performing block encoding [2024-11-23 02:54:03,329 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-23 02:54:03,330 INFO L316 CfgBuilder]: Removed 11 assume(true) statements. [2024-11-23 02:54:03,330 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:54:03 BoogieIcfgContainer [2024-11-23 02:54:03,330 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-23 02:54:03,331 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-23 02:54:03,332 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-23 02:54:03,336 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-23 02:54:03,336 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:54:03,338 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 02:54:00" (1/3) ... [2024-11-23 02:54:03,339 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c1a96fc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:54:03, skipping insertion in model container [2024-11-23 02:54:03,340 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:54:03,340 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:54:01" (2/3) ... [2024-11-23 02:54:03,341 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c1a96fc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:54:03, skipping insertion in model container [2024-11-23 02:54:03,342 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:54:03,342 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:54:03" (3/3) ... [2024-11-23 02:54:03,343 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-2.c [2024-11-23 02:54:03,431 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-23 02:54:03,431 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-23 02:54:03,431 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-23 02:54:03,431 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-23 02:54:03,431 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-23 02:54:03,431 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-23 02:54:03,431 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-23 02:54:03,432 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-23 02:54:03,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1017 states, 1016 states have (on average 1.5098425196850394) internal successors, (1534), 1016 states have internal predecessors, (1534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:03,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 898 [2024-11-23 02:54:03,501 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:03,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:03,515 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:03,515 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:03,515 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-23 02:54:03,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1017 states, 1016 states have (on average 1.5098425196850394) internal successors, (1534), 1016 states have internal predecessors, (1534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:03,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 898 [2024-11-23 02:54:03,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:03,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:03,540 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:03,540 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:03,550 INFO L745 eck$LassoCheckResult]: Stem: 124#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 936#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 760#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 934#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 318#L609true assume !(1 == ~m_i~0);~m_st~0 := 2; 1016#L609-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 59#L614-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 104#L619-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 735#L624-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 978#L629-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 43#L634-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 289#L639-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 874#L644-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 310#L649-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 107#L866true assume !(0 == ~M_E~0); 982#L866-2true assume !(0 == ~T1_E~0); 457#L871-1true assume !(0 == ~T2_E~0); 857#L876-1true assume !(0 == ~T3_E~0); 850#L881-1true assume !(0 == ~T4_E~0); 472#L886-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 283#L891-1true assume !(0 == ~T6_E~0); 462#L896-1true assume !(0 == ~T7_E~0); 595#L901-1true assume !(0 == ~T8_E~0); 485#L906-1true assume !(0 == ~E_M~0); 871#L911-1true assume !(0 == ~E_1~0); 316#L916-1true assume !(0 == ~E_2~0); 597#L921-1true assume !(0 == ~E_3~0); 756#L926-1true assume 0 == ~E_4~0;~E_4~0 := 1; 878#L931-1true assume !(0 == ~E_5~0); 903#L936-1true assume !(0 == ~E_6~0); 992#L941-1true assume !(0 == ~E_7~0); 319#L946-1true assume !(0 == ~E_8~0); 796#L951-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 907#L430true assume !(1 == ~m_pc~0); 699#L430-2true is_master_triggered_~__retres1~0#1 := 0; 16#L441true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 651#is_master_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 405#L1073true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 833#L1073-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 575#L449true assume 1 == ~t1_pc~0; 600#L450true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 828#L460true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 912#L1081true assume !(0 != activate_threads_~tmp___0~0#1); 497#L1081-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 358#L468true assume !(1 == ~t2_pc~0); 228#L468-2true is_transmit2_triggered_~__retres1~2#1 := 0; 445#L479true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 220#L1089true assume !(0 != activate_threads_~tmp___1~0#1); 17#L1089-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 905#L487true assume 1 == ~t3_pc~0; 836#L488true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62#L498true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 654#L1097true assume !(0 != activate_threads_~tmp___2~0#1); 271#L1097-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 354#L506true assume !(1 == ~t4_pc~0); 867#L506-2true is_transmit4_triggered_~__retres1~4#1 := 0; 983#L517true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 837#L1105true assume !(0 != activate_threads_~tmp___3~0#1); 348#L1105-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 229#L525true assume 1 == ~t5_pc~0; 185#L526true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 721#L536true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 656#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 969#L1113true assume !(0 != activate_threads_~tmp___4~0#1); 141#L1113-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 346#L544true assume !(1 == ~t6_pc~0); 230#L544-2true is_transmit6_triggered_~__retres1~6#1 := 0; 512#L555true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 211#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26#L1121true assume !(0 != activate_threads_~tmp___5~0#1); 810#L1121-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 715#L563true assume 1 == ~t7_pc~0; 528#L564true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38#L574true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 950#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 284#L1129true assume !(0 != activate_threads_~tmp___6~0#1); 113#L1129-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 513#L582true assume 1 == ~t8_pc~0; 71#L583true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 840#L593true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 583#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 262#L1137true assume !(0 != activate_threads_~tmp___7~0#1); 187#L1137-2true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 579#L964true assume 1 == ~M_E~0;~M_E~0 := 2; 832#L964-2true assume !(1 == ~T1_E~0); 142#L969-1true assume !(1 == ~T2_E~0); 766#L974-1true assume !(1 == ~T3_E~0); 623#L979-1true assume !(1 == ~T4_E~0); 964#L984-1true assume !(1 == ~T5_E~0); 233#L989-1true assume !(1 == ~T6_E~0); 466#L994-1true assume !(1 == ~T7_E~0); 160#L999-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 584#L1004-1true assume !(1 == ~E_M~0); 27#L1009-1true assume !(1 == ~E_1~0); 154#L1014-1true assume !(1 == ~E_2~0); 565#L1019-1true assume !(1 == ~E_3~0); 809#L1024-1true assume !(1 == ~E_4~0); 122#L1029-1true assume !(1 == ~E_5~0); 169#L1034-1true assume !(1 == ~E_6~0); 994#L1039-1true assume 1 == ~E_7~0;~E_7~0 := 2; 781#L1044-1true assume !(1 == ~E_8~0); 295#L1049-1true assume { :end_inline_reset_delta_events } true; 103#L1315-2true [2024-11-23 02:54:03,552 INFO L747 eck$LassoCheckResult]: Loop: 103#L1315-2true assume !false; 885#L1316true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 608#L841-1true assume !true; 593#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 355#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19#L866-3true assume 0 == ~M_E~0;~M_E~0 := 1; 845#L866-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 173#L871-3true assume !(0 == ~T2_E~0); 274#L876-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 182#L881-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 688#L886-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 335#L891-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 469#L896-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 245#L901-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 337#L906-3true assume 0 == ~E_M~0;~E_M~0 := 1; 609#L911-3true assume !(0 == ~E_1~0); 520#L916-3true assume 0 == ~E_2~0;~E_2~0 := 1; 196#L921-3true assume 0 == ~E_3~0;~E_3~0 := 1; 504#L926-3true assume 0 == ~E_4~0;~E_4~0 := 1; 603#L931-3true assume 0 == ~E_5~0;~E_5~0 := 1; 251#L936-3true assume 0 == ~E_6~0;~E_6~0 := 1; 347#L941-3true assume 0 == ~E_7~0;~E_7~0 := 1; 606#L946-3true assume 0 == ~E_8~0;~E_8~0 := 1; 174#L951-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 879#L430-30true assume !(1 == ~m_pc~0); 648#L430-32true is_master_triggered_~__retres1~0#1 := 0; 259#L441-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 236#is_master_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 545#L1073-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 927#L1073-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 555#L449-30true assume 1 == ~t1_pc~0; 189#L450-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25#L460-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 387#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 232#L1081-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68#L1081-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 397#L468-30true assume 1 == ~t2_pc~0; 120#L469-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 617#L479-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 330#L1089-30true assume !(0 != activate_threads_~tmp___1~0#1); 795#L1089-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224#L487-30true assume !(1 == ~t3_pc~0); 106#L487-32true is_transmit3_triggered_~__retres1~3#1 := 0; 862#L498-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 375#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 821#L1097-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 573#L1097-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 280#L506-30true assume !(1 == ~t4_pc~0); 535#L506-32true is_transmit4_triggered_~__retres1~4#1 := 0; 297#L517-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 849#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 638#L1105-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 225#L1105-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 985#L525-30true assume 1 == ~t5_pc~0; 709#L526-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 930#L536-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 477#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 694#L1113-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 227#L1113-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94#L544-30true assume 1 == ~t6_pc~0; 4#L545-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 881#L555-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 723#L1121-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1004#L1121-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 685#L563-30true assume !(1 == ~t7_pc~0); 162#L563-32true is_transmit7_triggered_~__retres1~7#1 := 0; 88#L574-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 540#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 290#L1129-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 920#L1129-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 666#L582-30true assume !(1 == ~t8_pc~0); 135#L582-32true is_transmit8_triggered_~__retres1~8#1 := 0; 281#L593-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 989#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1002#L1137-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 914#L1137-32true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32#L964-3true assume 1 == ~M_E~0;~M_E~0 := 2; 101#L964-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 208#L969-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 96#L974-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 932#L979-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 363#L984-3true assume !(1 == ~T5_E~0); 996#L989-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 125#L994-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 843#L999-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 494#L1004-3true assume 1 == ~E_M~0;~E_M~0 := 2; 51#L1009-3true assume 1 == ~E_1~0;~E_1~0 := 2; 558#L1014-3true assume 1 == ~E_2~0;~E_2~0 := 2; 343#L1019-3true assume 1 == ~E_3~0;~E_3~0 := 2; 980#L1024-3true assume !(1 == ~E_4~0); 331#L1029-3true assume 1 == ~E_5~0;~E_5~0 := 2; 313#L1034-3true assume 1 == ~E_6~0;~E_6~0 := 2; 564#L1039-3true assume 1 == ~E_7~0;~E_7~0 := 2; 598#L1044-3true assume 1 == ~E_8~0;~E_8~0 := 2; 119#L1049-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 470#L662-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 706#L709-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 190#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 138#L1334true assume !(0 == start_simulation_~tmp~3#1); 827#L1334-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 144#L662-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2#L709-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 28#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 928#L1289true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 758#L1296true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 371#stop_simulation_returnLabel#1true start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 734#L1347true assume !(0 != start_simulation_~tmp___0~1#1); 103#L1315-2true [2024-11-23 02:54:03,567 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:03,567 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2024-11-23 02:54:03,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:03,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957361826] [2024-11-23 02:54:03,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:03,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:03,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:03,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:03,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:03,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957361826] [2024-11-23 02:54:03,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [957361826] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:03,928 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:03,929 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:03,931 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965941881] [2024-11-23 02:54:03,932 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:03,937 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:03,939 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:03,939 INFO L85 PathProgramCache]: Analyzing trace with hash -1219078109, now seen corresponding path program 1 times [2024-11-23 02:54:03,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:03,940 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417404257] [2024-11-23 02:54:03,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:03,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:03,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:04,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:04,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:04,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417404257] [2024-11-23 02:54:04,020 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417404257] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:04,020 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:04,020 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:54:04,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790145161] [2024-11-23 02:54:04,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:04,022 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:04,022 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:04,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:04,058 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:04,062 INFO L87 Difference]: Start difference. First operand has 1017 states, 1016 states have (on average 1.5098425196850394) internal successors, (1534), 1016 states have internal predecessors, (1534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:04,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:04,147 INFO L93 Difference]: Finished difference Result 1013 states and 1505 transitions. [2024-11-23 02:54:04,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1013 states and 1505 transitions. [2024-11-23 02:54:04,159 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:04,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1013 states to 1007 states and 1499 transitions. [2024-11-23 02:54:04,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2024-11-23 02:54:04,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2024-11-23 02:54:04,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1499 transitions. [2024-11-23 02:54:04,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:04,185 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1499 transitions. [2024-11-23 02:54:04,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1499 transitions. [2024-11-23 02:54:04,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2024-11-23 02:54:04,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4885799404170805) internal successors, (1499), 1006 states have internal predecessors, (1499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:04,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1499 transitions. [2024-11-23 02:54:04,269 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1499 transitions. [2024-11-23 02:54:04,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:04,277 INFO L425 stractBuchiCegarLoop]: Abstraction has 1007 states and 1499 transitions. [2024-11-23 02:54:04,278 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-23 02:54:04,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1499 transitions. [2024-11-23 02:54:04,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:04,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:04,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:04,288 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:04,291 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:04,292 INFO L745 eck$LassoCheckResult]: Stem: 2287#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2288#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3001#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3002#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2601#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 2602#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2159#L614-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2160#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2251#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2987#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2127#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2128#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2556#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2588#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2255#L866 assume !(0 == ~M_E~0); 2256#L866-2 assume !(0 == ~T1_E~0); 2786#L871-1 assume !(0 == ~T2_E~0); 2787#L876-1 assume !(0 == ~T3_E~0); 3027#L881-1 assume !(0 == ~T4_E~0); 2800#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2545#L891-1 assume !(0 == ~T6_E~0); 2546#L896-1 assume !(0 == ~T7_E~0); 2794#L901-1 assume !(0 == ~T8_E~0); 2815#L906-1 assume !(0 == ~E_M~0); 2816#L911-1 assume !(0 == ~E_1~0); 2598#L916-1 assume !(0 == ~E_2~0); 2599#L921-1 assume !(0 == ~E_3~0); 2908#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2998#L931-1 assume !(0 == ~E_5~0); 3030#L936-1 assume !(0 == ~E_6~0); 3034#L941-1 assume !(0 == ~E_7~0); 2603#L946-1 assume !(0 == ~E_8~0); 2604#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3015#L430 assume !(1 == ~m_pc~0); 2445#L430-2 is_master_triggered_~__retres1~0#1 := 0; 2074#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2075#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2720#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2721#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2889#L449 assume 1 == ~t1_pc~0; 2890#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2262#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2101#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2102#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 2830#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2660#L468 assume !(1 == ~t2_pc~0); 2062#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2061#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2455#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2450#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 2076#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2077#L487 assume 1 == ~t3_pc~0; 3025#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2165#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2058#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2059#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 2523#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2524#L506 assume !(1 == ~t4_pc~0); 2655#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2705#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2151#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2152#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 2649#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2462#L525 assume 1 == ~t5_pc~0; 2396#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2115#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2946#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2947#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 2319#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2320#L544 assume !(1 == ~t6_pc~0); 2463#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2464#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2435#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2096#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 2097#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2979#L563 assume 1 == ~t7_pc~0; 2853#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2119#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2120#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2547#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 2263#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2264#L582 assume 1 == ~t8_pc~0; 2183#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2184#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2895#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2511#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 2400#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2401#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 2893#L964-2 assume !(1 == ~T1_E~0); 2321#L969-1 assume !(1 == ~T2_E~0); 2322#L974-1 assume !(1 == ~T3_E~0); 2926#L979-1 assume !(1 == ~T4_E~0); 2927#L984-1 assume !(1 == ~T5_E~0); 2469#L989-1 assume !(1 == ~T6_E~0); 2470#L994-1 assume !(1 == ~T7_E~0); 2352#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2353#L1004-1 assume !(1 == ~E_M~0); 2098#L1009-1 assume !(1 == ~E_1~0); 2099#L1014-1 assume !(1 == ~E_2~0); 2341#L1019-1 assume !(1 == ~E_3~0); 2881#L1024-1 assume !(1 == ~E_4~0); 2284#L1029-1 assume !(1 == ~E_5~0); 2285#L1034-1 assume !(1 == ~E_6~0); 2368#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3011#L1044-1 assume !(1 == ~E_8~0); 2567#L1049-1 assume { :end_inline_reset_delta_events } true; 2249#L1315-2 [2024-11-23 02:54:04,295 INFO L747 eck$LassoCheckResult]: Loop: 2249#L1315-2 assume !false; 2250#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2663#L841-1 assume !false; 2917#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2314#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2315#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2496#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2071#L724 assume !(0 != eval_~tmp~0#1); 2073#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2657#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2080#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2081#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2373#L871-3 assume !(0 == ~T2_E~0); 2374#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2390#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2391#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2631#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2632#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2489#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2490#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2633#L911-3 assume !(0 == ~E_1~0); 2847#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2417#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2418#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2836#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2497#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2498#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2648#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2375#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2376#L430-30 assume 1 == ~m_pc~0; 2402#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2403#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2474#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2475#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2864#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2870#L449-30 assume 1 == ~t1_pc~0; 2405#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2094#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2095#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2468#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2179#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2180#L468-30 assume 1 == ~t2_pc~0; 2279#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2280#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2371#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2372#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 2623#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2456#L487-30 assume 1 == ~t3_pc~0; 2434#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2254#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2685#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2686#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2888#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2540#L506-30 assume !(1 == ~t4_pc~0); 2541#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2570#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2571#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2934#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2457#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2458#L525-30 assume !(1 == ~t5_pc~0); 2977#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2976#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2804#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2805#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2461#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2231#L544-30 assume 1 == ~t6_pc~0; 2043#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2044#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2157#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2158#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2982#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2965#L563-30 assume 1 == ~t7_pc~0; 2198#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2199#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2220#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2557#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2558#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2955#L582-30 assume 1 == ~t8_pc~0; 2915#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2308#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2543#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3045#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3035#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2106#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2107#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2245#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2234#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2235#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2669#L984-3 assume !(1 == ~T5_E~0); 2670#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2289#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2290#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2828#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2142#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2143#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2645#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2646#L1024-3 assume !(1 == ~E_4~0); 2624#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2593#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2594#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2880#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2277#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2278#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2398#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2407#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2311#L1334 assume !(0 == start_simulation_~tmp~3#1); 2312#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2325#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2039#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2040#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2100#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3000#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2679#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2680#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 2249#L1315-2 [2024-11-23 02:54:04,296 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:04,297 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2024-11-23 02:54:04,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:04,297 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165683144] [2024-11-23 02:54:04,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:04,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:04,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:04,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:04,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:04,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165683144] [2024-11-23 02:54:04,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1165683144] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:04,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:04,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:04,425 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1870323467] [2024-11-23 02:54:04,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:04,425 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:04,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:04,426 INFO L85 PathProgramCache]: Analyzing trace with hash 13135423, now seen corresponding path program 1 times [2024-11-23 02:54:04,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:04,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299540981] [2024-11-23 02:54:04,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:04,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:04,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:04,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:04,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:04,564 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1299540981] [2024-11-23 02:54:04,565 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1299540981] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:04,565 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:04,565 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:04,565 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [267821486] [2024-11-23 02:54:04,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:04,566 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:04,568 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:04,569 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:04,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:04,570 INFO L87 Difference]: Start difference. First operand 1007 states and 1499 transitions. cyclomatic complexity: 493 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:04,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:04,593 INFO L93 Difference]: Finished difference Result 1007 states and 1498 transitions. [2024-11-23 02:54:04,594 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1498 transitions. [2024-11-23 02:54:04,602 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:04,609 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1498 transitions. [2024-11-23 02:54:04,609 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2024-11-23 02:54:04,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2024-11-23 02:54:04,611 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1498 transitions. [2024-11-23 02:54:04,615 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:04,615 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1498 transitions. [2024-11-23 02:54:04,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1498 transitions. [2024-11-23 02:54:04,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2024-11-23 02:54:04,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4875868917576962) internal successors, (1498), 1006 states have internal predecessors, (1498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:04,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1498 transitions. [2024-11-23 02:54:04,636 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1498 transitions. [2024-11-23 02:54:04,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:04,637 INFO L425 stractBuchiCegarLoop]: Abstraction has 1007 states and 1498 transitions. [2024-11-23 02:54:04,640 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-23 02:54:04,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1498 transitions. [2024-11-23 02:54:04,646 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:04,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:04,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:04,650 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:04,650 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:04,651 INFO L745 eck$LassoCheckResult]: Stem: 4308#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4309#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5023#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4622#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 4623#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4180#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4181#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4272#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5008#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4148#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4149#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4577#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4609#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4276#L866 assume !(0 == ~M_E~0); 4277#L866-2 assume !(0 == ~T1_E~0); 4807#L871-1 assume !(0 == ~T2_E~0); 4808#L876-1 assume !(0 == ~T3_E~0); 5048#L881-1 assume !(0 == ~T4_E~0); 4821#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4566#L891-1 assume !(0 == ~T6_E~0); 4567#L896-1 assume !(0 == ~T7_E~0); 4815#L901-1 assume !(0 == ~T8_E~0); 4836#L906-1 assume !(0 == ~E_M~0); 4837#L911-1 assume !(0 == ~E_1~0); 4619#L916-1 assume !(0 == ~E_2~0); 4620#L921-1 assume !(0 == ~E_3~0); 4929#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 5019#L931-1 assume !(0 == ~E_5~0); 5051#L936-1 assume !(0 == ~E_6~0); 5055#L941-1 assume !(0 == ~E_7~0); 4624#L946-1 assume !(0 == ~E_8~0); 4625#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5036#L430 assume !(1 == ~m_pc~0); 4466#L430-2 is_master_triggered_~__retres1~0#1 := 0; 4095#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4096#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4741#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4742#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4910#L449 assume 1 == ~t1_pc~0; 4911#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4283#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4122#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4123#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 4851#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4681#L468 assume !(1 == ~t2_pc~0); 4083#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4082#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4476#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4471#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 4097#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4098#L487 assume 1 == ~t3_pc~0; 5046#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4186#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4079#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4080#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 4544#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4545#L506 assume !(1 == ~t4_pc~0); 4676#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4726#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4172#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4173#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 4670#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4483#L525 assume 1 == ~t5_pc~0; 4417#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4136#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4967#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4968#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 4340#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4341#L544 assume !(1 == ~t6_pc~0); 4484#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4485#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4456#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4117#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 4118#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5000#L563 assume 1 == ~t7_pc~0; 4874#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4140#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4141#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4568#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 4284#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4285#L582 assume 1 == ~t8_pc~0; 4204#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4205#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4916#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4532#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 4421#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4422#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 4914#L964-2 assume !(1 == ~T1_E~0); 4342#L969-1 assume !(1 == ~T2_E~0); 4343#L974-1 assume !(1 == ~T3_E~0); 4947#L979-1 assume !(1 == ~T4_E~0); 4948#L984-1 assume !(1 == ~T5_E~0); 4490#L989-1 assume !(1 == ~T6_E~0); 4491#L994-1 assume !(1 == ~T7_E~0); 4373#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4374#L1004-1 assume !(1 == ~E_M~0); 4119#L1009-1 assume !(1 == ~E_1~0); 4120#L1014-1 assume !(1 == ~E_2~0); 4362#L1019-1 assume !(1 == ~E_3~0); 4902#L1024-1 assume !(1 == ~E_4~0); 4305#L1029-1 assume !(1 == ~E_5~0); 4306#L1034-1 assume !(1 == ~E_6~0); 4389#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5032#L1044-1 assume !(1 == ~E_8~0); 4588#L1049-1 assume { :end_inline_reset_delta_events } true; 4270#L1315-2 [2024-11-23 02:54:04,651 INFO L747 eck$LassoCheckResult]: Loop: 4270#L1315-2 assume !false; 4271#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4684#L841-1 assume !false; 4938#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4335#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4336#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4517#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4092#L724 assume !(0 != eval_~tmp~0#1); 4094#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4678#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4101#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4102#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4394#L871-3 assume !(0 == ~T2_E~0); 4395#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4411#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4412#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4652#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4653#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4510#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4511#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4654#L911-3 assume !(0 == ~E_1~0); 4868#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4438#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4439#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4857#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4518#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4519#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4669#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4396#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4397#L430-30 assume 1 == ~m_pc~0; 4423#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4424#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4495#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4496#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4885#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4891#L449-30 assume 1 == ~t1_pc~0; 4426#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4115#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4116#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4489#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4200#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4201#L468-30 assume 1 == ~t2_pc~0; 4300#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4301#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4392#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4393#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 4644#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4477#L487-30 assume !(1 == ~t3_pc~0); 4274#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 4275#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4706#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4707#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4909#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4561#L506-30 assume !(1 == ~t4_pc~0); 4562#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4591#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4592#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4955#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4478#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4479#L525-30 assume 1 == ~t5_pc~0; 4996#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4997#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4825#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4826#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4482#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4252#L544-30 assume 1 == ~t6_pc~0; 4064#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4065#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4178#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4179#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5003#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4986#L563-30 assume 1 == ~t7_pc~0; 4219#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4220#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4241#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4578#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4579#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4976#L582-30 assume 1 == ~t8_pc~0; 4936#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4329#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4564#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5066#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5056#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4127#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4128#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4266#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4255#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4256#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4690#L984-3 assume !(1 == ~T5_E~0); 4691#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4310#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4311#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4849#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4163#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4164#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4666#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4667#L1024-3 assume !(1 == ~E_4~0); 4645#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4614#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4615#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4901#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4298#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4299#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4419#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4428#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4332#L1334 assume !(0 == start_simulation_~tmp~3#1); 4333#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4346#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4060#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4061#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 4121#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5021#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4700#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4701#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 4270#L1315-2 [2024-11-23 02:54:04,654 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:04,654 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2024-11-23 02:54:04,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:04,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077868190] [2024-11-23 02:54:04,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:04,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:04,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:04,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:04,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:04,720 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077868190] [2024-11-23 02:54:04,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077868190] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:04,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:04,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:04,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [412266292] [2024-11-23 02:54:04,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:04,722 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:04,722 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:04,722 INFO L85 PathProgramCache]: Analyzing trace with hash -1036208961, now seen corresponding path program 1 times [2024-11-23 02:54:04,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:04,723 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040150924] [2024-11-23 02:54:04,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:04,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:04,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:04,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:04,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:04,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040150924] [2024-11-23 02:54:04,791 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040150924] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:04,791 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:04,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:04,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1545697738] [2024-11-23 02:54:04,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:04,792 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:04,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:04,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:04,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:04,797 INFO L87 Difference]: Start difference. First operand 1007 states and 1498 transitions. cyclomatic complexity: 492 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:04,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:04,817 INFO L93 Difference]: Finished difference Result 1007 states and 1497 transitions. [2024-11-23 02:54:04,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1497 transitions. [2024-11-23 02:54:04,823 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:04,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1497 transitions. [2024-11-23 02:54:04,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2024-11-23 02:54:04,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2024-11-23 02:54:04,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1497 transitions. [2024-11-23 02:54:04,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:04,831 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1497 transitions. [2024-11-23 02:54:04,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1497 transitions. [2024-11-23 02:54:04,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2024-11-23 02:54:04,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4865938430983119) internal successors, (1497), 1006 states have internal predecessors, (1497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:04,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1497 transitions. [2024-11-23 02:54:04,870 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1497 transitions. [2024-11-23 02:54:04,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:04,871 INFO L425 stractBuchiCegarLoop]: Abstraction has 1007 states and 1497 transitions. [2024-11-23 02:54:04,872 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-23 02:54:04,872 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1497 transitions. [2024-11-23 02:54:04,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:04,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:04,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:04,883 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:04,886 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:04,886 INFO L745 eck$LassoCheckResult]: Stem: 6329#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 7043#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7044#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6643#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 6644#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6201#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6202#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6293#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7029#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6169#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6170#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6598#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6630#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6297#L866 assume !(0 == ~M_E~0); 6298#L866-2 assume !(0 == ~T1_E~0); 6828#L871-1 assume !(0 == ~T2_E~0); 6829#L876-1 assume !(0 == ~T3_E~0); 7069#L881-1 assume !(0 == ~T4_E~0); 6842#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6587#L891-1 assume !(0 == ~T6_E~0); 6588#L896-1 assume !(0 == ~T7_E~0); 6836#L901-1 assume !(0 == ~T8_E~0); 6857#L906-1 assume !(0 == ~E_M~0); 6858#L911-1 assume !(0 == ~E_1~0); 6640#L916-1 assume !(0 == ~E_2~0); 6641#L921-1 assume !(0 == ~E_3~0); 6950#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7040#L931-1 assume !(0 == ~E_5~0); 7072#L936-1 assume !(0 == ~E_6~0); 7076#L941-1 assume !(0 == ~E_7~0); 6645#L946-1 assume !(0 == ~E_8~0); 6646#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7057#L430 assume !(1 == ~m_pc~0); 6487#L430-2 is_master_triggered_~__retres1~0#1 := 0; 6116#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6117#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6762#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6763#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6931#L449 assume 1 == ~t1_pc~0; 6932#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6304#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6144#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 6872#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6702#L468 assume !(1 == ~t2_pc~0); 6104#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6103#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6497#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6492#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 6118#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6119#L487 assume 1 == ~t3_pc~0; 7067#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6207#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6100#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6101#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 6565#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6566#L506 assume !(1 == ~t4_pc~0); 6697#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6747#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6193#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6194#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 6691#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6504#L525 assume 1 == ~t5_pc~0; 6438#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6157#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6988#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6989#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 6361#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6362#L544 assume !(1 == ~t6_pc~0); 6505#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6506#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6477#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6138#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 6139#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7021#L563 assume 1 == ~t7_pc~0; 6895#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6161#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6162#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6589#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 6305#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6306#L582 assume 1 == ~t8_pc~0; 6225#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6226#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6937#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6553#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 6442#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6443#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 6935#L964-2 assume !(1 == ~T1_E~0); 6363#L969-1 assume !(1 == ~T2_E~0); 6364#L974-1 assume !(1 == ~T3_E~0); 6968#L979-1 assume !(1 == ~T4_E~0); 6969#L984-1 assume !(1 == ~T5_E~0); 6511#L989-1 assume !(1 == ~T6_E~0); 6512#L994-1 assume !(1 == ~T7_E~0); 6394#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6395#L1004-1 assume !(1 == ~E_M~0); 6140#L1009-1 assume !(1 == ~E_1~0); 6141#L1014-1 assume !(1 == ~E_2~0); 6383#L1019-1 assume !(1 == ~E_3~0); 6923#L1024-1 assume !(1 == ~E_4~0); 6326#L1029-1 assume !(1 == ~E_5~0); 6327#L1034-1 assume !(1 == ~E_6~0); 6410#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7053#L1044-1 assume !(1 == ~E_8~0); 6609#L1049-1 assume { :end_inline_reset_delta_events } true; 6291#L1315-2 [2024-11-23 02:54:04,887 INFO L747 eck$LassoCheckResult]: Loop: 6291#L1315-2 assume !false; 6292#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6705#L841-1 assume !false; 6959#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6356#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6357#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6538#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6113#L724 assume !(0 != eval_~tmp~0#1); 6115#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6699#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6122#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6123#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6415#L871-3 assume !(0 == ~T2_E~0); 6416#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6432#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6433#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6673#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6674#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6531#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6532#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6675#L911-3 assume !(0 == ~E_1~0); 6889#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6459#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6460#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6878#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6539#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6540#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6690#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6417#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6418#L430-30 assume 1 == ~m_pc~0; 6444#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6445#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6516#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6517#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6906#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6912#L449-30 assume !(1 == ~t1_pc~0); 6448#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 6136#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6137#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6510#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6221#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6222#L468-30 assume 1 == ~t2_pc~0; 6321#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6322#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6413#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6414#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 6665#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6498#L487-30 assume !(1 == ~t3_pc~0); 6295#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 6296#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6727#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6728#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6930#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6582#L506-30 assume !(1 == ~t4_pc~0); 6583#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 6612#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6613#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6976#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6499#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6500#L525-30 assume 1 == ~t5_pc~0; 7017#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7018#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6846#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6847#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6503#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6273#L544-30 assume 1 == ~t6_pc~0; 6085#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6086#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6199#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6200#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7024#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7007#L563-30 assume 1 == ~t7_pc~0; 6240#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6241#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6262#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6599#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6600#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6997#L582-30 assume 1 == ~t8_pc~0; 6957#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6350#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6585#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7087#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7077#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6148#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6149#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6287#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6276#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6277#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6711#L984-3 assume !(1 == ~T5_E~0); 6712#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6331#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6332#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6870#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6184#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6185#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6687#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6688#L1024-3 assume !(1 == ~E_4~0); 6666#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6635#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6636#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6922#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6319#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6320#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6440#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6449#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6353#L1334 assume !(0 == start_simulation_~tmp~3#1); 6354#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6367#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6081#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6082#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 6142#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7042#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6721#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6722#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 6291#L1315-2 [2024-11-23 02:54:04,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:04,888 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2024-11-23 02:54:04,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:04,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042371542] [2024-11-23 02:54:04,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:04,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:04,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:04,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:04,956 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:04,956 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2042371542] [2024-11-23 02:54:04,957 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2042371542] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:04,957 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:04,957 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:04,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [434200138] [2024-11-23 02:54:04,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:04,957 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:04,958 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:04,958 INFO L85 PathProgramCache]: Analyzing trace with hash -1973236160, now seen corresponding path program 1 times [2024-11-23 02:54:04,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:04,958 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079937729] [2024-11-23 02:54:04,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:04,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:04,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:05,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:05,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:05,026 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079937729] [2024-11-23 02:54:05,026 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079937729] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:05,026 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:05,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:05,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266941941] [2024-11-23 02:54:05,026 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:05,027 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:05,028 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:05,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:05,028 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:05,028 INFO L87 Difference]: Start difference. First operand 1007 states and 1497 transitions. cyclomatic complexity: 491 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:05,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:05,047 INFO L93 Difference]: Finished difference Result 1007 states and 1496 transitions. [2024-11-23 02:54:05,047 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1496 transitions. [2024-11-23 02:54:05,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:05,057 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1496 transitions. [2024-11-23 02:54:05,057 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2024-11-23 02:54:05,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2024-11-23 02:54:05,058 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1496 transitions. [2024-11-23 02:54:05,059 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:05,059 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1496 transitions. [2024-11-23 02:54:05,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1496 transitions. [2024-11-23 02:54:05,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2024-11-23 02:54:05,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4856007944389276) internal successors, (1496), 1006 states have internal predecessors, (1496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:05,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1496 transitions. [2024-11-23 02:54:05,080 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1496 transitions. [2024-11-23 02:54:05,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:05,081 INFO L425 stractBuchiCegarLoop]: Abstraction has 1007 states and 1496 transitions. [2024-11-23 02:54:05,081 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-23 02:54:05,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1496 transitions. [2024-11-23 02:54:05,087 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:05,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:05,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:05,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:05,091 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:05,092 INFO L745 eck$LassoCheckResult]: Stem: 8350#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8351#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9064#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9065#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8664#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 8665#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8222#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8223#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8314#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9050#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8190#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8191#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8619#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8651#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8318#L866 assume !(0 == ~M_E~0); 8319#L866-2 assume !(0 == ~T1_E~0); 8849#L871-1 assume !(0 == ~T2_E~0); 8850#L876-1 assume !(0 == ~T3_E~0); 9090#L881-1 assume !(0 == ~T4_E~0); 8863#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8608#L891-1 assume !(0 == ~T6_E~0); 8609#L896-1 assume !(0 == ~T7_E~0); 8857#L901-1 assume !(0 == ~T8_E~0); 8878#L906-1 assume !(0 == ~E_M~0); 8879#L911-1 assume !(0 == ~E_1~0); 8661#L916-1 assume !(0 == ~E_2~0); 8662#L921-1 assume !(0 == ~E_3~0); 8971#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 9061#L931-1 assume !(0 == ~E_5~0); 9093#L936-1 assume !(0 == ~E_6~0); 9097#L941-1 assume !(0 == ~E_7~0); 8666#L946-1 assume !(0 == ~E_8~0); 8667#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9078#L430 assume !(1 == ~m_pc~0); 8508#L430-2 is_master_triggered_~__retres1~0#1 := 0; 8137#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8138#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8783#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8784#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8952#L449 assume 1 == ~t1_pc~0; 8953#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8325#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8164#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8165#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 8893#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8723#L468 assume !(1 == ~t2_pc~0); 8125#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8124#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8513#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 8139#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8140#L487 assume 1 == ~t3_pc~0; 9088#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8228#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8121#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8122#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 8586#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8587#L506 assume !(1 == ~t4_pc~0); 8718#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8768#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8214#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8215#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 8712#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8525#L525 assume 1 == ~t5_pc~0; 8459#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8178#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9009#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9010#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 8382#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8383#L544 assume !(1 == ~t6_pc~0); 8526#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8527#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8498#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8159#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 8160#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9042#L563 assume 1 == ~t7_pc~0; 8916#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8182#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8183#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8610#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 8326#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8327#L582 assume 1 == ~t8_pc~0; 8246#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8247#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8958#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8574#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 8463#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8464#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 8956#L964-2 assume !(1 == ~T1_E~0); 8384#L969-1 assume !(1 == ~T2_E~0); 8385#L974-1 assume !(1 == ~T3_E~0); 8989#L979-1 assume !(1 == ~T4_E~0); 8990#L984-1 assume !(1 == ~T5_E~0); 8532#L989-1 assume !(1 == ~T6_E~0); 8533#L994-1 assume !(1 == ~T7_E~0); 8415#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8416#L1004-1 assume !(1 == ~E_M~0); 8161#L1009-1 assume !(1 == ~E_1~0); 8162#L1014-1 assume !(1 == ~E_2~0); 8404#L1019-1 assume !(1 == ~E_3~0); 8944#L1024-1 assume !(1 == ~E_4~0); 8347#L1029-1 assume !(1 == ~E_5~0); 8348#L1034-1 assume !(1 == ~E_6~0); 8431#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9074#L1044-1 assume !(1 == ~E_8~0); 8630#L1049-1 assume { :end_inline_reset_delta_events } true; 8312#L1315-2 [2024-11-23 02:54:05,092 INFO L747 eck$LassoCheckResult]: Loop: 8312#L1315-2 assume !false; 8313#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8726#L841-1 assume !false; 8980#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8377#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8378#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8559#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8134#L724 assume !(0 != eval_~tmp~0#1); 8136#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8720#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8143#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8144#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8436#L871-3 assume !(0 == ~T2_E~0); 8437#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8453#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8454#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8694#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8695#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8552#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8553#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8696#L911-3 assume !(0 == ~E_1~0); 8910#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8480#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8481#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8899#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8560#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8561#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8711#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8438#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8439#L430-30 assume 1 == ~m_pc~0; 8465#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8466#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8537#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8538#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8927#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8933#L449-30 assume 1 == ~t1_pc~0; 8468#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8157#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8158#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8531#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8242#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8243#L468-30 assume 1 == ~t2_pc~0; 8342#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8343#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8434#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8435#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 8686#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8519#L487-30 assume 1 == ~t3_pc~0; 8497#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8317#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8748#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8749#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8951#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8603#L506-30 assume !(1 == ~t4_pc~0); 8604#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 8633#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8634#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8997#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8520#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8521#L525-30 assume !(1 == ~t5_pc~0); 9040#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 9039#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8867#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8868#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8524#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8294#L544-30 assume 1 == ~t6_pc~0; 8106#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8107#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8220#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8221#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9045#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9028#L563-30 assume 1 == ~t7_pc~0; 8261#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8262#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8283#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8620#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8621#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9018#L582-30 assume 1 == ~t8_pc~0; 8978#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8371#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8606#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9108#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9098#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8169#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8170#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8308#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8297#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8298#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8732#L984-3 assume !(1 == ~T5_E~0); 8733#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8352#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8353#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8891#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8205#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8206#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8708#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8709#L1024-3 assume !(1 == ~E_4~0); 8687#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8656#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8657#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8943#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8340#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8341#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8461#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8470#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8374#L1334 assume !(0 == start_simulation_~tmp~3#1); 8375#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8388#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8102#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8103#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 8163#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9063#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8742#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 8743#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 8312#L1315-2 [2024-11-23 02:54:05,093 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:05,093 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2024-11-23 02:54:05,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:05,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078561411] [2024-11-23 02:54:05,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:05,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:05,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:05,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:05,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:05,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078561411] [2024-11-23 02:54:05,142 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1078561411] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:05,143 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:05,143 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:05,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1825417487] [2024-11-23 02:54:05,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:05,143 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:05,143 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:05,144 INFO L85 PathProgramCache]: Analyzing trace with hash 13135423, now seen corresponding path program 2 times [2024-11-23 02:54:05,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:05,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245146345] [2024-11-23 02:54:05,144 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:54:05,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:05,163 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:54:05,164 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-23 02:54:05,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:05,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:05,203 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245146345] [2024-11-23 02:54:05,203 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1245146345] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:05,203 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:05,203 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:05,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1195869729] [2024-11-23 02:54:05,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:05,204 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:05,205 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:05,205 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:05,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:05,206 INFO L87 Difference]: Start difference. First operand 1007 states and 1496 transitions. cyclomatic complexity: 490 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:05,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:05,224 INFO L93 Difference]: Finished difference Result 1007 states and 1495 transitions. [2024-11-23 02:54:05,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1495 transitions. [2024-11-23 02:54:05,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:05,234 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1495 transitions. [2024-11-23 02:54:05,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2024-11-23 02:54:05,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2024-11-23 02:54:05,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1495 transitions. [2024-11-23 02:54:05,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:05,236 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1495 transitions. [2024-11-23 02:54:05,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1495 transitions. [2024-11-23 02:54:05,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2024-11-23 02:54:05,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4846077457795432) internal successors, (1495), 1006 states have internal predecessors, (1495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:05,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1495 transitions. [2024-11-23 02:54:05,251 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1495 transitions. [2024-11-23 02:54:05,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:05,252 INFO L425 stractBuchiCegarLoop]: Abstraction has 1007 states and 1495 transitions. [2024-11-23 02:54:05,252 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-23 02:54:05,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1495 transitions. [2024-11-23 02:54:05,257 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:05,257 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:05,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:05,258 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:05,258 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:05,259 INFO L745 eck$LassoCheckResult]: Stem: 10371#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10372#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 11085#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11086#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10685#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 10686#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10243#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10244#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10335#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11071#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10211#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10212#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10640#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10672#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10339#L866 assume !(0 == ~M_E~0); 10340#L866-2 assume !(0 == ~T1_E~0); 10870#L871-1 assume !(0 == ~T2_E~0); 10871#L876-1 assume !(0 == ~T3_E~0); 11111#L881-1 assume !(0 == ~T4_E~0); 10884#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10629#L891-1 assume !(0 == ~T6_E~0); 10630#L896-1 assume !(0 == ~T7_E~0); 10878#L901-1 assume !(0 == ~T8_E~0); 10899#L906-1 assume !(0 == ~E_M~0); 10900#L911-1 assume !(0 == ~E_1~0); 10682#L916-1 assume !(0 == ~E_2~0); 10683#L921-1 assume !(0 == ~E_3~0); 10992#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 11082#L931-1 assume !(0 == ~E_5~0); 11114#L936-1 assume !(0 == ~E_6~0); 11118#L941-1 assume !(0 == ~E_7~0); 10687#L946-1 assume !(0 == ~E_8~0); 10688#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11099#L430 assume !(1 == ~m_pc~0); 10529#L430-2 is_master_triggered_~__retres1~0#1 := 0; 10158#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10159#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10804#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10805#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10973#L449 assume 1 == ~t1_pc~0; 10974#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10346#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10185#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10186#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 10914#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10744#L468 assume !(1 == ~t2_pc~0); 10146#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10145#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10539#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10534#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 10160#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10161#L487 assume 1 == ~t3_pc~0; 11109#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10249#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10142#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10143#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 10607#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10608#L506 assume !(1 == ~t4_pc~0); 10739#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10789#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10235#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10236#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 10733#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10546#L525 assume 1 == ~t5_pc~0; 10480#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10199#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11030#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11031#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 10403#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10404#L544 assume !(1 == ~t6_pc~0); 10547#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10548#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10519#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10180#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 10181#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11063#L563 assume 1 == ~t7_pc~0; 10937#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10203#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10204#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10631#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 10347#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10348#L582 assume 1 == ~t8_pc~0; 10267#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10268#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10979#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10595#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 10484#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10485#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 10977#L964-2 assume !(1 == ~T1_E~0); 10405#L969-1 assume !(1 == ~T2_E~0); 10406#L974-1 assume !(1 == ~T3_E~0); 11010#L979-1 assume !(1 == ~T4_E~0); 11011#L984-1 assume !(1 == ~T5_E~0); 10553#L989-1 assume !(1 == ~T6_E~0); 10554#L994-1 assume !(1 == ~T7_E~0); 10436#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10437#L1004-1 assume !(1 == ~E_M~0); 10182#L1009-1 assume !(1 == ~E_1~0); 10183#L1014-1 assume !(1 == ~E_2~0); 10425#L1019-1 assume !(1 == ~E_3~0); 10965#L1024-1 assume !(1 == ~E_4~0); 10368#L1029-1 assume !(1 == ~E_5~0); 10369#L1034-1 assume !(1 == ~E_6~0); 10452#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11095#L1044-1 assume !(1 == ~E_8~0); 10651#L1049-1 assume { :end_inline_reset_delta_events } true; 10333#L1315-2 [2024-11-23 02:54:05,259 INFO L747 eck$LassoCheckResult]: Loop: 10333#L1315-2 assume !false; 10334#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10747#L841-1 assume !false; 11001#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10398#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10399#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10580#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10155#L724 assume !(0 != eval_~tmp~0#1); 10157#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10741#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10164#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10165#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10457#L871-3 assume !(0 == ~T2_E~0); 10458#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10474#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10475#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10715#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10716#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10573#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10574#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10717#L911-3 assume !(0 == ~E_1~0); 10931#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10501#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10502#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10920#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10581#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10582#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10732#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10459#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10460#L430-30 assume 1 == ~m_pc~0; 10486#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10487#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10558#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10559#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10948#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10954#L449-30 assume 1 == ~t1_pc~0; 10489#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10178#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10179#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10552#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10263#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10264#L468-30 assume 1 == ~t2_pc~0; 10363#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10364#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10455#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10456#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 10707#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10540#L487-30 assume !(1 == ~t3_pc~0); 10337#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 10338#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10769#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10770#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10972#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10624#L506-30 assume !(1 == ~t4_pc~0); 10625#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 10654#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10655#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11018#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10541#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10542#L525-30 assume 1 == ~t5_pc~0; 11059#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11060#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10888#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10889#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10545#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10315#L544-30 assume !(1 == ~t6_pc~0); 10129#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 10128#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10241#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10242#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11066#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11049#L563-30 assume 1 == ~t7_pc~0; 10282#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10283#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10304#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10641#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10642#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11039#L582-30 assume 1 == ~t8_pc~0; 10999#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10392#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10627#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11129#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11119#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10190#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10191#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10329#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10318#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10319#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10753#L984-3 assume !(1 == ~T5_E~0); 10754#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10373#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10374#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10912#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10226#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10227#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10729#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10730#L1024-3 assume !(1 == ~E_4~0); 10708#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10677#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10678#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10964#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10361#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10362#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10482#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10491#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10395#L1334 assume !(0 == start_simulation_~tmp~3#1); 10396#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10409#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10123#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10124#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 10184#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11084#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10763#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 10764#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 10333#L1315-2 [2024-11-23 02:54:05,260 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:05,260 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2024-11-23 02:54:05,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:05,260 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675783259] [2024-11-23 02:54:05,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:05,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:05,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:05,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:05,305 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:05,305 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675783259] [2024-11-23 02:54:05,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [675783259] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:05,306 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:05,308 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:05,309 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149686930] [2024-11-23 02:54:05,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:05,309 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:05,309 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:05,310 INFO L85 PathProgramCache]: Analyzing trace with hash 431994368, now seen corresponding path program 1 times [2024-11-23 02:54:05,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:05,310 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [840863356] [2024-11-23 02:54:05,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:05,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:05,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:05,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:05,360 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:05,360 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [840863356] [2024-11-23 02:54:05,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [840863356] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:05,361 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:05,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:05,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108393031] [2024-11-23 02:54:05,362 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:05,362 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:05,362 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:05,364 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:05,364 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:05,364 INFO L87 Difference]: Start difference. First operand 1007 states and 1495 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:05,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:05,385 INFO L93 Difference]: Finished difference Result 1007 states and 1494 transitions. [2024-11-23 02:54:05,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1494 transitions. [2024-11-23 02:54:05,391 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:05,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1494 transitions. [2024-11-23 02:54:05,395 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2024-11-23 02:54:05,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2024-11-23 02:54:05,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1494 transitions. [2024-11-23 02:54:05,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:05,397 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1494 transitions. [2024-11-23 02:54:05,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1494 transitions. [2024-11-23 02:54:05,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2024-11-23 02:54:05,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.483614697120159) internal successors, (1494), 1006 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:05,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1494 transitions. [2024-11-23 02:54:05,442 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1494 transitions. [2024-11-23 02:54:05,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:05,444 INFO L425 stractBuchiCegarLoop]: Abstraction has 1007 states and 1494 transitions. [2024-11-23 02:54:05,444 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-23 02:54:05,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1494 transitions. [2024-11-23 02:54:05,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:05,449 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:05,449 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:05,451 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:05,451 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:05,451 INFO L745 eck$LassoCheckResult]: Stem: 12392#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12393#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13106#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13107#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12706#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 12707#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12264#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12265#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12356#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13092#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12232#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12233#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12661#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12693#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12360#L866 assume !(0 == ~M_E~0); 12361#L866-2 assume !(0 == ~T1_E~0); 12891#L871-1 assume !(0 == ~T2_E~0); 12892#L876-1 assume !(0 == ~T3_E~0); 13132#L881-1 assume !(0 == ~T4_E~0); 12905#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12650#L891-1 assume !(0 == ~T6_E~0); 12651#L896-1 assume !(0 == ~T7_E~0); 12899#L901-1 assume !(0 == ~T8_E~0); 12920#L906-1 assume !(0 == ~E_M~0); 12921#L911-1 assume !(0 == ~E_1~0); 12703#L916-1 assume !(0 == ~E_2~0); 12704#L921-1 assume !(0 == ~E_3~0); 13013#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 13103#L931-1 assume !(0 == ~E_5~0); 13135#L936-1 assume !(0 == ~E_6~0); 13139#L941-1 assume !(0 == ~E_7~0); 12708#L946-1 assume !(0 == ~E_8~0); 12709#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13120#L430 assume !(1 == ~m_pc~0); 12550#L430-2 is_master_triggered_~__retres1~0#1 := 0; 12179#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12180#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12825#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12826#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12994#L449 assume 1 == ~t1_pc~0; 12995#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12367#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12206#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12207#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 12935#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12765#L468 assume !(1 == ~t2_pc~0); 12167#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12166#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12560#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12555#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 12181#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12182#L487 assume 1 == ~t3_pc~0; 13130#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12270#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12163#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12164#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 12628#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12629#L506 assume !(1 == ~t4_pc~0); 12760#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12810#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12256#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12257#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 12754#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12567#L525 assume 1 == ~t5_pc~0; 12501#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12220#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13051#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13052#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 12424#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12425#L544 assume !(1 == ~t6_pc~0); 12568#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12569#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12540#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12201#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 12202#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13084#L563 assume 1 == ~t7_pc~0; 12958#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12224#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12652#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 12368#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12369#L582 assume 1 == ~t8_pc~0; 12288#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12289#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13000#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12616#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 12505#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12506#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 12998#L964-2 assume !(1 == ~T1_E~0); 12426#L969-1 assume !(1 == ~T2_E~0); 12427#L974-1 assume !(1 == ~T3_E~0); 13031#L979-1 assume !(1 == ~T4_E~0); 13032#L984-1 assume !(1 == ~T5_E~0); 12574#L989-1 assume !(1 == ~T6_E~0); 12575#L994-1 assume !(1 == ~T7_E~0); 12457#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12458#L1004-1 assume !(1 == ~E_M~0); 12203#L1009-1 assume !(1 == ~E_1~0); 12204#L1014-1 assume !(1 == ~E_2~0); 12446#L1019-1 assume !(1 == ~E_3~0); 12986#L1024-1 assume !(1 == ~E_4~0); 12389#L1029-1 assume !(1 == ~E_5~0); 12390#L1034-1 assume !(1 == ~E_6~0); 12473#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 13116#L1044-1 assume !(1 == ~E_8~0); 12672#L1049-1 assume { :end_inline_reset_delta_events } true; 12354#L1315-2 [2024-11-23 02:54:05,452 INFO L747 eck$LassoCheckResult]: Loop: 12354#L1315-2 assume !false; 12355#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12768#L841-1 assume !false; 13022#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12419#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12420#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12601#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12176#L724 assume !(0 != eval_~tmp~0#1); 12178#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12762#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12185#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12186#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12478#L871-3 assume !(0 == ~T2_E~0); 12479#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12495#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12496#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12736#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12737#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12594#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12595#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12738#L911-3 assume !(0 == ~E_1~0); 12952#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12522#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12523#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12941#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12602#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12603#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12753#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12480#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12481#L430-30 assume 1 == ~m_pc~0; 12507#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12508#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12579#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12580#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12969#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12975#L449-30 assume 1 == ~t1_pc~0; 12510#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12199#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12200#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12573#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12284#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12285#L468-30 assume 1 == ~t2_pc~0; 12384#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12385#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12476#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12477#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 12728#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12561#L487-30 assume !(1 == ~t3_pc~0); 12358#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 12359#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12790#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12791#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12993#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12645#L506-30 assume !(1 == ~t4_pc~0); 12646#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 12675#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12676#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13039#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12562#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12563#L525-30 assume 1 == ~t5_pc~0; 13080#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13081#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12909#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12910#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12566#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12336#L544-30 assume 1 == ~t6_pc~0; 12148#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12149#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12262#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12263#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13087#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13070#L563-30 assume !(1 == ~t7_pc~0); 12305#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 12304#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12325#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12662#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12663#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13060#L582-30 assume 1 == ~t8_pc~0; 13020#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12413#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12648#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13150#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13140#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12211#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12212#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12350#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12339#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12340#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12774#L984-3 assume !(1 == ~T5_E~0); 12775#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12394#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12395#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12933#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12247#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12248#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12750#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12751#L1024-3 assume !(1 == ~E_4~0); 12729#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12698#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12699#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12985#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12382#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12383#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12503#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12512#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12416#L1334 assume !(0 == start_simulation_~tmp~3#1); 12417#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12430#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12144#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12145#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 12205#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13105#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12784#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12785#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 12354#L1315-2 [2024-11-23 02:54:05,453 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:05,453 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2024-11-23 02:54:05,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:05,454 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58156489] [2024-11-23 02:54:05,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:05,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:05,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:05,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:05,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:05,489 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58156489] [2024-11-23 02:54:05,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58156489] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:05,489 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:05,489 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:05,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120723788] [2024-11-23 02:54:05,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:05,490 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:05,490 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:05,490 INFO L85 PathProgramCache]: Analyzing trace with hash 862321344, now seen corresponding path program 1 times [2024-11-23 02:54:05,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:05,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321015378] [2024-11-23 02:54:05,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:05,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:05,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:05,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:05,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:05,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321015378] [2024-11-23 02:54:05,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321015378] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:05,549 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:05,549 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:05,549 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741662100] [2024-11-23 02:54:05,549 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:05,550 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:05,550 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:05,550 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:05,550 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:05,550 INFO L87 Difference]: Start difference. First operand 1007 states and 1494 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:05,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:05,569 INFO L93 Difference]: Finished difference Result 1007 states and 1493 transitions. [2024-11-23 02:54:05,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1493 transitions. [2024-11-23 02:54:05,574 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:05,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1493 transitions. [2024-11-23 02:54:05,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2024-11-23 02:54:05,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2024-11-23 02:54:05,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1493 transitions. [2024-11-23 02:54:05,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:05,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1493 transitions. [2024-11-23 02:54:05,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1493 transitions. [2024-11-23 02:54:05,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2024-11-23 02:54:05,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4826216484607746) internal successors, (1493), 1006 states have internal predecessors, (1493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:05,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1493 transitions. [2024-11-23 02:54:05,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1493 transitions. [2024-11-23 02:54:05,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:05,600 INFO L425 stractBuchiCegarLoop]: Abstraction has 1007 states and 1493 transitions. [2024-11-23 02:54:05,600 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-23 02:54:05,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1493 transitions. [2024-11-23 02:54:05,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:05,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:05,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:05,606 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:05,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:05,606 INFO L745 eck$LassoCheckResult]: Stem: 14413#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15127#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15128#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14727#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 14728#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14285#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14286#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14377#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15113#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14253#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14254#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14682#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14714#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14381#L866 assume !(0 == ~M_E~0); 14382#L866-2 assume !(0 == ~T1_E~0); 14912#L871-1 assume !(0 == ~T2_E~0); 14913#L876-1 assume !(0 == ~T3_E~0); 15153#L881-1 assume !(0 == ~T4_E~0); 14926#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14671#L891-1 assume !(0 == ~T6_E~0); 14672#L896-1 assume !(0 == ~T7_E~0); 14920#L901-1 assume !(0 == ~T8_E~0); 14941#L906-1 assume !(0 == ~E_M~0); 14942#L911-1 assume !(0 == ~E_1~0); 14724#L916-1 assume !(0 == ~E_2~0); 14725#L921-1 assume !(0 == ~E_3~0); 15034#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 15124#L931-1 assume !(0 == ~E_5~0); 15156#L936-1 assume !(0 == ~E_6~0); 15160#L941-1 assume !(0 == ~E_7~0); 14729#L946-1 assume !(0 == ~E_8~0); 14730#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15141#L430 assume !(1 == ~m_pc~0); 14571#L430-2 is_master_triggered_~__retres1~0#1 := 0; 14200#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14201#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14846#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14847#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15015#L449 assume 1 == ~t1_pc~0; 15016#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14388#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14227#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14228#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 14956#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14786#L468 assume !(1 == ~t2_pc~0); 14188#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14187#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14581#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14576#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 14202#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14203#L487 assume 1 == ~t3_pc~0; 15151#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14291#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14184#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14185#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 14649#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14650#L506 assume !(1 == ~t4_pc~0); 14781#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14831#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14277#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14278#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 14775#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14588#L525 assume 1 == ~t5_pc~0; 14522#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14241#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15072#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15073#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 14445#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14446#L544 assume !(1 == ~t6_pc~0); 14589#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14590#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14561#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14222#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 14223#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15105#L563 assume 1 == ~t7_pc~0; 14979#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14245#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14246#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14673#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 14389#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14390#L582 assume 1 == ~t8_pc~0; 14309#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14310#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15021#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14637#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 14526#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14527#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 15019#L964-2 assume !(1 == ~T1_E~0); 14447#L969-1 assume !(1 == ~T2_E~0); 14448#L974-1 assume !(1 == ~T3_E~0); 15052#L979-1 assume !(1 == ~T4_E~0); 15053#L984-1 assume !(1 == ~T5_E~0); 14595#L989-1 assume !(1 == ~T6_E~0); 14596#L994-1 assume !(1 == ~T7_E~0); 14478#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14479#L1004-1 assume !(1 == ~E_M~0); 14224#L1009-1 assume !(1 == ~E_1~0); 14225#L1014-1 assume !(1 == ~E_2~0); 14467#L1019-1 assume !(1 == ~E_3~0); 15007#L1024-1 assume !(1 == ~E_4~0); 14410#L1029-1 assume !(1 == ~E_5~0); 14411#L1034-1 assume !(1 == ~E_6~0); 14494#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15137#L1044-1 assume !(1 == ~E_8~0); 14693#L1049-1 assume { :end_inline_reset_delta_events } true; 14375#L1315-2 [2024-11-23 02:54:05,607 INFO L747 eck$LassoCheckResult]: Loop: 14375#L1315-2 assume !false; 14376#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14789#L841-1 assume !false; 15043#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14440#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14441#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14622#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14197#L724 assume !(0 != eval_~tmp~0#1); 14199#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14783#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14206#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14207#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14499#L871-3 assume !(0 == ~T2_E~0); 14500#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14516#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14517#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14757#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14758#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14615#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14616#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14759#L911-3 assume !(0 == ~E_1~0); 14973#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14543#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14544#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14962#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14623#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14624#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14774#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14501#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14502#L430-30 assume 1 == ~m_pc~0; 14528#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14529#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14600#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14601#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14990#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14996#L449-30 assume 1 == ~t1_pc~0; 14531#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14220#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14221#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14594#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14305#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14306#L468-30 assume 1 == ~t2_pc~0; 14405#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14406#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14497#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14498#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 14749#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14582#L487-30 assume 1 == ~t3_pc~0; 14560#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14380#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14811#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14812#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15014#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14666#L506-30 assume !(1 == ~t4_pc~0); 14667#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14696#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14697#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15060#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14583#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14584#L525-30 assume 1 == ~t5_pc~0; 15101#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15102#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14930#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14931#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14587#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14357#L544-30 assume 1 == ~t6_pc~0; 14169#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14170#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14283#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14284#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15108#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15091#L563-30 assume 1 == ~t7_pc~0; 14324#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14325#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14346#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14683#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14684#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15081#L582-30 assume 1 == ~t8_pc~0; 15041#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14434#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14669#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15171#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15161#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14232#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14233#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14371#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14360#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14361#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14795#L984-3 assume !(1 == ~T5_E~0); 14796#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14415#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14416#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14954#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14268#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14269#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14771#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14772#L1024-3 assume !(1 == ~E_4~0); 14750#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14719#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14720#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15006#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14403#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14404#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14524#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14533#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14437#L1334 assume !(0 == start_simulation_~tmp~3#1); 14438#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14451#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14165#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14166#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 14226#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15126#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14805#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14806#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 14375#L1315-2 [2024-11-23 02:54:05,607 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:05,608 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2024-11-23 02:54:05,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:05,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760231240] [2024-11-23 02:54:05,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:05,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:05,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:05,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:05,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:05,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760231240] [2024-11-23 02:54:05,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760231240] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:05,649 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:05,650 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:05,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630804084] [2024-11-23 02:54:05,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:05,651 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:05,652 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:05,652 INFO L85 PathProgramCache]: Analyzing trace with hash 1121264062, now seen corresponding path program 1 times [2024-11-23 02:54:05,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:05,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455300845] [2024-11-23 02:54:05,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:05,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:05,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:05,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:05,705 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:05,706 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455300845] [2024-11-23 02:54:05,706 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [455300845] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:05,708 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:05,708 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:05,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [762247308] [2024-11-23 02:54:05,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:05,709 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:05,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:05,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:05,710 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:05,710 INFO L87 Difference]: Start difference. First operand 1007 states and 1493 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:05,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:05,726 INFO L93 Difference]: Finished difference Result 1007 states and 1492 transitions. [2024-11-23 02:54:05,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1492 transitions. [2024-11-23 02:54:05,732 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:05,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1492 transitions. [2024-11-23 02:54:05,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2024-11-23 02:54:05,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2024-11-23 02:54:05,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1492 transitions. [2024-11-23 02:54:05,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:05,739 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1492 transitions. [2024-11-23 02:54:05,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1492 transitions. [2024-11-23 02:54:05,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2024-11-23 02:54:05,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4816285998013903) internal successors, (1492), 1006 states have internal predecessors, (1492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:05,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1492 transitions. [2024-11-23 02:54:05,754 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1492 transitions. [2024-11-23 02:54:05,755 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:05,756 INFO L425 stractBuchiCegarLoop]: Abstraction has 1007 states and 1492 transitions. [2024-11-23 02:54:05,757 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-23 02:54:05,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1492 transitions. [2024-11-23 02:54:05,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2024-11-23 02:54:05,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:05,762 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:05,763 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:05,763 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:05,764 INFO L745 eck$LassoCheckResult]: Stem: 16434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17148#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17149#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16748#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 16749#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16306#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16307#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16398#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17134#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16274#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16275#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16703#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16735#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16402#L866 assume !(0 == ~M_E~0); 16403#L866-2 assume !(0 == ~T1_E~0); 16933#L871-1 assume !(0 == ~T2_E~0); 16934#L876-1 assume !(0 == ~T3_E~0); 17174#L881-1 assume !(0 == ~T4_E~0); 16947#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16692#L891-1 assume !(0 == ~T6_E~0); 16693#L896-1 assume !(0 == ~T7_E~0); 16941#L901-1 assume !(0 == ~T8_E~0); 16962#L906-1 assume !(0 == ~E_M~0); 16963#L911-1 assume !(0 == ~E_1~0); 16745#L916-1 assume !(0 == ~E_2~0); 16746#L921-1 assume !(0 == ~E_3~0); 17055#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 17145#L931-1 assume !(0 == ~E_5~0); 17177#L936-1 assume !(0 == ~E_6~0); 17181#L941-1 assume !(0 == ~E_7~0); 16750#L946-1 assume !(0 == ~E_8~0); 16751#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17162#L430 assume !(1 == ~m_pc~0); 16592#L430-2 is_master_triggered_~__retres1~0#1 := 0; 16221#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16222#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16867#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16868#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17036#L449 assume 1 == ~t1_pc~0; 17037#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16409#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16248#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16249#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 16977#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16807#L468 assume !(1 == ~t2_pc~0); 16209#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16208#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16602#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16597#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 16223#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16224#L487 assume 1 == ~t3_pc~0; 17172#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16312#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16205#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16206#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 16670#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16671#L506 assume !(1 == ~t4_pc~0); 16802#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16852#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16298#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16299#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 16796#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16609#L525 assume 1 == ~t5_pc~0; 16543#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16262#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17093#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17094#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 16466#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16467#L544 assume !(1 == ~t6_pc~0); 16610#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16611#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16582#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16243#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 16244#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17126#L563 assume 1 == ~t7_pc~0; 17000#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16266#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16694#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 16410#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16411#L582 assume 1 == ~t8_pc~0; 16330#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16331#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17042#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16658#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 16547#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16548#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 17040#L964-2 assume !(1 == ~T1_E~0); 16468#L969-1 assume !(1 == ~T2_E~0); 16469#L974-1 assume !(1 == ~T3_E~0); 17073#L979-1 assume !(1 == ~T4_E~0); 17074#L984-1 assume !(1 == ~T5_E~0); 16616#L989-1 assume !(1 == ~T6_E~0); 16617#L994-1 assume !(1 == ~T7_E~0); 16499#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16500#L1004-1 assume !(1 == ~E_M~0); 16245#L1009-1 assume !(1 == ~E_1~0); 16246#L1014-1 assume !(1 == ~E_2~0); 16488#L1019-1 assume !(1 == ~E_3~0); 17028#L1024-1 assume !(1 == ~E_4~0); 16431#L1029-1 assume !(1 == ~E_5~0); 16432#L1034-1 assume !(1 == ~E_6~0); 16515#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17158#L1044-1 assume !(1 == ~E_8~0); 16714#L1049-1 assume { :end_inline_reset_delta_events } true; 16396#L1315-2 [2024-11-23 02:54:05,764 INFO L747 eck$LassoCheckResult]: Loop: 16396#L1315-2 assume !false; 16397#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16810#L841-1 assume !false; 17064#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16461#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16462#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16643#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16218#L724 assume !(0 != eval_~tmp~0#1); 16220#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16804#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16227#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16228#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16520#L871-3 assume !(0 == ~T2_E~0); 16521#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16537#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16538#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16778#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16779#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16636#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16637#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16780#L911-3 assume !(0 == ~E_1~0); 16994#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16564#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16565#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16983#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16644#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16645#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16795#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16522#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16523#L430-30 assume 1 == ~m_pc~0; 16549#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16550#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16621#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16622#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17011#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17017#L449-30 assume 1 == ~t1_pc~0; 16552#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16241#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16242#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16615#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16326#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16327#L468-30 assume 1 == ~t2_pc~0; 16426#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16427#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16518#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16519#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 16770#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16603#L487-30 assume !(1 == ~t3_pc~0); 16400#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 16401#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16832#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16833#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17035#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16687#L506-30 assume !(1 == ~t4_pc~0); 16688#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 16717#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16718#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17081#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16604#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16605#L525-30 assume 1 == ~t5_pc~0; 17122#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17123#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16951#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16952#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16608#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16378#L544-30 assume !(1 == ~t6_pc~0); 16192#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 16191#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16304#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16305#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17129#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17112#L563-30 assume 1 == ~t7_pc~0; 16345#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16346#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16367#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16704#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16705#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17102#L582-30 assume 1 == ~t8_pc~0; 17062#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16455#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16690#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17192#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17182#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16253#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16254#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16392#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16381#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16382#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16816#L984-3 assume !(1 == ~T5_E~0); 16817#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16436#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16437#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16975#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16289#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16290#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16792#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16793#L1024-3 assume !(1 == ~E_4~0); 16771#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16740#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16741#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17027#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16424#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16425#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16545#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16554#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16458#L1334 assume !(0 == start_simulation_~tmp~3#1); 16459#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16472#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16186#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16187#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 16247#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17147#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16826#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 16827#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 16396#L1315-2 [2024-11-23 02:54:05,764 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:05,765 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2024-11-23 02:54:05,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:05,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416671101] [2024-11-23 02:54:05,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:05,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:05,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:05,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:05,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:05,835 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416671101] [2024-11-23 02:54:05,835 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416671101] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:05,835 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:05,835 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:05,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1150823353] [2024-11-23 02:54:05,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:05,836 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:05,836 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:05,836 INFO L85 PathProgramCache]: Analyzing trace with hash 431994368, now seen corresponding path program 2 times [2024-11-23 02:54:05,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:05,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387963378] [2024-11-23 02:54:05,837 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:54:05,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:05,854 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:54:05,854 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-23 02:54:05,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:05,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:05,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387963378] [2024-11-23 02:54:05,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387963378] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:05,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:05,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:05,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259443464] [2024-11-23 02:54:05,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:05,899 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:05,899 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:05,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:54:05,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:54:05,899 INFO L87 Difference]: Start difference. First operand 1007 states and 1492 transitions. cyclomatic complexity: 486 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:06,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:06,057 INFO L93 Difference]: Finished difference Result 1834 states and 2707 transitions. [2024-11-23 02:54:06,058 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1834 states and 2707 transitions. [2024-11-23 02:54:06,069 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1701 [2024-11-23 02:54:06,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1834 states to 1834 states and 2707 transitions. [2024-11-23 02:54:06,078 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1834 [2024-11-23 02:54:06,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1834 [2024-11-23 02:54:06,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1834 states and 2707 transitions. [2024-11-23 02:54:06,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:06,082 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1834 states and 2707 transitions. [2024-11-23 02:54:06,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1834 states and 2707 transitions. [2024-11-23 02:54:06,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1834 to 1834. [2024-11-23 02:54:06,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1834 states, 1834 states have (on average 1.4760087241003272) internal successors, (2707), 1833 states have internal predecessors, (2707), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:06,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1834 states to 1834 states and 2707 transitions. [2024-11-23 02:54:06,121 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1834 states and 2707 transitions. [2024-11-23 02:54:06,121 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:54:06,122 INFO L425 stractBuchiCegarLoop]: Abstraction has 1834 states and 2707 transitions. [2024-11-23 02:54:06,122 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-23 02:54:06,122 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1834 states and 2707 transitions. [2024-11-23 02:54:06,128 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1701 [2024-11-23 02:54:06,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:06,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:06,130 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:06,130 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:06,130 INFO L745 eck$LassoCheckResult]: Stem: 19286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 20088#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20089#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19617#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 19618#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19157#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19158#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19250#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20066#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19125#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19126#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19570#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19604#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19254#L866 assume !(0 == ~M_E~0); 19255#L866-2 assume !(0 == ~T1_E~0); 19816#L871-1 assume !(0 == ~T2_E~0); 19817#L876-1 assume !(0 == ~T3_E~0); 20138#L881-1 assume !(0 == ~T4_E~0); 19830#L886-1 assume !(0 == ~T5_E~0); 19559#L891-1 assume !(0 == ~T6_E~0); 19560#L896-1 assume !(0 == ~T7_E~0); 19824#L901-1 assume !(0 == ~T8_E~0); 19845#L906-1 assume !(0 == ~E_M~0); 19846#L911-1 assume !(0 == ~E_1~0); 19614#L916-1 assume !(0 == ~E_2~0); 19615#L921-1 assume !(0 == ~E_3~0); 19955#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 20084#L931-1 assume !(0 == ~E_5~0); 20144#L936-1 assume !(0 == ~E_6~0); 20156#L941-1 assume !(0 == ~E_7~0); 19619#L946-1 assume !(0 == ~E_8~0); 19620#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20111#L430 assume !(1 == ~m_pc~0); 19455#L430-2 is_master_triggered_~__retres1~0#1 := 0; 19072#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19073#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19745#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19746#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19931#L449 assume 1 == ~t1_pc~0; 19932#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19261#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19099#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19100#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 19862#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19679#L468 assume !(1 == ~t2_pc~0); 19060#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19059#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19465#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19460#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 19074#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19075#L487 assume 1 == ~t3_pc~0; 20133#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19163#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19056#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19057#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 19537#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19538#L506 assume !(1 == ~t4_pc~0); 19673#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19729#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19149#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19150#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 19666#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19472#L525 assume 1 == ~t5_pc~0; 19403#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19113#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20006#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20007#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 19319#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19320#L544 assume !(1 == ~t6_pc~0); 19473#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19474#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19444#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19094#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 19095#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20054#L563 assume 1 == ~t7_pc~0; 19888#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19117#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19118#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19561#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 19262#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19263#L582 assume 1 == ~t8_pc~0; 19181#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19182#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19939#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19523#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 19407#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19408#L964 assume !(1 == ~M_E~0); 19935#L964-2 assume !(1 == ~T1_E~0); 19321#L969-1 assume !(1 == ~T2_E~0); 19322#L974-1 assume !(1 == ~T3_E~0); 19977#L979-1 assume !(1 == ~T4_E~0); 19978#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20176#L989-1 assume !(1 == ~T6_E~0); 20723#L994-1 assume !(1 == ~T7_E~0); 20722#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20721#L1004-1 assume !(1 == ~E_M~0); 20720#L1009-1 assume !(1 == ~E_1~0); 20719#L1014-1 assume !(1 == ~E_2~0); 20718#L1019-1 assume !(1 == ~E_3~0); 20717#L1024-1 assume !(1 == ~E_4~0); 19283#L1029-1 assume !(1 == ~E_5~0); 19284#L1034-1 assume !(1 == ~E_6~0); 19371#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 20180#L1044-1 assume !(1 == ~E_8~0); 19581#L1049-1 assume { :end_inline_reset_delta_events } true; 19248#L1315-2 [2024-11-23 02:54:06,131 INFO L747 eck$LassoCheckResult]: Loop: 19248#L1315-2 assume !false; 19249#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19682#L841-1 assume !false; 20113#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20114#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19980#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19507#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19069#L724 assume !(0 != eval_~tmp~0#1); 19071#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19675#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19676#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20136#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19377#L871-3 assume !(0 == ~T2_E~0); 19378#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19397#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19398#L886-3 assume !(0 == ~T5_E~0); 19648#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19649#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19500#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19501#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19650#L911-3 assume !(0 == ~E_1~0); 19881#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19424#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19425#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19869#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19508#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19509#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19665#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19379#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19380#L430-30 assume 1 == ~m_pc~0; 19409#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19410#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19484#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19485#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19903#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19911#L449-30 assume 1 == ~t1_pc~0; 19412#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19092#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19093#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19478#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19177#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19178#L468-30 assume !(1 == ~t2_pc~0); 19280#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 19279#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19375#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19376#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 19640#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19466#L487-30 assume 1 == ~t3_pc~0; 19443#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19253#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19705#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19706#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19930#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19554#L506-30 assume !(1 == ~t4_pc~0); 19555#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 19584#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19585#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19991#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19467#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19468#L525-30 assume 1 == ~t5_pc~0; 20049#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20050#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19834#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19835#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19471#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19229#L544-30 assume 1 == ~t6_pc~0; 19041#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19042#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19155#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19156#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20059#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20033#L563-30 assume 1 == ~t7_pc~0; 19196#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19197#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19218#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19571#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19572#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20017#L582-30 assume 1 == ~t8_pc~0; 19962#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19308#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19557#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20179#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20158#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19104#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19105#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19244#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19232#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19233#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19689#L984-3 assume !(1 == ~T5_E~0); 19690#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19288#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19289#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19860#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19140#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19141#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19662#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19663#L1024-3 assume !(1 == ~E_4~0); 19641#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19609#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19610#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19922#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19276#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19277#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19405#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20762#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 20761#L1334 assume !(0 == start_simulation_~tmp~3#1); 20027#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20758#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20751#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20750#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 20749#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20086#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20087#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 20065#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 19248#L1315-2 [2024-11-23 02:54:06,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:06,131 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2024-11-23 02:54:06,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:06,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904045002] [2024-11-23 02:54:06,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:06,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:06,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:06,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:06,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:06,192 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904045002] [2024-11-23 02:54:06,192 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904045002] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:06,192 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:06,193 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:06,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635835762] [2024-11-23 02:54:06,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:06,193 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:06,193 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:06,193 INFO L85 PathProgramCache]: Analyzing trace with hash -10674303, now seen corresponding path program 1 times [2024-11-23 02:54:06,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:06,194 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561168874] [2024-11-23 02:54:06,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:06,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:06,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:06,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:06,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:06,235 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561168874] [2024-11-23 02:54:06,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [561168874] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:06,236 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:06,236 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:06,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [364606216] [2024-11-23 02:54:06,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:06,236 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:06,236 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:06,237 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:54:06,237 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:54:06,237 INFO L87 Difference]: Start difference. First operand 1834 states and 2707 transitions. cyclomatic complexity: 875 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:06,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:06,384 INFO L93 Difference]: Finished difference Result 3342 states and 4920 transitions. [2024-11-23 02:54:06,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3342 states and 4920 transitions. [2024-11-23 02:54:06,400 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3189 [2024-11-23 02:54:06,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3342 states to 3342 states and 4920 transitions. [2024-11-23 02:54:06,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3342 [2024-11-23 02:54:06,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3342 [2024-11-23 02:54:06,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3342 states and 4920 transitions. [2024-11-23 02:54:06,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:06,427 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3342 states and 4920 transitions. [2024-11-23 02:54:06,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3342 states and 4920 transitions. [2024-11-23 02:54:06,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3342 to 3340. [2024-11-23 02:54:06,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3340 states, 3340 states have (on average 1.4724550898203592) internal successors, (4918), 3339 states have internal predecessors, (4918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:06,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3340 states to 3340 states and 4918 transitions. [2024-11-23 02:54:06,494 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3340 states and 4918 transitions. [2024-11-23 02:54:06,494 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:54:06,495 INFO L425 stractBuchiCegarLoop]: Abstraction has 3340 states and 4918 transitions. [2024-11-23 02:54:06,495 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-23 02:54:06,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3340 states and 4918 transitions. [2024-11-23 02:54:06,508 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3189 [2024-11-23 02:54:06,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:06,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:06,510 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:06,510 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:06,510 INFO L745 eck$LassoCheckResult]: Stem: 24475#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25231#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25232#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24799#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 24800#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24345#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24346#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24439#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25214#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24312#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24313#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24753#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24786#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24443#L866 assume !(0 == ~M_E~0); 24444#L866-2 assume !(0 == ~T1_E~0); 24993#L871-1 assume !(0 == ~T2_E~0); 24994#L876-1 assume !(0 == ~T3_E~0); 25272#L881-1 assume !(0 == ~T4_E~0); 25008#L886-1 assume !(0 == ~T5_E~0); 24742#L891-1 assume !(0 == ~T6_E~0); 24743#L896-1 assume !(0 == ~T7_E~0); 25001#L901-1 assume !(0 == ~T8_E~0); 25024#L906-1 assume !(0 == ~E_M~0); 25025#L911-1 assume !(0 == ~E_1~0); 24796#L916-1 assume !(0 == ~E_2~0); 24797#L921-1 assume !(0 == ~E_3~0); 25125#L926-1 assume !(0 == ~E_4~0); 25228#L931-1 assume !(0 == ~E_5~0); 25280#L936-1 assume !(0 == ~E_6~0); 25286#L941-1 assume !(0 == ~E_7~0); 24801#L946-1 assume !(0 == ~E_8~0); 24802#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25252#L430 assume !(1 == ~m_pc~0); 24640#L430-2 is_master_triggered_~__retres1~0#1 := 0; 24258#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24259#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24925#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24926#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25101#L449 assume 1 == ~t1_pc~0; 25102#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24450#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24285#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24286#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 25039#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24863#L468 assume !(1 == ~t2_pc~0); 24246#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24245#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24650#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24645#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 24260#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24261#L487 assume 1 == ~t3_pc~0; 25269#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24351#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24242#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24243#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 24720#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24721#L506 assume !(1 == ~t4_pc~0); 24858#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24910#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24337#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24338#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 24850#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24657#L525 assume 1 == ~t5_pc~0; 24586#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24300#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25166#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25167#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 24507#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24508#L544 assume !(1 == ~t6_pc~0); 24658#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24659#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24629#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24280#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 24281#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25203#L563 assume 1 == ~t7_pc~0; 25064#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24304#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24305#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24744#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 24451#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24452#L582 assume 1 == ~t8_pc~0; 24369#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24370#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25108#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24707#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 24590#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24591#L964 assume !(1 == ~M_E~0); 25105#L964-2 assume !(1 == ~T1_E~0); 25488#L969-1 assume !(1 == ~T2_E~0); 25486#L974-1 assume !(1 == ~T3_E~0); 25143#L979-1 assume !(1 == ~T4_E~0); 25144#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25300#L989-1 assume !(1 == ~T6_E~0); 25439#L994-1 assume !(1 == ~T7_E~0); 25437#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25435#L1004-1 assume !(1 == ~E_M~0); 24282#L1009-1 assume !(1 == ~E_1~0); 24283#L1014-1 assume !(1 == ~E_2~0); 25405#L1019-1 assume !(1 == ~E_3~0); 25383#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25381#L1029-1 assume !(1 == ~E_5~0); 25380#L1034-1 assume !(1 == ~E_6~0); 25360#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25351#L1044-1 assume !(1 == ~E_8~0); 25343#L1049-1 assume { :end_inline_reset_delta_events } true; 25336#L1315-2 [2024-11-23 02:54:06,510 INFO L747 eck$LassoCheckResult]: Loop: 25336#L1315-2 assume !false; 25332#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25331#L841-1 assume !false; 25330#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25325#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25320#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25319#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25317#L724 assume !(0 != eval_~tmp~0#1); 25316#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25315#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25313#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25314#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25881#L871-3 assume !(0 == ~T2_E~0); 25878#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25876#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25874#L886-3 assume !(0 == ~T5_E~0); 25872#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25870#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25868#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25865#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25863#L911-3 assume !(0 == ~E_1~0); 25861#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25859#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25858#L926-3 assume !(0 == ~E_4~0); 25857#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25855#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25852#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25850#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25848#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25846#L430-30 assume 1 == ~m_pc~0; 25842#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25839#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25837#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25835#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25833#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25831#L449-30 assume !(1 == ~t1_pc~0); 25828#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 25825#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25823#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25821#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25819#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25817#L468-30 assume 1 == ~t2_pc~0; 25814#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25811#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25809#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25807#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 25805#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25803#L487-30 assume 1 == ~t3_pc~0; 25800#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25797#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25795#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25793#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25791#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25789#L506-30 assume !(1 == ~t4_pc~0); 25786#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 25783#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25781#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25780#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25779#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25778#L525-30 assume 1 == ~t5_pc~0; 25776#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25775#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25774#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25773#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25772#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25771#L544-30 assume !(1 == ~t6_pc~0); 25769#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 25768#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25767#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25766#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25765#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25764#L563-30 assume 1 == ~t7_pc~0; 25760#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25758#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25756#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25755#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25754#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25753#L582-30 assume !(1 == ~t8_pc~0); 25731#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 25704#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25701#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25699#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25697#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25696#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24291#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25662#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25661#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25659#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25641#L984-3 assume !(1 == ~T5_E~0); 25640#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25637#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25635#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25634#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25609#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25597#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25593#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25582#L1024-3 assume !(1 == ~E_4~0); 25549#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25523#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25513#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25507#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25506#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25474#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25465#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25464#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25460#L1334 assume !(0 == start_simulation_~tmp~3#1); 25185#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25430#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25397#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25379#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 25375#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25359#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25350#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 25342#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 25336#L1315-2 [2024-11-23 02:54:06,511 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:06,511 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2024-11-23 02:54:06,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:06,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084643371] [2024-11-23 02:54:06,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:06,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:06,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:06,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:06,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:06,570 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2084643371] [2024-11-23 02:54:06,570 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2084643371] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:06,570 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:06,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:06,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972215760] [2024-11-23 02:54:06,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:06,571 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:06,572 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:06,572 INFO L85 PathProgramCache]: Analyzing trace with hash 1868159045, now seen corresponding path program 1 times [2024-11-23 02:54:06,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:06,573 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348027403] [2024-11-23 02:54:06,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:06,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:06,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:06,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:06,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:06,692 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348027403] [2024-11-23 02:54:06,692 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [348027403] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:06,692 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:06,692 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:06,692 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694906221] [2024-11-23 02:54:06,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:06,693 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:06,693 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:06,694 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:54:06,694 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:54:06,694 INFO L87 Difference]: Start difference. First operand 3340 states and 4918 transitions. cyclomatic complexity: 1582 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:06,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:06,948 INFO L93 Difference]: Finished difference Result 3460 states and 5038 transitions. [2024-11-23 02:54:06,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3460 states and 5038 transitions. [2024-11-23 02:54:06,969 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3306 [2024-11-23 02:54:06,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3460 states to 3460 states and 5038 transitions. [2024-11-23 02:54:06,991 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3460 [2024-11-23 02:54:06,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3460 [2024-11-23 02:54:06,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3460 states and 5038 transitions. [2024-11-23 02:54:06,999 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:06,999 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3460 states and 5038 transitions. [2024-11-23 02:54:07,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3460 states and 5038 transitions. [2024-11-23 02:54:07,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3460 to 3460. [2024-11-23 02:54:07,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3460 states, 3460 states have (on average 1.4560693641618496) internal successors, (5038), 3459 states have internal predecessors, (5038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:07,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3460 states to 3460 states and 5038 transitions. [2024-11-23 02:54:07,068 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3460 states and 5038 transitions. [2024-11-23 02:54:07,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:54:07,069 INFO L425 stractBuchiCegarLoop]: Abstraction has 3460 states and 5038 transitions. [2024-11-23 02:54:07,069 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-23 02:54:07,069 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3460 states and 5038 transitions. [2024-11-23 02:54:07,079 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3306 [2024-11-23 02:54:07,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:07,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:07,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:07,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:07,081 INFO L745 eck$LassoCheckResult]: Stem: 31288#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 31289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 32092#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32093#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31617#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 31618#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31157#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31158#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31252#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32071#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31123#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31124#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31569#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31604#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31256#L866 assume !(0 == ~M_E~0); 31257#L866-2 assume !(0 == ~T1_E~0); 31821#L871-1 assume !(0 == ~T2_E~0); 31822#L876-1 assume !(0 == ~T3_E~0); 32141#L881-1 assume !(0 == ~T4_E~0); 31839#L886-1 assume !(0 == ~T5_E~0); 31557#L891-1 assume !(0 == ~T6_E~0); 31558#L896-1 assume !(0 == ~T7_E~0); 31830#L901-1 assume !(0 == ~T8_E~0); 31855#L906-1 assume !(0 == ~E_M~0); 31856#L911-1 assume !(0 == ~E_1~0); 31614#L916-1 assume !(0 == ~E_2~0); 31615#L921-1 assume !(0 == ~E_3~0); 31967#L926-1 assume !(0 == ~E_4~0); 32087#L931-1 assume !(0 == ~E_5~0); 32147#L936-1 assume !(0 == ~E_6~0); 32163#L941-1 assume !(0 == ~E_7~0); 31619#L946-1 assume !(0 == ~E_8~0); 31620#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32118#L430 assume !(1 == ~m_pc~0); 31453#L430-2 is_master_triggered_~__retres1~0#1 := 0; 31069#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31070#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31748#L1073 assume !(0 != activate_threads_~tmp~1#1); 31749#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31944#L449 assume 1 == ~t1_pc~0; 31945#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31263#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31096#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31097#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 31870#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31680#L468 assume !(1 == ~t2_pc~0); 31057#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31056#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31463#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31458#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 31071#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31072#L487 assume 1 == ~t3_pc~0; 32136#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31163#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31053#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31054#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 31535#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31536#L506 assume !(1 == ~t4_pc~0); 31674#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31731#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31149#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31150#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 31666#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31473#L525 assume 1 == ~t5_pc~0; 31400#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31111#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32012#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32013#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 31320#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31321#L544 assume !(1 == ~t6_pc~0); 31474#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31475#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31441#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31091#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 31092#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32057#L563 assume 1 == ~t7_pc~0; 31900#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31115#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31116#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31559#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 31264#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31265#L582 assume 1 == ~t8_pc~0; 31181#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31182#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31951#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31523#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 31404#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31405#L964 assume !(1 == ~M_E~0); 31948#L964-2 assume !(1 == ~T1_E~0); 31322#L969-1 assume !(1 == ~T2_E~0); 31323#L974-1 assume !(1 == ~T3_E~0); 31987#L979-1 assume !(1 == ~T4_E~0); 31988#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32742#L989-1 assume !(1 == ~T6_E~0); 32780#L994-1 assume !(1 == ~T7_E~0); 32772#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32764#L1004-1 assume !(1 == ~E_M~0); 31093#L1009-1 assume !(1 == ~E_1~0); 31094#L1014-1 assume !(1 == ~E_2~0); 32750#L1019-1 assume !(1 == ~E_3~0); 32719#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 32714#L1029-1 assume !(1 == ~E_5~0); 32288#L1034-1 assume !(1 == ~E_6~0); 32271#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 32262#L1044-1 assume !(1 == ~E_8~0); 32254#L1049-1 assume { :end_inline_reset_delta_events } true; 32247#L1315-2 [2024-11-23 02:54:07,081 INFO L747 eck$LassoCheckResult]: Loop: 32247#L1315-2 assume !false; 32243#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32242#L841-1 assume !false; 32241#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32236#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 32231#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32230#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32228#L724 assume !(0 != eval_~tmp~0#1); 32227#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32226#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32224#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32225#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33137#L871-3 assume !(0 == ~T2_E~0); 33135#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33133#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33131#L886-3 assume !(0 == ~T5_E~0); 33129#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33127#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33125#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33123#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33121#L911-3 assume !(0 == ~E_1~0); 33119#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33117#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33115#L926-3 assume !(0 == ~E_4~0); 33113#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33111#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33109#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33107#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33105#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33103#L430-30 assume 1 == ~m_pc~0; 33100#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33097#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33093#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33089#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33086#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33083#L449-30 assume !(1 == ~t1_pc~0); 33080#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 33078#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33075#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33073#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33071#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33069#L468-30 assume 1 == ~t2_pc~0; 33065#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33061#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33056#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33052#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 33046#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33038#L487-30 assume 1 == ~t3_pc~0; 33033#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33028#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33023#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33018#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33013#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33008#L506-30 assume !(1 == ~t4_pc~0); 33002#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 32997#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32992#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32987#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32983#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32979#L525-30 assume 1 == ~t5_pc~0; 32974#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32969#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32964#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32959#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32955#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32951#L544-30 assume !(1 == ~t6_pc~0); 32946#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 32940#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32933#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32926#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32920#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32914#L563-30 assume 1 == ~t7_pc~0; 32908#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32902#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32895#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32889#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32882#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32876#L582-30 assume !(1 == ~t8_pc~0); 32867#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 32861#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32853#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32846#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32840#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32833#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31102#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32817#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32806#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32797#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32789#L984-3 assume !(1 == ~T5_E~0); 32784#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32775#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32768#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32760#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32753#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32721#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32715#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32710#L1024-3 assume !(1 == ~E_4~0); 32693#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32685#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32680#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32675#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32672#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32668#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 32656#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32651#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 32646#L1334 assume !(0 == start_simulation_~tmp~3#1); 32035#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32637#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 32628#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32287#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 32283#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32270#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32261#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 32253#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 32247#L1315-2 [2024-11-23 02:54:07,081 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:07,081 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2024-11-23 02:54:07,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:07,082 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752264320] [2024-11-23 02:54:07,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:07,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:07,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:07,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:07,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:07,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1752264320] [2024-11-23 02:54:07,132 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1752264320] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:07,132 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:07,132 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:54:07,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203989783] [2024-11-23 02:54:07,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:07,132 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:07,133 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:07,133 INFO L85 PathProgramCache]: Analyzing trace with hash 1868159045, now seen corresponding path program 2 times [2024-11-23 02:54:07,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:07,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609202043] [2024-11-23 02:54:07,133 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:54:07,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:07,145 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:54:07,146 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-23 02:54:07,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:07,191 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:07,192 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [609202043] [2024-11-23 02:54:07,192 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [609202043] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:07,192 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:07,192 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:07,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [468632650] [2024-11-23 02:54:07,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:07,192 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:07,193 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:07,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:07,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:07,193 INFO L87 Difference]: Start difference. First operand 3460 states and 5038 transitions. cyclomatic complexity: 1582 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:07,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:07,288 INFO L93 Difference]: Finished difference Result 6454 states and 9332 transitions. [2024-11-23 02:54:07,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6454 states and 9332 transitions. [2024-11-23 02:54:07,317 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6293 [2024-11-23 02:54:07,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6454 states to 6454 states and 9332 transitions. [2024-11-23 02:54:07,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6454 [2024-11-23 02:54:07,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6454 [2024-11-23 02:54:07,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6454 states and 9332 transitions. [2024-11-23 02:54:07,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:07,358 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6454 states and 9332 transitions. [2024-11-23 02:54:07,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6454 states and 9332 transitions. [2024-11-23 02:54:07,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6454 to 6446. [2024-11-23 02:54:07,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6446 states, 6446 states have (on average 1.4464784362395284) internal successors, (9324), 6445 states have internal predecessors, (9324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:07,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6446 states to 6446 states and 9324 transitions. [2024-11-23 02:54:07,544 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6446 states and 9324 transitions. [2024-11-23 02:54:07,544 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:07,545 INFO L425 stractBuchiCegarLoop]: Abstraction has 6446 states and 9324 transitions. [2024-11-23 02:54:07,545 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-23 02:54:07,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6446 states and 9324 transitions. [2024-11-23 02:54:07,566 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6285 [2024-11-23 02:54:07,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:07,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:07,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:07,568 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:07,568 INFO L745 eck$LassoCheckResult]: Stem: 41208#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 41209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 42005#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42006#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41535#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 41536#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41080#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41081#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41172#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41986#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41046#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41047#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41489#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41522#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41176#L866 assume !(0 == ~M_E~0); 41177#L866-2 assume !(0 == ~T1_E~0); 41738#L871-1 assume !(0 == ~T2_E~0); 41739#L876-1 assume !(0 == ~T3_E~0); 42048#L881-1 assume !(0 == ~T4_E~0); 41753#L886-1 assume !(0 == ~T5_E~0); 41477#L891-1 assume !(0 == ~T6_E~0); 41478#L896-1 assume !(0 == ~T7_E~0); 41746#L901-1 assume !(0 == ~T8_E~0); 41771#L906-1 assume !(0 == ~E_M~0); 41772#L911-1 assume !(0 == ~E_1~0); 41532#L916-1 assume !(0 == ~E_2~0); 41533#L921-1 assume !(0 == ~E_3~0); 41882#L926-1 assume !(0 == ~E_4~0); 42000#L931-1 assume !(0 == ~E_5~0); 42055#L936-1 assume !(0 == ~E_6~0); 42064#L941-1 assume !(0 == ~E_7~0); 41537#L946-1 assume !(0 == ~E_8~0); 41538#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42031#L430 assume !(1 == ~m_pc~0); 41377#L430-2 is_master_triggered_~__retres1~0#1 := 0; 40992#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40993#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41665#L1073 assume !(0 != activate_threads_~tmp~1#1); 41666#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41861#L449 assume !(1 == ~t1_pc~0); 41182#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41183#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41019#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41020#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 41786#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41599#L468 assume !(1 == ~t2_pc~0); 40980#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40979#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41387#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41382#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 40994#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40995#L487 assume 1 == ~t3_pc~0; 42046#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41086#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40976#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40977#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 41456#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41457#L506 assume !(1 == ~t4_pc~0); 41593#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41646#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41072#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41073#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 41586#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41394#L525 assume 1 == ~t5_pc~0; 41322#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41034#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41931#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41932#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 41240#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41241#L544 assume !(1 == ~t6_pc~0); 41395#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41396#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41365#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41014#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 41015#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41971#L563 assume 1 == ~t7_pc~0; 41813#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41038#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41039#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41479#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 41184#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41185#L582 assume 1 == ~t8_pc~0; 41104#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41105#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41867#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41444#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 41326#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41327#L964 assume !(1 == ~M_E~0); 41864#L964-2 assume !(1 == ~T1_E~0); 41242#L969-1 assume !(1 == ~T2_E~0); 41243#L974-1 assume !(1 == ~T3_E~0); 41904#L979-1 assume !(1 == ~T4_E~0); 41905#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45309#L989-1 assume !(1 == ~T6_E~0); 46518#L994-1 assume !(1 == ~T7_E~0); 46516#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46514#L1004-1 assume !(1 == ~E_M~0); 46512#L1009-1 assume !(1 == ~E_1~0); 46510#L1014-1 assume !(1 == ~E_2~0); 46508#L1019-1 assume !(1 == ~E_3~0); 46505#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 41205#L1029-1 assume !(1 == ~E_5~0); 41206#L1034-1 assume !(1 == ~E_6~0); 46331#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46321#L1044-1 assume !(1 == ~E_8~0); 46312#L1049-1 assume { :end_inline_reset_delta_events } true; 46304#L1315-2 [2024-11-23 02:54:07,569 INFO L747 eck$LassoCheckResult]: Loop: 46304#L1315-2 assume !false; 46299#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46297#L841-1 assume !false; 46295#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 46288#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 46282#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 46280#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 46278#L724 assume !(0 != eval_~tmp~0#1); 41878#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41595#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41596#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46955#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47229#L871-3 assume !(0 == ~T2_E~0); 47228#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47227#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47226#L886-3 assume !(0 == ~T5_E~0); 47225#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47224#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47223#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47222#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47221#L911-3 assume !(0 == ~E_1~0); 47220#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47219#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47218#L926-3 assume !(0 == ~E_4~0); 47217#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47216#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47215#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47214#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47213#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47212#L430-30 assume !(1 == ~m_pc~0); 47210#L430-32 is_master_triggered_~__retres1~0#1 := 0; 47208#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47206#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47205#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 47203#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47202#L449-30 assume !(1 == ~t1_pc~0); 47201#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 47200#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47199#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47198#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47197#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47196#L468-30 assume 1 == ~t2_pc~0; 47194#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47193#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47192#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47191#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 47190#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47189#L487-30 assume 1 == ~t3_pc~0; 47187#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47186#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47185#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47184#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47183#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47182#L506-30 assume !(1 == ~t4_pc~0); 47180#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 47179#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47178#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47177#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47176#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47175#L525-30 assume 1 == ~t5_pc~0; 47173#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47172#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47171#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47170#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47169#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47168#L544-30 assume !(1 == ~t6_pc~0); 47166#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 47165#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47164#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47163#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47162#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47161#L563-30 assume 1 == ~t7_pc~0; 47159#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47158#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47157#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47156#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47155#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47154#L582-30 assume !(1 == ~t8_pc~0); 47152#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 47151#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47150#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47149#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47148#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47147#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41025#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47146#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47145#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47144#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41608#L984-3 assume !(1 == ~T5_E~0); 41609#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41210#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41211#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41784#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41062#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41063#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41582#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41583#L1024-3 assume !(1 == ~E_4~0); 41559#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41560#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46970#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41883#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41884#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 46734#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 46712#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 46703#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 46696#L1334 assume !(0 == start_simulation_~tmp~3#1); 41950#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 46682#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 46648#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 46625#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 46354#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46330#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46320#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 46311#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 46304#L1315-2 [2024-11-23 02:54:07,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:07,569 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2024-11-23 02:54:07,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:07,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502564181] [2024-11-23 02:54:07,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:07,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:07,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:07,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:07,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:07,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502564181] [2024-11-23 02:54:07,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [502564181] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:07,619 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:07,620 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:54:07,620 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2001873959] [2024-11-23 02:54:07,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:07,620 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:07,620 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:07,621 INFO L85 PathProgramCache]: Analyzing trace with hash -406865656, now seen corresponding path program 1 times [2024-11-23 02:54:07,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:07,621 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1606403404] [2024-11-23 02:54:07,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:07,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:07,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:07,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:07,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:07,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1606403404] [2024-11-23 02:54:07,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1606403404] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:07,687 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:07,687 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:07,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260174256] [2024-11-23 02:54:07,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:07,688 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:07,688 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:07,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:07,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:07,689 INFO L87 Difference]: Start difference. First operand 6446 states and 9324 transitions. cyclomatic complexity: 2886 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:07,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:07,795 INFO L93 Difference]: Finished difference Result 12382 states and 17784 transitions. [2024-11-23 02:54:07,795 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12382 states and 17784 transitions. [2024-11-23 02:54:07,857 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12206 [2024-11-23 02:54:07,905 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12382 states to 12382 states and 17784 transitions. [2024-11-23 02:54:07,906 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12382 [2024-11-23 02:54:07,920 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12382 [2024-11-23 02:54:07,921 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12382 states and 17784 transitions. [2024-11-23 02:54:07,938 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:07,938 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12382 states and 17784 transitions. [2024-11-23 02:54:07,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12382 states and 17784 transitions. [2024-11-23 02:54:08,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12382 to 12366. [2024-11-23 02:54:08,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12366 states, 12366 states have (on average 1.4368429564936116) internal successors, (17768), 12365 states have internal predecessors, (17768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:08,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12366 states to 12366 states and 17768 transitions. [2024-11-23 02:54:08,350 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12366 states and 17768 transitions. [2024-11-23 02:54:08,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:08,351 INFO L425 stractBuchiCegarLoop]: Abstraction has 12366 states and 17768 transitions. [2024-11-23 02:54:08,351 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-23 02:54:08,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12366 states and 17768 transitions. [2024-11-23 02:54:08,395 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12190 [2024-11-23 02:54:08,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:08,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:08,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:08,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:08,398 INFO L745 eck$LassoCheckResult]: Stem: 60046#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 60047#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 60908#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60909#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60380#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 60381#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59915#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59916#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60008#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60888#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59882#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59883#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60334#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 60367#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60014#L866 assume !(0 == ~M_E~0); 60015#L866-2 assume !(0 == ~T1_E~0); 60602#L871-1 assume !(0 == ~T2_E~0); 60603#L876-1 assume !(0 == ~T3_E~0); 60967#L881-1 assume !(0 == ~T4_E~0); 60617#L886-1 assume !(0 == ~T5_E~0); 60322#L891-1 assume !(0 == ~T6_E~0); 60323#L896-1 assume !(0 == ~T7_E~0); 60610#L901-1 assume !(0 == ~T8_E~0); 60633#L906-1 assume !(0 == ~E_M~0); 60634#L911-1 assume !(0 == ~E_1~0); 60377#L916-1 assume !(0 == ~E_2~0); 60378#L921-1 assume !(0 == ~E_3~0); 60762#L926-1 assume !(0 == ~E_4~0); 60902#L931-1 assume !(0 == ~E_5~0); 60984#L936-1 assume !(0 == ~E_6~0); 60995#L941-1 assume !(0 == ~E_7~0); 60382#L946-1 assume !(0 == ~E_8~0); 60383#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60939#L430 assume !(1 == ~m_pc~0); 60217#L430-2 is_master_triggered_~__retres1~0#1 := 0; 60857#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61040#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 60518#L1073 assume !(0 != activate_threads_~tmp~1#1); 60519#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60738#L449 assume !(1 == ~t1_pc~0); 60020#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 60021#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59856#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 59857#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 60648#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60443#L468 assume !(1 == ~t2_pc~0); 59817#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59816#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60227#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 60222#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 59831#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59832#L487 assume !(1 == ~t3_pc~0); 59950#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59921#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59813#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59814#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 60302#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60303#L506 assume !(1 == ~t4_pc~0); 60438#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 60496#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59907#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59908#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 60432#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60236#L525 assume 1 == ~t5_pc~0; 60162#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59870#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60821#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60822#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 60078#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60079#L544 assume !(1 == ~t6_pc~0); 60237#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 60238#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60205#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59851#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 59852#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60870#L563 assume 1 == ~t7_pc~0; 60682#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59874#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59875#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60324#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 60022#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60023#L582 assume 1 == ~t8_pc~0; 59939#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59940#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60747#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60288#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 60166#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60167#L964 assume !(1 == ~M_E~0); 60743#L964-2 assume !(1 == ~T1_E~0); 63594#L969-1 assume !(1 == ~T2_E~0); 63593#L974-1 assume !(1 == ~T3_E~0); 63592#L979-1 assume !(1 == ~T4_E~0); 63590#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63591#L989-1 assume !(1 == ~T6_E~0); 63651#L994-1 assume !(1 == ~T7_E~0); 63586#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63584#L1004-1 assume !(1 == ~E_M~0); 63582#L1009-1 assume !(1 == ~E_1~0); 63581#L1014-1 assume !(1 == ~E_2~0); 63580#L1019-1 assume !(1 == ~E_3~0); 63532#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 63495#L1029-1 assume !(1 == ~E_5~0); 63493#L1034-1 assume !(1 == ~E_6~0); 63457#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 63425#L1044-1 assume !(1 == ~E_8~0); 63399#L1049-1 assume { :end_inline_reset_delta_events } true; 63375#L1315-2 [2024-11-23 02:54:08,398 INFO L747 eck$LassoCheckResult]: Loop: 63375#L1315-2 assume !false; 63350#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63347#L841-1 assume !false; 63314#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 60073#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 60074#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 60272#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 59826#L724 assume !(0 != eval_~tmp~0#1); 59828#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65187#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65185#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65183#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65181#L871-3 assume !(0 == ~T2_E~0); 65179#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65177#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65174#L886-3 assume !(0 == ~T5_E~0); 65172#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65170#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64982#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64979#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 64977#L911-3 assume !(0 == ~E_1~0); 64975#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64973#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64971#L926-3 assume !(0 == ~E_4~0); 64969#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64966#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 64964#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64962#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 64960#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64958#L430-30 assume !(1 == ~m_pc~0); 64954#L430-32 is_master_triggered_~__retres1~0#1 := 0; 64952#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64950#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 64948#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 64945#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64943#L449-30 assume !(1 == ~t1_pc~0); 64941#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 64939#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64228#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 64226#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64224#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64222#L468-30 assume 1 == ~t2_pc~0; 64219#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64218#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64215#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64213#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 64211#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64031#L487-30 assume !(1 == ~t3_pc~0); 64029#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 64027#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64025#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64023#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64021#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64019#L506-30 assume !(1 == ~t4_pc~0); 64014#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 64012#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64010#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64008#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64005#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64003#L525-30 assume !(1 == ~t5_pc~0); 64000#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 63997#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63995#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63993#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 63991#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63989#L544-30 assume !(1 == ~t6_pc~0); 63984#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 63982#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63980#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63978#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 63976#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63973#L563-30 assume 1 == ~t7_pc~0; 63970#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63968#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63966#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63964#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 63962#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63961#L582-30 assume !(1 == ~t8_pc~0); 63955#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 63953#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63951#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63948#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63946#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63856#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 63784#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63850#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63848#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 63846#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63769#L984-3 assume !(1 == ~T5_E~0); 63767#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 63766#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63764#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63762#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 63760#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 63758#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 63756#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 63719#L1024-3 assume !(1 == ~E_4~0); 63717#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63715#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63713#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63667#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 63664#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 63611#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 63601#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 63599#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 63597#L1334 assume !(0 == start_simulation_~tmp~3#1); 60846#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 63541#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 63496#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 63494#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 63458#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63456#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63424#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 63398#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 63375#L1315-2 [2024-11-23 02:54:08,399 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:08,399 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2024-11-23 02:54:08,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:08,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31708156] [2024-11-23 02:54:08,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:08,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:08,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:08,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:08,452 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:08,452 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31708156] [2024-11-23 02:54:08,452 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [31708156] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:08,452 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:08,452 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:54:08,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [748288619] [2024-11-23 02:54:08,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:08,453 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:08,453 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:08,454 INFO L85 PathProgramCache]: Analyzing trace with hash 622499978, now seen corresponding path program 1 times [2024-11-23 02:54:08,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:08,454 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121196154] [2024-11-23 02:54:08,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:08,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:08,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:08,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:08,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:08,513 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2121196154] [2024-11-23 02:54:08,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2121196154] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:08,514 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:08,514 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:08,514 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623995485] [2024-11-23 02:54:08,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:08,514 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:08,515 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:08,515 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:08,515 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:08,515 INFO L87 Difference]: Start difference. First operand 12366 states and 17768 transitions. cyclomatic complexity: 5418 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:08,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:08,828 INFO L93 Difference]: Finished difference Result 23363 states and 33403 transitions. [2024-11-23 02:54:08,828 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23363 states and 33403 transitions. [2024-11-23 02:54:08,931 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23132 [2024-11-23 02:54:09,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23363 states to 23363 states and 33403 transitions. [2024-11-23 02:54:09,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23363 [2024-11-23 02:54:09,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23363 [2024-11-23 02:54:09,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23363 states and 33403 transitions. [2024-11-23 02:54:09,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:09,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23363 states and 33403 transitions. [2024-11-23 02:54:09,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23363 states and 33403 transitions. [2024-11-23 02:54:09,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23363 to 23331. [2024-11-23 02:54:09,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23331 states, 23331 states have (on average 1.4303287471604302) internal successors, (33371), 23330 states have internal predecessors, (33371), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:09,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23331 states to 23331 states and 33371 transitions. [2024-11-23 02:54:09,618 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23331 states and 33371 transitions. [2024-11-23 02:54:09,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:09,619 INFO L425 stractBuchiCegarLoop]: Abstraction has 23331 states and 33371 transitions. [2024-11-23 02:54:09,619 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-23 02:54:09,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23331 states and 33371 transitions. [2024-11-23 02:54:09,710 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23100 [2024-11-23 02:54:09,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:09,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:09,712 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:09,713 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:09,713 INFO L745 eck$LassoCheckResult]: Stem: 95783#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 95784#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 96598#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96599#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96105#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 96106#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95652#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95653#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95744#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96581#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95621#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95622#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96059#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96092#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95750#L866 assume !(0 == ~M_E~0); 95751#L866-2 assume !(0 == ~T1_E~0); 96313#L871-1 assume !(0 == ~T2_E~0); 96314#L876-1 assume !(0 == ~T3_E~0); 96656#L881-1 assume !(0 == ~T4_E~0); 96330#L886-1 assume !(0 == ~T5_E~0); 96048#L891-1 assume !(0 == ~T6_E~0); 96049#L896-1 assume !(0 == ~T7_E~0); 96321#L901-1 assume !(0 == ~T8_E~0); 96345#L906-1 assume !(0 == ~E_M~0); 96346#L911-1 assume !(0 == ~E_1~0); 96102#L916-1 assume !(0 == ~E_2~0); 96103#L921-1 assume !(0 == ~E_3~0); 96465#L926-1 assume !(0 == ~E_4~0); 96595#L931-1 assume !(0 == ~E_5~0); 96664#L936-1 assume !(0 == ~E_6~0); 96674#L941-1 assume !(0 == ~E_7~0); 96107#L946-1 assume !(0 == ~E_8~0); 96108#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96629#L430 assume !(1 == ~m_pc~0); 95947#L430-2 is_master_triggered_~__retres1~0#1 := 0; 96556#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96701#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96238#L1073 assume !(0 != activate_threads_~tmp~1#1); 96239#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96440#L449 assume !(1 == ~t1_pc~0); 95756#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95757#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95594#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 95595#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 96360#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96170#L468 assume !(1 == ~t2_pc~0); 95555#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95554#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95957#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95952#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 95569#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95570#L487 assume !(1 == ~t3_pc~0); 95687#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95658#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95551#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95552#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 96028#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96029#L506 assume !(1 == ~t4_pc~0); 96163#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 96223#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95644#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95645#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 96154#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95964#L525 assume !(1 == ~t5_pc~0); 95606#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 95607#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96520#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96521#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 95817#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95818#L544 assume !(1 == ~t6_pc~0); 95965#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95966#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95937#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95589#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 95590#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96571#L563 assume 1 == ~t7_pc~0; 96391#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95611#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95612#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96050#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 95758#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95759#L582 assume 1 == ~t8_pc~0; 95676#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 95677#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96449#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96015#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 95899#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95900#L964 assume !(1 == ~M_E~0); 96444#L964-2 assume !(1 == ~T1_E~0); 109236#L969-1 assume !(1 == ~T2_E~0); 96603#L974-1 assume !(1 == ~T3_E~0); 96485#L979-1 assume !(1 == ~T4_E~0); 96486#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 95971#L989-1 assume !(1 == ~T6_E~0); 95972#L994-1 assume !(1 == ~T7_E~0); 95849#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 95850#L1004-1 assume !(1 == ~E_M~0); 95591#L1009-1 assume !(1 == ~E_1~0); 95592#L1014-1 assume !(1 == ~E_2~0); 95839#L1019-1 assume !(1 == ~E_3~0); 96430#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 109172#L1029-1 assume !(1 == ~E_5~0); 109168#L1034-1 assume !(1 == ~E_6~0); 107096#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 107094#L1044-1 assume !(1 == ~E_8~0); 107092#L1049-1 assume { :end_inline_reset_delta_events } true; 105354#L1315-2 [2024-11-23 02:54:09,713 INFO L747 eck$LassoCheckResult]: Loop: 105354#L1315-2 assume !false; 103796#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103794#L841-1 assume !false; 103792#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 103727#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 103721#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 103719#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 103716#L724 assume !(0 != eval_~tmp~0#1); 103717#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103362#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 103363#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 118247#L871-3 assume !(0 == ~T2_E~0); 117927#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117708#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117706#L886-3 assume !(0 == ~T5_E~0); 117704#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117703#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 117701#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 117699#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 117697#L911-3 assume !(0 == ~E_1~0); 117696#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 117692#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117690#L926-3 assume !(0 == ~E_4~0); 117688#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117686#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 117683#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 117681#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 117679#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117677#L430-30 assume !(1 == ~m_pc~0); 117675#L430-32 is_master_triggered_~__retres1~0#1 := 0; 117667#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117664#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 117662#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 117659#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117657#L449-30 assume !(1 == ~t1_pc~0); 117654#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 117651#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117649#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 117647#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 116615#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116614#L468-30 assume 1 == ~t2_pc~0; 116611#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 116609#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116607#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 116605#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 116603#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116601#L487-30 assume !(1 == ~t3_pc~0); 116598#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 116596#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116594#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 116592#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 116590#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116588#L506-30 assume 1 == ~t4_pc~0; 116585#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 116582#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116581#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 116580#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 116579#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 116578#L525-30 assume !(1 == ~t5_pc~0); 116577#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 116576#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116575#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 116574#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 116573#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116572#L544-30 assume 1 == ~t6_pc~0; 116571#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 116569#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116567#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 116565#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 116563#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 116561#L563-30 assume !(1 == ~t7_pc~0); 116559#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 116555#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 116553#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 116551#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 116549#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 116547#L582-30 assume 1 == ~t8_pc~0; 116545#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 116541#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 116539#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 116537#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 116535#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116533#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 103028#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116529#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116528#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 116527#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116493#L984-3 assume !(1 == ~T5_E~0); 116491#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 116488#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 116486#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 116484#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 116482#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 116480#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116478#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 109218#L1024-3 assume !(1 == ~E_4~0); 109216#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 109214#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 109212#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 109210#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 109208#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 107128#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 107118#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 107116#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 107113#L1334 assume !(0 == start_simulation_~tmp~3#1); 107112#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 107109#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 107102#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 107101#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 107100#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 107099#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 107098#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 107091#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 105354#L1315-2 [2024-11-23 02:54:09,714 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:09,714 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2024-11-23 02:54:09,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:09,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049303445] [2024-11-23 02:54:09,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:09,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:09,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:09,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:09,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:09,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1049303445] [2024-11-23 02:54:09,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1049303445] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:09,897 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:09,897 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:09,897 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [859241851] [2024-11-23 02:54:09,897 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:09,897 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:09,897 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:09,898 INFO L85 PathProgramCache]: Analyzing trace with hash -1100965176, now seen corresponding path program 1 times [2024-11-23 02:54:09,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:09,898 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985484790] [2024-11-23 02:54:09,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:09,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:09,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:09,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:09,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:09,955 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [985484790] [2024-11-23 02:54:09,956 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [985484790] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:09,956 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:09,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:09,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1625973000] [2024-11-23 02:54:09,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:09,956 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:09,957 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:09,957 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:54:09,957 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:54:09,958 INFO L87 Difference]: Start difference. First operand 23331 states and 33371 transitions. cyclomatic complexity: 10072 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:10,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:10,477 INFO L93 Difference]: Finished difference Result 54594 states and 77544 transitions. [2024-11-23 02:54:10,477 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54594 states and 77544 transitions. [2024-11-23 02:54:10,732 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 54140 [2024-11-23 02:54:11,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54594 states to 54594 states and 77544 transitions. [2024-11-23 02:54:11,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54594 [2024-11-23 02:54:11,107 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54594 [2024-11-23 02:54:11,107 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54594 states and 77544 transitions. [2024-11-23 02:54:11,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:11,178 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54594 states and 77544 transitions. [2024-11-23 02:54:11,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54594 states and 77544 transitions. [2024-11-23 02:54:11,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54594 to 44046. [2024-11-23 02:54:11,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44046 states, 44046 states have (on average 1.424783181219634) internal successors, (62756), 44045 states have internal predecessors, (62756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:11,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44046 states to 44046 states and 62756 transitions. [2024-11-23 02:54:11,946 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44046 states and 62756 transitions. [2024-11-23 02:54:11,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:54:11,947 INFO L425 stractBuchiCegarLoop]: Abstraction has 44046 states and 62756 transitions. [2024-11-23 02:54:11,948 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-23 02:54:11,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44046 states and 62756 transitions. [2024-11-23 02:54:12,272 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43736 [2024-11-23 02:54:12,272 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:12,272 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:12,274 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:12,274 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:12,275 INFO L745 eck$LassoCheckResult]: Stem: 173716#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 173717#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 174538#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174539#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 174042#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 174043#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 173587#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 173588#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 173678#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174521#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 173555#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 173556#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 174000#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 174029#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 173685#L866 assume !(0 == ~M_E~0); 173686#L866-2 assume !(0 == ~T1_E~0); 174240#L871-1 assume !(0 == ~T2_E~0); 174241#L876-1 assume !(0 == ~T3_E~0); 174584#L881-1 assume !(0 == ~T4_E~0); 174256#L886-1 assume !(0 == ~T5_E~0); 173987#L891-1 assume !(0 == ~T6_E~0); 173988#L896-1 assume !(0 == ~T7_E~0); 174248#L901-1 assume !(0 == ~T8_E~0); 174276#L906-1 assume !(0 == ~E_M~0); 174277#L911-1 assume !(0 == ~E_1~0); 174039#L916-1 assume !(0 == ~E_2~0); 174040#L921-1 assume !(0 == ~E_3~0); 174397#L926-1 assume !(0 == ~E_4~0); 174535#L931-1 assume !(0 == ~E_5~0); 174592#L936-1 assume !(0 == ~E_6~0); 174603#L941-1 assume !(0 == ~E_7~0); 174045#L946-1 assume !(0 == ~E_8~0); 174046#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174565#L430 assume !(1 == ~m_pc~0); 173887#L430-2 is_master_triggered_~__retres1~0#1 := 0; 174502#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174637#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 174169#L1073 assume !(0 != activate_threads_~tmp~1#1); 174170#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174372#L449 assume !(1 == ~t1_pc~0); 173690#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 173691#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 173534#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 173535#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 174293#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174106#L468 assume !(1 == ~t2_pc~0); 173490#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 173489#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 173894#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 173890#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 173506#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173507#L487 assume !(1 == ~t3_pc~0); 173620#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 173591#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 173486#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 173487#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 173967#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 173968#L506 assume !(1 == ~t4_pc~0); 174097#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 174154#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 173577#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 173578#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 174094#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 173900#L525 assume !(1 == ~t5_pc~0); 173541#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 173542#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 174458#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 174459#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 173748#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 173749#L544 assume !(1 == ~t6_pc~0); 173901#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 173902#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 173874#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 173524#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 173525#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 174512#L563 assume !(1 == ~t7_pc~0); 174307#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 173546#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 173547#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 173994#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 173694#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 173695#L582 assume 1 == ~t8_pc~0; 173609#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 173610#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 174380#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 173955#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 173835#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 173836#L964 assume !(1 == ~M_E~0); 174377#L964-2 assume !(1 == ~T1_E~0); 173750#L969-1 assume !(1 == ~T2_E~0); 173751#L974-1 assume !(1 == ~T3_E~0); 174421#L979-1 assume !(1 == ~T4_E~0); 174422#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 173907#L989-1 assume !(1 == ~T6_E~0); 173908#L994-1 assume !(1 == ~T7_E~0); 173788#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 173789#L1004-1 assume !(1 == ~E_M~0); 173527#L1009-1 assume !(1 == ~E_1~0); 173528#L1014-1 assume !(1 == ~E_2~0); 174360#L1019-1 assume !(1 == ~E_3~0); 174361#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 173713#L1029-1 assume !(1 == ~E_5~0); 173714#L1034-1 assume !(1 == ~E_6~0); 174634#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 174635#L1044-1 assume !(1 == ~E_8~0); 174010#L1049-1 assume { :end_inline_reset_delta_events } true; 174011#L1315-2 [2024-11-23 02:54:12,275 INFO L747 eck$LassoCheckResult]: Loop: 174011#L1315-2 assume !false; 212485#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 212481#L841-1 assume !false; 212479#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 212381#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 212294#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 212284#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 210512#L724 assume !(0 != eval_~tmp~0#1); 210513#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 216733#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 216729#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 216727#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 216725#L871-3 assume !(0 == ~T2_E~0); 216723#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 216720#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 216718#L886-3 assume !(0 == ~T5_E~0); 216716#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 216715#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 216714#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 216712#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 216710#L911-3 assume !(0 == ~E_1~0); 216709#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 216708#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 216707#L926-3 assume !(0 == ~E_4~0); 216706#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 216705#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 216617#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 216504#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 216499#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216495#L430-30 assume 1 == ~m_pc~0; 216491#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 216486#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 216482#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 216413#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 216411#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216409#L449-30 assume !(1 == ~t1_pc~0); 216406#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 216404#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216402#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 216400#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 216392#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216387#L468-30 assume !(1 == ~t2_pc~0); 216381#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 216375#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216370#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 216359#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 216357#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216355#L487-30 assume !(1 == ~t3_pc~0); 216352#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 216350#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216348#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 216345#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 216343#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216341#L506-30 assume 1 == ~t4_pc~0; 216337#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 174012#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 174013#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 174434#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 173895#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 173896#L525-30 assume !(1 == ~t5_pc~0); 216153#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 216152#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216151#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 216148#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 216146#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 216145#L544-30 assume !(1 == ~t6_pc~0); 216131#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 216130#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 216129#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 216128#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 216127#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 216124#L563-30 assume !(1 == ~t7_pc~0); 183858#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 216123#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 174330#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 173998#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 173999#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 174469#L582-30 assume !(1 == ~t8_pc~0); 173734#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 173735#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 173985#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 174633#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 174608#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 173532#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 173533#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 173672#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 173661#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 173662#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 174111#L984-3 assume !(1 == ~T5_E~0); 174112#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 173718#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 173719#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 174289#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 173570#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 173571#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 174087#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 174088#L1024-3 assume !(1 == ~E_4~0); 174066#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 174034#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 174035#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 174357#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 174396#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 212679#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 212669#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 212667#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 212664#L1334 assume !(0 == start_simulation_~tmp~3#1); 212663#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 212659#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 212652#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 212651#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 212650#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 212646#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 212644#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 212642#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 174011#L1315-2 [2024-11-23 02:54:12,275 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:12,275 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2024-11-23 02:54:12,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:12,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667517696] [2024-11-23 02:54:12,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:12,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:12,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:12,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:12,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:12,339 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667517696] [2024-11-23 02:54:12,339 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667517696] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:12,339 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:12,339 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:54:12,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562038356] [2024-11-23 02:54:12,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:12,340 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:12,340 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:12,340 INFO L85 PathProgramCache]: Analyzing trace with hash 1604543560, now seen corresponding path program 1 times [2024-11-23 02:54:12,340 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:12,340 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [110671676] [2024-11-23 02:54:12,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:12,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:12,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:12,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:12,383 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:12,383 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [110671676] [2024-11-23 02:54:12,383 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [110671676] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:12,383 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:12,383 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:12,384 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000001150] [2024-11-23 02:54:12,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:12,384 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:12,384 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:12,384 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:12,385 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:12,385 INFO L87 Difference]: Start difference. First operand 44046 states and 62756 transitions. cyclomatic complexity: 18742 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:12,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:12,904 INFO L93 Difference]: Finished difference Result 83205 states and 118105 transitions. [2024-11-23 02:54:12,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83205 states and 118105 transitions. [2024-11-23 02:54:13,393 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 82608 [2024-11-23 02:54:13,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83205 states to 83205 states and 118105 transitions. [2024-11-23 02:54:13,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83205 [2024-11-23 02:54:13,733 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83205 [2024-11-23 02:54:13,734 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83205 states and 118105 transitions. [2024-11-23 02:54:13,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:13,984 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83205 states and 118105 transitions. [2024-11-23 02:54:14,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83205 states and 118105 transitions. [2024-11-23 02:54:14,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83205 to 83077. [2024-11-23 02:54:15,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83077 states, 83077 states have (on average 1.4200922036183299) internal successors, (117977), 83076 states have internal predecessors, (117977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:15,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83077 states to 83077 states and 117977 transitions. [2024-11-23 02:54:15,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 83077 states and 117977 transitions. [2024-11-23 02:54:15,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:15,311 INFO L425 stractBuchiCegarLoop]: Abstraction has 83077 states and 117977 transitions. [2024-11-23 02:54:15,311 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-23 02:54:15,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83077 states and 117977 transitions. [2024-11-23 02:54:15,764 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 82480 [2024-11-23 02:54:15,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:15,765 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:15,767 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:15,767 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:15,767 INFO L745 eck$LassoCheckResult]: Stem: 300969#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 300970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 301797#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 301798#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 301294#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 301295#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 300846#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 300847#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 300933#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 301776#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 300813#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 300814#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 301248#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 301280#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 300938#L866 assume !(0 == ~M_E~0); 300939#L866-2 assume !(0 == ~T1_E~0); 301500#L871-1 assume !(0 == ~T2_E~0); 301501#L876-1 assume !(0 == ~T3_E~0); 301855#L881-1 assume !(0 == ~T4_E~0); 301517#L886-1 assume !(0 == ~T5_E~0); 301235#L891-1 assume !(0 == ~T6_E~0); 301236#L896-1 assume !(0 == ~T7_E~0); 301509#L901-1 assume !(0 == ~T8_E~0); 301537#L906-1 assume !(0 == ~E_M~0); 301538#L911-1 assume !(0 == ~E_1~0); 301291#L916-1 assume !(0 == ~E_2~0); 301292#L921-1 assume !(0 == ~E_3~0); 301657#L926-1 assume !(0 == ~E_4~0); 301794#L931-1 assume !(0 == ~E_5~0); 301867#L936-1 assume !(0 == ~E_6~0); 301880#L941-1 assume !(0 == ~E_7~0); 301297#L946-1 assume !(0 == ~E_8~0); 301298#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 301823#L430 assume !(1 == ~m_pc~0); 301132#L430-2 is_master_triggered_~__retres1~0#1 := 0; 301751#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 301923#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 301429#L1073 assume !(0 != activate_threads_~tmp~1#1); 301430#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 301633#L449 assume !(1 == ~t1_pc~0); 300943#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 300944#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 300792#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 300793#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 301551#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 301362#L468 assume !(1 == ~t2_pc~0); 300748#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 300747#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 301139#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 301135#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 300764#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 300765#L487 assume !(1 == ~t3_pc~0); 300876#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 300850#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 300744#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 300745#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 301211#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 301212#L506 assume !(1 == ~t4_pc~0); 301355#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 301412#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 300836#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 300837#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 301348#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 301145#L525 assume !(1 == ~t5_pc~0); 300800#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 300801#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 301712#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 301713#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 301003#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 301004#L544 assume !(1 == ~t6_pc~0); 301146#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 301147#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 301116#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 300782#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 300783#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 301763#L563 assume !(1 == ~t7_pc~0); 301563#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 300805#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 300806#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 301242#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 300947#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 300948#L582 assume !(1 == ~t8_pc~0); 301566#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 301846#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 301641#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 301198#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 301080#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 301081#L964 assume !(1 == ~M_E~0); 301638#L964-2 assume !(1 == ~T1_E~0); 301842#L969-1 assume !(1 == ~T2_E~0); 301804#L974-1 assume !(1 == ~T3_E~0); 301805#L979-1 assume !(1 == ~T4_E~0); 305798#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 305796#L989-1 assume !(1 == ~T6_E~0); 305657#L994-1 assume !(1 == ~T7_E~0); 305655#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 305653#L1004-1 assume !(1 == ~E_M~0); 305652#L1009-1 assume !(1 == ~E_1~0); 305651#L1014-1 assume !(1 == ~E_2~0); 305649#L1019-1 assume !(1 == ~E_3~0); 305645#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 305644#L1029-1 assume !(1 == ~E_5~0); 305643#L1034-1 assume !(1 == ~E_6~0); 305642#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 305641#L1044-1 assume !(1 == ~E_8~0); 305640#L1049-1 assume { :end_inline_reset_delta_events } true; 305638#L1315-2 [2024-11-23 02:54:15,768 INFO L747 eck$LassoCheckResult]: Loop: 305638#L1315-2 assume !false; 305631#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 305629#L841-1 assume !false; 305627#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 305508#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 305499#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 305493#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 305483#L724 assume !(0 != eval_~tmp~0#1); 305484#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 307350#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 307348#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 307346#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 307344#L871-3 assume !(0 == ~T2_E~0); 307342#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 307340#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 307338#L886-3 assume !(0 == ~T5_E~0); 307336#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 307334#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 307331#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 307329#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 307327#L911-3 assume !(0 == ~E_1~0); 307325#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 307323#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 307321#L926-3 assume !(0 == ~E_4~0); 307319#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 307317#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 307316#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 307301#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 307294#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 307288#L430-30 assume 1 == ~m_pc~0; 307280#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 307271#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 307108#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 307102#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 307100#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 307098#L449-30 assume !(1 == ~t1_pc~0); 307094#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 307092#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 307090#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 307088#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 307086#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 307084#L468-30 assume 1 == ~t2_pc~0; 307081#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 307079#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 307077#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 307075#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 307073#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 307071#L487-30 assume !(1 == ~t3_pc~0); 307070#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 307069#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 307065#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 307063#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 307061#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 307060#L506-30 assume !(1 == ~t4_pc~0); 307058#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 307057#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 307055#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 307053#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 307051#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 307049#L525-30 assume !(1 == ~t5_pc~0); 307047#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 307045#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 307044#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 307027#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 307019#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 306975#L544-30 assume !(1 == ~t6_pc~0); 306964#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 306957#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 306567#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 306564#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 306562#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 306560#L563-30 assume !(1 == ~t7_pc~0); 305257#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 306557#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 306555#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 306553#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 306551#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 306549#L582-30 assume !(1 == ~t8_pc~0); 306547#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 306545#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 306543#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 306505#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 306493#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306484#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 306033#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 306027#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 306011#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 305996#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 305984#L984-3 assume !(1 == ~T5_E~0); 305975#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 305967#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 305959#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 305951#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 305943#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 305936#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 305911#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 305901#L1024-3 assume !(1 == ~E_4~0); 305893#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 305887#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 305880#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 305874#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 305808#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 305807#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 305797#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 305795#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 305712#L1334 assume !(0 == start_simulation_~tmp~3#1); 305710#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 305704#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 305696#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 305694#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 305692#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 305690#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 305688#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 305639#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 305638#L1315-2 [2024-11-23 02:54:15,768 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:15,768 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2024-11-23 02:54:15,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:15,769 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999602606] [2024-11-23 02:54:15,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:15,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:15,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:15,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:15,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:15,830 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [999602606] [2024-11-23 02:54:15,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [999602606] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:15,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:15,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:15,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343708684] [2024-11-23 02:54:15,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:15,831 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:15,831 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:15,831 INFO L85 PathProgramCache]: Analyzing trace with hash 501087688, now seen corresponding path program 1 times [2024-11-23 02:54:15,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:15,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753567642] [2024-11-23 02:54:15,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:15,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:15,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:15,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:15,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:15,888 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753567642] [2024-11-23 02:54:15,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753567642] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:15,888 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:15,888 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:15,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1149684099] [2024-11-23 02:54:15,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:15,889 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:15,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:15,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:54:15,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:54:15,890 INFO L87 Difference]: Start difference. First operand 83077 states and 117977 transitions. cyclomatic complexity: 34964 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:16,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:16,443 INFO L93 Difference]: Finished difference Result 63510 states and 89995 transitions. [2024-11-23 02:54:16,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63510 states and 89995 transitions. [2024-11-23 02:54:16,696 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 63056 [2024-11-23 02:54:16,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63510 states to 63510 states and 89995 transitions. [2024-11-23 02:54:16,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63510 [2024-11-23 02:54:16,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63510 [2024-11-23 02:54:16,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63510 states and 89995 transitions. [2024-11-23 02:54:16,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:16,982 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63510 states and 89995 transitions. [2024-11-23 02:54:17,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63510 states and 89995 transitions. [2024-11-23 02:54:17,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63510 to 43969. [2024-11-23 02:54:17,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43969 states, 43969 states have (on average 1.4174077190748027) internal successors, (62322), 43968 states have internal predecessors, (62322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:17,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43969 states to 43969 states and 62322 transitions. [2024-11-23 02:54:17,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43969 states and 62322 transitions. [2024-11-23 02:54:17,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:54:17,956 INFO L425 stractBuchiCegarLoop]: Abstraction has 43969 states and 62322 transitions. [2024-11-23 02:54:17,956 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-23 02:54:17,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43969 states and 62322 transitions. [2024-11-23 02:54:18,089 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43632 [2024-11-23 02:54:18,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:18,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:18,091 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:18,091 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:18,091 INFO L745 eck$LassoCheckResult]: Stem: 447570#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 447571#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 448376#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 448377#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 447893#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 447894#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 447444#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 447445#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 447531#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 448354#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 447412#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 447413#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 447849#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 447880#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 447538#L866 assume !(0 == ~M_E~0); 447539#L866-2 assume !(0 == ~T1_E~0); 448096#L871-1 assume !(0 == ~T2_E~0); 448097#L876-1 assume !(0 == ~T3_E~0); 448426#L881-1 assume !(0 == ~T4_E~0); 448112#L886-1 assume !(0 == ~T5_E~0); 447836#L891-1 assume !(0 == ~T6_E~0); 447837#L896-1 assume !(0 == ~T7_E~0); 448105#L901-1 assume !(0 == ~T8_E~0); 448130#L906-1 assume !(0 == ~E_M~0); 448131#L911-1 assume !(0 == ~E_1~0); 447890#L916-1 assume !(0 == ~E_2~0); 447891#L921-1 assume !(0 == ~E_3~0); 448237#L926-1 assume !(0 == ~E_4~0); 448373#L931-1 assume !(0 == ~E_5~0); 448434#L936-1 assume !(0 == ~E_6~0); 448441#L941-1 assume !(0 == ~E_7~0); 447896#L946-1 assume !(0 == ~E_8~0); 447897#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 448406#L430 assume !(1 == ~m_pc~0); 447735#L430-2 is_master_triggered_~__retres1~0#1 := 0; 447361#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 447362#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 448024#L1073 assume !(0 != activate_threads_~tmp~1#1); 448025#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 448213#L449 assume !(1 == ~t1_pc~0); 447544#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 447545#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 447392#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 447393#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 448144#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 447961#L468 assume !(1 == ~t2_pc~0); 447347#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 447346#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 447742#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 447738#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 447363#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 447364#L487 assume !(1 == ~t3_pc~0); 447474#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 447448#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 447343#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 447344#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 447813#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 447814#L506 assume !(1 == ~t4_pc~0); 447951#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 448007#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 447434#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 447435#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 447946#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 447748#L525 assume !(1 == ~t5_pc~0); 447399#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 447400#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 448288#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 448289#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 447602#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 447603#L544 assume !(1 == ~t6_pc~0); 447749#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 447750#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 447719#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 447381#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 447382#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 448342#L563 assume !(1 == ~t7_pc~0); 448158#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 447404#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 447405#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 447843#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 447548#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 447549#L582 assume !(1 == ~t8_pc~0); 448161#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 448418#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 448222#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 447802#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 447682#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 447683#L964 assume !(1 == ~M_E~0); 448219#L964-2 assume !(1 == ~T1_E~0); 447604#L969-1 assume !(1 == ~T2_E~0); 447605#L974-1 assume !(1 == ~T3_E~0); 448260#L979-1 assume !(1 == ~T4_E~0); 448261#L984-1 assume !(1 == ~T5_E~0); 447755#L989-1 assume !(1 == ~T6_E~0); 447756#L994-1 assume !(1 == ~T7_E~0); 447638#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 447639#L1004-1 assume !(1 == ~E_M~0); 447385#L1009-1 assume !(1 == ~E_1~0); 447386#L1014-1 assume !(1 == ~E_2~0); 447627#L1019-1 assume !(1 == ~E_3~0); 448206#L1024-1 assume !(1 == ~E_4~0); 447567#L1029-1 assume !(1 == ~E_5~0); 447568#L1034-1 assume !(1 == ~E_6~0); 447650#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 448393#L1044-1 assume !(1 == ~E_8~0); 447860#L1049-1 assume { :end_inline_reset_delta_events } true; 447861#L1315-2 [2024-11-23 02:54:18,092 INFO L747 eck$LassoCheckResult]: Loop: 447861#L1315-2 assume !false; 460906#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 460904#L841-1 assume !false; 460902#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 460886#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 460880#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 460878#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 460875#L724 assume !(0 != eval_~tmp~0#1); 460876#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 461985#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 461981#L866-3 assume !(0 == ~M_E~0); 461979#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 461977#L871-3 assume !(0 == ~T2_E~0); 461975#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 461972#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 461970#L886-3 assume !(0 == ~T5_E~0); 461968#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 461966#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 461964#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 461962#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 461960#L911-3 assume !(0 == ~E_1~0); 461959#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 461953#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 461951#L926-3 assume !(0 == ~E_4~0); 461949#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 461945#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 461943#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 461941#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 461939#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 461936#L430-30 assume !(1 == ~m_pc~0); 461934#L430-32 is_master_triggered_~__retres1~0#1 := 0; 462101#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 462099#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 461926#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 461923#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 461921#L449-30 assume !(1 == ~t1_pc~0); 461919#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 461916#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 461914#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 461912#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 461910#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 461908#L468-30 assume !(1 == ~t2_pc~0); 461885#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 461876#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 461868#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 461862#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 461856#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 461850#L487-30 assume !(1 == ~t3_pc~0); 461843#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 461835#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 461828#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 461821#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 461814#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 461806#L506-30 assume 1 == ~t4_pc~0; 461798#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 461788#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 461780#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 461772#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 461764#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 461757#L525-30 assume !(1 == ~t5_pc~0); 461750#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 461742#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 461735#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 461728#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 461721#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 461713#L544-30 assume 1 == ~t6_pc~0; 461706#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 461696#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 461689#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 461673#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 461672#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 458704#L563-30 assume !(1 == ~t7_pc~0); 458702#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 458460#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 458450#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 458448#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 458446#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 458443#L582-30 assume !(1 == ~t8_pc~0); 458441#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 458439#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 458437#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 458435#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 458433#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 458431#L964-3 assume !(1 == ~M_E~0); 458429#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 458427#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 458425#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 458423#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 458421#L984-3 assume !(1 == ~T5_E~0); 458419#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 458417#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 458415#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 458413#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 458411#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 458409#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 458407#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 458405#L1024-3 assume !(1 == ~E_4~0); 458403#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 458401#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 458400#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 458384#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 458380#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 458378#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 458368#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 458120#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 453655#L1334 assume !(0 == start_simulation_~tmp~3#1); 453656#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 461087#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 461079#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 461077#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 461074#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 461072#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 461070#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 461068#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 447861#L1315-2 [2024-11-23 02:54:18,092 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:18,092 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2024-11-23 02:54:18,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:18,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108030959] [2024-11-23 02:54:18,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:18,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:18,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:18,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:18,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:18,151 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [108030959] [2024-11-23 02:54:18,151 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [108030959] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:18,151 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:18,151 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:18,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1325992168] [2024-11-23 02:54:18,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:18,152 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:18,152 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:18,152 INFO L85 PathProgramCache]: Analyzing trace with hash -47790582, now seen corresponding path program 1 times [2024-11-23 02:54:18,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:18,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657779374] [2024-11-23 02:54:18,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:18,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:18,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:18,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:18,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:18,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [657779374] [2024-11-23 02:54:18,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [657779374] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:18,186 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:18,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:18,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063658632] [2024-11-23 02:54:18,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:18,187 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:18,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:18,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:54:18,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:54:18,187 INFO L87 Difference]: Start difference. First operand 43969 states and 62322 transitions. cyclomatic complexity: 18385 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:18,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:18,438 INFO L93 Difference]: Finished difference Result 69931 states and 99092 transitions. [2024-11-23 02:54:18,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69931 states and 99092 transitions. [2024-11-23 02:54:19,117 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 69392 [2024-11-23 02:54:19,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69931 states to 69931 states and 99092 transitions. [2024-11-23 02:54:19,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69931 [2024-11-23 02:54:19,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69931 [2024-11-23 02:54:19,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69931 states and 99092 transitions. [2024-11-23 02:54:19,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:19,416 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69931 states and 99092 transitions. [2024-11-23 02:54:19,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69931 states and 99092 transitions. [2024-11-23 02:54:19,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69931 to 49329. [2024-11-23 02:54:19,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49329 states, 49329 states have (on average 1.419388189503132) internal successors, (70017), 49328 states have internal predecessors, (70017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:20,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49329 states to 49329 states and 70017 transitions. [2024-11-23 02:54:20,431 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49329 states and 70017 transitions. [2024-11-23 02:54:20,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:54:20,436 INFO L425 stractBuchiCegarLoop]: Abstraction has 49329 states and 70017 transitions. [2024-11-23 02:54:20,436 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-23 02:54:20,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49329 states and 70017 transitions. [2024-11-23 02:54:20,548 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48912 [2024-11-23 02:54:20,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:20,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:20,550 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:20,550 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:20,550 INFO L745 eck$LassoCheckResult]: Stem: 561480#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 561481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 562302#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 562303#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 561807#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 561808#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 561353#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 561354#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 561442#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 562284#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 561321#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 561322#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 561764#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 561794#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 561449#L866 assume !(0 == ~M_E~0); 561450#L866-2 assume !(0 == ~T1_E~0); 562012#L871-1 assume !(0 == ~T2_E~0); 562013#L876-1 assume !(0 == ~T3_E~0); 562357#L881-1 assume !(0 == ~T4_E~0); 562028#L886-1 assume !(0 == ~T5_E~0); 561751#L891-1 assume !(0 == ~T6_E~0); 561752#L896-1 assume !(0 == ~T7_E~0); 562020#L901-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 562159#L906-1 assume !(0 == ~E_M~0); 562363#L911-1 assume !(0 == ~E_1~0); 562364#L916-1 assume !(0 == ~E_2~0); 562162#L921-1 assume !(0 == ~E_3~0); 562163#L926-1 assume !(0 == ~E_4~0); 562366#L931-1 assume !(0 == ~E_5~0); 562367#L936-1 assume !(0 == ~E_6~0); 562446#L941-1 assume !(0 == ~E_7~0); 561810#L946-1 assume !(0 == ~E_8~0); 561811#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 562379#L430 assume !(1 == ~m_pc~0); 562380#L430-2 is_master_triggered_~__retres1~0#1 := 0; 562443#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 562444#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 561940#L1073 assume !(0 != activate_threads_~tmp~1#1); 561941#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 562138#L449 assume !(1 == ~t1_pc~0); 562139#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 562344#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 562345#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 562382#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 562062#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 562063#L468 assume !(1 == ~t2_pc~0); 561257#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 561256#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 561658#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 561659#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 561273#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 561274#L487 assume !(1 == ~t3_pc~0); 561384#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 561385#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 561253#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 561254#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 561730#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 561731#L506 assume !(1 == ~t4_pc~0); 561924#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 561925#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 562439#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 562438#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 562437#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 562436#L525 assume !(1 == ~t5_pc~0); 561308#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 561309#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 562223#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 562224#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 562399#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 562432#L544 assume !(1 == ~t6_pc~0); 562430#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 562429#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 562428#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 561291#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 561292#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 562275#L563 assume !(1 == ~t7_pc~0); 562076#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 562077#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 562424#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 561758#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 561458#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 561459#L582 assume !(1 == ~t8_pc~0); 562080#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 562349#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 562350#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 562419#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 562418#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 562144#L964 assume !(1 == ~M_E~0); 562145#L964-2 assume !(1 == ~T1_E~0); 562346#L969-1 assume !(1 == ~T2_E~0); 562416#L974-1 assume !(1 == ~T3_E~0); 562415#L979-1 assume !(1 == ~T4_E~0); 562414#L984-1 assume !(1 == ~T5_E~0); 562413#L989-1 assume !(1 == ~T6_E~0); 562412#L994-1 assume !(1 == ~T7_E~0); 562411#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 561550#L1004-1 assume !(1 == ~E_M~0); 561294#L1009-1 assume !(1 == ~E_1~0); 561295#L1014-1 assume !(1 == ~E_2~0); 561538#L1019-1 assume !(1 == ~E_3~0); 562127#L1024-1 assume !(1 == ~E_4~0); 561477#L1029-1 assume !(1 == ~E_5~0); 561478#L1034-1 assume !(1 == ~E_6~0); 561561#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 562316#L1044-1 assume !(1 == ~E_8~0); 561774#L1049-1 assume { :end_inline_reset_delta_events } true; 561775#L1315-2 [2024-11-23 02:54:20,550 INFO L747 eck$LassoCheckResult]: Loop: 561775#L1315-2 assume !false; 578549#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 578547#L841-1 assume !false; 578545#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 578532#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 578526#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 578524#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 578521#L724 assume !(0 != eval_~tmp~0#1); 578522#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 585155#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 585149#L866-3 assume !(0 == ~M_E~0); 585143#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 585137#L871-3 assume !(0 == ~T2_E~0); 585130#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 585124#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 585119#L886-3 assume !(0 == ~T5_E~0); 585113#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 585108#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 585102#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 581113#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 581114#L911-3 assume !(0 == ~E_1~0); 581107#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 581108#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 581101#L926-3 assume !(0 == ~E_4~0); 581102#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 581095#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 581096#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 581089#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 581090#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 581081#L430-30 assume 1 == ~m_pc~0; 581082#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 581175#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 581176#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 581066#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 581067#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 581060#L449-30 assume !(1 == ~t1_pc~0); 581061#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 581054#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 581055#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 581048#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 581049#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 581040#L468-30 assume !(1 == ~t2_pc~0); 581041#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 581033#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 581034#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 581027#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 581028#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 581022#L487-30 assume !(1 == ~t3_pc~0); 581023#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 581016#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 581017#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 581010#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 581011#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 581003#L506-30 assume !(1 == ~t4_pc~0); 581004#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 580996#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 580997#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 580990#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 580991#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 580984#L525-30 assume !(1 == ~t5_pc~0); 580985#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 580978#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 580979#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 580972#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 580973#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 580965#L544-30 assume !(1 == ~t6_pc~0); 580966#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 580958#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 580959#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 580952#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 580953#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 580949#L563-30 assume !(1 == ~t7_pc~0); 580948#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 580947#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 580946#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 580945#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 580944#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 580943#L582-30 assume !(1 == ~t8_pc~0); 580942#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 580941#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 580940#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 580939#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 580938#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 580937#L964-3 assume !(1 == ~M_E~0); 580936#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 580935#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 580934#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 580933#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 580932#L984-3 assume !(1 == ~T5_E~0); 580931#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 580930#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 580928#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 580926#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 580924#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 580922#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 580920#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 580918#L1024-3 assume !(1 == ~E_4~0); 580894#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 580886#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 580880#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 580874#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 580867#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 580689#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 580679#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 566919#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 566051#L1334 assume !(0 == start_simulation_~tmp~3#1); 566052#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 578728#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 578721#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 578717#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 578715#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 578713#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 578711#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 578708#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 561775#L1315-2 [2024-11-23 02:54:20,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:20,551 INFO L85 PathProgramCache]: Analyzing trace with hash -2085143865, now seen corresponding path program 1 times [2024-11-23 02:54:20,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:20,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [543057973] [2024-11-23 02:54:20,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:20,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:20,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:20,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:20,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:20,597 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [543057973] [2024-11-23 02:54:20,597 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [543057973] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:20,597 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:20,597 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:20,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [944844428] [2024-11-23 02:54:20,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:20,598 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:20,598 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:20,598 INFO L85 PathProgramCache]: Analyzing trace with hash 429002313, now seen corresponding path program 1 times [2024-11-23 02:54:20,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:20,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981980132] [2024-11-23 02:54:20,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:20,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:20,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:20,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:20,646 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:20,646 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981980132] [2024-11-23 02:54:20,647 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981980132] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:20,647 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:20,647 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:20,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975669337] [2024-11-23 02:54:20,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:20,647 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:20,648 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:20,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:54:20,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:54:20,649 INFO L87 Difference]: Start difference. First operand 49329 states and 70017 transitions. cyclomatic complexity: 20720 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:20,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:20,834 INFO L93 Difference]: Finished difference Result 43969 states and 62160 transitions. [2024-11-23 02:54:20,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43969 states and 62160 transitions. [2024-11-23 02:54:21,002 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43632 [2024-11-23 02:54:21,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43969 states to 43969 states and 62160 transitions. [2024-11-23 02:54:21,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43969 [2024-11-23 02:54:21,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43969 [2024-11-23 02:54:21,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43969 states and 62160 transitions. [2024-11-23 02:54:21,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:21,166 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43969 states and 62160 transitions. [2024-11-23 02:54:21,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43969 states and 62160 transitions. [2024-11-23 02:54:21,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43969 to 43969. [2024-11-23 02:54:21,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43969 states, 43969 states have (on average 1.4137233050558349) internal successors, (62160), 43968 states have internal predecessors, (62160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:21,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43969 states to 43969 states and 62160 transitions. [2024-11-23 02:54:21,973 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43969 states and 62160 transitions. [2024-11-23 02:54:21,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:54:21,974 INFO L425 stractBuchiCegarLoop]: Abstraction has 43969 states and 62160 transitions. [2024-11-23 02:54:21,974 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-23 02:54:21,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43969 states and 62160 transitions. [2024-11-23 02:54:22,097 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43632 [2024-11-23 02:54:22,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:22,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:22,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:22,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:22,099 INFO L745 eck$LassoCheckResult]: Stem: 654791#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 654792#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 655587#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 655588#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 655110#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 655111#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 654664#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 654665#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 654755#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 655567#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 654633#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 654634#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 655064#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 655097#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 654759#L866 assume !(0 == ~M_E~0); 654760#L866-2 assume !(0 == ~T1_E~0); 655308#L871-1 assume !(0 == ~T2_E~0); 655309#L876-1 assume !(0 == ~T3_E~0); 655633#L881-1 assume !(0 == ~T4_E~0); 655323#L886-1 assume !(0 == ~T5_E~0); 655053#L891-1 assume !(0 == ~T6_E~0); 655054#L896-1 assume !(0 == ~T7_E~0); 655316#L901-1 assume !(0 == ~T8_E~0); 655343#L906-1 assume !(0 == ~E_M~0); 655344#L911-1 assume !(0 == ~E_1~0); 655107#L916-1 assume !(0 == ~E_2~0); 655108#L921-1 assume !(0 == ~E_3~0); 655458#L926-1 assume !(0 == ~E_4~0); 655583#L931-1 assume !(0 == ~E_5~0); 655646#L936-1 assume !(0 == ~E_6~0); 655653#L941-1 assume !(0 == ~E_7~0); 655112#L946-1 assume !(0 == ~E_8~0); 655113#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 655611#L430 assume !(1 == ~m_pc~0); 654951#L430-2 is_master_triggered_~__retres1~0#1 := 0; 654579#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 654580#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 655238#L1073 assume !(0 != activate_threads_~tmp~1#1); 655239#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 655436#L449 assume !(1 == ~t1_pc~0); 654765#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 654766#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 654606#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 654607#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 655359#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 655171#L468 assume !(1 == ~t2_pc~0); 654567#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 654566#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 654961#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 654956#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 654581#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 654582#L487 assume !(1 == ~t3_pc~0); 654696#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 654670#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 654563#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 654564#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 655032#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 655033#L506 assume !(1 == ~t4_pc~0); 655166#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 655222#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 654656#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 654657#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 655160#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 654968#L525 assume !(1 == ~t5_pc~0); 654619#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 654620#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 655510#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 655511#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 654823#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 654824#L544 assume !(1 == ~t6_pc~0); 654969#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 654970#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 654940#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 654601#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 654602#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 655558#L563 assume !(1 == ~t7_pc~0); 655372#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 654624#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 654625#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 655055#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 654767#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 654768#L582 assume !(1 == ~t8_pc~0); 655376#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 655625#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 655443#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 655019#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 654905#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 654906#L964 assume !(1 == ~M_E~0); 655439#L964-2 assume !(1 == ~T1_E~0); 654825#L969-1 assume !(1 == ~T2_E~0); 654826#L974-1 assume !(1 == ~T3_E~0); 655481#L979-1 assume !(1 == ~T4_E~0); 655482#L984-1 assume !(1 == ~T5_E~0); 654975#L989-1 assume !(1 == ~T6_E~0); 654976#L994-1 assume !(1 == ~T7_E~0); 654858#L999-1 assume !(1 == ~T8_E~0); 654859#L1004-1 assume !(1 == ~E_M~0); 654603#L1009-1 assume !(1 == ~E_1~0); 654604#L1014-1 assume !(1 == ~E_2~0); 654845#L1019-1 assume !(1 == ~E_3~0); 655427#L1024-1 assume !(1 == ~E_4~0); 654788#L1029-1 assume !(1 == ~E_5~0); 654789#L1034-1 assume !(1 == ~E_6~0); 654874#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 655599#L1044-1 assume !(1 == ~E_8~0); 655075#L1049-1 assume { :end_inline_reset_delta_events } true; 655076#L1315-2 [2024-11-23 02:54:22,100 INFO L747 eck$LassoCheckResult]: Loop: 655076#L1315-2 assume !false; 664138#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 664135#L841-1 assume !false; 664131#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 661944#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 661938#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 661937#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 661933#L724 assume !(0 != eval_~tmp~0#1); 661934#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 665211#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 665209#L866-3 assume !(0 == ~M_E~0); 665207#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 665205#L871-3 assume !(0 == ~T2_E~0); 665203#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 665201#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 665199#L886-3 assume !(0 == ~T5_E~0); 665197#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 665195#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 665193#L901-3 assume !(0 == ~T8_E~0); 665191#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 665189#L911-3 assume !(0 == ~E_1~0); 665186#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 665184#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 665182#L926-3 assume !(0 == ~E_4~0); 665180#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 665178#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 665176#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 665174#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 665172#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 665170#L430-30 assume !(1 == ~m_pc~0); 665166#L430-32 is_master_triggered_~__retres1~0#1 := 0; 665164#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 665162#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 665159#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 665156#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 665154#L449-30 assume !(1 == ~t1_pc~0); 665152#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 665150#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 665148#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 665147#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 665145#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 665144#L468-30 assume 1 == ~t2_pc~0; 665142#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 665141#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 665140#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 665138#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 665137#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 665136#L487-30 assume !(1 == ~t3_pc~0); 665135#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 665131#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 665129#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 665127#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 665125#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 665122#L506-30 assume !(1 == ~t4_pc~0); 665119#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 665117#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 665115#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 665113#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 665111#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 665109#L525-30 assume !(1 == ~t5_pc~0); 665107#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 665105#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 665104#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 665103#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 665102#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 665100#L544-30 assume 1 == ~t6_pc~0; 665006#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 665003#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 665001#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 664999#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 664997#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 664995#L563-30 assume !(1 == ~t7_pc~0); 660696#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 664991#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 664989#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 664987#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 664985#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 664983#L582-30 assume !(1 == ~t8_pc~0); 664981#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 664980#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 664978#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 664976#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 664974#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 664972#L964-3 assume !(1 == ~M_E~0); 664970#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 664967#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 664965#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 664963#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 664961#L984-3 assume !(1 == ~T5_E~0); 664959#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 664957#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 664943#L999-3 assume !(1 == ~T8_E~0); 664937#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 664931#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 664925#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 664919#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 664914#L1024-3 assume !(1 == ~E_4~0); 664908#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 664901#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 664894#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 664890#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 664504#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 664386#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 664372#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 664366#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 664359#L1334 assume !(0 == start_simulation_~tmp~3#1); 664351#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 664277#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 664269#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 664267#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 664265#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 664174#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 664164#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 664156#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 655076#L1315-2 [2024-11-23 02:54:22,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:22,101 INFO L85 PathProgramCache]: Analyzing trace with hash 1031757063, now seen corresponding path program 1 times [2024-11-23 02:54:22,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:22,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280437117] [2024-11-23 02:54:22,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:22,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:22,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:22,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:22,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:22,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280437117] [2024-11-23 02:54:22,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280437117] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:22,173 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:22,174 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:22,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41996468] [2024-11-23 02:54:22,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:22,174 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:22,174 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:22,175 INFO L85 PathProgramCache]: Analyzing trace with hash 281551306, now seen corresponding path program 1 times [2024-11-23 02:54:22,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:22,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709349167] [2024-11-23 02:54:22,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:22,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:22,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:22,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:22,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:22,239 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709349167] [2024-11-23 02:54:22,240 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709349167] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:22,240 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:22,240 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:22,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259008473] [2024-11-23 02:54:22,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:22,240 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:22,241 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:22,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:54:22,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:54:22,241 INFO L87 Difference]: Start difference. First operand 43969 states and 62160 transitions. cyclomatic complexity: 18223 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:22,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:22,575 INFO L93 Difference]: Finished difference Result 68195 states and 96162 transitions. [2024-11-23 02:54:22,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68195 states and 96162 transitions. [2024-11-23 02:54:22,876 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 67632 [2024-11-23 02:54:23,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68195 states to 68195 states and 96162 transitions. [2024-11-23 02:54:23,510 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68195 [2024-11-23 02:54:23,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68195 [2024-11-23 02:54:23,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68195 states and 96162 transitions. [2024-11-23 02:54:23,606 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:23,606 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68195 states and 96162 transitions. [2024-11-23 02:54:23,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68195 states and 96162 transitions. [2024-11-23 02:54:23,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68195 to 49297. [2024-11-23 02:54:24,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49297 states, 49297 states have (on average 1.4115057711422603) internal successors, (69583), 49296 states have internal predecessors, (69583), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:24,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49297 states to 49297 states and 69583 transitions. [2024-11-23 02:54:24,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49297 states and 69583 transitions. [2024-11-23 02:54:24,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:54:24,077 INFO L425 stractBuchiCegarLoop]: Abstraction has 49297 states and 69583 transitions. [2024-11-23 02:54:24,078 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-23 02:54:24,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49297 states and 69583 transitions. [2024-11-23 02:54:24,200 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48880 [2024-11-23 02:54:24,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:24,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:24,201 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:24,201 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:24,202 INFO L745 eck$LassoCheckResult]: Stem: 766966#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 766967#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 767787#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 767788#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 767299#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 767300#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 766838#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 766839#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 766928#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 767769#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 766808#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 766809#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 767251#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 767286#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 766934#L866 assume !(0 == ~M_E~0); 766935#L866-2 assume !(0 == ~T1_E~0); 767509#L871-1 assume !(0 == ~T2_E~0); 767510#L876-1 assume !(0 == ~T3_E~0); 767857#L881-1 assume !(0 == ~T4_E~0); 767525#L886-1 assume !(0 == ~T5_E~0); 767239#L891-1 assume !(0 == ~T6_E~0); 767240#L896-1 assume !(0 == ~T7_E~0); 767517#L901-1 assume !(0 == ~T8_E~0); 767544#L906-1 assume !(0 == ~E_M~0); 767545#L911-1 assume !(0 == ~E_1~0); 767296#L916-1 assume !(0 == ~E_2~0); 767297#L921-1 assume !(0 == ~E_3~0); 767659#L926-1 assume !(0 == ~E_4~0); 767784#L931-1 assume !(0 == ~E_5~0); 767863#L936-1 assume !(0 == ~E_6~0); 767870#L941-1 assume 0 == ~E_7~0;~E_7~0 := 1; 767301#L946-1 assume !(0 == ~E_8~0); 767302#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 767873#L430 assume !(1 == ~m_pc~0); 767874#L430-2 is_master_triggered_~__retres1~0#1 := 0; 766755#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 766756#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 767439#L1073 assume !(0 != activate_threads_~tmp~1#1); 767440#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 767633#L449 assume !(1 == ~t1_pc~0); 767634#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 767838#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 767839#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 767877#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 767878#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 767367#L468 assume !(1 == ~t2_pc~0); 767368#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 767489#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 767490#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 767138#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 767139#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 767871#L487 assume !(1 == ~t3_pc~0); 767872#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 766844#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 766845#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 767707#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 767708#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 767361#L506 assume !(1 == ~t4_pc~0); 767362#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 767905#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 767906#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 767845#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 767846#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 767152#L525 assume !(1 == ~t5_pc~0); 767153#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 767761#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 767762#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 767900#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 767901#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 767347#L544 assume !(1 == ~t6_pc~0); 767348#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 767923#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 767120#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 767121#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 767830#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 767831#L563 assume !(1 == ~t7_pc~0); 767922#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 766800#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 766801#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 767241#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 767242#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 767921#L582 assume !(1 == ~t8_pc~0); 767884#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 767885#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 767643#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 767204#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 767205#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 767637#L964 assume !(1 == ~M_E~0); 767638#L964-2 assume !(1 == ~T1_E~0); 767002#L969-1 assume !(1 == ~T2_E~0); 767003#L974-1 assume !(1 == ~T3_E~0); 767681#L979-1 assume !(1 == ~T4_E~0); 767682#L984-1 assume !(1 == ~T5_E~0); 767160#L989-1 assume !(1 == ~T6_E~0); 767161#L994-1 assume !(1 == ~T7_E~0); 767035#L999-1 assume !(1 == ~T8_E~0); 767036#L1004-1 assume !(1 == ~E_M~0); 766779#L1009-1 assume !(1 == ~E_1~0); 766780#L1014-1 assume !(1 == ~E_2~0); 767622#L1019-1 assume !(1 == ~E_3~0); 767623#L1024-1 assume !(1 == ~E_4~0); 766963#L1029-1 assume !(1 == ~E_5~0); 766964#L1034-1 assume !(1 == ~E_6~0); 767914#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 767807#L1044-1 assume !(1 == ~E_8~0); 767262#L1049-1 assume { :end_inline_reset_delta_events } true; 767263#L1315-2 [2024-11-23 02:54:24,202 INFO L747 eck$LassoCheckResult]: Loop: 767263#L1315-2 assume !false; 779839#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 779837#L841-1 assume !false; 779834#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 779822#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 779389#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 779386#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 779383#L724 assume !(0 != eval_~tmp~0#1); 779381#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 779379#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 779377#L866-3 assume !(0 == ~M_E~0); 779375#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 779359#L871-3 assume !(0 == ~T2_E~0); 779352#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 779345#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 779337#L886-3 assume !(0 == ~T5_E~0); 779330#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 779323#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 779315#L901-3 assume !(0 == ~T8_E~0); 779308#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 779301#L911-3 assume !(0 == ~E_1~0); 779294#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 779287#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 779279#L926-3 assume !(0 == ~E_4~0); 779269#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 779260#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 779249#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 779247#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 779245#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 779243#L430-30 assume !(1 == ~m_pc~0); 779240#L430-32 is_master_triggered_~__retres1~0#1 := 0; 779236#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 779232#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 779228#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 779225#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 779223#L449-30 assume !(1 == ~t1_pc~0); 779221#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 779219#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 779217#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 779215#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 779213#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 779211#L468-30 assume !(1 == ~t2_pc~0); 779208#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 779205#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 779203#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 779201#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 779199#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 779197#L487-30 assume !(1 == ~t3_pc~0); 779195#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 779193#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 779191#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 779189#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 779187#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 779185#L506-30 assume 1 == ~t4_pc~0; 779182#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 779179#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 779177#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 779175#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 779173#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 779171#L525-30 assume !(1 == ~t5_pc~0); 779169#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 779167#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 779165#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 779163#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 779161#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 779159#L544-30 assume !(1 == ~t6_pc~0); 779155#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 779153#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 779151#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 779112#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 779113#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 779097#L563-30 assume !(1 == ~t7_pc~0); 779096#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 779095#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 779094#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 779093#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 779092#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 779091#L582-30 assume !(1 == ~t8_pc~0); 779090#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 779089#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 779088#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 779087#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 779086#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 779085#L964-3 assume !(1 == ~M_E~0); 779084#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 779083#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 779082#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 779081#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 779080#L984-3 assume !(1 == ~T5_E~0); 779079#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 779078#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 779077#L999-3 assume !(1 == ~T8_E~0); 779076#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 779075#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 779074#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 779073#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 779072#L1024-3 assume !(1 == ~E_4~0); 779071#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 779070#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 779068#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 779065#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 778963#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 778926#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 778816#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 778470#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 775221#L1334 assume !(0 == start_simulation_~tmp~3#1); 775222#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 779993#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 779983#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 779980#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 779977#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 779974#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 779971#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 779968#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 767263#L1315-2 [2024-11-23 02:54:24,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:24,203 INFO L85 PathProgramCache]: Analyzing trace with hash -1185873335, now seen corresponding path program 1 times [2024-11-23 02:54:24,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:24,203 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230753956] [2024-11-23 02:54:24,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:24,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:24,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:24,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:24,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:24,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230753956] [2024-11-23 02:54:24,249 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [230753956] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:24,249 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:24,249 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:24,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804494476] [2024-11-23 02:54:24,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:24,249 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:54:24,250 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:24,250 INFO L85 PathProgramCache]: Analyzing trace with hash -1441756789, now seen corresponding path program 1 times [2024-11-23 02:54:24,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:24,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360860476] [2024-11-23 02:54:24,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:24,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:24,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:24,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:24,278 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:24,278 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [360860476] [2024-11-23 02:54:24,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [360860476] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:24,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:24,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:24,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1447410203] [2024-11-23 02:54:24,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:24,279 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:24,279 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:24,279 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:54:24,279 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:54:24,279 INFO L87 Difference]: Start difference. First operand 49297 states and 69583 transitions. cyclomatic complexity: 20318 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:24,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:24,918 INFO L93 Difference]: Finished difference Result 62497 states and 87838 transitions. [2024-11-23 02:54:24,918 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62497 states and 87838 transitions. [2024-11-23 02:54:25,149 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 62016 [2024-11-23 02:54:25,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62497 states to 62497 states and 87838 transitions. [2024-11-23 02:54:25,278 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62497 [2024-11-23 02:54:25,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62497 [2024-11-23 02:54:25,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62497 states and 87838 transitions. [2024-11-23 02:54:25,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:25,344 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62497 states and 87838 transitions. [2024-11-23 02:54:25,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62497 states and 87838 transitions. [2024-11-23 02:54:25,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62497 to 43969. [2024-11-23 02:54:25,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43969 states, 43969 states have (on average 1.4045804998976552) internal successors, (61758), 43968 states have internal predecessors, (61758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:25,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43969 states to 43969 states and 61758 transitions. [2024-11-23 02:54:25,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43969 states and 61758 transitions. [2024-11-23 02:54:25,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:54:25,807 INFO L425 stractBuchiCegarLoop]: Abstraction has 43969 states and 61758 transitions. [2024-11-23 02:54:25,807 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-23 02:54:25,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43969 states and 61758 transitions. [2024-11-23 02:54:25,911 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43632 [2024-11-23 02:54:25,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:25,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:25,912 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:25,912 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:25,913 INFO L745 eck$LassoCheckResult]: Stem: 878768#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 878769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 879567#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 879568#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 879086#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 879087#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 878644#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 878645#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 878732#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 879550#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 878613#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 878614#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 879041#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 879073#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 878736#L866 assume !(0 == ~M_E~0); 878737#L866-2 assume !(0 == ~T1_E~0); 879285#L871-1 assume !(0 == ~T2_E~0); 879286#L876-1 assume !(0 == ~T3_E~0); 879603#L881-1 assume !(0 == ~T4_E~0); 879300#L886-1 assume !(0 == ~T5_E~0); 879029#L891-1 assume !(0 == ~T6_E~0); 879030#L896-1 assume !(0 == ~T7_E~0); 879293#L901-1 assume !(0 == ~T8_E~0); 879319#L906-1 assume !(0 == ~E_M~0); 879320#L911-1 assume !(0 == ~E_1~0); 879083#L916-1 assume !(0 == ~E_2~0); 879084#L921-1 assume !(0 == ~E_3~0); 879443#L926-1 assume !(0 == ~E_4~0); 879564#L931-1 assume !(0 == ~E_5~0); 879609#L936-1 assume !(0 == ~E_6~0); 879618#L941-1 assume !(0 == ~E_7~0); 879088#L946-1 assume !(0 == ~E_8~0); 879089#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 879587#L430 assume !(1 == ~m_pc~0); 878926#L430-2 is_master_triggered_~__retres1~0#1 := 0; 878559#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 878560#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 879214#L1073 assume !(0 != activate_threads_~tmp~1#1); 879215#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 879418#L449 assume !(1 == ~t1_pc~0); 878742#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 878743#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 878586#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 878587#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 879333#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 879147#L468 assume !(1 == ~t2_pc~0); 878547#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 878546#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 878936#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 878931#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 878561#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 878562#L487 assume !(1 == ~t3_pc~0); 878675#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 878650#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 878543#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 878544#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 879007#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 879008#L506 assume !(1 == ~t4_pc~0); 879142#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 879198#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 878636#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 878637#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 879136#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 878942#L525 assume !(1 == ~t5_pc~0); 878599#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 878600#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 879495#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 879496#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 878799#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 878800#L544 assume !(1 == ~t6_pc~0); 878943#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 878944#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 878913#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 878581#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 878582#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 879539#L563 assume !(1 == ~t7_pc~0); 879349#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 878604#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 878605#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 879031#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 878744#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 878745#L582 assume !(1 == ~t8_pc~0); 879353#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 879600#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 879428#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 878994#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 878876#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 878877#L964 assume !(1 == ~M_E~0); 879423#L964-2 assume !(1 == ~T1_E~0); 878801#L969-1 assume !(1 == ~T2_E~0); 878802#L974-1 assume !(1 == ~T3_E~0); 879465#L979-1 assume !(1 == ~T4_E~0); 879466#L984-1 assume !(1 == ~T5_E~0); 878949#L989-1 assume !(1 == ~T6_E~0); 878950#L994-1 assume !(1 == ~T7_E~0); 878832#L999-1 assume !(1 == ~T8_E~0); 878833#L1004-1 assume !(1 == ~E_M~0); 878583#L1009-1 assume !(1 == ~E_1~0); 878584#L1014-1 assume !(1 == ~E_2~0); 878820#L1019-1 assume !(1 == ~E_3~0); 879407#L1024-1 assume !(1 == ~E_4~0); 878765#L1029-1 assume !(1 == ~E_5~0); 878766#L1034-1 assume !(1 == ~E_6~0); 878845#L1039-1 assume !(1 == ~E_7~0); 879580#L1044-1 assume !(1 == ~E_8~0); 879052#L1049-1 assume { :end_inline_reset_delta_events } true; 879053#L1315-2 [2024-11-23 02:54:25,913 INFO L747 eck$LassoCheckResult]: Loop: 879053#L1315-2 assume !false; 910773#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 907060#L841-1 assume !false; 910770#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 910758#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 910753#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 910749#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 910746#L724 assume !(0 != eval_~tmp~0#1); 910747#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 917036#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 917034#L866-3 assume !(0 == ~M_E~0); 917031#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 917029#L871-3 assume !(0 == ~T2_E~0); 917027#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 917025#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 917023#L886-3 assume !(0 == ~T5_E~0); 917022#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 917021#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 917020#L901-3 assume !(0 == ~T8_E~0); 917019#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 917018#L911-3 assume !(0 == ~E_1~0); 917017#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 917016#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 917015#L926-3 assume !(0 == ~E_4~0); 917014#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 917013#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 917012#L941-3 assume !(0 == ~E_7~0); 917011#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 917010#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 917009#L430-30 assume !(1 == ~m_pc~0); 917007#L430-32 is_master_triggered_~__retres1~0#1 := 0; 917005#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 917003#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 917002#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 917000#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 916999#L449-30 assume !(1 == ~t1_pc~0); 916997#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 916996#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 916995#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 916994#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 916993#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 916992#L468-30 assume !(1 == ~t2_pc~0); 916991#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 916989#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 916986#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 916985#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 916984#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 916978#L487-30 assume !(1 == ~t3_pc~0); 916976#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 916974#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 916970#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 916968#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 916966#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 916964#L506-30 assume 1 == ~t4_pc~0; 916961#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 916958#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 916956#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 916954#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 916952#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 916950#L525-30 assume !(1 == ~t5_pc~0); 916948#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 916946#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 916944#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 916941#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 916939#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 916937#L544-30 assume 1 == ~t6_pc~0; 916935#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 916932#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 916930#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 916928#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 916926#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 916924#L563-30 assume !(1 == ~t7_pc~0); 902361#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 916921#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 916919#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 916916#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 916914#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 916912#L582-30 assume !(1 == ~t8_pc~0); 915470#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 915467#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 915465#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 915463#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 915460#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 915458#L964-3 assume !(1 == ~M_E~0); 915456#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 915454#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 915452#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 915450#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 915447#L984-3 assume !(1 == ~T5_E~0); 915445#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 915443#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 915441#L999-3 assume !(1 == ~T8_E~0); 915439#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 915437#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 915434#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 915432#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 915430#L1024-3 assume !(1 == ~E_4~0); 915428#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 915426#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 915424#L1039-3 assume !(1 == ~E_7~0); 915421#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 915419#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 915417#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 915407#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 914315#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 890776#L1334 assume !(0 == start_simulation_~tmp~3#1); 890777#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 910795#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 910787#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 910784#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 910782#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 910780#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 910778#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 910776#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 879053#L1315-2 [2024-11-23 02:54:25,914 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:25,914 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 1 times [2024-11-23 02:54:25,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:25,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655322861] [2024-11-23 02:54:25,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:25,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:25,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:54:25,926 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:54:25,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:54:26,265 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:54:26,266 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:26,266 INFO L85 PathProgramCache]: Analyzing trace with hash -889550198, now seen corresponding path program 1 times [2024-11-23 02:54:26,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:26,266 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093957500] [2024-11-23 02:54:26,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:26,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:26,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:26,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:26,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:26,307 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093957500] [2024-11-23 02:54:26,307 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093957500] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:26,307 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:26,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:26,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1076158537] [2024-11-23 02:54:26,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:26,308 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:26,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:26,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:26,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:26,308 INFO L87 Difference]: Start difference. First operand 43969 states and 61758 transitions. cyclomatic complexity: 17821 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:26,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:26,621 INFO L93 Difference]: Finished difference Result 82300 states and 114602 transitions. [2024-11-23 02:54:26,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82300 states and 114602 transitions. [2024-11-23 02:54:26,922 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 81696 [2024-11-23 02:54:27,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82300 states to 82300 states and 114602 transitions. [2024-11-23 02:54:27,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82300 [2024-11-23 02:54:27,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82300 [2024-11-23 02:54:27,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82300 states and 114602 transitions. [2024-11-23 02:54:27,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:27,213 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82300 states and 114602 transitions. [2024-11-23 02:54:27,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82300 states and 114602 transitions. [2024-11-23 02:54:28,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82300 to 82268. [2024-11-23 02:54:28,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82268 states, 82268 states have (on average 1.3926435552098022) internal successors, (114570), 82267 states have internal predecessors, (114570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:28,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82268 states to 82268 states and 114570 transitions. [2024-11-23 02:54:28,450 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82268 states and 114570 transitions. [2024-11-23 02:54:28,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:28,451 INFO L425 stractBuchiCegarLoop]: Abstraction has 82268 states and 114570 transitions. [2024-11-23 02:54:28,451 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-23 02:54:28,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82268 states and 114570 transitions. [2024-11-23 02:54:28,689 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 81664 [2024-11-23 02:54:28,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:28,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:28,690 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:28,690 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:28,691 INFO L745 eck$LassoCheckResult]: Stem: 1005041#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1005042#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1005876#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1005877#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1005366#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1005367#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1004916#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1004917#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1005005#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1005857#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1004885#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1004886#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1005320#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1005353#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1005009#L866 assume !(0 == ~M_E~0); 1005010#L866-2 assume !(0 == ~T1_E~0); 1005579#L871-1 assume !(0 == ~T2_E~0); 1005580#L876-1 assume !(0 == ~T3_E~0); 1005938#L881-1 assume !(0 == ~T4_E~0); 1005596#L886-1 assume !(0 == ~T5_E~0); 1005308#L891-1 assume !(0 == ~T6_E~0); 1005309#L896-1 assume !(0 == ~T7_E~0); 1005587#L901-1 assume !(0 == ~T8_E~0); 1005615#L906-1 assume !(0 == ~E_M~0); 1005616#L911-1 assume !(0 == ~E_1~0); 1005363#L916-1 assume !(0 == ~E_2~0); 1005364#L921-1 assume !(0 == ~E_3~0); 1005733#L926-1 assume !(0 == ~E_4~0); 1005872#L931-1 assume !(0 == ~E_5~0); 1005948#L936-1 assume !(0 == ~E_6~0); 1005960#L941-1 assume !(0 == ~E_7~0); 1005368#L946-1 assume !(0 == ~E_8~0); 1005369#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1005905#L430 assume !(1 == ~m_pc~0); 1005203#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1005827#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1006010#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1005507#L1073 assume !(0 != activate_threads_~tmp~1#1); 1005508#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1005709#L449 assume !(1 == ~t1_pc~0); 1005015#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1005016#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1004860#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1004861#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1005630#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1005432#L468 assume !(1 == ~t2_pc~0); 1004822#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1004821#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1005214#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1005209#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1004836#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1004837#L487 assume !(1 == ~t3_pc~0); 1004947#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1004922#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1004818#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1004819#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1005286#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1005287#L506 assume !(1 == ~t4_pc~0); 1005426#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1005944#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1006000#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1005926#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1005927#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1005220#L525 assume !(1 == ~t5_pc~0); 1005221#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1005848#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1005849#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1005992#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1005993#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1005412#L544 assume !(1 == ~t6_pc~0); 1005413#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1006020#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1005189#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1005190#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1005913#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1005914#L563 assume !(1 == ~t7_pc~0); 1006019#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1004877#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1004878#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1005310#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1005311#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1006018#L582 assume !(1 == ~t8_pc~0); 1005968#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1005969#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1005718#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1005273#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1005274#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1005714#L964 assume !(1 == ~M_E~0); 1005715#L964-2 assume !(1 == ~T1_E~0); 1005077#L969-1 assume !(1 == ~T2_E~0); 1005078#L974-1 assume !(1 == ~T3_E~0); 1005754#L979-1 assume !(1 == ~T4_E~0); 1005755#L984-1 assume !(1 == ~T5_E~0); 1005228#L989-1 assume !(1 == ~T6_E~0); 1005229#L994-1 assume !(1 == ~T7_E~0); 1006016#L999-1 assume !(1 == ~T8_E~0); 1006015#L1004-1 assume !(1 == ~E_M~0); 1006014#L1009-1 assume !(1 == ~E_1~0); 1006013#L1014-1 assume !(1 == ~E_2~0); 1006012#L1019-1 assume !(1 == ~E_3~0); 1006011#L1024-1 assume !(1 == ~E_4~0); 1005038#L1029-1 assume !(1 == ~E_5~0); 1005039#L1034-1 assume !(1 == ~E_6~0); 1005122#L1039-1 assume !(1 == ~E_7~0); 1005895#L1044-1 assume !(1 == ~E_8~0); 1005331#L1049-1 assume { :end_inline_reset_delta_events } true; 1005332#L1315-2 [2024-11-23 02:54:28,692 INFO L747 eck$LassoCheckResult]: Loop: 1005332#L1315-2 assume !false; 1016711#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1016710#L841-1 assume !false; 1016709#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1016699#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1016693#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1016690#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1016687#L724 assume !(0 != eval_~tmp~0#1); 1016685#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1016682#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1016680#L866-3 assume !(0 == ~M_E~0); 1016678#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1016676#L871-3 assume !(0 == ~T2_E~0); 1016674#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1016672#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1016671#L886-3 assume !(0 == ~T5_E~0); 1016670#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1016669#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1016668#L901-3 assume !(0 == ~T8_E~0); 1016666#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1016665#L911-3 assume !(0 == ~E_1~0); 1016664#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1016663#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1016662#L926-3 assume !(0 == ~E_4~0); 1016661#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1016659#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1016658#L941-3 assume !(0 == ~E_7~0); 1016657#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1016656#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1016655#L430-30 assume 1 == ~m_pc~0; 1016654#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1016652#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1016650#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1016647#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1016646#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1016645#L449-30 assume !(1 == ~t1_pc~0); 1016644#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1016643#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1016642#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1016641#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1016640#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1016639#L468-30 assume !(1 == ~t2_pc~0); 1016638#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1016636#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1016635#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1016633#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 1016632#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1016631#L487-30 assume !(1 == ~t3_pc~0); 1016630#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1016629#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1016628#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1016627#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1016626#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1016625#L506-30 assume 1 == ~t4_pc~0; 1016623#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1016624#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1038230#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1038228#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1038226#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1038224#L525-30 assume !(1 == ~t5_pc~0); 1038222#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1038220#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1038218#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1038216#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1038214#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1038212#L544-30 assume 1 == ~t6_pc~0; 1038210#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1038208#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1038207#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1038203#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1038201#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1038199#L563-30 assume !(1 == ~t7_pc~0); 1016546#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1016543#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1016542#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1016540#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1016538#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1016536#L582-30 assume !(1 == ~t8_pc~0); 1016534#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1016532#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1016530#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1016528#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1016526#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1016524#L964-3 assume !(1 == ~M_E~0); 1016522#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1016519#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1016517#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1016515#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1016513#L984-3 assume !(1 == ~T5_E~0); 1016511#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1016509#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1016508#L999-3 assume !(1 == ~T8_E~0); 1016506#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1016504#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1016502#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1016500#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1016498#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1016495#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1016493#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1016491#L1039-3 assume !(1 == ~E_7~0); 1016489#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1016487#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1013556#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1013546#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1013545#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1013540#L1334 assume !(0 == start_simulation_~tmp~3#1); 1013541#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1017034#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1017027#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1017026#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1017025#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1017024#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1017021#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1017020#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1005332#L1315-2 [2024-11-23 02:54:28,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:28,692 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 2 times [2024-11-23 02:54:28,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:28,693 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220318535] [2024-11-23 02:54:28,693 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:54:28,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:28,712 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:54:28,712 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:54:28,712 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:54:28,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:54:28,751 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:54:28,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:28,752 INFO L85 PathProgramCache]: Analyzing trace with hash -915348087, now seen corresponding path program 1 times [2024-11-23 02:54:28,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:28,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659839183] [2024-11-23 02:54:28,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:28,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:28,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:28,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:28,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:28,814 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659839183] [2024-11-23 02:54:28,814 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [659839183] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:28,815 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:28,815 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:28,815 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464731881] [2024-11-23 02:54:28,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:28,815 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:28,816 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:28,816 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:54:28,816 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:54:28,816 INFO L87 Difference]: Start difference. First operand 82268 states and 114570 transitions. cyclomatic complexity: 32334 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:29,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:29,126 INFO L93 Difference]: Finished difference Result 82908 states and 115210 transitions. [2024-11-23 02:54:29,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82908 states and 115210 transitions. [2024-11-23 02:54:30,125 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 82304 [2024-11-23 02:54:30,287 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82908 states to 82908 states and 115210 transitions. [2024-11-23 02:54:30,287 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82908 [2024-11-23 02:54:30,342 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82908 [2024-11-23 02:54:30,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82908 states and 115210 transitions. [2024-11-23 02:54:30,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:30,381 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82908 states and 115210 transitions. [2024-11-23 02:54:30,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82908 states and 115210 transitions. [2024-11-23 02:54:31,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82908 to 82652. [2024-11-23 02:54:31,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82652 states, 82652 states have (on average 1.3908193389149688) internal successors, (114954), 82651 states have internal predecessors, (114954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:31,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82652 states to 82652 states and 114954 transitions. [2024-11-23 02:54:31,740 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82652 states and 114954 transitions. [2024-11-23 02:54:31,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:54:31,741 INFO L425 stractBuchiCegarLoop]: Abstraction has 82652 states and 114954 transitions. [2024-11-23 02:54:31,741 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-23 02:54:31,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82652 states and 114954 transitions. [2024-11-23 02:54:31,924 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 82048 [2024-11-23 02:54:31,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:31,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:31,925 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:31,925 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:31,925 INFO L745 eck$LassoCheckResult]: Stem: 1170225#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1170226#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1171178#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1171179#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1170577#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1170578#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1170101#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1170102#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1170189#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1171148#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1170070#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1170071#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1170528#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1170564#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1170193#L866 assume !(0 == ~M_E~0); 1170194#L866-2 assume !(0 == ~T1_E~0); 1170801#L871-1 assume !(0 == ~T2_E~0); 1170802#L876-1 assume !(0 == ~T3_E~0); 1171262#L881-1 assume !(0 == ~T4_E~0); 1170818#L886-1 assume !(0 == ~T5_E~0); 1170516#L891-1 assume !(0 == ~T6_E~0); 1170517#L896-1 assume !(0 == ~T7_E~0); 1170809#L901-1 assume !(0 == ~T8_E~0); 1170840#L906-1 assume !(0 == ~E_M~0); 1170841#L911-1 assume !(0 == ~E_1~0); 1170574#L916-1 assume !(0 == ~E_2~0); 1170575#L921-1 assume !(0 == ~E_3~0); 1170982#L926-1 assume !(0 == ~E_4~0); 1171174#L931-1 assume !(0 == ~E_5~0); 1171283#L936-1 assume !(0 == ~E_6~0); 1171305#L941-1 assume !(0 == ~E_7~0); 1170579#L946-1 assume !(0 == ~E_8~0); 1170580#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1171218#L430 assume !(1 == ~m_pc~0); 1170404#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1171111#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1171387#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1170716#L1073 assume !(0 != activate_threads_~tmp~1#1); 1170717#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1170949#L449 assume !(1 == ~t1_pc~0); 1170199#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1170200#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1170044#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1170045#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1170858#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1170646#L468 assume !(1 == ~t2_pc~0); 1170006#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1170005#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1170414#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1170409#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1170017#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1170018#L487 assume !(1 == ~t3_pc~0); 1170132#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1170107#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1170002#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1170003#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1170494#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1170495#L506 assume !(1 == ~t4_pc~0); 1170640#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1171276#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1171371#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1171247#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1171248#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1170421#L525 assume !(1 == ~t5_pc~0); 1170422#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1171131#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1171132#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1171356#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1171357#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1170627#L544 assume !(1 == ~t6_pc~0); 1170628#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1171397#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1170392#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1170393#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1171230#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1171231#L563 assume !(1 == ~t7_pc~0); 1171396#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1170062#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1170063#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1170518#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1170519#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1171395#L582 assume !(1 == ~t8_pc~0); 1171324#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1171325#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1170962#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1170480#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1170481#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1170955#L964 assume !(1 == ~M_E~0); 1170956#L964-2 assume !(1 == ~T1_E~0); 1170264#L969-1 assume !(1 == ~T2_E~0); 1170265#L974-1 assume !(1 == ~T3_E~0); 1171013#L979-1 assume !(1 == ~T4_E~0); 1171014#L984-1 assume !(1 == ~T5_E~0); 1170429#L989-1 assume !(1 == ~T6_E~0); 1170430#L994-1 assume !(1 == ~T7_E~0); 1171393#L999-1 assume !(1 == ~T8_E~0); 1171392#L1004-1 assume !(1 == ~E_M~0); 1171391#L1009-1 assume !(1 == ~E_1~0); 1171390#L1014-1 assume !(1 == ~E_2~0); 1171389#L1019-1 assume !(1 == ~E_3~0); 1171388#L1024-1 assume !(1 == ~E_4~0); 1170222#L1029-1 assume !(1 == ~E_5~0); 1170223#L1034-1 assume !(1 == ~E_6~0); 1170314#L1039-1 assume !(1 == ~E_7~0); 1171197#L1044-1 assume !(1 == ~E_8~0); 1170538#L1049-1 assume { :end_inline_reset_delta_events } true; 1170539#L1315-2 [2024-11-23 02:54:31,925 INFO L747 eck$LassoCheckResult]: Loop: 1170539#L1315-2 assume !false; 1186508#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1186507#L841-1 assume !false; 1186506#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1186500#L662 assume !(0 == ~m_st~0); 1186501#L666 assume !(0 == ~t1_st~0); 1186504#L670 assume !(0 == ~t2_st~0); 1186498#L674 assume !(0 == ~t3_st~0); 1186499#L678 assume !(0 == ~t4_st~0); 1186503#L682 assume !(0 == ~t5_st~0); 1186496#L686 assume !(0 == ~t6_st~0); 1186497#L690 assume !(0 == ~t7_st~0); 1186502#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1186505#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1186480#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1186481#L724 assume !(0 != eval_~tmp~0#1); 1187481#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1187478#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1187475#L866-3 assume !(0 == ~M_E~0); 1187472#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1187469#L871-3 assume !(0 == ~T2_E~0); 1187466#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1187463#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1187460#L886-3 assume !(0 == ~T5_E~0); 1187457#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1187454#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1187451#L901-3 assume !(0 == ~T8_E~0); 1187448#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1187445#L911-3 assume !(0 == ~E_1~0); 1187442#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1187439#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1187436#L926-3 assume !(0 == ~E_4~0); 1187433#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1187430#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1187427#L941-3 assume !(0 == ~E_7~0); 1187424#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1187421#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1187416#L430-30 assume 1 == ~m_pc~0; 1187410#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1187404#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1187398#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1187394#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1187391#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1187388#L449-30 assume !(1 == ~t1_pc~0); 1187385#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1187382#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1187379#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1187376#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1187373#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1187368#L468-30 assume 1 == ~t2_pc~0; 1187364#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1187361#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1187358#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1187355#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 1187352#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1187349#L487-30 assume !(1 == ~t3_pc~0); 1187346#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1187343#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1187340#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1187337#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1187334#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1187329#L506-30 assume 1 == ~t4_pc~0; 1187328#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1187327#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1187324#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1187321#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1187318#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1187315#L525-30 assume !(1 == ~t5_pc~0); 1187312#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1187309#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1187306#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1187303#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1187300#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1187297#L544-30 assume !(1 == ~t6_pc~0); 1187292#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1187130#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1187131#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1186970#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1186971#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1186800#L563-30 assume !(1 == ~t7_pc~0); 1186798#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1186796#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1186794#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1186792#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1186790#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1186788#L582-30 assume !(1 == ~t8_pc~0); 1186786#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1186784#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1186782#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1186780#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1186778#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1186776#L964-3 assume !(1 == ~M_E~0); 1186774#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1186772#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1186770#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1186768#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1186766#L984-3 assume !(1 == ~T5_E~0); 1186764#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1186762#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1186760#L999-3 assume !(1 == ~T8_E~0); 1186758#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1186756#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1186754#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1186752#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1186750#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1186748#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1186747#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1186746#L1039-3 assume !(1 == ~E_7~0); 1186745#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1186744#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1186743#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1186730#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1186727#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1186723#L1334 assume !(0 == start_simulation_~tmp~3#1); 1186721#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1186718#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1186549#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1186528#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1186523#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1186518#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1186515#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1186513#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1170539#L1315-2 [2024-11-23 02:54:31,926 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:31,926 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 3 times [2024-11-23 02:54:31,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:31,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326838275] [2024-11-23 02:54:31,926 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-23 02:54:31,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:31,937 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-23 02:54:31,937 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:54:31,937 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:54:31,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:54:31,963 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:54:31,963 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:31,964 INFO L85 PathProgramCache]: Analyzing trace with hash 535246643, now seen corresponding path program 1 times [2024-11-23 02:54:31,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:31,964 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665334177] [2024-11-23 02:54:31,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:31,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:31,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:32,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:32,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:32,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665334177] [2024-11-23 02:54:32,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665334177] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:32,012 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:32,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:32,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880102645] [2024-11-23 02:54:32,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:32,013 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:32,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:32,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:54:32,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:54:32,014 INFO L87 Difference]: Start difference. First operand 82652 states and 114954 transitions. cyclomatic complexity: 32334 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:32,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:32,447 INFO L93 Difference]: Finished difference Result 85535 states and 117837 transitions. [2024-11-23 02:54:32,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85535 states and 117837 transitions. [2024-11-23 02:54:32,724 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 84928 [2024-11-23 02:54:32,906 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85535 states to 85535 states and 117837 transitions. [2024-11-23 02:54:32,906 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 85535 [2024-11-23 02:54:32,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 85535 [2024-11-23 02:54:32,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85535 states and 117837 transitions. [2024-11-23 02:54:33,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:33,559 INFO L218 hiAutomatonCegarLoop]: Abstraction has 85535 states and 117837 transitions. [2024-11-23 02:54:33,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85535 states and 117837 transitions. [2024-11-23 02:54:34,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85535 to 85535. [2024-11-23 02:54:34,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85535 states, 85535 states have (on average 1.3776465774244462) internal successors, (117837), 85534 states have internal predecessors, (117837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:34,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85535 states to 85535 states and 117837 transitions. [2024-11-23 02:54:34,350 INFO L240 hiAutomatonCegarLoop]: Abstraction has 85535 states and 117837 transitions. [2024-11-23 02:54:34,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:54:34,350 INFO L425 stractBuchiCegarLoop]: Abstraction has 85535 states and 117837 transitions. [2024-11-23 02:54:34,350 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-23 02:54:34,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85535 states and 117837 transitions. [2024-11-23 02:54:34,567 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 84928 [2024-11-23 02:54:34,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:34,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:34,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:34,568 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:34,569 INFO L745 eck$LassoCheckResult]: Stem: 1338419#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1338420#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1339312#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1339313#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1338766#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1338767#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1338295#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1338296#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1338383#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1339290#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1338263#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1338264#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1338715#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1338752#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1338388#L866 assume !(0 == ~M_E~0); 1338389#L866-2 assume !(0 == ~T1_E~0); 1338989#L871-1 assume !(0 == ~T2_E~0); 1338990#L876-1 assume !(0 == ~T3_E~0); 1339386#L881-1 assume !(0 == ~T4_E~0); 1339012#L886-1 assume !(0 == ~T5_E~0); 1338701#L891-1 assume !(0 == ~T6_E~0); 1338702#L896-1 assume !(0 == ~T7_E~0); 1339000#L901-1 assume !(0 == ~T8_E~0); 1339031#L906-1 assume !(0 == ~E_M~0); 1339032#L911-1 assume !(0 == ~E_1~0); 1338763#L916-1 assume !(0 == ~E_2~0); 1338764#L921-1 assume !(0 == ~E_3~0); 1339154#L926-1 assume !(0 == ~E_4~0); 1339308#L931-1 assume !(0 == ~E_5~0); 1339400#L936-1 assume !(0 == ~E_6~0); 1339413#L941-1 assume !(0 == ~E_7~0); 1338768#L946-1 assume !(0 == ~E_8~0); 1338769#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1339350#L430 assume !(1 == ~m_pc~0); 1338596#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1339258#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1339475#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1338911#L1073 assume !(0 != activate_threads_~tmp~1#1); 1338912#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1339126#L449 assume !(1 == ~t1_pc~0); 1338393#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1338394#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1338244#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1338245#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1339045#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1338840#L468 assume !(1 == ~t2_pc~0); 1338201#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1338610#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1338603#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1338604#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1338214#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1338215#L487 assume !(1 == ~t3_pc~0); 1338326#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1338301#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1338197#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1338198#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1338680#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1338681#L506 assume !(1 == ~t4_pc~0); 1338828#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1339393#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1338287#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1338288#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1338823#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1338824#L525 assume !(1 == ~t5_pc~0); 1338250#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1338251#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1339211#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1339212#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1338454#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1338455#L544 assume !(1 == ~t6_pc~0); 1338613#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1338614#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1339063#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1338233#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1338234#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1339273#L563 assume !(1 == ~t7_pc~0); 1339059#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1339060#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1339439#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1339440#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1338397#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1338398#L582 assume !(1 == ~t8_pc~0); 1339064#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1339379#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1339380#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1339481#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1338540#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1338541#L964 assume !(1 == ~M_E~0); 1339375#L964-2 assume !(1 == ~T1_E~0); 1339376#L969-1 assume !(1 == ~T2_E~0); 1339317#L974-1 assume !(1 == ~T3_E~0); 1339318#L979-1 assume !(1 == ~T4_E~0); 1339446#L984-1 assume !(1 == ~T5_E~0); 1339447#L989-1 assume !(1 == ~T6_E~0); 1339004#L994-1 assume !(1 == ~T7_E~0); 1338493#L999-1 assume !(1 == ~T8_E~0); 1338494#L1004-1 assume !(1 == ~E_M~0); 1339137#L1009-1 assume !(1 == ~E_1~0); 1339478#L1014-1 assume !(1 == ~E_2~0); 1339477#L1019-1 assume !(1 == ~E_3~0); 1339476#L1024-1 assume !(1 == ~E_4~0); 1338416#L1029-1 assume !(1 == ~E_5~0); 1338417#L1034-1 assume !(1 == ~E_6~0); 1338507#L1039-1 assume !(1 == ~E_7~0); 1339335#L1044-1 assume !(1 == ~E_8~0); 1338726#L1049-1 assume { :end_inline_reset_delta_events } true; 1338727#L1315-2 [2024-11-23 02:54:34,569 INFO L747 eck$LassoCheckResult]: Loop: 1338727#L1315-2 assume !false; 1382854#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1382852#L841-1 assume !false; 1382850#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1382848#L662 assume !(0 == ~m_st~0); 1382846#L666 assume !(0 == ~t1_st~0); 1382844#L670 assume !(0 == ~t2_st~0); 1382842#L674 assume !(0 == ~t3_st~0); 1382840#L678 assume !(0 == ~t4_st~0); 1382838#L682 assume !(0 == ~t5_st~0); 1382836#L686 assume !(0 == ~t6_st~0); 1382835#L690 assume !(0 == ~t7_st~0); 1382830#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1382828#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1382826#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1382824#L724 assume !(0 != eval_~tmp~0#1); 1382821#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1382817#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1382814#L866-3 assume !(0 == ~M_E~0); 1382811#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1382810#L871-3 assume !(0 == ~T2_E~0); 1382809#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1382808#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1382807#L886-3 assume !(0 == ~T5_E~0); 1382806#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1382805#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1382804#L901-3 assume !(0 == ~T8_E~0); 1382802#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1382801#L911-3 assume !(0 == ~E_1~0); 1382800#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1382799#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1382797#L926-3 assume !(0 == ~E_4~0); 1382795#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1382794#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1382793#L941-3 assume !(0 == ~E_7~0); 1382791#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1382790#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1382789#L430-30 assume 1 == ~m_pc~0; 1382788#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1382786#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1382784#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1382781#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1382780#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1382778#L449-30 assume !(1 == ~t1_pc~0); 1382776#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1382772#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1382770#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1382768#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1382766#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1382763#L468-30 assume !(1 == ~t2_pc~0); 1382761#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1382798#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1382796#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1382753#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 1382751#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1382749#L487-30 assume !(1 == ~t3_pc~0); 1382747#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1382743#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1382741#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1382739#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1382737#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1382734#L506-30 assume 1 == ~t4_pc~0; 1382732#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1382733#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1389700#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1389698#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1389695#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1389694#L525-30 assume !(1 == ~t5_pc~0); 1389692#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1389690#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1389688#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1389686#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1389684#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1389682#L544-30 assume 1 == ~t6_pc~0; 1389680#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1389677#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1389675#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1389673#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1389670#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1389668#L563-30 assume !(1 == ~t7_pc~0); 1374810#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1389665#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1389664#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1389663#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1389661#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1389659#L582-30 assume !(1 == ~t8_pc~0); 1389657#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1389655#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1389653#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1389651#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1377767#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1376009#L964-3 assume !(1 == ~M_E~0); 1376005#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1376003#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1376001#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1375999#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1375997#L984-3 assume !(1 == ~T5_E~0); 1375995#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1375993#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1375991#L999-3 assume !(1 == ~T8_E~0); 1375989#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1375987#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1375985#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1375983#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1375982#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1375980#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1375979#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1375978#L1039-3 assume !(1 == ~E_7~0); 1375977#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1375976#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1375956#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1375946#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1375944#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1375941#L1334 assume !(0 == start_simulation_~tmp~3#1); 1375942#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1383109#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1383101#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1383098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1383096#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1383094#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1383092#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1383090#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1338727#L1315-2 [2024-11-23 02:54:34,570 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:34,570 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 4 times [2024-11-23 02:54:34,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:34,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437203625] [2024-11-23 02:54:34,570 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-23 02:54:34,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:34,581 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-23 02:54:34,581 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:54:34,581 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:54:34,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:54:34,611 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:54:34,612 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:34,612 INFO L85 PathProgramCache]: Analyzing trace with hash 1199031347, now seen corresponding path program 1 times [2024-11-23 02:54:34,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:34,613 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1385064599] [2024-11-23 02:54:34,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:34,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:34,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:35,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:35,243 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:35,243 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1385064599] [2024-11-23 02:54:35,243 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1385064599] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:35,243 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:35,244 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:35,244 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [233152917] [2024-11-23 02:54:35,244 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:35,244 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:35,244 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:35,245 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:54:35,245 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:54:35,245 INFO L87 Difference]: Start difference. First operand 85535 states and 117837 transitions. cyclomatic complexity: 32334 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:35,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:35,707 INFO L93 Difference]: Finished difference Result 87071 states and 118924 transitions. [2024-11-23 02:54:35,707 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87071 states and 118924 transitions. [2024-11-23 02:54:36,077 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86464 [2024-11-23 02:54:36,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87071 states to 87071 states and 118924 transitions. [2024-11-23 02:54:36,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 87071 [2024-11-23 02:54:36,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 87071 [2024-11-23 02:54:36,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87071 states and 118924 transitions. [2024-11-23 02:54:36,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:36,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 87071 states and 118924 transitions. [2024-11-23 02:54:36,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87071 states and 118924 transitions. [2024-11-23 02:54:37,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87071 to 87071. [2024-11-23 02:54:37,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87071 states, 87071 states have (on average 1.365827887585993) internal successors, (118924), 87070 states have internal predecessors, (118924), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:37,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87071 states to 87071 states and 118924 transitions. [2024-11-23 02:54:37,858 INFO L240 hiAutomatonCegarLoop]: Abstraction has 87071 states and 118924 transitions. [2024-11-23 02:54:37,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:54:37,859 INFO L425 stractBuchiCegarLoop]: Abstraction has 87071 states and 118924 transitions. [2024-11-23 02:54:37,859 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-23 02:54:37,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87071 states and 118924 transitions. [2024-11-23 02:54:38,076 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86464 [2024-11-23 02:54:38,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:38,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:38,077 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:38,077 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:38,077 INFO L745 eck$LassoCheckResult]: Stem: 1511033#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1511034#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1511904#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1511905#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1511378#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1511379#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1510908#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1510909#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1510995#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1511884#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1510876#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1510877#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1511329#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1511364#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1511002#L866 assume !(0 == ~M_E~0); 1511003#L866-2 assume !(0 == ~T1_E~0); 1511590#L871-1 assume !(0 == ~T2_E~0); 1511591#L876-1 assume !(0 == ~T3_E~0); 1511961#L881-1 assume !(0 == ~T4_E~0); 1511609#L886-1 assume !(0 == ~T5_E~0); 1511315#L891-1 assume !(0 == ~T6_E~0); 1511316#L896-1 assume !(0 == ~T7_E~0); 1511599#L901-1 assume !(0 == ~T8_E~0); 1511626#L906-1 assume !(0 == ~E_M~0); 1511627#L911-1 assume !(0 == ~E_1~0); 1511375#L916-1 assume !(0 == ~E_2~0); 1511376#L921-1 assume !(0 == ~E_3~0); 1511752#L926-1 assume !(0 == ~E_4~0); 1511901#L931-1 assume !(0 == ~E_5~0); 1511968#L936-1 assume !(0 == ~E_6~0); 1511982#L941-1 assume !(0 == ~E_7~0); 1511381#L946-1 assume !(0 == ~E_8~0); 1511382#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1511935#L430 assume !(1 == ~m_pc~0); 1511212#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1511858#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1512033#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1511516#L1073 assume !(0 != activate_threads_~tmp~1#1); 1511517#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1511723#L449 assume !(1 == ~t1_pc~0); 1511007#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1511008#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1510857#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1510858#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1511644#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1511448#L468 assume !(1 == ~t2_pc~0); 1510815#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1511225#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1511219#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1511220#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1510830#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1510831#L487 assume !(1 == ~t3_pc~0); 1510937#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1510912#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1510811#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1510812#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1511294#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1511295#L506 assume !(1 == ~t4_pc~0); 1511438#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1511966#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1510898#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1510899#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1511431#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1511432#L525 assume !(1 == ~t5_pc~0); 1510863#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1510864#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1511813#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1511814#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1511069#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1511070#L544 assume !(1 == ~t6_pc~0); 1511228#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1511229#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1511662#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1510847#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1510848#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1511872#L563 assume !(1 == ~t7_pc~0); 1511657#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1511658#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1512011#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1512012#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1511011#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1511012#L582 assume !(1 == ~t8_pc~0); 1511663#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1511953#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1511954#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1512039#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1511153#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1511154#L964 assume !(1 == ~M_E~0); 1511949#L964-2 assume !(1 == ~T1_E~0); 1511950#L969-1 assume !(1 == ~T2_E~0); 1511909#L974-1 assume !(1 == ~T3_E~0); 1511910#L979-1 assume !(1 == ~T4_E~0); 1512017#L984-1 assume !(1 == ~T5_E~0); 1512018#L989-1 assume !(1 == ~T6_E~0); 1511602#L994-1 assume !(1 == ~T7_E~0); 1511106#L999-1 assume !(1 == ~T8_E~0); 1511107#L1004-1 assume !(1 == ~E_M~0); 1511735#L1009-1 assume !(1 == ~E_1~0); 1512036#L1014-1 assume !(1 == ~E_2~0); 1512035#L1019-1 assume !(1 == ~E_3~0); 1512034#L1024-1 assume !(1 == ~E_4~0); 1511030#L1029-1 assume !(1 == ~E_5~0); 1511031#L1034-1 assume !(1 == ~E_6~0); 1511119#L1039-1 assume !(1 == ~E_7~0); 1511920#L1044-1 assume !(1 == ~E_8~0); 1511340#L1049-1 assume { :end_inline_reset_delta_events } true; 1511341#L1315-2 [2024-11-23 02:54:38,077 INFO L747 eck$LassoCheckResult]: Loop: 1511341#L1315-2 assume !false; 1526955#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1521867#L841-1 assume !false; 1526952#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1526950#L662 assume !(0 == ~m_st~0); 1526948#L666 assume !(0 == ~t1_st~0); 1526946#L670 assume !(0 == ~t2_st~0); 1526944#L674 assume !(0 == ~t3_st~0); 1526942#L678 assume !(0 == ~t4_st~0); 1526940#L682 assume !(0 == ~t5_st~0); 1526938#L686 assume !(0 == ~t6_st~0); 1526936#L690 assume !(0 == ~t7_st~0); 1526933#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1526931#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1526929#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1526927#L724 assume !(0 != eval_~tmp~0#1); 1526925#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1526923#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1526920#L866-3 assume !(0 == ~M_E~0); 1526918#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1526916#L871-3 assume !(0 == ~T2_E~0); 1526914#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1526912#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1526910#L886-3 assume !(0 == ~T5_E~0); 1526900#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1526898#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1526896#L901-3 assume !(0 == ~T8_E~0); 1526895#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1526894#L911-3 assume !(0 == ~E_1~0); 1526893#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1526892#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1526891#L926-3 assume !(0 == ~E_4~0); 1526890#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1526889#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1526888#L941-3 assume !(0 == ~E_7~0); 1526887#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1526886#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1526885#L430-30 assume 1 == ~m_pc~0; 1526884#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1526882#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1526880#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1526877#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1526876#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1526875#L449-30 assume !(1 == ~t1_pc~0); 1526874#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1526872#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1526870#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1526868#L1081-30 assume !(0 != activate_threads_~tmp___0~0#1); 1526866#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1526864#L468-30 assume 1 == ~t2_pc~0; 1526861#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1526856#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1526851#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1526846#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1526842#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1526839#L487-30 assume !(1 == ~t3_pc~0); 1526836#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1526833#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1526830#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1526827#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1526824#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1526817#L506-30 assume 1 == ~t4_pc~0; 1526816#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1526810#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1526807#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1526804#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1526801#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1526798#L525-30 assume !(1 == ~t5_pc~0); 1526795#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1526792#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1526788#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1526784#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1526780#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1526775#L544-30 assume 1 == ~t6_pc~0; 1526770#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1526763#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1526758#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1526754#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1526750#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1526746#L563-30 assume !(1 == ~t7_pc~0); 1526438#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1526736#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1526730#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1526724#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1526717#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1526709#L582-30 assume !(1 == ~t8_pc~0); 1526701#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1526693#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1526685#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1526678#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1526671#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1526664#L964-3 assume !(1 == ~M_E~0); 1526656#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1526648#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1526639#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1526631#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1526624#L984-3 assume !(1 == ~T5_E~0); 1526616#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1526610#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1526603#L999-3 assume !(1 == ~T8_E~0); 1526597#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1526590#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1526583#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1526576#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1526568#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1526561#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1526556#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1526513#L1039-3 assume !(1 == ~E_7~0); 1526509#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1526502#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1526497#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1526487#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1526485#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1526482#L1334 assume !(0 == start_simulation_~tmp~3#1); 1526483#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1526977#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1526969#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1526967#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1526965#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1526963#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1526961#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1526959#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1511341#L1315-2 [2024-11-23 02:54:38,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:38,078 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 5 times [2024-11-23 02:54:38,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:38,078 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728531437] [2024-11-23 02:54:38,078 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-23 02:54:38,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:38,089 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:54:38,089 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:54:38,090 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:54:38,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:54:38,115 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:54:38,116 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:38,116 INFO L85 PathProgramCache]: Analyzing trace with hash 1293773938, now seen corresponding path program 1 times [2024-11-23 02:54:38,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:38,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321598565] [2024-11-23 02:54:38,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:38,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:38,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:38,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:38,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:38,181 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321598565] [2024-11-23 02:54:38,181 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321598565] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:38,181 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:38,181 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:38,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1244676427] [2024-11-23 02:54:38,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:38,182 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:38,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:38,183 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:54:38,183 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:54:38,183 INFO L87 Difference]: Start difference. First operand 87071 states and 118924 transitions. cyclomatic complexity: 31885 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:38,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:38,533 INFO L93 Difference]: Finished difference Result 88559 states and 119947 transitions. [2024-11-23 02:54:38,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88559 states and 119947 transitions. [2024-11-23 02:54:38,831 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 87952 [2024-11-23 02:54:39,829 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88559 states to 88559 states and 119947 transitions. [2024-11-23 02:54:39,829 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88559 [2024-11-23 02:54:39,891 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88559 [2024-11-23 02:54:39,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88559 states and 119947 transitions. [2024-11-23 02:54:39,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:39,932 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88559 states and 119947 transitions. [2024-11-23 02:54:39,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88559 states and 119947 transitions. [2024-11-23 02:54:40,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88559 to 88559. [2024-11-23 02:54:40,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88559 states, 88559 states have (on average 1.3544303797468353) internal successors, (119947), 88558 states have internal predecessors, (119947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:40,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88559 states to 88559 states and 119947 transitions. [2024-11-23 02:54:40,684 INFO L240 hiAutomatonCegarLoop]: Abstraction has 88559 states and 119947 transitions. [2024-11-23 02:54:40,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:54:40,684 INFO L425 stractBuchiCegarLoop]: Abstraction has 88559 states and 119947 transitions. [2024-11-23 02:54:40,684 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-23 02:54:40,684 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88559 states and 119947 transitions. [2024-11-23 02:54:41,412 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 87952 [2024-11-23 02:54:41,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:41,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:41,414 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:41,414 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:41,414 INFO L745 eck$LassoCheckResult]: Stem: 1686675#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1686676#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1687566#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1687567#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1687013#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1687014#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1686548#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1686549#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1686637#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1687546#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1686517#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1686518#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1686965#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1686999#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1686643#L866 assume !(0 == ~M_E~0); 1686644#L866-2 assume !(0 == ~T1_E~0); 1687232#L871-1 assume !(0 == ~T2_E~0); 1687233#L876-1 assume !(0 == ~T3_E~0); 1687644#L881-1 assume !(0 == ~T4_E~0); 1687258#L886-1 assume !(0 == ~T5_E~0); 1686952#L891-1 assume !(0 == ~T6_E~0); 1686953#L896-1 assume !(0 == ~T7_E~0); 1687241#L901-1 assume !(0 == ~T8_E~0); 1687278#L906-1 assume !(0 == ~E_M~0); 1687279#L911-1 assume !(0 == ~E_1~0); 1687010#L916-1 assume !(0 == ~E_2~0); 1687011#L921-1 assume !(0 == ~E_3~0); 1687407#L926-1 assume !(0 == ~E_4~0); 1687562#L931-1 assume !(0 == ~E_5~0); 1687657#L936-1 assume !(0 == ~E_6~0); 1687670#L941-1 assume !(0 == ~E_7~0); 1687015#L946-1 assume !(0 == ~E_8~0); 1687016#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1687602#L430 assume !(1 == ~m_pc~0); 1686841#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1687515#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1687729#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1687155#L1073 assume !(0 != activate_threads_~tmp~1#1); 1687156#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1687381#L449 assume !(1 == ~t1_pc~0); 1686649#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1686650#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1686490#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1686491#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1687293#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1687081#L468 assume !(1 == ~t2_pc~0); 1686453#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1686858#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1686851#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1686852#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1686466#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1686467#L487 assume !(1 == ~t3_pc~0); 1686579#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1686554#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1686449#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1686450#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1686930#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1686931#L506 assume !(1 == ~t4_pc~0); 1687075#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1687651#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1687715#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1687629#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1687630#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1686859#L525 assume !(1 == ~t5_pc~0); 1686860#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1687532#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1687533#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1687708#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1687709#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1687062#L544 assume !(1 == ~t6_pc~0); 1687063#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1687738#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1686829#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1686830#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1687613#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1687614#L563 assume !(1 == ~t7_pc~0); 1687737#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1686508#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1686509#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1686954#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1686955#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1687736#L582 assume !(1 == ~t8_pc~0); 1687684#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1687685#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1687392#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1686914#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1686915#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1687385#L964 assume !(1 == ~M_E~0); 1687386#L964-2 assume !(1 == ~T1_E~0); 1686712#L969-1 assume !(1 == ~T2_E~0); 1686713#L974-1 assume !(1 == ~T3_E~0); 1687432#L979-1 assume !(1 == ~T4_E~0); 1687433#L984-1 assume !(1 == ~T5_E~0); 1687706#L989-1 assume !(1 == ~T6_E~0); 1687249#L994-1 assume !(1 == ~T7_E~0); 1687250#L999-1 assume !(1 == ~T8_E~0); 1687390#L1004-1 assume !(1 == ~E_M~0); 1687391#L1009-1 assume !(1 == ~E_1~0); 1687733#L1014-1 assume !(1 == ~E_2~0); 1687732#L1019-1 assume !(1 == ~E_3~0); 1687731#L1024-1 assume !(1 == ~E_4~0); 1686672#L1029-1 assume !(1 == ~E_5~0); 1686673#L1034-1 assume !(1 == ~E_6~0); 1686761#L1039-1 assume !(1 == ~E_7~0); 1687589#L1044-1 assume !(1 == ~E_8~0); 1686975#L1049-1 assume { :end_inline_reset_delta_events } true; 1686976#L1315-2 [2024-11-23 02:54:41,417 INFO L747 eck$LassoCheckResult]: Loop: 1686976#L1315-2 assume !false; 1742106#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1742105#L841-1 assume !false; 1742104#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1739542#L662 assume !(0 == ~m_st~0); 1739543#L666 assume !(0 == ~t1_st~0); 1739546#L670 assume !(0 == ~t2_st~0); 1739540#L674 assume !(0 == ~t3_st~0); 1739541#L678 assume !(0 == ~t4_st~0); 1739545#L682 assume !(0 == ~t5_st~0); 1739538#L686 assume !(0 == ~t6_st~0); 1739539#L690 assume !(0 == ~t7_st~0); 1739544#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1739547#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1755043#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1755041#L724 assume !(0 != eval_~tmp~0#1); 1755037#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1755035#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1755033#L866-3 assume !(0 == ~M_E~0); 1755031#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1755029#L871-3 assume !(0 == ~T2_E~0); 1755026#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1755024#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1755022#L886-3 assume !(0 == ~T5_E~0); 1755020#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1755018#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1755015#L901-3 assume !(0 == ~T8_E~0); 1755012#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1755010#L911-3 assume !(0 == ~E_1~0); 1755008#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1755006#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1755004#L926-3 assume !(0 == ~E_4~0); 1755002#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1754999#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1754997#L941-3 assume !(0 == ~E_7~0); 1754995#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1754993#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1754991#L430-30 assume !(1 == ~m_pc~0); 1754988#L430-32 is_master_triggered_~__retres1~0#1 := 0; 1754984#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1754982#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1754980#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 1754978#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1754975#L449-30 assume !(1 == ~t1_pc~0); 1754971#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1754967#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1754962#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1754960#L1081-30 assume !(0 != activate_threads_~tmp___0~0#1); 1754958#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1754957#L468-30 assume 1 == ~t2_pc~0; 1754955#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1754953#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1754951#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1754950#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1754948#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1754947#L487-30 assume !(1 == ~t3_pc~0); 1754946#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1754945#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1754944#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1754933#L1097-30 assume !(0 != activate_threads_~tmp___2~0#1); 1754931#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1754929#L506-30 assume !(1 == ~t4_pc~0); 1754925#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1754923#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1754921#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1754919#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1754917#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1754915#L525-30 assume !(1 == ~t5_pc~0); 1754913#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1754911#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1754909#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1754907#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1754905#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1754903#L544-30 assume !(1 == ~t6_pc~0); 1754899#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1754897#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1754895#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1754893#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1754891#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1742287#L563-30 assume !(1 == ~t7_pc~0); 1742284#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1742280#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1742279#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1742278#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1742277#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1742276#L582-30 assume !(1 == ~t8_pc~0); 1742275#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1742274#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1742273#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1742272#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1742271#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1742270#L964-3 assume !(1 == ~M_E~0); 1742269#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1742268#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1742267#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1742266#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1742264#L984-3 assume !(1 == ~T5_E~0); 1742263#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1742262#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1742261#L999-3 assume !(1 == ~T8_E~0); 1742257#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1742255#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1742253#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1742251#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1742174#L1024-3 assume !(1 == ~E_4~0); 1742172#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1742171#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1742169#L1039-3 assume !(1 == ~E_7~0); 1742167#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1742165#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1742163#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1742153#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1742151#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1742148#L1334 assume !(0 == start_simulation_~tmp~3#1); 1742146#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1742134#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1742124#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1742120#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1742115#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1742113#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1742111#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1742110#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1686976#L1315-2 [2024-11-23 02:54:41,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:41,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 6 times [2024-11-23 02:54:41,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:41,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978006631] [2024-11-23 02:54:41,419 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-23 02:54:41,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:41,441 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2024-11-23 02:54:41,442 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:54:41,445 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:54:41,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:54:41,494 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:54:41,495 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:41,497 INFO L85 PathProgramCache]: Analyzing trace with hash -896056585, now seen corresponding path program 1 times [2024-11-23 02:54:41,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:41,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147657979] [2024-11-23 02:54:41,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:41,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:41,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:41,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:41,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:41,532 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147657979] [2024-11-23 02:54:41,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1147657979] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:41,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:41,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:54:41,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638286800] [2024-11-23 02:54:41,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:41,532 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:41,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:41,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:54:41,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:54:41,534 INFO L87 Difference]: Start difference. First operand 88559 states and 119947 transitions. cyclomatic complexity: 31420 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:41,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:41,893 INFO L93 Difference]: Finished difference Result 167999 states and 224763 transitions. [2024-11-23 02:54:41,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 167999 states and 224763 transitions. [2024-11-23 02:54:42,516 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 166944 [2024-11-23 02:54:43,704 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 167999 states to 167999 states and 224763 transitions. [2024-11-23 02:54:43,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 167999 [2024-11-23 02:54:43,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 167999 [2024-11-23 02:54:43,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 167999 states and 224763 transitions. [2024-11-23 02:54:43,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:43,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 167999 states and 224763 transitions. [2024-11-23 02:54:43,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167999 states and 224763 transitions. [2024-11-23 02:54:45,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167999 to 160127. [2024-11-23 02:54:45,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 160127 states, 160127 states have (on average 1.340904407126843) internal successors, (214715), 160126 states have internal predecessors, (214715), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:46,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160127 states to 160127 states and 214715 transitions. [2024-11-23 02:54:46,250 INFO L240 hiAutomatonCegarLoop]: Abstraction has 160127 states and 214715 transitions. [2024-11-23 02:54:46,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:54:46,251 INFO L425 stractBuchiCegarLoop]: Abstraction has 160127 states and 214715 transitions. [2024-11-23 02:54:46,251 INFO L332 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-23 02:54:46,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 160127 states and 214715 transitions. [2024-11-23 02:54:46,632 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 159072 [2024-11-23 02:54:46,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:54:46,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:54:46,633 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:46,633 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:54:46,633 INFO L745 eck$LassoCheckResult]: Stem: 1943240#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1943241#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1944145#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1944146#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1943582#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1943583#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1943112#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1943113#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1943201#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1944115#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1943080#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1943081#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1943534#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1943568#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1943208#L866 assume !(0 == ~M_E~0); 1943209#L866-2 assume !(0 == ~T1_E~0); 1943805#L871-1 assume !(0 == ~T2_E~0); 1943806#L876-1 assume !(0 == ~T3_E~0); 1944215#L881-1 assume !(0 == ~T4_E~0); 1943824#L886-1 assume !(0 == ~T5_E~0); 1943520#L891-1 assume !(0 == ~T6_E~0); 1943521#L896-1 assume !(0 == ~T7_E~0); 1943814#L901-1 assume !(0 == ~T8_E~0); 1943844#L906-1 assume !(0 == ~E_M~0); 1943845#L911-1 assume !(0 == ~E_1~0); 1943579#L916-1 assume !(0 == ~E_2~0); 1943580#L921-1 assume !(0 == ~E_3~0); 1943975#L926-1 assume !(0 == ~E_4~0); 1944141#L931-1 assume !(0 == ~E_5~0); 1944227#L936-1 assume !(0 == ~E_6~0); 1944243#L941-1 assume !(0 == ~E_7~0); 1943585#L946-1 assume !(0 == ~E_8~0); 1943586#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1944179#L430 assume !(1 == ~m_pc~0); 1943413#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1944086#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1944313#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1943725#L1073 assume !(0 != activate_threads_~tmp~1#1); 1943726#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1943947#L449 assume !(1 == ~t1_pc~0); 1943213#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1943214#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1943059#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1943060#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1943861#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1943654#L468 assume !(1 == ~t2_pc~0); 1943017#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1943427#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1943420#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1943421#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1943032#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1943033#L487 assume !(1 == ~t3_pc~0); 1943141#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1943116#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1943013#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1943014#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1943497#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1943498#L506 assume !(1 == ~t4_pc~0); 1943643#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1944224#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1943102#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1943103#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1943638#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1943639#L525 assume !(1 == ~t5_pc~0); 1943066#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1943067#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1944040#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1944041#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1943271#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1943272#L544 assume !(1 == ~t6_pc~0); 1943430#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1943431#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1943878#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1943049#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1943050#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1944102#L563 assume !(1 == ~t7_pc~0); 1943873#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1943874#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1944274#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1944275#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1943217#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1943218#L582 assume !(1 == ~t8_pc~0); 1943879#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1944210#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1944211#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1944319#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1943356#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1943357#L964 assume !(1 == ~M_E~0); 1944203#L964-2 assume !(1 == ~T1_E~0); 1944204#L969-1 assume !(1 == ~T2_E~0); 1944150#L974-1 assume !(1 == ~T3_E~0); 1944151#L979-1 assume !(1 == ~T4_E~0); 1944285#L984-1 assume !(1 == ~T5_E~0); 1944286#L989-1 assume !(1 == ~T6_E~0); 1943818#L994-1 assume !(1 == ~T7_E~0); 1943311#L999-1 assume !(1 == ~T8_E~0); 1943312#L1004-1 assume !(1 == ~E_M~0); 1943959#L1009-1 assume !(1 == ~E_1~0); 1944316#L1014-1 assume !(1 == ~E_2~0); 1944315#L1019-1 assume !(1 == ~E_3~0); 1944314#L1024-1 assume !(1 == ~E_4~0); 1943237#L1029-1 assume !(1 == ~E_5~0); 1943238#L1034-1 assume !(1 == ~E_6~0); 1943322#L1039-1 assume !(1 == ~E_7~0); 1944162#L1044-1 assume !(1 == ~E_8~0); 1943544#L1049-1 assume { :end_inline_reset_delta_events } true; 1943545#L1315-2 [2024-11-23 02:54:46,634 INFO L747 eck$LassoCheckResult]: Loop: 1943545#L1315-2 assume !false; 1984693#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1984691#L841-1 assume !false; 1984688#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1984685#L662 assume !(0 == ~m_st~0); 1984686#L666 assume !(0 == ~t1_st~0); 1986066#L670 assume !(0 == ~t2_st~0); 1986064#L674 assume !(0 == ~t3_st~0); 1986062#L678 assume !(0 == ~t4_st~0); 1986060#L682 assume !(0 == ~t5_st~0); 1986058#L686 assume !(0 == ~t6_st~0); 1986056#L690 assume !(0 == ~t7_st~0); 1986053#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1986050#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1986048#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1986046#L724 assume !(0 != eval_~tmp~0#1); 1986043#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1986041#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1986039#L866-3 assume !(0 == ~M_E~0); 1986037#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1986035#L871-3 assume !(0 == ~T2_E~0); 1986033#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1986031#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1986029#L886-3 assume !(0 == ~T5_E~0); 1986027#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1986025#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1986023#L901-3 assume !(0 == ~T8_E~0); 1986021#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1986019#L911-3 assume !(0 == ~E_1~0); 1986017#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1986015#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1986013#L926-3 assume !(0 == ~E_4~0); 1986011#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1986009#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1986007#L941-3 assume !(0 == ~E_7~0); 1986005#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1986003#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1986001#L430-30 assume 1 == ~m_pc~0; 1985998#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1985995#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1985993#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1985990#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1985987#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1985985#L449-30 assume !(1 == ~t1_pc~0); 1985983#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1985981#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1985979#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1985977#L1081-30 assume !(0 != activate_threads_~tmp___0~0#1); 1985975#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1985973#L468-30 assume 1 == ~t2_pc~0; 1985970#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1985967#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1985965#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1985963#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1985959#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1985957#L487-30 assume !(1 == ~t3_pc~0); 1985955#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1985953#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1985951#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1985949#L1097-30 assume !(0 != activate_threads_~tmp___2~0#1); 1985947#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1985945#L506-30 assume 1 == ~t4_pc~0; 1985944#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1985938#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1985936#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1985934#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1985932#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1985930#L525-30 assume !(1 == ~t5_pc~0); 1985928#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1985926#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1985924#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1985922#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1985920#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1985918#L544-30 assume !(1 == ~t6_pc~0); 1985914#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1985912#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1985910#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1985908#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1985906#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1985904#L563-30 assume !(1 == ~t7_pc~0); 1985341#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1985902#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1985900#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1985898#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1985896#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1985894#L582-30 assume !(1 == ~t8_pc~0); 1985892#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1985890#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1985888#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1985886#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1985884#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1985882#L964-3 assume !(1 == ~M_E~0); 1985880#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1985878#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1985876#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1985874#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1985872#L984-3 assume !(1 == ~T5_E~0); 1985870#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1985868#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1985866#L999-3 assume !(1 == ~T8_E~0); 1985864#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1985862#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1985860#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1985858#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1985857#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1985855#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1985854#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1985853#L1039-3 assume !(1 == ~E_7~0); 1985851#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1985850#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1985848#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1985846#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1985845#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1985843#L1334 assume !(0 == start_simulation_~tmp~3#1); 1985842#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1985840#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1985838#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1985837#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1985836#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1985834#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1985833#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1985832#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1943545#L1315-2 [2024-11-23 02:54:46,634 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:46,634 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 7 times [2024-11-23 02:54:46,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:46,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886645050] [2024-11-23 02:54:46,635 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-23 02:54:46,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:46,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:54:46,644 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:54:46,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:54:46,681 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:54:46,682 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:54:46,682 INFO L85 PathProgramCache]: Analyzing trace with hash -1950386635, now seen corresponding path program 1 times [2024-11-23 02:54:46,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:54:46,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445445276] [2024-11-23 02:54:46,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:54:46,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:54:46,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:54:46,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:54:46,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:54:46,751 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445445276] [2024-11-23 02:54:46,752 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445445276] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:54:46,752 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:54:46,752 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:54:46,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380732334] [2024-11-23 02:54:46,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:54:46,753 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:54:46,753 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:54:46,753 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:54:46,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:54:46,754 INFO L87 Difference]: Start difference. First operand 160127 states and 214715 transitions. cyclomatic complexity: 54620 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:48,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:54:48,027 INFO L93 Difference]: Finished difference Result 163103 states and 216825 transitions. [2024-11-23 02:54:48,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 163103 states and 216825 transitions. [2024-11-23 02:54:48,643 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 162048 [2024-11-23 02:54:48,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 163103 states to 163103 states and 216825 transitions. [2024-11-23 02:54:48,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 163103 [2024-11-23 02:54:48,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 163103 [2024-11-23 02:54:48,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 163103 states and 216825 transitions. [2024-11-23 02:54:49,031 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:54:49,031 INFO L218 hiAutomatonCegarLoop]: Abstraction has 163103 states and 216825 transitions. [2024-11-23 02:54:49,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163103 states and 216825 transitions. [2024-11-23 02:54:50,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163103 to 163103. [2024-11-23 02:54:50,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 163103 states, 163103 states have (on average 1.3293746896133118) internal successors, (216825), 163102 states have internal predecessors, (216825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:54:51,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163103 states to 163103 states and 216825 transitions. [2024-11-23 02:54:51,055 INFO L240 hiAutomatonCegarLoop]: Abstraction has 163103 states and 216825 transitions. [2024-11-23 02:54:51,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:54:51,056 INFO L425 stractBuchiCegarLoop]: Abstraction has 163103 states and 216825 transitions. [2024-11-23 02:54:51,056 INFO L332 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-23 02:54:51,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163103 states and 216825 transitions.