./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 803cd42f Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-assert-order-craig-803cd42-m [2024-11-23 02:55:16,246 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-23 02:55:16,323 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-23 02:55:16,330 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-23 02:55:16,332 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-23 02:55:16,361 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-23 02:55:16,363 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-23 02:55:16,364 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-23 02:55:16,365 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-23 02:55:16,366 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-23 02:55:16,367 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-23 02:55:16,367 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-23 02:55:16,368 INFO L153 SettingsManager]: * Use SBE=true [2024-11-23 02:55:16,368 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-23 02:55:16,368 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-23 02:55:16,369 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-23 02:55:16,369 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-23 02:55:16,371 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-23 02:55:16,371 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-23 02:55:16,372 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-23 02:55:16,375 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-23 02:55:16,375 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-23 02:55:16,376 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-23 02:55:16,376 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-23 02:55:16,376 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-23 02:55:16,377 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-23 02:55:16,377 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-23 02:55:16,377 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-23 02:55:16,377 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-23 02:55:16,378 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-23 02:55:16,378 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-23 02:55:16,378 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-23 02:55:16,378 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-23 02:55:16,379 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-23 02:55:16,379 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-23 02:55:16,379 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-23 02:55:16,380 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-23 02:55:16,380 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-23 02:55:16,380 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-23 02:55:16,381 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2024-11-23 02:55:16,665 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-23 02:55:16,693 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-23 02:55:16,697 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-23 02:55:16,699 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-23 02:55:16,700 INFO L274 PluginConnector]: CDTParser initialized [2024-11-23 02:55:16,701 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.02.cil.c [2024-11-23 02:55:18,118 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-23 02:55:18,351 INFO L384 CDTParser]: Found 1 translation units. [2024-11-23 02:55:18,352 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c [2024-11-23 02:55:18,365 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d5a03afe3/e1f76dc4d0dd41ed887b251ca5fbeddb/FLAG40f1aad7b [2024-11-23 02:55:18,384 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d5a03afe3/e1f76dc4d0dd41ed887b251ca5fbeddb [2024-11-23 02:55:18,388 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-23 02:55:18,390 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-23 02:55:18,393 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-23 02:55:18,394 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-23 02:55:18,400 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-23 02:55:18,401 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,402 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@350ff81b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18, skipping insertion in model container [2024-11-23 02:55:18,402 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,441 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-23 02:55:18,702 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-23 02:55:18,714 INFO L200 MainTranslator]: Completed pre-run [2024-11-23 02:55:18,747 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-23 02:55:18,794 INFO L204 MainTranslator]: Completed translation [2024-11-23 02:55:18,795 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18 WrapperNode [2024-11-23 02:55:18,795 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-23 02:55:18,797 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-23 02:55:18,797 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-23 02:55:18,797 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-23 02:55:18,805 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,814 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,854 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 45, statements flattened = 536 [2024-11-23 02:55:18,854 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-23 02:55:18,855 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-23 02:55:18,855 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-23 02:55:18,855 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-23 02:55:18,867 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,868 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,877 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,907 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-23 02:55:18,908 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,908 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,915 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,929 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,931 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,932 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,936 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-23 02:55:18,937 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-23 02:55:18,937 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-23 02:55:18,937 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-23 02:55:18,938 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (1/1) ... [2024-11-23 02:55:18,944 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:18,960 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:18,977 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:18,980 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-23 02:55:19,024 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-23 02:55:19,024 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-23 02:55:19,024 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-23 02:55:19,024 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-23 02:55:19,089 INFO L238 CfgBuilder]: Building ICFG [2024-11-23 02:55:19,091 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-23 02:55:19,630 INFO L? ?]: Removed 90 outVars from TransFormulas that were not future-live. [2024-11-23 02:55:19,631 INFO L287 CfgBuilder]: Performing block encoding [2024-11-23 02:55:19,653 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-23 02:55:19,654 INFO L316 CfgBuilder]: Removed 6 assume(true) statements. [2024-11-23 02:55:19,655 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:55:19 BoogieIcfgContainer [2024-11-23 02:55:19,655 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-23 02:55:19,656 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-23 02:55:19,656 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-23 02:55:19,660 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-23 02:55:19,660 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:55:19,661 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 02:55:18" (1/3) ... [2024-11-23 02:55:19,662 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bb1f9af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:55:19, skipping insertion in model container [2024-11-23 02:55:19,662 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:55:19,662 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:18" (2/3) ... [2024-11-23 02:55:19,662 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bb1f9af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:55:19, skipping insertion in model container [2024-11-23 02:55:19,663 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:55:19,663 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:55:19" (3/3) ... [2024-11-23 02:55:19,664 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2024-11-23 02:55:19,721 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-23 02:55:19,721 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-23 02:55:19,721 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-23 02:55:19,721 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-23 02:55:19,722 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-23 02:55:19,722 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-23 02:55:19,723 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-23 02:55:19,723 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-23 02:55:19,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:19,768 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2024-11-23 02:55:19,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:19,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:19,783 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:19,784 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:19,785 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-23 02:55:19,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:19,794 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2024-11-23 02:55:19,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:19,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:19,797 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:19,798 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:19,804 INFO L745 eck$LassoCheckResult]: Stem: 147#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 158#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 205#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 155#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 182#L221true assume !(1 == ~m_i~0);~m_st~0 := 2; 60#L221-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 42#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 162#L231-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33#L334true assume !(0 == ~M_E~0); 169#L334-2true assume !(0 == ~T1_E~0); 113#L339-1true assume !(0 == ~T2_E~0); 108#L344-1true assume 0 == ~E_1~0;~E_1~0 := 1; 143#L349-1true assume !(0 == ~E_2~0); 41#L354-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117#L156true assume !(1 == ~m_pc~0); 154#L156-2true is_master_triggered_~__retres1~0#1 := 0; 136#L167true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128#is_master_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 78#L405true assume !(0 != activate_threads_~tmp~1#1); 63#L405-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126#L175true assume 1 == ~t1_pc~0; 161#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64#L186true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 115#L413true assume !(0 != activate_threads_~tmp___0~0#1); 185#L413-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187#L194true assume !(1 == ~t2_pc~0); 203#L194-2true is_transmit2_triggered_~__retres1~2#1 := 0; 70#L205true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27#L421true assume !(0 != activate_threads_~tmp___1~0#1); 85#L421-2true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12#L367true assume !(1 == ~M_E~0); 186#L367-2true assume !(1 == ~T1_E~0); 130#L372-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 132#L377-1true assume !(1 == ~E_1~0); 25#L382-1true assume !(1 == ~E_2~0); 80#L387-1true assume { :end_inline_reset_delta_events } true; 107#L528-2true [2024-11-23 02:55:19,806 INFO L747 eck$LassoCheckResult]: Loop: 107#L528-2true assume !false; 88#L529true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17#L309-1true assume false; 82#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 207#L334-3true assume 0 == ~M_E~0;~M_E~0 := 1; 159#L334-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 116#L339-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 183#L344-3true assume 0 == ~E_1~0;~E_1~0 := 1; 76#L349-3true assume !(0 == ~E_2~0); 32#L354-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101#L156-9true assume !(1 == ~m_pc~0); 4#L156-11true is_master_triggered_~__retres1~0#1 := 0; 57#L167-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135#is_master_triggered_returnLabel#4true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 118#L405-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21#L405-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192#L175-9true assume !(1 == ~t1_pc~0); 141#L175-11true is_transmit1_triggered_~__retres1~1#1 := 0; 14#L186-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201#is_transmit1_triggered_returnLabel#4true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 153#L413-9true assume !(0 != activate_threads_~tmp___0~0#1); 146#L413-11true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190#L194-9true assume !(1 == ~t2_pc~0); 28#L194-11true is_transmit2_triggered_~__retres1~2#1 := 0; 196#L205-3true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5#is_transmit2_triggered_returnLabel#4true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 110#L421-9true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 144#L421-11true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54#L367-3true assume 1 == ~M_E~0;~M_E~0 := 2; 7#L367-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 34#L372-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 18#L377-3true assume !(1 == ~E_1~0); 30#L382-3true assume 1 == ~E_2~0;~E_2~0 := 2; 111#L387-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 145#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 180#L261-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 188#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 152#L547true assume !(0 == start_simulation_~tmp~3#1); 166#L547-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 149#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 52#L261-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 37#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 40#L502true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49#L509true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 20#L560true assume !(0 != start_simulation_~tmp___0~1#1); 107#L528-2true [2024-11-23 02:55:19,812 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:19,812 INFO L85 PathProgramCache]: Analyzing trace with hash -886407522, now seen corresponding path program 1 times [2024-11-23 02:55:19,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:19,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230501776] [2024-11-23 02:55:19,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:19,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:19,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:20,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:20,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:20,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230501776] [2024-11-23 02:55:20,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230501776] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:20,046 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:20,046 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:20,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1480682815] [2024-11-23 02:55:20,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:20,051 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:20,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:20,052 INFO L85 PathProgramCache]: Analyzing trace with hash -294698413, now seen corresponding path program 1 times [2024-11-23 02:55:20,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:20,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201770802] [2024-11-23 02:55:20,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:20,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:20,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:20,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:20,094 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:20,094 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201770802] [2024-11-23 02:55:20,094 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201770802] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:20,094 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:20,094 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:20,094 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [165769049] [2024-11-23 02:55:20,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:20,096 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:20,096 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:20,123 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:20,124 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:20,126 INFO L87 Difference]: Start difference. First operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:20,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:20,165 INFO L93 Difference]: Finished difference Result 207 states and 302 transitions. [2024-11-23 02:55:20,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 207 states and 302 transitions. [2024-11-23 02:55:20,176 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-11-23 02:55:20,186 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 207 states to 201 states and 296 transitions. [2024-11-23 02:55:20,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2024-11-23 02:55:20,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2024-11-23 02:55:20,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 296 transitions. [2024-11-23 02:55:20,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:20,192 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2024-11-23 02:55:20,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 296 transitions. [2024-11-23 02:55:20,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2024-11-23 02:55:20,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.472636815920398) internal successors, (296), 200 states have internal predecessors, (296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:20,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 296 transitions. [2024-11-23 02:55:20,226 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2024-11-23 02:55:20,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:20,232 INFO L425 stractBuchiCegarLoop]: Abstraction has 201 states and 296 transitions. [2024-11-23 02:55:20,233 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-23 02:55:20,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 296 transitions. [2024-11-23 02:55:20,235 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-11-23 02:55:20,235 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:20,235 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:20,237 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:20,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:20,237 INFO L745 eck$LassoCheckResult]: Stem: 608#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 617#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 616#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 530#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 505#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 506#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 489#L334 assume !(0 == ~M_E~0); 490#L334-2 assume !(0 == ~T1_E~0); 585#L339-1 assume !(0 == ~T2_E~0); 579#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 580#L349-1 assume !(0 == ~E_2~0); 503#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 504#L156 assume !(1 == ~m_pc~0); 436#L156-2 is_master_triggered_~__retres1~0#1 := 0; 435#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 597#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 552#L405 assume !(0 != activate_threads_~tmp~1#1); 534#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 535#L175 assume 1 == ~t1_pc~0; 594#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 536#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 500#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 501#L413 assume !(0 != activate_threads_~tmp___0~0#1); 587#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 624#L194 assume !(1 == ~t2_pc~0); 578#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 546#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 478#L421 assume !(0 != activate_threads_~tmp___1~0#1); 479#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 448#L367 assume !(1 == ~M_E~0); 449#L367-2 assume !(1 == ~T1_E~0); 598#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 599#L377-1 assume !(1 == ~E_1~0); 475#L382-1 assume !(1 == ~E_2~0); 476#L387-1 assume { :end_inline_reset_delta_events } true; 465#L528-2 [2024-11-23 02:55:20,238 INFO L747 eck$LassoCheckResult]: Loop: 465#L528-2 assume !false; 559#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 458#L309-1 assume !false; 459#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 439#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 440#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 447#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 425#L276 assume !(0 != eval_~tmp~0#1); 427#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 584#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 618#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 588#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 589#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 551#L349-3 assume !(0 == ~E_2~0); 487#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 488#L156-9 assume 1 == ~m_pc~0; 573#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 431#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 527#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 590#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 466#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 467#L175-9 assume 1 == ~t1_pc~0; 512#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 452#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 453#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 614#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 606#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607#L194-9 assume !(1 == ~t2_pc~0); 480#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 481#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 432#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 433#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 582#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 523#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 437#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 438#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 460#L377-3 assume !(1 == ~E_1~0); 461#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 484#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 583#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 492#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 623#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 613#L547 assume !(0 == start_simulation_~tmp~3#1); 600#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 610#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 521#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 495#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 496#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 502#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 517#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 464#L560 assume !(0 != start_simulation_~tmp___0~1#1); 465#L528-2 [2024-11-23 02:55:20,239 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:20,239 INFO L85 PathProgramCache]: Analyzing trace with hash 1357575776, now seen corresponding path program 1 times [2024-11-23 02:55:20,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:20,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233928182] [2024-11-23 02:55:20,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:20,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:20,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:20,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:20,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:20,368 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233928182] [2024-11-23 02:55:20,368 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [233928182] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:20,368 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:20,368 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:20,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [200491477] [2024-11-23 02:55:20,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:20,369 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:20,370 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:20,370 INFO L85 PathProgramCache]: Analyzing trace with hash -724130786, now seen corresponding path program 1 times [2024-11-23 02:55:20,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:20,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525783572] [2024-11-23 02:55:20,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:20,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:20,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:20,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:20,460 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:20,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1525783572] [2024-11-23 02:55:20,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1525783572] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:20,461 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:20,461 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:20,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1087991206] [2024-11-23 02:55:20,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:20,462 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:20,462 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:20,462 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:20,462 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:20,463 INFO L87 Difference]: Start difference. First operand 201 states and 296 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:20,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:20,489 INFO L93 Difference]: Finished difference Result 201 states and 295 transitions. [2024-11-23 02:55:20,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201 states and 295 transitions. [2024-11-23 02:55:20,491 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-11-23 02:55:20,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201 states to 201 states and 295 transitions. [2024-11-23 02:55:20,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2024-11-23 02:55:20,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2024-11-23 02:55:20,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 295 transitions. [2024-11-23 02:55:20,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:20,495 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2024-11-23 02:55:20,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 295 transitions. [2024-11-23 02:55:20,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2024-11-23 02:55:20,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.4676616915422886) internal successors, (295), 200 states have internal predecessors, (295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:20,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 295 transitions. [2024-11-23 02:55:20,502 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2024-11-23 02:55:20,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:20,503 INFO L425 stractBuchiCegarLoop]: Abstraction has 201 states and 295 transitions. [2024-11-23 02:55:20,504 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-23 02:55:20,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 295 transitions. [2024-11-23 02:55:20,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-11-23 02:55:20,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:20,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:20,509 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:20,509 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:20,509 INFO L745 eck$LassoCheckResult]: Stem: 1017#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1025#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 939#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 914#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 915#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 898#L334 assume !(0 == ~M_E~0); 899#L334-2 assume !(0 == ~T1_E~0); 994#L339-1 assume !(0 == ~T2_E~0); 988#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 989#L349-1 assume !(0 == ~E_2~0); 912#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 913#L156 assume !(1 == ~m_pc~0); 845#L156-2 is_master_triggered_~__retres1~0#1 := 0; 844#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1006#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 961#L405 assume !(0 != activate_threads_~tmp~1#1); 943#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 944#L175 assume 1 == ~t1_pc~0; 1003#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 945#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 909#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 910#L413 assume !(0 != activate_threads_~tmp___0~0#1); 996#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1033#L194 assume !(1 == ~t2_pc~0); 987#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 955#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 887#L421 assume !(0 != activate_threads_~tmp___1~0#1); 888#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 857#L367 assume !(1 == ~M_E~0); 858#L367-2 assume !(1 == ~T1_E~0); 1007#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1008#L377-1 assume !(1 == ~E_1~0); 884#L382-1 assume !(1 == ~E_2~0); 885#L387-1 assume { :end_inline_reset_delta_events } true; 874#L528-2 [2024-11-23 02:55:20,509 INFO L747 eck$LassoCheckResult]: Loop: 874#L528-2 assume !false; 968#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 867#L309-1 assume !false; 868#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 848#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 849#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 856#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 834#L276 assume !(0 != eval_~tmp~0#1); 836#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 964#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 993#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1027#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 997#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 998#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 960#L349-3 assume !(0 == ~E_2~0); 896#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 897#L156-9 assume 1 == ~m_pc~0; 982#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 840#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 936#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 999#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 875#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 876#L175-9 assume 1 == ~t1_pc~0; 921#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 861#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 862#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1023#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 1015#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1016#L194-9 assume 1 == ~t2_pc~0; 963#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 890#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 841#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 842#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 991#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 932#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 846#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 847#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 869#L377-3 assume !(1 == ~E_1~0); 870#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 893#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 992#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 901#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1032#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1022#L547 assume !(0 == start_simulation_~tmp~3#1); 1009#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1019#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 930#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 904#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 905#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 911#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 926#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 873#L560 assume !(0 != start_simulation_~tmp___0~1#1); 874#L528-2 [2024-11-23 02:55:20,510 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:20,510 INFO L85 PathProgramCache]: Analyzing trace with hash 1082816162, now seen corresponding path program 1 times [2024-11-23 02:55:20,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:20,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435313923] [2024-11-23 02:55:20,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:20,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:20,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:20,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:20,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:20,614 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435313923] [2024-11-23 02:55:20,614 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435313923] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:20,614 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:20,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:20,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1057746804] [2024-11-23 02:55:20,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:20,616 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:20,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:20,617 INFO L85 PathProgramCache]: Analyzing trace with hash 866264191, now seen corresponding path program 1 times [2024-11-23 02:55:20,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:20,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828638425] [2024-11-23 02:55:20,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:20,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:20,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:20,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:20,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:20,684 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828638425] [2024-11-23 02:55:20,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [828638425] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:20,684 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:20,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:20,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [470072068] [2024-11-23 02:55:20,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:20,686 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:20,686 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:20,686 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:55:20,687 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:55:20,688 INFO L87 Difference]: Start difference. First operand 201 states and 295 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:20,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:20,820 INFO L93 Difference]: Finished difference Result 342 states and 498 transitions. [2024-11-23 02:55:20,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 498 transitions. [2024-11-23 02:55:20,823 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2024-11-23 02:55:20,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 498 transitions. [2024-11-23 02:55:20,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 342 [2024-11-23 02:55:20,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 342 [2024-11-23 02:55:20,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 498 transitions. [2024-11-23 02:55:20,829 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:20,829 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 498 transitions. [2024-11-23 02:55:20,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 498 transitions. [2024-11-23 02:55:20,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 340. [2024-11-23 02:55:20,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 340 states, 340 states have (on average 1.4588235294117646) internal successors, (496), 339 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:20,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 496 transitions. [2024-11-23 02:55:20,843 INFO L240 hiAutomatonCegarLoop]: Abstraction has 340 states and 496 transitions. [2024-11-23 02:55:20,844 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:55:20,844 INFO L425 stractBuchiCegarLoop]: Abstraction has 340 states and 496 transitions. [2024-11-23 02:55:20,845 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-23 02:55:20,845 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 340 states and 496 transitions. [2024-11-23 02:55:20,847 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2024-11-23 02:55:20,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:20,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:20,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:20,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:20,848 INFO L745 eck$LassoCheckResult]: Stem: 1591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1602#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1599#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1600#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1501#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1472#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1473#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1454#L334 assume !(0 == ~M_E~0); 1455#L334-2 assume !(0 == ~T1_E~0); 1561#L339-1 assume !(0 == ~T2_E~0); 1554#L344-1 assume !(0 == ~E_1~0); 1555#L349-1 assume !(0 == ~E_2~0); 1470#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1471#L156 assume !(1 == ~m_pc~0); 1398#L156-2 is_master_triggered_~__retres1~0#1 := 0; 1397#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1578#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1525#L405 assume !(0 != activate_threads_~tmp~1#1); 1505#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1506#L175 assume 1 == ~t1_pc~0; 1575#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1507#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1466#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1467#L413 assume !(0 != activate_threads_~tmp___0~0#1); 1563#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1612#L194 assume !(1 == ~t2_pc~0); 1552#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1517#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1442#L421 assume !(0 != activate_threads_~tmp___1~0#1); 1443#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1411#L367 assume !(1 == ~M_E~0); 1412#L367-2 assume !(1 == ~T1_E~0); 1579#L372-1 assume !(1 == ~T2_E~0); 1580#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1439#L382-1 assume !(1 == ~E_2~0); 1440#L387-1 assume { :end_inline_reset_delta_events } true; 1429#L528-2 [2024-11-23 02:55:20,848 INFO L747 eck$LassoCheckResult]: Loop: 1429#L528-2 assume !false; 1553#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1421#L309-1 assume !false; 1422#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1401#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1402#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1409#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1410#L276 assume !(0 != eval_~tmp~0#1); 1528#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1529#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1619#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1603#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1604#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1620#L344-3 assume !(0 == ~E_1~0); 1695#L349-3 assume !(0 == ~E_2~0); 1694#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1693#L156-9 assume !(1 == ~m_pc~0); 1691#L156-11 is_master_triggered_~__retres1~0#1 := 0; 1690#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1689#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1688#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1687#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1686#L175-9 assume 1 == ~t1_pc~0; 1481#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1415#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1416#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1598#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 1589#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1590#L194-9 assume 1 == ~t2_pc~0; 1613#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1680#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1679#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1678#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1677#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1676#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1675#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1674#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L377-3 assume !(1 == ~E_1~0); 1425#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1673#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1672#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1669#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1668#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1666#L547 assume !(0 == start_simulation_~tmp~3#1); 1664#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1593#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1595#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1462#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1486#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1487#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1428#L560 assume !(0 != start_simulation_~tmp___0~1#1); 1429#L528-2 [2024-11-23 02:55:20,849 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:20,849 INFO L85 PathProgramCache]: Analyzing trace with hash -1288865440, now seen corresponding path program 1 times [2024-11-23 02:55:20,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:20,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69012622] [2024-11-23 02:55:20,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:20,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:20,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:20,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:20,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:20,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69012622] [2024-11-23 02:55:20,897 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [69012622] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:20,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:20,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:20,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1898589634] [2024-11-23 02:55:20,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:20,899 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:20,899 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:20,899 INFO L85 PathProgramCache]: Analyzing trace with hash 1551047712, now seen corresponding path program 1 times [2024-11-23 02:55:20,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:20,900 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987397851] [2024-11-23 02:55:20,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:20,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:20,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:20,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:20,939 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:20,939 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987397851] [2024-11-23 02:55:20,939 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [987397851] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:20,940 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:20,940 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:20,940 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670452932] [2024-11-23 02:55:20,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:20,940 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:20,940 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:20,941 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:20,941 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:20,941 INFO L87 Difference]: Start difference. First operand 340 states and 496 transitions. cyclomatic complexity: 158 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:20,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:20,979 INFO L93 Difference]: Finished difference Result 582 states and 842 transitions. [2024-11-23 02:55:20,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 582 states and 842 transitions. [2024-11-23 02:55:20,983 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 535 [2024-11-23 02:55:20,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 582 states to 582 states and 842 transitions. [2024-11-23 02:55:20,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 582 [2024-11-23 02:55:20,989 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 582 [2024-11-23 02:55:20,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 582 states and 842 transitions. [2024-11-23 02:55:20,990 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:20,990 INFO L218 hiAutomatonCegarLoop]: Abstraction has 582 states and 842 transitions. [2024-11-23 02:55:20,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582 states and 842 transitions. [2024-11-23 02:55:21,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582 to 578. [2024-11-23 02:55:21,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 578 states, 578 states have (on average 1.4498269896193772) internal successors, (838), 577 states have internal predecessors, (838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:21,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 578 states to 578 states and 838 transitions. [2024-11-23 02:55:21,010 INFO L240 hiAutomatonCegarLoop]: Abstraction has 578 states and 838 transitions. [2024-11-23 02:55:21,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:21,011 INFO L425 stractBuchiCegarLoop]: Abstraction has 578 states and 838 transitions. [2024-11-23 02:55:21,011 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-23 02:55:21,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 578 states and 838 transitions. [2024-11-23 02:55:21,014 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 531 [2024-11-23 02:55:21,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:21,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:21,015 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:21,015 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:21,015 INFO L745 eck$LassoCheckResult]: Stem: 2518#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2519#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2531#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2526#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2527#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 2428#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2400#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2401#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2382#L334 assume !(0 == ~M_E~0); 2383#L334-2 assume !(0 == ~T1_E~0); 2490#L339-1 assume !(0 == ~T2_E~0); 2483#L344-1 assume !(0 == ~E_1~0); 2484#L349-1 assume !(0 == ~E_2~0); 2398#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2399#L156 assume !(1 == ~m_pc~0); 2329#L156-2 is_master_triggered_~__retres1~0#1 := 0; 2328#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2501#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2453#L405 assume !(0 != activate_threads_~tmp~1#1); 2436#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2437#L175 assume !(1 == ~t1_pc~0); 2441#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2438#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2394#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2395#L413 assume !(0 != activate_threads_~tmp___0~0#1); 2492#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2545#L194 assume !(1 == ~t2_pc~0); 2482#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2448#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2449#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2370#L421 assume !(0 != activate_threads_~tmp___1~0#1); 2371#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2339#L367 assume !(1 == ~M_E~0); 2340#L367-2 assume !(1 == ~T1_E~0); 2502#L372-1 assume !(1 == ~T2_E~0); 2503#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2506#L382-1 assume !(1 == ~E_2~0); 2825#L387-1 assume { :end_inline_reset_delta_events } true; 2823#L528-2 [2024-11-23 02:55:21,015 INFO L747 eck$LassoCheckResult]: Loop: 2823#L528-2 assume !false; 2785#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2783#L309-1 assume !false; 2782#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2780#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2778#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2777#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2316#L276 assume !(0 != eval_~tmp~0#1); 2318#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2456#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2775#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2774#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2772#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2773#L344-3 assume !(0 == ~E_1~0); 2893#L349-3 assume !(0 == ~E_2~0); 2892#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2891#L156-9 assume !(1 == ~m_pc~0); 2889#L156-11 is_master_triggered_~__retres1~0#1 := 0; 2888#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2887#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2886#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2885#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2884#L175-9 assume !(1 == ~t1_pc~0); 2883#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 2882#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2881#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2880#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 2879#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2878#L194-9 assume 1 == ~t2_pc~0; 2876#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2875#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2874#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2873#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2872#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2871#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2870#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2869#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2384#L377-3 assume !(1 == ~E_1~0); 2353#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2868#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2514#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2386#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2639#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2640#L547 assume !(0 == start_simulation_~tmp~3#1); 2835#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2834#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2831#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2830#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 2829#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2828#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2827#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2826#L560 assume !(0 != start_simulation_~tmp___0~1#1); 2823#L528-2 [2024-11-23 02:55:21,016 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:21,016 INFO L85 PathProgramCache]: Analyzing trace with hash -148513729, now seen corresponding path program 1 times [2024-11-23 02:55:21,016 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:21,016 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818873413] [2024-11-23 02:55:21,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:21,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:21,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:21,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:21,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:21,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818873413] [2024-11-23 02:55:21,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818873413] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:21,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:21,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:21,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [973262210] [2024-11-23 02:55:21,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:21,063 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:21,063 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:21,063 INFO L85 PathProgramCache]: Analyzing trace with hash 1493903487, now seen corresponding path program 1 times [2024-11-23 02:55:21,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:21,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [719164548] [2024-11-23 02:55:21,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:21,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:21,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:21,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:21,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:21,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [719164548] [2024-11-23 02:55:21,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [719164548] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:21,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:21,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:55:21,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669826408] [2024-11-23 02:55:21,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:21,163 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:21,163 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:21,163 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:55:21,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:55:21,164 INFO L87 Difference]: Start difference. First operand 578 states and 838 transitions. cyclomatic complexity: 264 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:21,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:21,273 INFO L93 Difference]: Finished difference Result 592 states and 834 transitions. [2024-11-23 02:55:21,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 592 states and 834 transitions. [2024-11-23 02:55:21,278 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 544 [2024-11-23 02:55:21,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 592 states to 592 states and 834 transitions. [2024-11-23 02:55:21,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 592 [2024-11-23 02:55:21,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 592 [2024-11-23 02:55:21,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 592 states and 834 transitions. [2024-11-23 02:55:21,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:21,284 INFO L218 hiAutomatonCegarLoop]: Abstraction has 592 states and 834 transitions. [2024-11-23 02:55:21,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states and 834 transitions. [2024-11-23 02:55:21,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 575. [2024-11-23 02:55:21,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 575 states, 575 states have (on average 1.413913043478261) internal successors, (813), 574 states have internal predecessors, (813), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:21,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 575 states to 575 states and 813 transitions. [2024-11-23 02:55:21,305 INFO L240 hiAutomatonCegarLoop]: Abstraction has 575 states and 813 transitions. [2024-11-23 02:55:21,305 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:55:21,306 INFO L425 stractBuchiCegarLoop]: Abstraction has 575 states and 813 transitions. [2024-11-23 02:55:21,306 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-23 02:55:21,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 575 states and 813 transitions. [2024-11-23 02:55:21,310 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 531 [2024-11-23 02:55:21,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:21,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:21,312 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:21,312 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:21,312 INFO L745 eck$LassoCheckResult]: Stem: 3706#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3719#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3715#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3716#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 3610#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3579#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3580#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3563#L334 assume !(0 == ~M_E~0); 3564#L334-2 assume !(0 == ~T1_E~0); 3673#L339-1 assume !(0 == ~T2_E~0); 3666#L344-1 assume !(0 == ~E_1~0); 3667#L349-1 assume !(0 == ~E_2~0); 3577#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3578#L156 assume !(1 == ~m_pc~0); 3511#L156-2 is_master_triggered_~__retres1~0#1 := 0; 3510#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3687#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3633#L405 assume !(0 != activate_threads_~tmp~1#1); 3617#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3618#L175 assume !(1 == ~t1_pc~0); 3622#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3619#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3574#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3575#L413 assume !(0 != activate_threads_~tmp___0~0#1); 3677#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3735#L194 assume !(1 == ~t2_pc~0); 3665#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3627#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3628#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3551#L421 assume !(0 != activate_threads_~tmp___1~0#1); 3552#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3522#L367 assume !(1 == ~M_E~0); 3523#L367-2 assume !(1 == ~T1_E~0); 3688#L372-1 assume !(1 == ~T2_E~0); 3689#L377-1 assume !(1 == ~E_1~0); 3548#L382-1 assume !(1 == ~E_2~0); 3549#L387-1 assume { :end_inline_reset_delta_events } true; 3635#L528-2 [2024-11-23 02:55:21,312 INFO L747 eck$LassoCheckResult]: Loop: 3635#L528-2 assume !false; 3819#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3813#L309-1 assume !false; 3792#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3793#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3684#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3519#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3498#L276 assume !(0 != eval_~tmp~0#1); 3500#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3806#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3804#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3802#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3799#L339-3 assume !(0 == ~T2_E~0); 3800#L344-3 assume !(0 == ~E_1~0); 3790#L349-3 assume !(0 == ~E_2~0); 3791#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3959#L156-9 assume !(1 == ~m_pc~0); 3957#L156-11 is_master_triggered_~__retres1~0#1 := 0; 3605#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3606#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3678#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3679#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3739#L175-9 assume !(1 == ~t1_pc~0); 3740#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 3955#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3949#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3946#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 3942#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3939#L194-9 assume 1 == ~t2_pc~0; 3934#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3930#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3926#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3922#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3917#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3912#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3908#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3904#L372-3 assume !(1 == ~T2_E~0); 3899#L377-3 assume !(1 == ~E_1~0); 3895#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3891#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3887#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3881#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3877#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 3872#L547 assume !(0 == start_simulation_~tmp~3#1); 3866#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3863#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3857#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3852#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 3841#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3837#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3835#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3833#L560 assume !(0 != start_simulation_~tmp___0~1#1); 3635#L528-2 [2024-11-23 02:55:21,316 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:21,316 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 1 times [2024-11-23 02:55:21,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:21,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430274822] [2024-11-23 02:55:21,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:21,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:21,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:21,331 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:21,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:21,371 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:21,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:21,372 INFO L85 PathProgramCache]: Analyzing trace with hash -898972165, now seen corresponding path program 1 times [2024-11-23 02:55:21,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:21,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153971223] [2024-11-23 02:55:21,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:21,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:21,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:21,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:21,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:21,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [153971223] [2024-11-23 02:55:21,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [153971223] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:21,471 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:21,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:55:21,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627803336] [2024-11-23 02:55:21,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:21,472 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:21,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:21,473 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:55:21,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:55:21,473 INFO L87 Difference]: Start difference. First operand 575 states and 813 transitions. cyclomatic complexity: 242 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:21,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:21,528 INFO L93 Difference]: Finished difference Result 603 states and 841 transitions. [2024-11-23 02:55:21,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 603 states and 841 transitions. [2024-11-23 02:55:21,532 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 559 [2024-11-23 02:55:21,536 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 603 states to 603 states and 841 transitions. [2024-11-23 02:55:21,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 603 [2024-11-23 02:55:21,537 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 603 [2024-11-23 02:55:21,537 INFO L73 IsDeterministic]: Start isDeterministic. Operand 603 states and 841 transitions. [2024-11-23 02:55:21,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:21,539 INFO L218 hiAutomatonCegarLoop]: Abstraction has 603 states and 841 transitions. [2024-11-23 02:55:21,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 603 states and 841 transitions. [2024-11-23 02:55:21,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 603 to 587. [2024-11-23 02:55:21,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 587 states, 587 states have (on average 1.405451448040886) internal successors, (825), 586 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:21,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 587 states and 825 transitions. [2024-11-23 02:55:21,552 INFO L240 hiAutomatonCegarLoop]: Abstraction has 587 states and 825 transitions. [2024-11-23 02:55:21,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:55:21,555 INFO L425 stractBuchiCegarLoop]: Abstraction has 587 states and 825 transitions. [2024-11-23 02:55:21,555 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-23 02:55:21,555 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 587 states and 825 transitions. [2024-11-23 02:55:21,558 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 543 [2024-11-23 02:55:21,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:21,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:21,560 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:21,560 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:21,561 INFO L745 eck$LassoCheckResult]: Stem: 4885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4901#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4895#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4896#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 4790#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4764#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4765#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4747#L334 assume !(0 == ~M_E~0); 4748#L334-2 assume !(0 == ~T1_E~0); 4855#L339-1 assume !(0 == ~T2_E~0); 4848#L344-1 assume !(0 == ~E_1~0); 4849#L349-1 assume !(0 == ~E_2~0); 4762#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4763#L156 assume !(1 == ~m_pc~0); 4694#L156-2 is_master_triggered_~__retres1~0#1 := 0; 4693#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4867#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4815#L405 assume !(0 != activate_threads_~tmp~1#1); 4796#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4797#L175 assume !(1 == ~t1_pc~0); 4804#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4798#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4759#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4760#L413 assume !(0 != activate_threads_~tmp___0~0#1); 4857#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4913#L194 assume !(1 == ~t2_pc~0); 4847#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4808#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4809#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4735#L421 assume !(0 != activate_threads_~tmp___1~0#1); 4736#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4705#L367 assume !(1 == ~M_E~0); 4706#L367-2 assume !(1 == ~T1_E~0); 4868#L372-1 assume !(1 == ~T2_E~0); 4869#L377-1 assume !(1 == ~E_1~0); 4732#L382-1 assume !(1 == ~E_2~0); 4733#L387-1 assume { :end_inline_reset_delta_events } true; 4818#L528-2 [2024-11-23 02:55:21,561 INFO L747 eck$LassoCheckResult]: Loop: 4818#L528-2 assume !false; 5014#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5008#L309-1 assume !false; 5006#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5004#L244 assume !(0 == ~m_st~0); 5002#L248 assume !(0 == ~t1_st~0); 5000#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 4997#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4995#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4993#L276 assume !(0 != eval_~tmp~0#1); 4991#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4989#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4987#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4985#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4982#L339-3 assume !(0 == ~T2_E~0); 4983#L344-3 assume !(0 == ~E_1~0); 5229#L349-3 assume !(0 == ~E_2~0); 4972#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4973#L156-9 assume !(1 == ~m_pc~0); 4965#L156-11 is_master_triggered_~__retres1~0#1 := 0; 4786#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4787#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4860#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4723#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4724#L175-9 assume !(1 == ~t1_pc~0); 4876#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4877#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5222#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5221#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 4881#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4882#L194-9 assume !(1 == ~t2_pc~0); 4737#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 4738#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4690#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4691#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4851#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4782#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4695#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4696#L372-3 assume !(1 == ~T2_E~0); 4749#L377-3 assume !(1 == ~E_1~0); 4741#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4742#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4879#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4751#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4911#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4891#L547 assume !(0 == start_simulation_~tmp~3#1); 4870#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4905#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5252#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5032#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 5027#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5026#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5024#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5022#L560 assume !(0 != start_simulation_~tmp___0~1#1); 4818#L528-2 [2024-11-23 02:55:21,565 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:21,566 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 2 times [2024-11-23 02:55:21,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:21,566 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150203696] [2024-11-23 02:55:21,566 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:55:21,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:21,578 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:21,580 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:21,580 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:21,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:21,592 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:21,593 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:21,593 INFO L85 PathProgramCache]: Analyzing trace with hash -975167437, now seen corresponding path program 1 times [2024-11-23 02:55:21,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:21,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [682659181] [2024-11-23 02:55:21,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:21,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:21,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:21,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:21,688 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:21,688 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [682659181] [2024-11-23 02:55:21,688 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [682659181] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:21,688 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:21,688 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:55:21,689 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719468348] [2024-11-23 02:55:21,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:21,689 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:21,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:21,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:55:21,690 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:55:21,690 INFO L87 Difference]: Start difference. First operand 587 states and 825 transitions. cyclomatic complexity: 242 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:21,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:21,777 INFO L93 Difference]: Finished difference Result 626 states and 864 transitions. [2024-11-23 02:55:21,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 864 transitions. [2024-11-23 02:55:21,781 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 579 [2024-11-23 02:55:21,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 864 transitions. [2024-11-23 02:55:21,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2024-11-23 02:55:21,784 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2024-11-23 02:55:21,785 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 864 transitions. [2024-11-23 02:55:21,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:21,785 INFO L218 hiAutomatonCegarLoop]: Abstraction has 626 states and 864 transitions. [2024-11-23 02:55:21,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 864 transitions. [2024-11-23 02:55:21,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2024-11-23 02:55:21,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.3801916932907348) internal successors, (864), 625 states have internal predecessors, (864), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:21,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 864 transitions. [2024-11-23 02:55:21,795 INFO L240 hiAutomatonCegarLoop]: Abstraction has 626 states and 864 transitions. [2024-11-23 02:55:21,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:55:21,796 INFO L425 stractBuchiCegarLoop]: Abstraction has 626 states and 864 transitions. [2024-11-23 02:55:21,796 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-23 02:55:21,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 864 transitions. [2024-11-23 02:55:21,799 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 579 [2024-11-23 02:55:21,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:21,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:21,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:21,800 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:21,800 INFO L745 eck$LassoCheckResult]: Stem: 6107#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6108#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6121#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6116#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6117#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 6013#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5984#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5985#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5968#L334 assume !(0 == ~M_E~0); 5969#L334-2 assume !(0 == ~T1_E~0); 6078#L339-1 assume !(0 == ~T2_E~0); 6072#L344-1 assume !(0 == ~E_1~0); 6073#L349-1 assume !(0 == ~E_2~0); 5982#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5983#L156 assume !(1 == ~m_pc~0); 5915#L156-2 is_master_triggered_~__retres1~0#1 := 0; 6100#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6093#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6039#L405 assume !(0 != activate_threads_~tmp~1#1); 6017#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6018#L175 assume !(1 == ~t1_pc~0); 6025#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6019#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5980#L413 assume !(0 != activate_threads_~tmp___0~0#1); 6080#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6135#L194 assume !(1 == ~t2_pc~0); 6071#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6029#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6030#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5957#L421 assume !(0 != activate_threads_~tmp___1~0#1); 5958#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5927#L367 assume !(1 == ~M_E~0); 5928#L367-2 assume !(1 == ~T1_E~0); 6094#L372-1 assume !(1 == ~T2_E~0); 6095#L377-1 assume !(1 == ~E_1~0); 5954#L382-1 assume !(1 == ~E_2~0); 5955#L387-1 assume { :end_inline_reset_delta_events } true; 6041#L528-2 [2024-11-23 02:55:21,800 INFO L747 eck$LassoCheckResult]: Loop: 6041#L528-2 assume !false; 6293#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6287#L309-1 assume !false; 6285#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6283#L244 assume !(0 == ~m_st~0); 6281#L248 assume !(0 == ~t1_st~0); 6278#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 6276#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6274#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6272#L276 assume !(0 != eval_~tmp~0#1); 6270#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6268#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6266#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6264#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6262#L339-3 assume !(0 == ~T2_E~0); 6260#L344-3 assume !(0 == ~E_1~0); 6258#L349-3 assume !(0 == ~E_2~0); 6256#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6254#L156-9 assume 1 == ~m_pc~0; 6251#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6247#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6243#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6239#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6236#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6234#L175-9 assume !(1 == ~t1_pc~0); 6232#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 6230#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6228#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6226#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 6224#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6222#L194-9 assume 1 == ~t2_pc~0; 6219#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6216#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6214#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6212#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6210#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6208#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6206#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6204#L372-3 assume !(1 == ~T2_E~0); 6199#L377-3 assume !(1 == ~E_1~0); 6200#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6194#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6195#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6342#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6339#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 6113#L547 assume !(0 == start_simulation_~tmp~3#1); 6114#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6365#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6361#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6359#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 6348#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6343#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6332#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6329#L560 assume !(0 != start_simulation_~tmp___0~1#1); 6041#L528-2 [2024-11-23 02:55:21,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:21,801 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 3 times [2024-11-23 02:55:21,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:21,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288563210] [2024-11-23 02:55:21,802 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-23 02:55:21,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:21,808 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-23 02:55:21,809 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:21,809 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:21,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:21,817 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:21,818 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:21,818 INFO L85 PathProgramCache]: Analyzing trace with hash -1914923147, now seen corresponding path program 1 times [2024-11-23 02:55:21,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:21,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809347493] [2024-11-23 02:55:21,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:21,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:21,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:21,827 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:21,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:21,841 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:21,842 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:21,842 INFO L85 PathProgramCache]: Analyzing trace with hash 1578773301, now seen corresponding path program 1 times [2024-11-23 02:55:21,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:21,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5812232] [2024-11-23 02:55:21,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:21,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:21,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:21,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:21,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:21,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5812232] [2024-11-23 02:55:21,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [5812232] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:21,909 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:21,909 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:21,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [600582625] [2024-11-23 02:55:21,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:22,417 INFO L204 LassoAnalysis]: Preferences: [2024-11-23 02:55:22,419 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-23 02:55:22,419 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-23 02:55:22,419 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-23 02:55:22,419 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-23 02:55:22,419 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:22,420 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-23 02:55:22,420 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-23 02:55:22,420 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration8_Loop [2024-11-23 02:55:22,420 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-23 02:55:22,420 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-23 02:55:22,437 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,445 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,447 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,449 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,452 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,454 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,457 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,459 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,461 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,464 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,466 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,469 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,474 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,479 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,484 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,487 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,489 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,492 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,493 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,496 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,498 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,501 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,504 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,506 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,512 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,515 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,518 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,521 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,523 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,526 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,530 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,532 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,535 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,537 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,542 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,547 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,549 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,551 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,553 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,555 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,558 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:22,828 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-23 02:55:22,829 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-23 02:55:22,831 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:22,831 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:22,833 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:22,836 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-23 02:55:22,837 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:22,837 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:22,856 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:22,856 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:22,866 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-23 02:55:22,867 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:22,867 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:22,870 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:22,871 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-23 02:55:22,872 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:22,872 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:22,885 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:22,885 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret13#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret13#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:22,891 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:22,892 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:22,892 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:22,893 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:22,893 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-23 02:55:22,895 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:22,895 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:22,911 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:22,911 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:22,917 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-23 02:55:22,917 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:22,917 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:22,918 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:22,919 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-23 02:55:22,920 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:22,920 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:22,934 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:22,934 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_master_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:22,940 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:22,941 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:22,941 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:22,942 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:22,943 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-23 02:55:22,944 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:22,944 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:22,956 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:22,956 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:22,962 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-23 02:55:22,963 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:22,963 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:22,965 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:22,966 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-23 02:55:22,968 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:22,969 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:22,980 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:22,980 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:22,987 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:22,987 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:22,987 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:22,988 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:22,989 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-23 02:55:22,990 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:22,990 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:23,001 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:23,002 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:23,007 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-23 02:55:23,008 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,008 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,009 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,010 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-23 02:55:23,011 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:23,011 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:23,025 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:23,025 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:23,033 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-23 02:55:23,034 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,034 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,036 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,037 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-23 02:55:23,039 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:23,039 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:23,063 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:23,064 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:23,072 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-23 02:55:23,073 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,073 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,074 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,077 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-23 02:55:23,078 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:23,078 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:23,092 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:23,093 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:23,101 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:23,102 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,102 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,103 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,105 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-23 02:55:23,106 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:23,106 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:23,120 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:23,120 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret8#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret8#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:23,126 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-11-23 02:55:23,126 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,126 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,127 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,128 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-23 02:55:23,129 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:23,129 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:23,147 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-23 02:55:23,148 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_1~0=-1} Honda state: {~E_1~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-23 02:55:23,154 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:23,154 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,154 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,156 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,157 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-23 02:55:23,158 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-23 02:55:23,158 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:23,187 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:23,188 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,188 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,190 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,193 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-23 02:55:23,194 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-23 02:55:23,194 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-23 02:55:23,227 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-23 02:55:23,232 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-11-23 02:55:23,233 INFO L204 LassoAnalysis]: Preferences: [2024-11-23 02:55:23,233 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-23 02:55:23,233 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-23 02:55:23,233 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-23 02:55:23,233 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-23 02:55:23,233 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,233 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-23 02:55:23,234 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-23 02:55:23,234 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration8_Loop [2024-11-23 02:55:23,234 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-23 02:55:23,234 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-23 02:55:23,236 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,241 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,246 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,249 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,251 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,253 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,256 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,258 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,260 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,263 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,265 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,270 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,276 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,281 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,283 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,288 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,290 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,292 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,294 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,297 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,299 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,304 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,307 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,309 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,311 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,313 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,316 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,318 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,320 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,322 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,325 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,327 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,332 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,334 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,339 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,341 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,343 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,345 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,348 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-23 02:55:23,579 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-23 02:55:23,586 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-23 02:55:23,587 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,587 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,590 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,591 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-23 02:55:23,592 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,605 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,606 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,606 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,606 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-23 02:55:23,606 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,608 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-23 02:55:23,608 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,613 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,621 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-11-23 02:55:23,621 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,622 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,624 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,626 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-23 02:55:23,628 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,641 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,641 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,641 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,641 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-23 02:55:23,641 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,642 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-23 02:55:23,642 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,643 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,651 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-23 02:55:23,652 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,652 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,653 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,656 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-23 02:55:23,657 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,670 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,671 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,671 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,671 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-23 02:55:23,671 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,671 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-23 02:55:23,672 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,676 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,684 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-11-23 02:55:23,685 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,685 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,687 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,689 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-23 02:55:23,690 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,703 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,703 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,703 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,703 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-23 02:55:23,703 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,704 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-23 02:55:23,704 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,707 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,715 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-23 02:55:23,716 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,716 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,718 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,721 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-23 02:55:23,722 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,732 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,732 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,732 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,732 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-23 02:55:23,732 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,734 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-23 02:55:23,734 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,735 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,743 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:23,743 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,743 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,746 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,747 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-23 02:55:23,748 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,759 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,759 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,759 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,759 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-23 02:55:23,759 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,759 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-23 02:55:23,759 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,761 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,768 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:23,769 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,769 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,770 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,770 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-23 02:55:23,772 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,782 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,782 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,782 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,782 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-23 02:55:23,782 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,783 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-23 02:55:23,783 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,784 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,792 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2024-11-23 02:55:23,793 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,793 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,794 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,797 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,800 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-23 02:55:23,809 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,810 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,810 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,810 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-23 02:55:23,810 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,812 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-23 02:55:23,812 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,815 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,822 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:23,823 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,823 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,826 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,828 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-23 02:55:23,829 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,842 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,842 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,842 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,842 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-23 02:55:23,842 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,843 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-23 02:55:23,843 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,845 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,856 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:23,856 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,856 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,858 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,859 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-23 02:55:23,879 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,893 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,894 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,894 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,894 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-23 02:55:23,894 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,895 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-23 02:55:23,895 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,900 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,908 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:23,909 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,909 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,911 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,913 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-23 02:55:23,915 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,928 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,928 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,928 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,928 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-23 02:55:23,928 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,929 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-23 02:55:23,929 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,933 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,942 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:23,943 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,943 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,944 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,947 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,951 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-23 02:55:23,960 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,960 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,961 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,961 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-23 02:55:23,961 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,962 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-23 02:55:23,962 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,964 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:23,972 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:23,972 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:23,973 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:23,975 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:23,977 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-11-23 02:55:23,978 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:23,992 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:23,992 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:23,992 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:23,992 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-23 02:55:23,992 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:23,994 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-23 02:55:23,994 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:23,999 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-23 02:55:24,007 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:24,008 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:24,008 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:24,010 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:24,012 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-11-23 02:55:24,013 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-23 02:55:24,025 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-23 02:55:24,025 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-23 02:55:24,026 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-23 02:55:24,026 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-23 02:55:24,026 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-23 02:55:24,028 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-23 02:55:24,028 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-23 02:55:24,031 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-23 02:55:24,034 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-23 02:55:24,034 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-23 02:55:24,035 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:24,036 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:24,038 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:24,040 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-11-23 02:55:24,041 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-23 02:55:24,045 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-23 02:55:24,045 INFO L474 LassoAnalysis]: Proved termination. [2024-11-23 02:55:24,046 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2024-11-23 02:55:24,066 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2024-11-23 02:55:24,068 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-23 02:55:24,104 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:24,133 INFO L255 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-23 02:55:24,135 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-23 02:55:24,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:24,220 INFO L255 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-23 02:55:24,222 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-23 02:55:24,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:24,373 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-23 02:55:24,374 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 626 states and 864 transitions. cyclomatic complexity: 242 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,481 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 626 states and 864 transitions. cyclomatic complexity: 242. Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 1566 states and 2181 transitions. Complement of second has 5 states. [2024-11-23 02:55:24,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-23 02:55:24,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 246 transitions. [2024-11-23 02:55:24,486 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 246 transitions. Stem has 38 letters. Loop has 54 letters. [2024-11-23 02:55:24,489 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-23 02:55:24,489 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 246 transitions. Stem has 92 letters. Loop has 54 letters. [2024-11-23 02:55:24,491 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-23 02:55:24,492 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 246 transitions. Stem has 38 letters. Loop has 108 letters. [2024-11-23 02:55:24,493 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-23 02:55:24,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2181 transitions. [2024-11-23 02:55:24,509 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1036 [2024-11-23 02:55:24,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2181 transitions. [2024-11-23 02:55:24,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1088 [2024-11-23 02:55:24,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1097 [2024-11-23 02:55:24,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2181 transitions. [2024-11-23 02:55:24,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-23 02:55:24,521 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2181 transitions. [2024-11-23 02:55:24,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2181 transitions. [2024-11-23 02:55:24,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1557. [2024-11-23 02:55:24,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1557 states, 1557 states have (on average 1.3924213230571612) internal successors, (2168), 1556 states have internal predecessors, (2168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1557 states to 1557 states and 2168 transitions. [2024-11-23 02:55:24,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1557 states and 2168 transitions. [2024-11-23 02:55:24,549 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:24,549 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:24,549 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:24,550 INFO L87 Difference]: Start difference. First operand 1557 states and 2168 transitions. Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:24,591 INFO L93 Difference]: Finished difference Result 2628 states and 3563 transitions. [2024-11-23 02:55:24,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2628 states and 3563 transitions. [2024-11-23 02:55:24,607 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1780 [2024-11-23 02:55:24,622 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2628 states to 2628 states and 3563 transitions. [2024-11-23 02:55:24,622 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1840 [2024-11-23 02:55:24,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1840 [2024-11-23 02:55:24,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2628 states and 3563 transitions. [2024-11-23 02:55:24,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-23 02:55:24,625 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2628 states and 3563 transitions. [2024-11-23 02:55:24,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2628 states and 3563 transitions. [2024-11-23 02:55:24,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2628 to 2523. [2024-11-23 02:55:24,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2523 states, 2523 states have (on average 1.3586999603646452) internal successors, (3428), 2522 states have internal predecessors, (3428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2523 states to 2523 states and 3428 transitions. [2024-11-23 02:55:24,668 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2523 states and 3428 transitions. [2024-11-23 02:55:24,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:24,670 INFO L425 stractBuchiCegarLoop]: Abstraction has 2523 states and 3428 transitions. [2024-11-23 02:55:24,670 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-23 02:55:24,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2523 states and 3428 transitions. [2024-11-23 02:55:24,682 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1710 [2024-11-23 02:55:24,682 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:24,682 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:24,683 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,683 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,683 INFO L745 eck$LassoCheckResult]: Stem: 12931#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 12932#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12954#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12949#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12950#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 12763#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12712#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12713#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12686#L334 assume !(0 == ~M_E~0); 12687#L334-2 assume !(0 == ~T1_E~0); 12873#L339-1 assume !(0 == ~T2_E~0); 12863#L344-1 assume !(0 == ~E_1~0); 12864#L349-1 assume !(0 == ~E_2~0); 12710#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12711#L156 assume !(1 == ~m_pc~0); 12600#L156-2 is_master_triggered_~__retres1~0#1 := 0; 12948#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13009#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12803#L405 assume !(0 != activate_threads_~tmp~1#1); 12779#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12780#L175 assume !(1 == ~t1_pc~0); 12784#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12781#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12706#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12707#L413 assume !(0 != activate_threads_~tmp___0~0#1); 12880#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12985#L194 assume !(1 == ~t2_pc~0); 12861#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12791#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12792#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12668#L421 assume !(0 != activate_threads_~tmp___1~0#1); 12669#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12616#L367 assume !(1 == ~M_E~0); 12617#L367-2 assume !(1 == ~T1_E~0); 12907#L372-1 assume !(1 == ~T2_E~0); 12908#L377-1 assume !(1 == ~E_1~0); 12663#L382-1 assume !(1 == ~E_2~0); 12664#L387-1 assume { :end_inline_reset_delta_events } true; 12808#L528-2 assume !false; 13302#L529 [2024-11-23 02:55:24,684 INFO L747 eck$LassoCheckResult]: Loop: 13302#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14418#L309-1 assume !false; 14419#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14406#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14404#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14402#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14398#L276 assume 0 != eval_~tmp~0#1; 14393#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 14381#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 14388#L47 assume !(0 == ~m_pc~0); 14401#L50 assume 1 == ~m_pc~0; 14397#$Ultimate##124 assume !false; 14392#L67 ~m_pc~0 := 1;~m_st~0 := 2; 14386#master_returnLabel#1 assume { :end_inline_master } true; 14379#L284-2 havoc eval_~tmp_ndt_1~0#1; 14372#L281-1 assume !(0 == ~t1_st~0); 14373#L295-1 assume !(0 == ~t2_st~0); 14422#L309-1 assume !false; 14415#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14416#L244 assume !(0 == ~m_st~0); 14648#L248 assume !(0 == ~t1_st~0); 14646#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 14647#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14530#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14531#L276 assume !(0 != eval_~tmp~0#1); 12811#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12812#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14969#L334-3 assume !(0 == ~M_E~0); 12955#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12876#L339-3 assume !(0 == ~T2_E~0); 12877#L344-3 assume !(0 == ~E_1~0); 12801#L349-3 assume !(0 == ~E_2~0); 12682#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12683#L156-9 assume 1 == ~m_pc~0; 12848#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14966#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14964#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 14965#L405-9 assume !(0 != activate_threads_~tmp~1#1); 12882#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14996#L175-9 assume !(1 == ~t1_pc~0); 14995#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 14994#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14993#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14992#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 14991#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14990#L194-9 assume 1 == ~t2_pc~0; 14988#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14986#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14984#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14982#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14980#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14978#L367-3 assume !(1 == ~M_E~0); 14976#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14975#L372-3 assume !(1 == ~T2_E~0); 14974#L377-3 assume !(1 == ~E_1~0); 14973#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14972#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14971#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14739#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14736#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 14733#L547 assume !(0 == start_simulation_~tmp~3#1); 14731#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14691#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14688#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14685#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 14682#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14678#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14673#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 14670#L560 assume !(0 != start_simulation_~tmp___0~1#1); 14666#L528-2 assume !false; 13302#L529 [2024-11-23 02:55:24,684 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,684 INFO L85 PathProgramCache]: Analyzing trace with hash -308898552, now seen corresponding path program 1 times [2024-11-23 02:55:24,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,684 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779505128] [2024-11-23 02:55:24,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:24,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:24,696 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:24,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:24,708 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:24,711 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,712 INFO L85 PathProgramCache]: Analyzing trace with hash 1365140293, now seen corresponding path program 1 times [2024-11-23 02:55:24,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728976492] [2024-11-23 02:55:24,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:24,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:24,746 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-11-23 02:55:24,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:24,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [728976492] [2024-11-23 02:55:24,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [728976492] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:24,747 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:24,747 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:24,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [143691578] [2024-11-23 02:55:24,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:24,748 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:24,748 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:24,748 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:24,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:24,749 INFO L87 Difference]: Start difference. First operand 2523 states and 3428 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:24,802 INFO L93 Difference]: Finished difference Result 3814 states and 5080 transitions. [2024-11-23 02:55:24,802 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3814 states and 5080 transitions. [2024-11-23 02:55:24,825 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 2339 [2024-11-23 02:55:24,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3814 states to 3626 states and 4832 transitions. [2024-11-23 02:55:24,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2453 [2024-11-23 02:55:24,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2453 [2024-11-23 02:55:24,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3626 states and 4832 transitions. [2024-11-23 02:55:24,875 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-23 02:55:24,875 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3626 states and 4832 transitions. [2024-11-23 02:55:24,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3626 states and 4832 transitions. [2024-11-23 02:55:24,887 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2024-11-23 02:55:24,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3626 to 3506. [2024-11-23 02:55:24,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3506 states, 3506 states have (on average 1.3331431831146605) internal successors, (4674), 3505 states have internal predecessors, (4674), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3506 states to 3506 states and 4674 transitions. [2024-11-23 02:55:24,939 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3506 states and 4674 transitions. [2024-11-23 02:55:24,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:24,940 INFO L425 stractBuchiCegarLoop]: Abstraction has 3506 states and 4674 transitions. [2024-11-23 02:55:24,941 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-23 02:55:24,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3506 states and 4674 transitions. [2024-11-23 02:55:24,956 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 2222 [2024-11-23 02:55:24,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:24,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:24,957 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,958 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,958 INFO L745 eck$LassoCheckResult]: Stem: 19291#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 19292#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 19312#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19309#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19310#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 19108#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19058#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19059#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19028#L334 assume 0 == ~M_E~0;~M_E~0 := 1; 19029#L334-2 assume !(0 == ~T1_E~0); 19222#L339-1 assume !(0 == ~T2_E~0); 19223#L344-1 assume !(0 == ~E_1~0); 19379#L349-1 assume !(0 == ~E_2~0); 19056#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19057#L156 assume !(1 == ~m_pc~0); 19232#L156-2 is_master_triggered_~__retres1~0#1 := 0; 19308#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19375#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 19151#L405 assume !(0 != activate_threads_~tmp~1#1); 19123#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19124#L175 assume !(1 == ~t1_pc~0); 19129#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19125#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19126#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 19366#L413 assume !(0 != activate_threads_~tmp___0~0#1); 19337#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19338#L194 assume !(1 == ~t2_pc~0); 19364#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19363#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19361#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19360#L421 assume !(0 != activate_threads_~tmp___1~0#1); 19359#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18959#L367 assume 1 == ~M_E~0;~M_E~0 := 2; 18960#L367-2 assume !(1 == ~T1_E~0); 19262#L372-1 assume !(1 == ~T2_E~0); 19263#L377-1 assume !(1 == ~E_1~0); 19005#L382-1 assume !(1 == ~E_2~0); 19006#L387-1 assume { :end_inline_reset_delta_events } true; 19156#L528-2 assume !false; 19171#L529 [2024-11-23 02:55:24,958 INFO L747 eck$LassoCheckResult]: Loop: 19171#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19172#L309-1 assume !false; 22306#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22304#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22231#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22301#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22300#L276 assume 0 != eval_~tmp~0#1; 19311#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 19109#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 19045#L47 assume !(0 == ~m_pc~0); 19047#L50 assume 1 == ~m_pc~0; 19342#$Ultimate##124 assume !false; 21902#L67 ~m_pc~0 := 1;~m_st~0 := 2; 21899#master_returnLabel#1 assume { :end_inline_master } true; 21896#L284-2 havoc eval_~tmp_ndt_1~0#1; 21892#L281-1 assume !(0 == ~t1_st~0); 21893#L295-1 assume !(0 == ~t2_st~0); 22238#L309-1 assume !false; 22235#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22230#L244 assume !(0 == ~m_st~0); 22225#L248 assume !(0 == ~t1_st~0); 22218#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 22213#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22208#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22202#L276 assume !(0 != eval_~tmp~0#1); 19159#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19160#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19220#L334-3 assume !(0 == ~M_E~0); 19313#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19227#L339-3 assume !(0 == ~T2_E~0); 19228#L344-3 assume !(0 == ~E_1~0); 22264#L349-3 assume !(0 == ~E_2~0); 22262#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22260#L156-9 assume !(1 == ~m_pc~0); 22249#L156-11 is_master_triggered_~__retres1~0#1 := 0; 22248#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22247#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 19233#L405-9 assume !(0 != activate_threads_~tmp~1#1); 19234#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22233#L175-9 assume !(1 == ~t1_pc~0); 22228#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 22223#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22216#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 22211#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 22206#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22200#L194-9 assume 1 == ~t2_pc~0; 22196#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22191#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22188#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22185#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22182#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22179#L367-3 assume !(1 == ~M_E~0); 22174#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22175#L372-3 assume !(1 == ~T2_E~0); 18975#L377-3 assume !(1 == ~E_1~0); 18976#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19020#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22032#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22033#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 19340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 19302#L547 assume !(0 == start_simulation_~tmp~3#1); 19303#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 19293#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 19090#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 19041#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 19042#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19053#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19081#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 18983#L560 assume !(0 != start_simulation_~tmp___0~1#1); 18984#L528-2 assume !false; 19171#L529 [2024-11-23 02:55:24,959 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,959 INFO L85 PathProgramCache]: Analyzing trace with hash 1509461508, now seen corresponding path program 1 times [2024-11-23 02:55:24,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048407913] [2024-11-23 02:55:24,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:24,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:24,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:24,983 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:24,983 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1048407913] [2024-11-23 02:55:24,983 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1048407913] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:24,983 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:24,983 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:24,983 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556008409] [2024-11-23 02:55:24,983 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:24,983 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:24,983 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,984 INFO L85 PathProgramCache]: Analyzing trace with hash -1804567034, now seen corresponding path program 1 times [2024-11-23 02:55:24,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617602756] [2024-11-23 02:55:24,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:24,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:25,009 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,009 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617602756] [2024-11-23 02:55:25,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617602756] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,010 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:25,010 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [400107296] [2024-11-23 02:55:25,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,010 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:25,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:25,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:25,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:25,011 INFO L87 Difference]: Start difference. First operand 3506 states and 4674 transitions. cyclomatic complexity: 1182 Second operand has 3 states, 3 states have (on average 13.0) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:25,041 INFO L93 Difference]: Finished difference Result 2160 states and 2841 transitions. [2024-11-23 02:55:25,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2160 states and 2841 transitions. [2024-11-23 02:55:25,050 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1478 [2024-11-23 02:55:25,057 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2160 states to 1535 states and 2021 transitions. [2024-11-23 02:55:25,058 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1535 [2024-11-23 02:55:25,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1535 [2024-11-23 02:55:25,059 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1535 states and 2021 transitions. [2024-11-23 02:55:25,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:25,061 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1535 states and 2021 transitions. [2024-11-23 02:55:25,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1535 states and 2021 transitions. [2024-11-23 02:55:25,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1535 to 909. [2024-11-23 02:55:25,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 909 states, 909 states have (on average 1.3124312431243124) internal successors, (1193), 908 states have internal predecessors, (1193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 909 states to 909 states and 1193 transitions. [2024-11-23 02:55:25,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 909 states and 1193 transitions. [2024-11-23 02:55:25,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:25,078 INFO L425 stractBuchiCegarLoop]: Abstraction has 909 states and 1193 transitions. [2024-11-23 02:55:25,078 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-23 02:55:25,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 909 states and 1193 transitions. [2024-11-23 02:55:25,081 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 861 [2024-11-23 02:55:25,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:25,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:25,082 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,082 INFO L745 eck$LassoCheckResult]: Stem: 24799#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 24800#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24811#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24809#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24810#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 24698#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24672#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24673#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24656#L334 assume !(0 == ~M_E~0); 24657#L334-2 assume !(0 == ~T1_E~0); 24765#L339-1 assume !(0 == ~T2_E~0); 24758#L344-1 assume !(0 == ~E_1~0); 24759#L349-1 assume !(0 == ~E_2~0); 24670#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24671#L156 assume !(1 == ~m_pc~0); 24607#L156-2 is_master_triggered_~__retres1~0#1 := 0; 24789#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24780#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 24724#L405 assume !(0 != activate_threads_~tmp~1#1); 24705#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24706#L175 assume !(1 == ~t1_pc~0); 24710#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24707#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24667#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 24668#L413 assume !(0 != activate_threads_~tmp___0~0#1); 24770#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24830#L194 assume !(1 == ~t2_pc~0); 24757#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24716#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24717#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24645#L421 assume !(0 != activate_threads_~tmp___1~0#1); 24646#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24617#L367 assume !(1 == ~M_E~0); 24618#L367-2 assume !(1 == ~T1_E~0); 24781#L372-1 assume !(1 == ~T2_E~0); 24782#L377-1 assume !(1 == ~E_1~0); 24642#L382-1 assume !(1 == ~E_2~0); 24643#L387-1 assume { :end_inline_reset_delta_events } true; 24727#L528-2 [2024-11-23 02:55:25,083 INFO L747 eck$LassoCheckResult]: Loop: 24727#L528-2 assume !false; 25183#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25181#L309-1 assume !false; 25180#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 25179#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 24922#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 25178#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25177#L276 assume 0 != eval_~tmp~0#1; 24858#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 24859#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 24852#L47 assume !(0 == ~m_pc~0); 24853#L50 assume 1 == ~m_pc~0; 24854#$Ultimate##124 assume !false; 24973#L67 ~m_pc~0 := 1;~m_st~0 := 2; 24971#master_returnLabel#1 assume { :end_inline_master } true; 24964#L284-2 havoc eval_~tmp_ndt_1~0#1; 24961#L281-1 assume !(0 == ~t1_st~0); 24933#L295-1 assume !(0 == ~t2_st~0); 24926#L309-1 assume !false; 24924#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 24921#L244 assume !(0 == ~m_st~0); 24918#L248 assume !(0 == ~t1_st~0); 24915#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 24912#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24910#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24907#L276 assume !(0 != eval_~tmp~0#1); 24904#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24902#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24900#L334-3 assume !(0 == ~M_E~0); 24898#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24895#L339-3 assume !(0 == ~T2_E~0); 24896#L344-3 assume !(0 == ~E_1~0); 25176#L349-3 assume !(0 == ~E_2~0); 25175#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25174#L156-9 assume !(1 == ~m_pc~0); 25172#L156-11 is_master_triggered_~__retres1~0#1 := 0; 25171#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24786#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 24771#L405-9 assume !(0 != activate_threads_~tmp~1#1); 24633#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24634#L175-9 assume !(1 == ~t1_pc~0); 24833#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 25468#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25168#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 25165#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 25133#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25130#L194-9 assume 1 == ~t2_pc~0; 25126#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25124#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25121#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25117#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25112#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25109#L367-3 assume !(1 == ~M_E~0); 25105#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25097#L372-3 assume !(1 == ~T2_E~0); 25091#L377-3 assume !(1 == ~E_1~0); 25088#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25085#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 25081#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 25082#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 25166#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 25077#L547 assume !(0 == start_simulation_~tmp~3#1); 25079#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 25200#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 25028#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 25199#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 25198#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25197#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25196#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 25195#L560 assume !(0 != start_simulation_~tmp___0~1#1); 24727#L528-2 [2024-11-23 02:55:25,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,083 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 4 times [2024-11-23 02:55:25,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587548576] [2024-11-23 02:55:25,084 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-23 02:55:25,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,090 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-23 02:55:25,091 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:25,091 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,099 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1131871900, now seen corresponding path program 2 times [2024-11-23 02:55:25,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687636043] [2024-11-23 02:55:25,100 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:55:25,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,107 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:25,108 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-23 02:55:25,128 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-11-23 02:55:25,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687636043] [2024-11-23 02:55:25,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [687636043] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,129 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,130 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:25,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571493260] [2024-11-23 02:55:25,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,130 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:25,130 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:25,131 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:25,131 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:25,131 INFO L87 Difference]: Start difference. First operand 909 states and 1193 transitions. cyclomatic complexity: 288 Second operand has 3 states, 3 states have (on average 22.666666666666668) internal successors, (68), 3 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:25,155 INFO L93 Difference]: Finished difference Result 857 states and 1113 transitions. [2024-11-23 02:55:25,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 857 states and 1113 transitions. [2024-11-23 02:55:25,159 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 809 [2024-11-23 02:55:25,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 857 states to 857 states and 1113 transitions. [2024-11-23 02:55:25,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 857 [2024-11-23 02:55:25,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 857 [2024-11-23 02:55:25,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 857 states and 1113 transitions. [2024-11-23 02:55:25,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:25,165 INFO L218 hiAutomatonCegarLoop]: Abstraction has 857 states and 1113 transitions. [2024-11-23 02:55:25,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 857 states and 1113 transitions. [2024-11-23 02:55:25,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 857 to 857. [2024-11-23 02:55:25,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 857 states, 857 states have (on average 1.2987164527421238) internal successors, (1113), 856 states have internal predecessors, (1113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 857 states to 857 states and 1113 transitions. [2024-11-23 02:55:25,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 857 states and 1113 transitions. [2024-11-23 02:55:25,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:25,179 INFO L425 stractBuchiCegarLoop]: Abstraction has 857 states and 1113 transitions. [2024-11-23 02:55:25,179 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-23 02:55:25,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 857 states and 1113 transitions. [2024-11-23 02:55:25,183 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 809 [2024-11-23 02:55:25,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:25,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:25,184 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,184 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,184 INFO L745 eck$LassoCheckResult]: Stem: 26565#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 26566#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 26578#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26575#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26576#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 26472#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26447#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26448#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26429#L334 assume !(0 == ~M_E~0); 26430#L334-2 assume !(0 == ~T1_E~0); 26536#L339-1 assume !(0 == ~T2_E~0); 26530#L344-1 assume !(0 == ~E_1~0); 26531#L349-1 assume !(0 == ~E_2~0); 26445#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26446#L156 assume !(1 == ~m_pc~0); 26377#L156-2 is_master_triggered_~__retres1~0#1 := 0; 26557#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26551#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 26499#L405 assume !(0 != activate_threads_~tmp~1#1); 26477#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26478#L175 assume !(1 == ~t1_pc~0); 26485#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26479#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26442#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26443#L413 assume !(0 != activate_threads_~tmp___0~0#1); 26538#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26594#L194 assume !(1 == ~t2_pc~0); 26529#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26489#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26490#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26418#L421 assume !(0 != activate_threads_~tmp___1~0#1); 26419#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26388#L367 assume !(1 == ~M_E~0); 26389#L367-2 assume !(1 == ~T1_E~0); 26552#L372-1 assume !(1 == ~T2_E~0); 26553#L377-1 assume !(1 == ~E_1~0); 26415#L382-1 assume !(1 == ~E_2~0); 26416#L387-1 assume { :end_inline_reset_delta_events } true; 26502#L528-2 [2024-11-23 02:55:25,185 INFO L747 eck$LassoCheckResult]: Loop: 26502#L528-2 assume !false; 26977#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26976#L309-1 assume !false; 26975#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 26974#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 26973#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 26621#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26619#L276 assume 0 != eval_~tmp~0#1; 26618#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 26616#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 26613#L47 assume !(0 == ~m_pc~0); 26614#L50 assume 1 == ~m_pc~0; 26954#$Ultimate##124 assume !false; 26949#L67 ~m_pc~0 := 1;~m_st~0 := 2; 26940#master_returnLabel#1 assume { :end_inline_master } true; 26933#L284-2 havoc eval_~tmp_ndt_1~0#1; 26930#L281-1 assume !(0 == ~t1_st~0); 26931#L295-1 assume !(0 == ~t2_st~0); 27093#L309-1 assume !false; 27092#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27091#L244 assume !(0 == ~m_st~0); 27090#L248 assume !(0 == ~t1_st~0); 27088#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 27087#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 27086#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27084#L276 assume !(0 != eval_~tmp~0#1); 27082#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27080#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27079#L334-3 assume !(0 == ~M_E~0); 27078#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27077#L339-3 assume !(0 == ~T2_E~0); 27076#L344-3 assume !(0 == ~E_1~0); 27075#L349-3 assume !(0 == ~E_2~0); 27074#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27072#L156-9 assume !(1 == ~m_pc~0); 27069#L156-11 is_master_triggered_~__retres1~0#1 := 0; 27067#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27066#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 27065#L405-9 assume !(0 != activate_threads_~tmp~1#1); 26406#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26407#L175-9 assume !(1 == ~t1_pc~0); 26560#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 26392#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26393#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26574#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 26563#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26564#L194-9 assume !(1 == ~t2_pc~0); 26420#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 26421#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26374#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26375#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26533#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26928#L367-3 assume !(1 == ~M_E~0); 26925#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26431#L372-3 assume !(1 == ~T2_E~0); 26432#L377-3 assume !(1 == ~E_1~0); 27073#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27070#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27068#L244-1 assume !(0 == ~m_st~0); 27056#L248-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 27054#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 27052#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 27049#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 27047#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27044#L156-12 assume 1 == ~m_pc~0; 27042#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27040#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27038#is_master_triggered_returnLabel#5 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 27036#L405-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27034#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27032#L175-12 assume !(1 == ~t1_pc~0); 27030#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 27028#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27026#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 27024#L413-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27023#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27020#L194-12 assume 1 == ~t2_pc~0; 27018#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27016#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27014#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27012#L421-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27010#L421-14 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 27008#L454 assume 1 == ~M_E~0;~M_E~0 := 2; 27006#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27003#L459-1 assume !(1 == ~T2_E~0); 27001#L464-1 assume !(1 == ~E_1~0); 26999#L469-1 assume 1 == ~E_2~0;~E_2~0 := 2; 26997#L474-1 assume { :end_inline_reset_time_events } true; 26995#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 26993#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 26991#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 26988#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 26986#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26985#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26984#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 26983#L560 assume !(0 != start_simulation_~tmp___0~1#1); 26502#L528-2 [2024-11-23 02:55:25,185 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,186 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 5 times [2024-11-23 02:55:25,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303615910] [2024-11-23 02:55:25,186 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-23 02:55:25,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,195 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:25,195 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:25,195 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,207 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,213 INFO L85 PathProgramCache]: Analyzing trace with hash 477919123, now seen corresponding path program 1 times [2024-11-23 02:55:25,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,213 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709994388] [2024-11-23 02:55:25,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:25,248 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709994388] [2024-11-23 02:55:25,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709994388] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,248 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,248 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:25,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537754688] [2024-11-23 02:55:25,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,249 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:25,249 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:25,249 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:25,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:25,249 INFO L87 Difference]: Start difference. First operand 857 states and 1113 transitions. cyclomatic complexity: 260 Second operand has 3 states, 3 states have (on average 32.0) internal successors, (96), 3 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:25,278 INFO L93 Difference]: Finished difference Result 983 states and 1260 transitions. [2024-11-23 02:55:25,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 983 states and 1260 transitions. [2024-11-23 02:55:25,282 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 813 [2024-11-23 02:55:25,286 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 983 states to 983 states and 1260 transitions. [2024-11-23 02:55:25,286 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 983 [2024-11-23 02:55:25,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 983 [2024-11-23 02:55:25,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 983 states and 1260 transitions. [2024-11-23 02:55:25,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:25,288 INFO L218 hiAutomatonCegarLoop]: Abstraction has 983 states and 1260 transitions. [2024-11-23 02:55:25,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 983 states and 1260 transitions. [2024-11-23 02:55:25,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 983 to 940. [2024-11-23 02:55:25,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 940 states, 940 states have (on average 1.2840425531914894) internal successors, (1207), 939 states have internal predecessors, (1207), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 940 states to 940 states and 1207 transitions. [2024-11-23 02:55:25,302 INFO L240 hiAutomatonCegarLoop]: Abstraction has 940 states and 1207 transitions. [2024-11-23 02:55:25,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:25,303 INFO L425 stractBuchiCegarLoop]: Abstraction has 940 states and 1207 transitions. [2024-11-23 02:55:25,304 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-23 02:55:25,304 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 940 states and 1207 transitions. [2024-11-23 02:55:25,306 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 813 [2024-11-23 02:55:25,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:25,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:25,307 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,307 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,307 INFO L745 eck$LassoCheckResult]: Stem: 28418#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 28419#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28431#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28428#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28429#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 28314#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28288#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28289#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28272#L334 assume !(0 == ~M_E~0); 28273#L334-2 assume !(0 == ~T1_E~0); 28383#L339-1 assume !(0 == ~T2_E~0); 28377#L344-1 assume !(0 == ~E_1~0); 28378#L349-1 assume !(0 == ~E_2~0); 28286#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28287#L156 assume 1 == ~m_pc~0; 28222#L157 assume !(1 == ~M_E~0); 28223#L156-2 is_master_triggered_~__retres1~0#1 := 0; 28427#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28553#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 28339#L405 assume !(0 != activate_threads_~tmp~1#1); 28319#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28320#L175 assume !(1 == ~t1_pc~0); 28395#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28544#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28283#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28284#L413 assume !(0 != activate_threads_~tmp___0~0#1); 28385#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28447#L194 assume !(1 == ~t2_pc~0); 28375#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28376#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28532#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28530#L421 assume !(0 != activate_threads_~tmp___1~0#1); 28350#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28351#L367 assume !(1 == ~M_E~0); 28446#L367-2 assume !(1 == ~T1_E~0); 28400#L372-1 assume !(1 == ~T2_E~0); 28401#L377-1 assume !(1 == ~E_1~0); 28404#L382-1 assume !(1 == ~E_2~0); 28342#L387-1 assume { :end_inline_reset_delta_events } true; 28343#L528-2 [2024-11-23 02:55:25,308 INFO L747 eck$LassoCheckResult]: Loop: 28343#L528-2 assume !false; 28949#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28947#L309-1 assume !false; 28938#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 28935#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 28934#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 28933#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28932#L276 assume 0 != eval_~tmp~0#1; 28929#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 28924#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 28925#L47 assume !(0 == ~m_pc~0); 28937#L50 assume 1 == ~m_pc~0; 28460#$Ultimate##124 assume !false; 28922#L67 ~m_pc~0 := 1;~m_st~0 := 2; 28918#master_returnLabel#1 assume { :end_inline_master } true; 28912#L284-2 havoc eval_~tmp_ndt_1~0#1; 28908#L281-1 assume !(0 == ~t1_st~0); 28255#L295-1 assume !(0 == ~t2_st~0); 28241#L309-1 assume !false; 28242#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 29024#L244 assume !(0 == ~m_st~0); 29023#L248 assume !(0 == ~t1_st~0); 29019#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 29016#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 29014#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 29012#L276 assume !(0 != eval_~tmp~0#1); 29010#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29005#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29002#L334-3 assume !(0 == ~M_E~0); 29001#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29000#L339-3 assume !(0 == ~T2_E~0); 28998#L344-3 assume !(0 == ~E_1~0); 28996#L349-3 assume !(0 == ~E_2~0); 28994#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28993#L156-9 assume 1 == ~m_pc~0; 28992#L157-3 assume !(1 == ~M_E~0); 28991#L156-11 is_master_triggered_~__retres1~0#1 := 0; 28989#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28987#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 28389#L405-9 assume !(0 != activate_threads_~tmp~1#1); 28249#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28250#L175-9 assume !(1 == ~t1_pc~0); 28449#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 28946#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28944#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28943#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 28942#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28941#L194-9 assume 1 == ~t2_pc~0; 28939#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28936#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28926#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28921#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28917#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28911#L367-3 assume !(1 == ~M_E~0); 28907#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28274#L372-3 assume !(1 == ~T2_E~0); 28243#L377-3 assume !(1 == ~E_1~0); 28244#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28267#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 28381#L244-1 assume !(0 == ~m_st~0); 29058#L248-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 29056#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 29054#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 29051#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 29049#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29047#L156-12 assume 1 == ~m_pc~0; 29045#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29043#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29041#is_master_triggered_returnLabel#5 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 29039#L405-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29037#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29036#L175-12 assume !(1 == ~t1_pc~0); 29035#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 29031#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29029#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 29027#L413-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29025#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29020#L194-12 assume 1 == ~t2_pc~0; 29017#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29015#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29013#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29011#L421-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29009#L421-14 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 29008#L454 assume 1 == ~M_E~0;~M_E~0 := 2; 29004#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28981#L459-1 assume !(1 == ~T2_E~0); 28977#L464-1 assume !(1 == ~E_1~0); 28973#L469-1 assume 1 == ~E_2~0;~E_2~0 := 2; 28971#L474-1 assume { :end_inline_reset_time_events } true; 28969#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 28967#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 28965#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 28963#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 28961#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28959#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28957#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28955#L560 assume !(0 != start_simulation_~tmp___0~1#1); 28343#L528-2 [2024-11-23 02:55:25,308 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,308 INFO L85 PathProgramCache]: Analyzing trace with hash -1839445214, now seen corresponding path program 1 times [2024-11-23 02:55:25,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,308 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083264238] [2024-11-23 02:55:25,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:25,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,346 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083264238] [2024-11-23 02:55:25,346 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083264238] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,346 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,346 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:25,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285668853] [2024-11-23 02:55:25,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,347 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:25,347 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,348 INFO L85 PathProgramCache]: Analyzing trace with hash 1301744625, now seen corresponding path program 1 times [2024-11-23 02:55:25,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624517955] [2024-11-23 02:55:25,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:25,388 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624517955] [2024-11-23 02:55:25,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624517955] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:25,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [52778001] [2024-11-23 02:55:25,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,390 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:25,390 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:25,391 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:25,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:25,391 INFO L87 Difference]: Start difference. First operand 940 states and 1207 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 13.0) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:25,412 INFO L93 Difference]: Finished difference Result 540 states and 692 transitions. [2024-11-23 02:55:25,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 540 states and 692 transitions. [2024-11-23 02:55:25,415 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 440 [2024-11-23 02:55:25,418 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 540 states to 540 states and 692 transitions. [2024-11-23 02:55:25,418 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 540 [2024-11-23 02:55:25,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 540 [2024-11-23 02:55:25,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 540 states and 692 transitions. [2024-11-23 02:55:25,419 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:25,419 INFO L218 hiAutomatonCegarLoop]: Abstraction has 540 states and 692 transitions. [2024-11-23 02:55:25,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states and 692 transitions. [2024-11-23 02:55:25,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 536. [2024-11-23 02:55:25,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 536 states, 536 states have (on average 1.2835820895522387) internal successors, (688), 535 states have internal predecessors, (688), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 536 states and 688 transitions. [2024-11-23 02:55:25,428 INFO L240 hiAutomatonCegarLoop]: Abstraction has 536 states and 688 transitions. [2024-11-23 02:55:25,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:25,430 INFO L425 stractBuchiCegarLoop]: Abstraction has 536 states and 688 transitions. [2024-11-23 02:55:25,430 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-23 02:55:25,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 536 states and 688 transitions. [2024-11-23 02:55:25,432 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 440 [2024-11-23 02:55:25,432 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:25,432 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:25,432 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,432 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,433 INFO L745 eck$LassoCheckResult]: Stem: 29893#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 29894#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 29909#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29905#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29906#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 29796#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29770#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29771#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29755#L334 assume !(0 == ~M_E~0); 29756#L334-2 assume !(0 == ~T1_E~0); 29862#L339-1 assume !(0 == ~T2_E~0); 29856#L344-1 assume !(0 == ~E_1~0); 29857#L349-1 assume !(0 == ~E_2~0); 29768#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29769#L156 assume !(1 == ~m_pc~0); 29867#L156-2 is_master_triggered_~__retres1~0#1 := 0; 29882#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29876#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 29821#L405 assume !(0 != activate_threads_~tmp~1#1); 29801#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29802#L175 assume !(1 == ~t1_pc~0); 29808#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29803#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29765#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 29766#L413 assume !(0 != activate_threads_~tmp___0~0#1); 29864#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29920#L194 assume !(1 == ~t2_pc~0); 29855#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29812#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29813#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29744#L421 assume !(0 != activate_threads_~tmp___1~0#1); 29745#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29716#L367 assume !(1 == ~M_E~0); 29717#L367-2 assume !(1 == ~T1_E~0); 29877#L372-1 assume !(1 == ~T2_E~0); 29878#L377-1 assume !(1 == ~E_1~0); 29741#L382-1 assume !(1 == ~E_2~0); 29742#L387-1 assume { :end_inline_reset_delta_events } true; 29824#L528-2 assume !false; 29972#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29973#L309-1 [2024-11-23 02:55:25,433 INFO L747 eck$LassoCheckResult]: Loop: 29973#L309-1 assume !false; 30154#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 30153#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 30152#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 30151#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30150#L276 assume 0 != eval_~tmp~0#1; 30149#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 30147#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 30148#L284-2 havoc eval_~tmp_ndt_1~0#1; 30159#L281-1 assume !(0 == ~t1_st~0); 30156#L295-1 assume !(0 == ~t2_st~0); 29973#L309-1 [2024-11-23 02:55:25,433 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,434 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 1 times [2024-11-23 02:55:25,434 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,434 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011618559] [2024-11-23 02:55:25,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,441 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,450 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,451 INFO L85 PathProgramCache]: Analyzing trace with hash 993947407, now seen corresponding path program 1 times [2024-11-23 02:55:25,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843814334] [2024-11-23 02:55:25,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,454 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,457 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,457 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,458 INFO L85 PathProgramCache]: Analyzing trace with hash 1252886829, now seen corresponding path program 1 times [2024-11-23 02:55:25,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1163458749] [2024-11-23 02:55:25,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:25,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,485 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,485 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1163458749] [2024-11-23 02:55:25,485 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1163458749] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,485 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,485 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:25,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045815151] [2024-11-23 02:55:25,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,525 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:25,526 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:25,526 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:25,526 INFO L87 Difference]: Start difference. First operand 536 states and 688 transitions. cyclomatic complexity: 156 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:25,565 INFO L93 Difference]: Finished difference Result 948 states and 1201 transitions. [2024-11-23 02:55:25,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 948 states and 1201 transitions. [2024-11-23 02:55:25,568 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 676 [2024-11-23 02:55:25,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 948 states to 948 states and 1201 transitions. [2024-11-23 02:55:25,572 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 948 [2024-11-23 02:55:25,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 948 [2024-11-23 02:55:25,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 948 states and 1201 transitions. [2024-11-23 02:55:25,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:25,574 INFO L218 hiAutomatonCegarLoop]: Abstraction has 948 states and 1201 transitions. [2024-11-23 02:55:25,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 948 states and 1201 transitions. [2024-11-23 02:55:25,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 948 to 915. [2024-11-23 02:55:25,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 915 states, 915 states have (on average 1.2666666666666666) internal successors, (1159), 914 states have internal predecessors, (1159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 915 states to 915 states and 1159 transitions. [2024-11-23 02:55:25,587 INFO L240 hiAutomatonCegarLoop]: Abstraction has 915 states and 1159 transitions. [2024-11-23 02:55:25,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:25,588 INFO L425 stractBuchiCegarLoop]: Abstraction has 915 states and 1159 transitions. [2024-11-23 02:55:25,588 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-23 02:55:25,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 915 states and 1159 transitions. [2024-11-23 02:55:25,591 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 643 [2024-11-23 02:55:25,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:25,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:25,592 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,592 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,592 INFO L745 eck$LassoCheckResult]: Stem: 31391#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 31392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 31404#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31401#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31402#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 31289#L221-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 31290#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31408#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31248#L334 assume !(0 == ~M_E~0); 31249#L334-2 assume !(0 == ~T1_E~0); 31357#L339-1 assume !(0 == ~T2_E~0); 31351#L344-1 assume !(0 == ~E_1~0); 31352#L349-1 assume !(0 == ~E_2~0); 31261#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31262#L156 assume !(1 == ~m_pc~0); 31362#L156-2 is_master_triggered_~__retres1~0#1 := 0; 31793#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31788#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 31317#L405 assume !(0 != activate_threads_~tmp~1#1); 31299#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31300#L175 assume !(1 == ~t1_pc~0); 31305#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31301#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31302#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 31766#L413 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31359#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31427#L194 assume !(1 == ~t2_pc~0); 31349#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31310#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31311#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31236#L421 assume !(0 != activate_threads_~tmp___1~0#1); 31237#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31210#L367 assume !(1 == ~M_E~0); 31211#L367-2 assume !(1 == ~T1_E~0); 31373#L372-1 assume !(1 == ~T2_E~0); 31374#L377-1 assume !(1 == ~E_1~0); 31233#L382-1 assume !(1 == ~E_2~0); 31234#L387-1 assume { :end_inline_reset_delta_events } true; 31320#L528-2 assume !false; 31818#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31813#L309-1 [2024-11-23 02:55:25,592 INFO L747 eck$LassoCheckResult]: Loop: 31813#L309-1 assume !false; 31810#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31804#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31798#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31795#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31790#L276 assume 0 != eval_~tmp~0#1; 31786#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 31782#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 31783#L284-2 havoc eval_~tmp_ndt_1~0#1; 31829#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 31743#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 31826#L298-2 havoc eval_~tmp_ndt_2~0#1; 31819#L295-1 assume !(0 == ~t2_st~0); 31813#L309-1 [2024-11-23 02:55:25,593 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,593 INFO L85 PathProgramCache]: Analyzing trace with hash -808857497, now seen corresponding path program 1 times [2024-11-23 02:55:25,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842085232] [2024-11-23 02:55:25,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:25,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842085232] [2024-11-23 02:55:25,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842085232] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,610 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,610 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:25,610 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615298967] [2024-11-23 02:55:25,610 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,611 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:25,611 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,611 INFO L85 PathProgramCache]: Analyzing trace with hash 1697436410, now seen corresponding path program 1 times [2024-11-23 02:55:25,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,611 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981297719] [2024-11-23 02:55:25,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,614 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,616 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:25,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:25,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:25,653 INFO L87 Difference]: Start difference. First operand 915 states and 1159 transitions. cyclomatic complexity: 251 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:25,660 INFO L93 Difference]: Finished difference Result 575 states and 726 transitions. [2024-11-23 02:55:25,660 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 575 states and 726 transitions. [2024-11-23 02:55:25,662 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2024-11-23 02:55:25,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 575 states to 575 states and 726 transitions. [2024-11-23 02:55:25,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 575 [2024-11-23 02:55:25,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 575 [2024-11-23 02:55:25,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 575 states and 726 transitions. [2024-11-23 02:55:25,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:25,665 INFO L218 hiAutomatonCegarLoop]: Abstraction has 575 states and 726 transitions. [2024-11-23 02:55:25,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 575 states and 726 transitions. [2024-11-23 02:55:25,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 575 to 575. [2024-11-23 02:55:25,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 575 states, 575 states have (on average 1.2626086956521738) internal successors, (726), 574 states have internal predecessors, (726), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 575 states to 575 states and 726 transitions. [2024-11-23 02:55:25,673 INFO L240 hiAutomatonCegarLoop]: Abstraction has 575 states and 726 transitions. [2024-11-23 02:55:25,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:25,674 INFO L425 stractBuchiCegarLoop]: Abstraction has 575 states and 726 transitions. [2024-11-23 02:55:25,674 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-23 02:55:25,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 575 states and 726 transitions. [2024-11-23 02:55:25,675 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2024-11-23 02:55:25,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:25,676 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:25,676 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,676 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,676 INFO L745 eck$LassoCheckResult]: Stem: 32876#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 32877#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 32887#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32885#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32886#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 32785#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32759#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32760#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32743#L334 assume !(0 == ~M_E~0); 32744#L334-2 assume !(0 == ~T1_E~0); 32848#L339-1 assume !(0 == ~T2_E~0); 32842#L344-1 assume !(0 == ~E_1~0); 32843#L349-1 assume !(0 == ~E_2~0); 32757#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32758#L156 assume !(1 == ~m_pc~0); 32853#L156-2 is_master_triggered_~__retres1~0#1 := 0; 32868#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32862#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 32809#L405 assume !(0 != activate_threads_~tmp~1#1); 32789#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32790#L175 assume !(1 == ~t1_pc~0); 32797#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32791#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32754#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 32755#L413 assume !(0 != activate_threads_~tmp___0~0#1); 32850#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32901#L194 assume !(1 == ~t2_pc~0); 32841#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32801#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32802#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 32732#L421 assume !(0 != activate_threads_~tmp___1~0#1); 32733#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32705#L367 assume !(1 == ~M_E~0); 32706#L367-2 assume !(1 == ~T1_E~0); 32863#L372-1 assume !(1 == ~T2_E~0); 32864#L377-1 assume !(1 == ~E_1~0); 32729#L382-1 assume !(1 == ~E_2~0); 32730#L387-1 assume { :end_inline_reset_delta_events } true; 32812#L528-2 assume !false; 32819#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32820#L309-1 [2024-11-23 02:55:25,677 INFO L747 eck$LassoCheckResult]: Loop: 32820#L309-1 assume !false; 33185#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 33184#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 32859#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 32704#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 32689#L276 assume 0 != eval_~tmp~0#1; 32690#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 32786#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 32787#L284-2 havoc eval_~tmp_ndt_1~0#1; 33202#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 33195#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 33192#L298-2 havoc eval_~tmp_ndt_2~0#1; 33187#L295-1 assume !(0 == ~t2_st~0); 32820#L309-1 [2024-11-23 02:55:25,677 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,677 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 2 times [2024-11-23 02:55:25,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982041173] [2024-11-23 02:55:25,677 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:55:25,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,683 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:25,684 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:25,684 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,690 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,691 INFO L85 PathProgramCache]: Analyzing trace with hash 1697436410, now seen corresponding path program 2 times [2024-11-23 02:55:25,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,691 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231428998] [2024-11-23 02:55:25,691 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:55:25,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,694 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:25,694 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:25,694 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,696 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,697 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,697 INFO L85 PathProgramCache]: Analyzing trace with hash 1430117784, now seen corresponding path program 1 times [2024-11-23 02:55:25,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [75402259] [2024-11-23 02:55:25,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:25,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,722 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [75402259] [2024-11-23 02:55:25,722 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [75402259] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,722 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:25,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [895707721] [2024-11-23 02:55:25,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:25,758 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:25,758 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:25,758 INFO L87 Difference]: Start difference. First operand 575 states and 726 transitions. cyclomatic complexity: 155 Second operand has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:25,790 INFO L93 Difference]: Finished difference Result 1020 states and 1275 transitions. [2024-11-23 02:55:25,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1020 states and 1275 transitions. [2024-11-23 02:55:25,794 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 815 [2024-11-23 02:55:25,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1020 states to 1020 states and 1275 transitions. [2024-11-23 02:55:25,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1020 [2024-11-23 02:55:25,798 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1020 [2024-11-23 02:55:25,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1020 states and 1275 transitions. [2024-11-23 02:55:25,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:25,799 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1020 states and 1275 transitions. [2024-11-23 02:55:25,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1020 states and 1275 transitions. [2024-11-23 02:55:25,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1020 to 1020. [2024-11-23 02:55:25,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1020 states, 1020 states have (on average 1.25) internal successors, (1275), 1019 states have internal predecessors, (1275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1020 states to 1020 states and 1275 transitions. [2024-11-23 02:55:25,812 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1020 states and 1275 transitions. [2024-11-23 02:55:25,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:25,813 INFO L425 stractBuchiCegarLoop]: Abstraction has 1020 states and 1275 transitions. [2024-11-23 02:55:25,813 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-23 02:55:25,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1020 states and 1275 transitions. [2024-11-23 02:55:25,816 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 815 [2024-11-23 02:55:25,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:25,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:25,816 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,817 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,817 INFO L745 eck$LassoCheckResult]: Stem: 34487#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 34488#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 34499#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34497#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34498#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 34389#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34362#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34363#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34346#L334 assume !(0 == ~M_E~0); 34347#L334-2 assume !(0 == ~T1_E~0); 34457#L339-1 assume !(0 == ~T2_E~0); 34450#L344-1 assume !(0 == ~E_1~0); 34451#L349-1 assume !(0 == ~E_2~0); 34360#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34361#L156 assume !(1 == ~m_pc~0); 34462#L156-2 is_master_triggered_~__retres1~0#1 := 0; 34478#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34472#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 34414#L405 assume !(0 != activate_threads_~tmp~1#1); 34394#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34395#L175 assume !(1 == ~t1_pc~0); 34402#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34396#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34357#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 34358#L413 assume !(0 != activate_threads_~tmp___0~0#1); 34459#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34514#L194 assume !(1 == ~t2_pc~0); 34448#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34406#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34407#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 34335#L421 assume !(0 != activate_threads_~tmp___1~0#1); 34336#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34308#L367 assume !(1 == ~M_E~0); 34309#L367-2 assume !(1 == ~T1_E~0); 34473#L372-1 assume !(1 == ~T2_E~0); 34474#L377-1 assume !(1 == ~E_1~0); 34332#L382-1 assume !(1 == ~E_2~0); 34333#L387-1 assume { :end_inline_reset_delta_events } true; 34417#L528-2 assume !false; 35158#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35156#L309-1 [2024-11-23 02:55:25,817 INFO L747 eck$LassoCheckResult]: Loop: 35156#L309-1 assume !false; 35153#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 35151#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 35147#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 35144#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35141#L276 assume 0 != eval_~tmp~0#1; 35139#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 35136#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 34483#L284-2 havoc eval_~tmp_ndt_1~0#1; 34432#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 34433#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 34490#L298-2 havoc eval_~tmp_ndt_2~0#1; 34439#L295-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 34440#L312 assume !(0 != eval_~tmp_ndt_3~0#1); 34466#L312-2 havoc eval_~tmp_ndt_3~0#1; 35156#L309-1 [2024-11-23 02:55:25,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,818 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 3 times [2024-11-23 02:55:25,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601816032] [2024-11-23 02:55:25,818 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-23 02:55:25,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,824 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-23 02:55:25,824 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:25,824 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,830 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,831 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,831 INFO L85 PathProgramCache]: Analyzing trace with hash -851208175, now seen corresponding path program 1 times [2024-11-23 02:55:25,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758001197] [2024-11-23 02:55:25,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,834 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,836 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,837 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,837 INFO L85 PathProgramCache]: Analyzing trace with hash -46370001, now seen corresponding path program 1 times [2024-11-23 02:55:25,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077136270] [2024-11-23 02:55:25,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,843 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,850 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:26,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:26,368 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:26,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:26,480 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 23.11 02:55:26 BoogieIcfgContainer [2024-11-23 02:55:26,481 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-23 02:55:26,481 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-23 02:55:26,481 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-23 02:55:26,484 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-23 02:55:26,485 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:55:19" (3/4) ... [2024-11-23 02:55:26,487 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-23 02:55:26,554 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-23 02:55:26,555 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-23 02:55:26,555 INFO L158 Benchmark]: Toolchain (without parser) took 8165.75ms. Allocated memory was 134.2MB in the beginning and 264.2MB in the end (delta: 130.0MB). Free memory was 79.6MB in the beginning and 172.8MB in the end (delta: -93.2MB). Peak memory consumption was 39.6MB. Max. memory is 16.1GB. [2024-11-23 02:55:26,556 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 134.2MB. Free memory is still 104.8MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-23 02:55:26,556 INFO L158 Benchmark]: CACSL2BoogieTranslator took 402.69ms. Allocated memory was 134.2MB in the beginning and 182.5MB in the end (delta: 48.2MB). Free memory was 79.3MB in the beginning and 151.9MB in the end (delta: -72.6MB). Peak memory consumption was 21.2MB. Max. memory is 16.1GB. [2024-11-23 02:55:26,556 INFO L158 Benchmark]: Boogie Procedure Inliner took 57.85ms. Allocated memory is still 182.5MB. Free memory was 151.9MB in the beginning and 150.7MB in the end (delta: 1.2MB). Peak memory consumption was 6.1MB. Max. memory is 16.1GB. [2024-11-23 02:55:26,557 INFO L158 Benchmark]: Boogie Preprocessor took 81.16ms. Allocated memory is still 182.5MB. Free memory was 150.7MB in the beginning and 147.5MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-23 02:55:26,557 INFO L158 Benchmark]: RCFGBuilder took 718.05ms. Allocated memory is still 182.5MB. Free memory was 147.5MB in the beginning and 116.0MB in the end (delta: 31.5MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. [2024-11-23 02:55:26,557 INFO L158 Benchmark]: BuchiAutomizer took 6824.85ms. Allocated memory was 182.5MB in the beginning and 264.2MB in the end (delta: 81.8MB). Free memory was 116.0MB in the beginning and 178.1MB in the end (delta: -62.1MB). Peak memory consumption was 18.5MB. Max. memory is 16.1GB. [2024-11-23 02:55:26,557 INFO L158 Benchmark]: Witness Printer took 73.55ms. Allocated memory is still 264.2MB. Free memory was 178.1MB in the beginning and 172.8MB in the end (delta: 5.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-23 02:55:26,559 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 134.2MB. Free memory is still 104.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 402.69ms. Allocated memory was 134.2MB in the beginning and 182.5MB in the end (delta: 48.2MB). Free memory was 79.3MB in the beginning and 151.9MB in the end (delta: -72.6MB). Peak memory consumption was 21.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 57.85ms. Allocated memory is still 182.5MB. Free memory was 151.9MB in the beginning and 150.7MB in the end (delta: 1.2MB). Peak memory consumption was 6.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 81.16ms. Allocated memory is still 182.5MB. Free memory was 150.7MB in the beginning and 147.5MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 718.05ms. Allocated memory is still 182.5MB. Free memory was 147.5MB in the beginning and 116.0MB in the end (delta: 31.5MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 6824.85ms. Allocated memory was 182.5MB in the beginning and 264.2MB in the end (delta: 81.8MB). Free memory was 116.0MB in the beginning and 178.1MB in the end (delta: -62.1MB). Peak memory consumption was 18.5MB. Max. memory is 16.1GB. * Witness Printer took 73.55ms. Allocated memory is still 264.2MB. Free memory was 178.1MB in the beginning and 172.8MB in the end (delta: 5.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (16 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * M_E) + 1) and consists of 3 locations. 16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1020 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 6.6s and 17 iterations. TraceHistogramMax:2. Analysis of lassos took 4.6s. Construction of modules took 0.4s. Büchi inclusion checks took 1.3s. Highest rank in rank-based complementation 3. Minimization of det autom 14. Minimization of nondet autom 3. Automata minimization 0.3s AutomataMinimizationTime, 17 MinimizatonAttempts, 979 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3932 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3931 mSDsluCounter, 9142 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3981 mSDsCounter, 143 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 387 IncrementalHoareTripleChecker+Invalid, 530 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 143 mSolverCounterUnsat, 5161 mSDtfsCounter, 387 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc2 concLT1 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital64 mio100 ax100 hnf100 lsp15 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 44ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 12 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.3s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-23 02:55:26,584 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)