./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 803cd42f Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-assert-order-craig-803cd42-m [2024-11-23 02:55:18,898 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-23 02:55:18,964 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-23 02:55:18,967 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-23 02:55:18,968 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-23 02:55:18,983 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-23 02:55:18,984 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-23 02:55:18,984 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-23 02:55:18,984 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-23 02:55:18,985 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-23 02:55:18,986 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-23 02:55:18,986 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-23 02:55:18,986 INFO L153 SettingsManager]: * Use SBE=true [2024-11-23 02:55:18,987 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-23 02:55:18,987 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-23 02:55:18,987 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-23 02:55:18,987 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-23 02:55:18,988 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-23 02:55:18,988 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-23 02:55:18,988 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-23 02:55:18,988 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-23 02:55:18,992 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-23 02:55:18,992 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-23 02:55:18,993 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-23 02:55:18,993 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-23 02:55:18,993 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-23 02:55:18,993 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-23 02:55:18,993 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-23 02:55:18,994 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-23 02:55:18,994 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-23 02:55:18,994 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-23 02:55:18,994 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-23 02:55:18,995 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-23 02:55:18,995 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-23 02:55:18,995 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-23 02:55:18,995 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-23 02:55:18,996 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-23 02:55:18,996 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-23 02:55:18,996 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-23 02:55:18,997 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa [2024-11-23 02:55:19,210 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-23 02:55:19,234 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-23 02:55:19,237 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-23 02:55:19,239 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-23 02:55:19,239 INFO L274 PluginConnector]: CDTParser initialized [2024-11-23 02:55:19,240 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.04.cil.c [2024-11-23 02:55:20,593 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-23 02:55:20,786 INFO L384 CDTParser]: Found 1 translation units. [2024-11-23 02:55:20,788 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c [2024-11-23 02:55:20,799 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b50c55fe2/b730f58363be45d1b1c22965b0d6f700/FLAG4a317cff0 [2024-11-23 02:55:20,816 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b50c55fe2/b730f58363be45d1b1c22965b0d6f700 [2024-11-23 02:55:20,818 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-23 02:55:20,819 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-23 02:55:20,820 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-23 02:55:20,821 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-23 02:55:20,825 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-23 02:55:20,825 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:55:20" (1/1) ... [2024-11-23 02:55:20,826 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@13237a59 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:20, skipping insertion in model container [2024-11-23 02:55:20,826 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:55:20" (1/1) ... [2024-11-23 02:55:20,857 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-23 02:55:21,079 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-23 02:55:21,092 INFO L200 MainTranslator]: Completed pre-run [2024-11-23 02:55:21,136 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-23 02:55:21,152 INFO L204 MainTranslator]: Completed translation [2024-11-23 02:55:21,152 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21 WrapperNode [2024-11-23 02:55:21,152 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-23 02:55:21,153 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-23 02:55:21,153 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-23 02:55:21,153 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-23 02:55:21,159 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,169 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,221 INFO L138 Inliner]: procedures = 36, calls = 43, calls flagged for inlining = 38, calls inlined = 71, statements flattened = 976 [2024-11-23 02:55:21,221 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-23 02:55:21,222 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-23 02:55:21,222 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-23 02:55:21,240 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-23 02:55:21,248 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,249 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,252 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,292 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-23 02:55:21,293 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,293 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,310 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,331 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,336 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,339 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,345 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-23 02:55:21,346 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-23 02:55:21,346 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-23 02:55:21,346 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-23 02:55:21,349 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (1/1) ... [2024-11-23 02:55:21,353 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-23 02:55:21,365 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-23 02:55:21,385 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-23 02:55:21,388 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-23 02:55:21,432 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-23 02:55:21,432 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-23 02:55:21,433 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-23 02:55:21,433 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-23 02:55:21,510 INFO L238 CfgBuilder]: Building ICFG [2024-11-23 02:55:21,512 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-23 02:55:22,238 INFO L? ?]: Removed 174 outVars from TransFormulas that were not future-live. [2024-11-23 02:55:22,238 INFO L287 CfgBuilder]: Performing block encoding [2024-11-23 02:55:22,255 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-23 02:55:22,256 INFO L316 CfgBuilder]: Removed 8 assume(true) statements. [2024-11-23 02:55:22,256 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:55:22 BoogieIcfgContainer [2024-11-23 02:55:22,256 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-23 02:55:22,257 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-23 02:55:22,257 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-23 02:55:22,260 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-23 02:55:22,261 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:55:22,261 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 02:55:20" (1/3) ... [2024-11-23 02:55:22,262 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4104df7b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:55:22, skipping insertion in model container [2024-11-23 02:55:22,262 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:55:22,262 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:55:21" (2/3) ... [2024-11-23 02:55:22,263 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4104df7b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:55:22, skipping insertion in model container [2024-11-23 02:55:22,263 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-23 02:55:22,263 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:55:22" (3/3) ... [2024-11-23 02:55:22,264 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2024-11-23 02:55:22,323 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-23 02:55:22,324 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-23 02:55:22,324 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-23 02:55:22,324 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-23 02:55:22,324 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-23 02:55:22,324 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-23 02:55:22,324 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-23 02:55:22,324 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-23 02:55:22,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:22,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 328 [2024-11-23 02:55:22,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:22,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:22,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:22,374 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:22,374 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-23 02:55:22,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:22,384 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 328 [2024-11-23 02:55:22,385 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:22,385 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:22,386 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:22,387 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:22,399 INFO L745 eck$LassoCheckResult]: Stem: 119#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 330#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 183#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 326#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56#L341true assume !(1 == ~m_i~0);~m_st~0 := 2; 368#L341-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 213#L346-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 117#L351-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 22#L356-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 108#L361-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L502true assume !(0 == ~M_E~0); 85#L502-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 16#L507-1true assume !(0 == ~T2_E~0); 57#L512-1true assume !(0 == ~T3_E~0); 316#L517-1true assume !(0 == ~T4_E~0); 10#L522-1true assume !(0 == ~E_1~0); 281#L527-1true assume !(0 == ~E_2~0); 121#L532-1true assume !(0 == ~E_3~0); 360#L537-1true assume !(0 == ~E_4~0); 136#L542-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116#L238true assume 1 == ~m_pc~0; 321#L239true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 192#L249true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102#is_master_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 101#L615true assume !(0 != activate_threads_~tmp~1#1); 199#L615-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91#L257true assume 1 == ~t1_pc~0; 322#L258true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 113#L268true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 189#L623true assume !(0 != activate_threads_~tmp___0~0#1); 23#L623-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 188#L276true assume !(1 == ~t2_pc~0); 283#L276-2true is_transmit2_triggered_~__retres1~2#1 := 0; 341#L287true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 345#L631true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 358#L631-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100#L295true assume 1 == ~t3_pc~0; 37#L296true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 93#L306true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 324#L639true assume !(0 != activate_threads_~tmp___2~0#1); 319#L639-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 378#L314true assume !(1 == ~t4_pc~0); 349#L314-2true is_transmit4_triggered_~__retres1~4#1 := 0; 143#L325true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 90#L647true assume !(0 != activate_threads_~tmp___3~0#1); 277#L647-2true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 392#L555true assume !(1 == ~M_E~0); 39#L555-2true assume !(1 == ~T1_E~0); 371#L560-1true assume !(1 == ~T2_E~0); 11#L565-1true assume !(1 == ~T3_E~0); 95#L570-1true assume !(1 == ~T4_E~0); 219#L575-1true assume !(1 == ~E_1~0); 295#L580-1true assume !(1 == ~E_2~0); 129#L585-1true assume 1 == ~E_3~0;~E_3~0 := 2; 29#L590-1true assume !(1 == ~E_4~0); 26#L595-1true assume { :end_inline_reset_delta_events } true; 175#L776-2true [2024-11-23 02:55:22,400 INFO L747 eck$LassoCheckResult]: Loop: 175#L776-2true assume !false; 18#L777true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 272#L477-1true assume false; 54#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 289#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78#L502-3true assume 0 == ~M_E~0;~M_E~0 := 1; 303#L502-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 314#L507-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 55#L512-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 397#L517-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 48#L522-3true assume 0 == ~E_1~0;~E_1~0 := 1; 92#L527-3true assume 0 == ~E_2~0;~E_2~0 := 1; 142#L532-3true assume !(0 == ~E_3~0); 268#L537-3true assume 0 == ~E_4~0;~E_4~0 := 1; 60#L542-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86#L238-15true assume 1 == ~m_pc~0; 9#L239-5true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 311#L249-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50#is_master_triggered_returnLabel#6true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 227#L615-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155#L615-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 211#L257-15true assume !(1 == ~t1_pc~0); 74#L257-17true is_transmit1_triggered_~__retres1~1#1 := 0; 338#L268-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 246#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 307#L623-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 315#L623-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 372#L276-15true assume !(1 == ~t2_pc~0); 382#L276-17true is_transmit2_triggered_~__retres1~2#1 := 0; 248#L287-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 367#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 179#L631-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 290#L631-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24#L295-15true assume !(1 == ~t3_pc~0); 172#L295-17true is_transmit3_triggered_~__retres1~3#1 := 0; 335#L306-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 343#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 162#L639-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122#L639-17true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161#L314-15true assume 1 == ~t4_pc~0; 285#L315-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 181#L325-5true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 308#is_transmit4_triggered_returnLabel#6true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 318#L647-15true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 120#L647-17true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84#L555-3true assume 1 == ~M_E~0;~M_E~0 := 2; 195#L555-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 42#L560-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 309#L565-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 350#L570-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 291#L575-3true assume !(1 == ~E_1~0); 191#L580-3true assume 1 == ~E_2~0;~E_2~0 := 2; 395#L585-3true assume 1 == ~E_3~0;~E_3~0 := 2; 234#L590-3true assume 1 == ~E_4~0;~E_4~0 := 2; 276#L595-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 163#L374-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 73#L401-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 160#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 99#L795true assume !(0 == start_simulation_~tmp~3#1); 320#L795-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 110#L374-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 273#L401-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 168#L750true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40#L757true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 299#stop_simulation_returnLabel#1true start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 280#L808true assume !(0 != start_simulation_~tmp___0~1#1); 175#L776-2true [2024-11-23 02:55:22,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:22,411 INFO L85 PathProgramCache]: Analyzing trace with hash 1110077256, now seen corresponding path program 1 times [2024-11-23 02:55:22,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:22,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452427003] [2024-11-23 02:55:22,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:22,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:22,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:22,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:22,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:22,646 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1452427003] [2024-11-23 02:55:22,646 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1452427003] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:22,646 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:22,646 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:22,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136160107] [2024-11-23 02:55:22,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:22,652 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:22,654 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:22,654 INFO L85 PathProgramCache]: Analyzing trace with hash -782872547, now seen corresponding path program 1 times [2024-11-23 02:55:22,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:22,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086639776] [2024-11-23 02:55:22,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:22,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:22,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:22,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:22,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:22,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086639776] [2024-11-23 02:55:22,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086639776] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:22,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:22,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:22,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [153872730] [2024-11-23 02:55:22,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:22,697 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:22,698 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:22,723 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:22,723 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:22,725 INFO L87 Difference]: Start difference. First operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:22,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:22,767 INFO L93 Difference]: Finished difference Result 395 states and 586 transitions. [2024-11-23 02:55:22,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 395 states and 586 transitions. [2024-11-23 02:55:22,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-23 02:55:22,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 395 states to 389 states and 580 transitions. [2024-11-23 02:55:22,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2024-11-23 02:55:22,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2024-11-23 02:55:22,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 580 transitions. [2024-11-23 02:55:22,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:22,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 580 transitions. [2024-11-23 02:55:22,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 580 transitions. [2024-11-23 02:55:22,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2024-11-23 02:55:22,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4910025706940875) internal successors, (580), 388 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:22,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 580 transitions. [2024-11-23 02:55:22,846 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 580 transitions. [2024-11-23 02:55:22,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:22,857 INFO L425 stractBuchiCegarLoop]: Abstraction has 389 states and 580 transitions. [2024-11-23 02:55:22,858 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-23 02:55:22,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 580 transitions. [2024-11-23 02:55:22,860 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-23 02:55:22,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:22,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:22,877 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:22,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:22,880 INFO L745 eck$LassoCheckResult]: Stem: 1010#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1011#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1077#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1078#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 910#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 911#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1104#L346-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1008#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 845#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 846#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 865#L502 assume !(0 == ~M_E~0); 866#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 831#L507-1 assume !(0 == ~T2_E~0); 832#L512-1 assume !(0 == ~T3_E~0); 912#L517-1 assume !(0 == ~T4_E~0); 819#L522-1 assume !(0 == ~E_1~0); 820#L527-1 assume !(0 == ~E_2~0); 1013#L532-1 assume !(0 == ~E_3~0); 1014#L537-1 assume !(0 == ~E_4~0); 1029#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1005#L238 assume 1 == ~m_pc~0; 1006#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1052#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 988#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 986#L615 assume !(0 != activate_threads_~tmp~1#1); 987#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 968#L257 assume 1 == ~t1_pc~0; 969#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1003#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 863#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 864#L623 assume !(0 != activate_threads_~tmp___0~0#1); 847#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 848#L276 assume !(1 == ~t2_pc~0); 1082#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1158#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1080#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1081#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1182#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 985#L295 assume 1 == ~t3_pc~0; 877#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 853#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 814#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 815#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1176#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1177#L314 assume !(1 == ~t4_pc~0); 871#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 870#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 902#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 903#L647 assume !(0 != activate_threads_~tmp___3~0#1); 967#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1154#L555 assume !(1 == ~M_E~0); 880#L555-2 assume !(1 == ~T1_E~0); 881#L560-1 assume !(1 == ~T2_E~0); 821#L565-1 assume !(1 == ~T3_E~0); 822#L570-1 assume !(1 == ~T4_E~0); 974#L575-1 assume !(1 == ~E_1~0); 1109#L580-1 assume !(1 == ~E_2~0); 1021#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 860#L590-1 assume !(1 == ~E_4~0); 854#L595-1 assume { :end_inline_reset_delta_events } true; 855#L776-2 [2024-11-23 02:55:22,880 INFO L747 eck$LassoCheckResult]: Loop: 855#L776-2 assume !false; 836#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 837#L477-1 assume !false; 1127#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1128#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 956#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1089#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1093#L416 assume !(0 != eval_~tmp~0#1); 906#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 907#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 948#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 949#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1168#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 908#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 909#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 896#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 897#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 971#L532-3 assume !(0 == ~E_3~0); 1037#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 916#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 917#L238-15 assume 1 == ~m_pc~0; 816#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 817#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 900#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 901#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1047#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1048#L257-15 assume 1 == ~t1_pc~0; 1057#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 942#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1132#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1133#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1169#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1175#L276-15 assume 1 == ~t2_pc~0; 1143#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1138#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1139#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1070#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1071#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 849#L295-15 assume 1 == ~t3_pc~0; 850#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1065#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1179#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1055#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1015#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1016#L314-15 assume !(1 == ~t4_pc~0); 1053#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 1074#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1075#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1170#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1012#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 961#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 962#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 887#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 888#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1171#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1161#L575-3 assume !(1 == ~E_1~0); 1085#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1086#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1123#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1124#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1056#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 841#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 940#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 983#L795 assume !(0 == start_simulation_~tmp~3#1); 984#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 999#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1000#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 861#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 862#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 882#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 883#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1157#L808 assume !(0 != start_simulation_~tmp___0~1#1); 855#L776-2 [2024-11-23 02:55:22,882 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:22,882 INFO L85 PathProgramCache]: Analyzing trace with hash 1069402506, now seen corresponding path program 1 times [2024-11-23 02:55:22,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:22,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076526989] [2024-11-23 02:55:22,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:22,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:22,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:22,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:22,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:22,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1076526989] [2024-11-23 02:55:22,949 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1076526989] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:22,949 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:22,949 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:22,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491113493] [2024-11-23 02:55:22,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:22,950 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:22,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:22,951 INFO L85 PathProgramCache]: Analyzing trace with hash -1797968696, now seen corresponding path program 1 times [2024-11-23 02:55:22,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:22,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276105070] [2024-11-23 02:55:22,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:22,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:22,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276105070] [2024-11-23 02:55:23,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276105070] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,046 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,046 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:23,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037608200] [2024-11-23 02:55:23,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,046 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:23,046 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:23,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:23,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:23,047 INFO L87 Difference]: Start difference. First operand 389 states and 580 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:23,072 INFO L93 Difference]: Finished difference Result 389 states and 579 transitions. [2024-11-23 02:55:23,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 579 transitions. [2024-11-23 02:55:23,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-23 02:55:23,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 579 transitions. [2024-11-23 02:55:23,078 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2024-11-23 02:55:23,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2024-11-23 02:55:23,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 579 transitions. [2024-11-23 02:55:23,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:23,080 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 579 transitions. [2024-11-23 02:55:23,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 579 transitions. [2024-11-23 02:55:23,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2024-11-23 02:55:23,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4884318766066837) internal successors, (579), 388 states have internal predecessors, (579), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 579 transitions. [2024-11-23 02:55:23,089 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 579 transitions. [2024-11-23 02:55:23,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:23,090 INFO L425 stractBuchiCegarLoop]: Abstraction has 389 states and 579 transitions. [2024-11-23 02:55:23,090 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-23 02:55:23,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 579 transitions. [2024-11-23 02:55:23,095 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-23 02:55:23,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:23,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:23,101 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,101 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,101 INFO L745 eck$LassoCheckResult]: Stem: 1795#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1862#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1863#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1695#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1696#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1889#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1793#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1630#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1631#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1650#L502 assume !(0 == ~M_E~0); 1651#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1616#L507-1 assume !(0 == ~T2_E~0); 1617#L512-1 assume !(0 == ~T3_E~0); 1697#L517-1 assume !(0 == ~T4_E~0); 1604#L522-1 assume !(0 == ~E_1~0); 1605#L527-1 assume !(0 == ~E_2~0); 1798#L532-1 assume !(0 == ~E_3~0); 1799#L537-1 assume !(0 == ~E_4~0); 1814#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1790#L238 assume 1 == ~m_pc~0; 1791#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1837#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1773#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1771#L615 assume !(0 != activate_threads_~tmp~1#1); 1772#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1753#L257 assume 1 == ~t1_pc~0; 1754#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1788#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1648#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1649#L623 assume !(0 != activate_threads_~tmp___0~0#1); 1632#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1633#L276 assume !(1 == ~t2_pc~0); 1867#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1943#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1865#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1866#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1967#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1770#L295 assume 1 == ~t3_pc~0; 1662#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1638#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1599#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1600#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1961#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1962#L314 assume !(1 == ~t4_pc~0); 1656#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1655#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1687#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1688#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1752#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1939#L555 assume !(1 == ~M_E~0); 1665#L555-2 assume !(1 == ~T1_E~0); 1666#L560-1 assume !(1 == ~T2_E~0); 1606#L565-1 assume !(1 == ~T3_E~0); 1607#L570-1 assume !(1 == ~T4_E~0); 1759#L575-1 assume !(1 == ~E_1~0); 1894#L580-1 assume !(1 == ~E_2~0); 1806#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1645#L590-1 assume !(1 == ~E_4~0); 1639#L595-1 assume { :end_inline_reset_delta_events } true; 1640#L776-2 [2024-11-23 02:55:23,101 INFO L747 eck$LassoCheckResult]: Loop: 1640#L776-2 assume !false; 1621#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1622#L477-1 assume !false; 1912#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1913#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1741#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1874#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1878#L416 assume !(0 != eval_~tmp~0#1); 1691#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1733#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1734#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1953#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1693#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1694#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1681#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1682#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1756#L532-3 assume !(0 == ~E_3~0); 1822#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1701#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1702#L238-15 assume 1 == ~m_pc~0; 1601#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1602#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1685#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1686#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1832#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1833#L257-15 assume 1 == ~t1_pc~0; 1842#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1727#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1917#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1918#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1954#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1960#L276-15 assume 1 == ~t2_pc~0; 1928#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1923#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1924#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1855#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1856#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1634#L295-15 assume 1 == ~t3_pc~0; 1635#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1850#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1964#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1840#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1800#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1801#L314-15 assume !(1 == ~t4_pc~0); 1838#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 1859#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1860#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1955#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1797#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1746#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1747#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1672#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1673#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1956#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1946#L575-3 assume !(1 == ~E_1~0); 1870#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1871#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1908#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1909#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1841#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1626#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1725#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1768#L795 assume !(0 == start_simulation_~tmp~3#1); 1769#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1784#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1785#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1646#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1647#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1667#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1668#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1942#L808 assume !(0 != start_simulation_~tmp___0~1#1); 1640#L776-2 [2024-11-23 02:55:23,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,102 INFO L85 PathProgramCache]: Analyzing trace with hash 193383500, now seen corresponding path program 1 times [2024-11-23 02:55:23,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737237694] [2024-11-23 02:55:23,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:23,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,146 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1737237694] [2024-11-23 02:55:23,146 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1737237694] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,146 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,146 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:23,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [716198192] [2024-11-23 02:55:23,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,147 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:23,147 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,151 INFO L85 PathProgramCache]: Analyzing trace with hash -1797968696, now seen corresponding path program 2 times [2024-11-23 02:55:23,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095367197] [2024-11-23 02:55:23,152 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:55:23,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,163 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:23,163 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-23 02:55:23,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,211 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,212 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095367197] [2024-11-23 02:55:23,212 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095367197] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,212 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,212 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:23,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102088686] [2024-11-23 02:55:23,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,213 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:23,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:23,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:23,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:23,214 INFO L87 Difference]: Start difference. First operand 389 states and 579 transitions. cyclomatic complexity: 191 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:23,230 INFO L93 Difference]: Finished difference Result 389 states and 578 transitions. [2024-11-23 02:55:23,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 578 transitions. [2024-11-23 02:55:23,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-23 02:55:23,234 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 578 transitions. [2024-11-23 02:55:23,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2024-11-23 02:55:23,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2024-11-23 02:55:23,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 578 transitions. [2024-11-23 02:55:23,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:23,239 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 578 transitions. [2024-11-23 02:55:23,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 578 transitions. [2024-11-23 02:55:23,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2024-11-23 02:55:23,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4858611825192802) internal successors, (578), 388 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 578 transitions. [2024-11-23 02:55:23,254 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 578 transitions. [2024-11-23 02:55:23,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:23,254 INFO L425 stractBuchiCegarLoop]: Abstraction has 389 states and 578 transitions. [2024-11-23 02:55:23,254 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-23 02:55:23,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 578 transitions. [2024-11-23 02:55:23,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-23 02:55:23,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:23,256 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:23,257 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,257 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,257 INFO L745 eck$LassoCheckResult]: Stem: 2580#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2581#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2647#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2648#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2480#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 2481#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2674#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2578#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2415#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2416#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2435#L502 assume !(0 == ~M_E~0); 2436#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2404#L507-1 assume !(0 == ~T2_E~0); 2405#L512-1 assume !(0 == ~T3_E~0); 2483#L517-1 assume !(0 == ~T4_E~0); 2391#L522-1 assume !(0 == ~E_1~0); 2392#L527-1 assume !(0 == ~E_2~0); 2583#L532-1 assume !(0 == ~E_3~0); 2584#L537-1 assume !(0 == ~E_4~0); 2599#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2575#L238 assume 1 == ~m_pc~0; 2576#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2622#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2558#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2556#L615 assume !(0 != activate_threads_~tmp~1#1); 2557#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2538#L257 assume 1 == ~t1_pc~0; 2539#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2574#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2433#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2434#L623 assume !(0 != activate_threads_~tmp___0~0#1); 2417#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2418#L276 assume !(1 == ~t2_pc~0); 2652#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2728#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2650#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2651#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2753#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2555#L295 assume 1 == ~t3_pc~0; 2447#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2423#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2384#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2385#L639 assume !(0 != activate_threads_~tmp___2~0#1); 2746#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2747#L314 assume !(1 == ~t4_pc~0); 2441#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2440#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2473#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2474#L647 assume !(0 != activate_threads_~tmp___3~0#1); 2537#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2724#L555 assume !(1 == ~M_E~0); 2450#L555-2 assume !(1 == ~T1_E~0); 2451#L560-1 assume !(1 == ~T2_E~0); 2393#L565-1 assume !(1 == ~T3_E~0); 2394#L570-1 assume !(1 == ~T4_E~0); 2544#L575-1 assume !(1 == ~E_1~0); 2679#L580-1 assume !(1 == ~E_2~0); 2592#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2432#L590-1 assume !(1 == ~E_4~0); 2424#L595-1 assume { :end_inline_reset_delta_events } true; 2425#L776-2 [2024-11-23 02:55:23,257 INFO L747 eck$LassoCheckResult]: Loop: 2425#L776-2 assume !false; 2406#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2407#L477-1 assume !false; 2697#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2698#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2526#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2659#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2663#L416 assume !(0 != eval_~tmp~0#1); 2476#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2477#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2518#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2519#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2738#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2478#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2479#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2466#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2467#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2541#L532-3 assume !(0 == ~E_3~0); 2607#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2486#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2487#L238-15 assume 1 == ~m_pc~0; 2386#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2387#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2470#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2471#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2617#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2618#L257-15 assume 1 == ~t1_pc~0; 2627#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2512#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2702#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2703#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2739#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2745#L276-15 assume 1 == ~t2_pc~0; 2713#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2708#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2709#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2640#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2641#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2419#L295-15 assume 1 == ~t3_pc~0; 2420#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2635#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2749#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2625#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2585#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2586#L314-15 assume 1 == ~t4_pc~0; 2624#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2644#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2645#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2740#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2582#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2531#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2532#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2457#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2458#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2741#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2731#L575-3 assume !(1 == ~E_1~0); 2655#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2656#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2693#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2694#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2626#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2411#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2510#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2553#L795 assume !(0 == start_simulation_~tmp~3#1); 2554#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2569#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2570#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2430#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2431#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2452#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2453#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2727#L808 assume !(0 != start_simulation_~tmp___0~1#1); 2425#L776-2 [2024-11-23 02:55:23,259 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,259 INFO L85 PathProgramCache]: Analyzing trace with hash -250517174, now seen corresponding path program 1 times [2024-11-23 02:55:23,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,260 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413746036] [2024-11-23 02:55:23,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:23,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,293 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,293 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413746036] [2024-11-23 02:55:23,293 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413746036] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,294 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,294 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:23,294 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1649256405] [2024-11-23 02:55:23,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,294 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:23,294 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,294 INFO L85 PathProgramCache]: Analyzing trace with hash -1489529687, now seen corresponding path program 1 times [2024-11-23 02:55:23,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743845419] [2024-11-23 02:55:23,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:23,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [743845419] [2024-11-23 02:55:23,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [743845419] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,330 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,330 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:23,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891773683] [2024-11-23 02:55:23,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,331 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:23,331 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:23,331 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:23,331 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:23,332 INFO L87 Difference]: Start difference. First operand 389 states and 578 transitions. cyclomatic complexity: 190 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:23,338 INFO L93 Difference]: Finished difference Result 389 states and 577 transitions. [2024-11-23 02:55:23,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 577 transitions. [2024-11-23 02:55:23,340 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-23 02:55:23,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 577 transitions. [2024-11-23 02:55:23,342 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2024-11-23 02:55:23,342 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2024-11-23 02:55:23,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 577 transitions. [2024-11-23 02:55:23,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:23,343 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 577 transitions. [2024-11-23 02:55:23,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 577 transitions. [2024-11-23 02:55:23,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2024-11-23 02:55:23,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4832904884318765) internal successors, (577), 388 states have internal predecessors, (577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 577 transitions. [2024-11-23 02:55:23,349 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 577 transitions. [2024-11-23 02:55:23,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:23,350 INFO L425 stractBuchiCegarLoop]: Abstraction has 389 states and 577 transitions. [2024-11-23 02:55:23,350 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-23 02:55:23,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 577 transitions. [2024-11-23 02:55:23,352 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-23 02:55:23,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:23,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:23,353 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,353 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,353 INFO L745 eck$LassoCheckResult]: Stem: 3365#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3366#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3432#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3433#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3265#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 3266#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3459#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3363#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3200#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3201#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3220#L502 assume !(0 == ~M_E~0); 3221#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3186#L507-1 assume !(0 == ~T2_E~0); 3187#L512-1 assume !(0 == ~T3_E~0); 3267#L517-1 assume !(0 == ~T4_E~0); 3174#L522-1 assume !(0 == ~E_1~0); 3175#L527-1 assume !(0 == ~E_2~0); 3368#L532-1 assume !(0 == ~E_3~0); 3369#L537-1 assume !(0 == ~E_4~0); 3384#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3360#L238 assume 1 == ~m_pc~0; 3361#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3407#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3343#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3341#L615 assume !(0 != activate_threads_~tmp~1#1); 3342#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3323#L257 assume 1 == ~t1_pc~0; 3324#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3359#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3218#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3219#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3202#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3203#L276 assume !(1 == ~t2_pc~0); 3437#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3513#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3435#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3436#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3537#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3340#L295 assume 1 == ~t3_pc~0; 3232#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3208#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3169#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3170#L639 assume !(0 != activate_threads_~tmp___2~0#1); 3531#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3532#L314 assume !(1 == ~t4_pc~0); 3226#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3225#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3258#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3259#L647 assume !(0 != activate_threads_~tmp___3~0#1); 3322#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3509#L555 assume !(1 == ~M_E~0); 3235#L555-2 assume !(1 == ~T1_E~0); 3236#L560-1 assume !(1 == ~T2_E~0); 3176#L565-1 assume !(1 == ~T3_E~0); 3177#L570-1 assume !(1 == ~T4_E~0); 3329#L575-1 assume !(1 == ~E_1~0); 3464#L580-1 assume !(1 == ~E_2~0); 3376#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3217#L590-1 assume !(1 == ~E_4~0); 3209#L595-1 assume { :end_inline_reset_delta_events } true; 3210#L776-2 [2024-11-23 02:55:23,353 INFO L747 eck$LassoCheckResult]: Loop: 3210#L776-2 assume !false; 3191#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3192#L477-1 assume !false; 3482#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3483#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3311#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3446#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3448#L416 assume !(0 != eval_~tmp~0#1); 3261#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3262#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3303#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3304#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3523#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3263#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3264#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3251#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3252#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3326#L532-3 assume !(0 == ~E_3~0); 3392#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3271#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3272#L238-15 assume 1 == ~m_pc~0; 3171#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3172#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3255#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3256#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3402#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3403#L257-15 assume !(1 == ~t1_pc~0); 3296#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3297#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3489#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3490#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3524#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3530#L276-15 assume 1 == ~t2_pc~0; 3498#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3493#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3494#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3427#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3428#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3204#L295-15 assume 1 == ~t3_pc~0; 3205#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3420#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3534#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3410#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3370#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3371#L314-15 assume !(1 == ~t4_pc~0); 3408#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 3425#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3426#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3525#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3367#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3316#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3317#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3242#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3243#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3526#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3516#L575-3 assume !(1 == ~E_1~0); 3440#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3441#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3478#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3479#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3411#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3196#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3295#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3338#L795 assume !(0 == start_simulation_~tmp~3#1); 3339#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3353#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3354#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3215#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3216#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3237#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3238#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3512#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3210#L776-2 [2024-11-23 02:55:23,354 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,354 INFO L85 PathProgramCache]: Analyzing trace with hash -1788857204, now seen corresponding path program 1 times [2024-11-23 02:55:23,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,354 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268572805] [2024-11-23 02:55:23,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:23,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,390 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1268572805] [2024-11-23 02:55:23,391 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1268572805] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,391 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,391 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:23,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [713985406] [2024-11-23 02:55:23,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,391 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:23,391 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,391 INFO L85 PathProgramCache]: Analyzing trace with hash 1188993831, now seen corresponding path program 1 times [2024-11-23 02:55:23,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208687306] [2024-11-23 02:55:23,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:23,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1208687306] [2024-11-23 02:55:23,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1208687306] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:23,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920324537] [2024-11-23 02:55:23,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,456 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:23,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:23,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:23,457 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:23,457 INFO L87 Difference]: Start difference. First operand 389 states and 577 transitions. cyclomatic complexity: 189 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:23,470 INFO L93 Difference]: Finished difference Result 389 states and 572 transitions. [2024-11-23 02:55:23,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 572 transitions. [2024-11-23 02:55:23,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-23 02:55:23,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 572 transitions. [2024-11-23 02:55:23,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2024-11-23 02:55:23,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2024-11-23 02:55:23,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 572 transitions. [2024-11-23 02:55:23,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:23,476 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 572 transitions. [2024-11-23 02:55:23,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 572 transitions. [2024-11-23 02:55:23,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2024-11-23 02:55:23,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4704370179948587) internal successors, (572), 388 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 572 transitions. [2024-11-23 02:55:23,483 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 572 transitions. [2024-11-23 02:55:23,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:23,484 INFO L425 stractBuchiCegarLoop]: Abstraction has 389 states and 572 transitions. [2024-11-23 02:55:23,484 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-23 02:55:23,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 572 transitions. [2024-11-23 02:55:23,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-23 02:55:23,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:23,486 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:23,487 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,488 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,488 INFO L745 eck$LassoCheckResult]: Stem: 4150#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4217#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4218#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4050#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 4051#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4244#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4148#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3985#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3986#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4005#L502 assume !(0 == ~M_E~0); 4006#L502-2 assume !(0 == ~T1_E~0); 3971#L507-1 assume !(0 == ~T2_E~0); 3972#L512-1 assume !(0 == ~T3_E~0); 4052#L517-1 assume !(0 == ~T4_E~0); 3959#L522-1 assume !(0 == ~E_1~0); 3960#L527-1 assume !(0 == ~E_2~0); 4153#L532-1 assume !(0 == ~E_3~0); 4154#L537-1 assume !(0 == ~E_4~0); 4169#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4145#L238 assume 1 == ~m_pc~0; 4146#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4192#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4128#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4126#L615 assume !(0 != activate_threads_~tmp~1#1); 4127#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4108#L257 assume 1 == ~t1_pc~0; 4109#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4143#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4003#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4004#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3987#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3988#L276 assume !(1 == ~t2_pc~0); 4222#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4298#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4220#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4221#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4322#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4125#L295 assume 1 == ~t3_pc~0; 4017#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3993#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3955#L639 assume !(0 != activate_threads_~tmp___2~0#1); 4316#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4317#L314 assume !(1 == ~t4_pc~0); 4011#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4010#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4042#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4043#L647 assume !(0 != activate_threads_~tmp___3~0#1); 4107#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4294#L555 assume !(1 == ~M_E~0); 4020#L555-2 assume !(1 == ~T1_E~0); 4021#L560-1 assume !(1 == ~T2_E~0); 3961#L565-1 assume !(1 == ~T3_E~0); 3962#L570-1 assume !(1 == ~T4_E~0); 4114#L575-1 assume !(1 == ~E_1~0); 4249#L580-1 assume !(1 == ~E_2~0); 4161#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4000#L590-1 assume !(1 == ~E_4~0); 3994#L595-1 assume { :end_inline_reset_delta_events } true; 3995#L776-2 [2024-11-23 02:55:23,489 INFO L747 eck$LassoCheckResult]: Loop: 3995#L776-2 assume !false; 3976#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3977#L477-1 assume !false; 4267#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4268#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4096#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4229#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4233#L416 assume !(0 != eval_~tmp~0#1); 4046#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4047#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4088#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4089#L502-5 assume !(0 == ~T1_E~0); 4308#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4048#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4049#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4036#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4037#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4111#L532-3 assume !(0 == ~E_3~0); 4177#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4056#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4057#L238-15 assume 1 == ~m_pc~0; 3956#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3957#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4040#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4041#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4187#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4188#L257-15 assume !(1 == ~t1_pc~0); 4081#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 4082#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4272#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4273#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4309#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4315#L276-15 assume 1 == ~t2_pc~0; 4283#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4278#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4279#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4210#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4211#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3989#L295-15 assume 1 == ~t3_pc~0; 3990#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4205#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4319#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4195#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4155#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4156#L314-15 assume !(1 == ~t4_pc~0); 4193#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 4214#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4215#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4310#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4152#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4101#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4102#L555-5 assume !(1 == ~T1_E~0); 4027#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4028#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4311#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4301#L575-3 assume !(1 == ~E_1~0); 4225#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4226#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4263#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4264#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4196#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3981#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4080#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4123#L795 assume !(0 == start_simulation_~tmp~3#1); 4124#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4139#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4140#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4001#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 4002#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4022#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4023#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4297#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3995#L776-2 [2024-11-23 02:55:23,490 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,490 INFO L85 PathProgramCache]: Analyzing trace with hash -1804375922, now seen corresponding path program 1 times [2024-11-23 02:55:23,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891777131] [2024-11-23 02:55:23,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:23,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,546 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [891777131] [2024-11-23 02:55:23,546 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [891777131] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,546 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:23,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [676791216] [2024-11-23 02:55:23,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,546 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:23,546 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,546 INFO L85 PathProgramCache]: Analyzing trace with hash -721696981, now seen corresponding path program 1 times [2024-11-23 02:55:23,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059799473] [2024-11-23 02:55:23,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:23,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059799473] [2024-11-23 02:55:23,576 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059799473] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,576 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,576 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:23,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591972696] [2024-11-23 02:55:23,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,576 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:23,576 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:23,577 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:23,577 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:23,577 INFO L87 Difference]: Start difference. First operand 389 states and 572 transitions. cyclomatic complexity: 184 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:23,631 INFO L93 Difference]: Finished difference Result 705 states and 1024 transitions. [2024-11-23 02:55:23,631 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 705 states and 1024 transitions. [2024-11-23 02:55:23,636 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 639 [2024-11-23 02:55:23,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 705 states to 705 states and 1024 transitions. [2024-11-23 02:55:23,640 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 705 [2024-11-23 02:55:23,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 705 [2024-11-23 02:55:23,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 705 states and 1024 transitions. [2024-11-23 02:55:23,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:23,643 INFO L218 hiAutomatonCegarLoop]: Abstraction has 705 states and 1024 transitions. [2024-11-23 02:55:23,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 705 states and 1024 transitions. [2024-11-23 02:55:23,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 705 to 669. [2024-11-23 02:55:23,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 669 states, 669 states have (on average 1.4573991031390134) internal successors, (975), 668 states have internal predecessors, (975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 669 states to 669 states and 975 transitions. [2024-11-23 02:55:23,657 INFO L240 hiAutomatonCegarLoop]: Abstraction has 669 states and 975 transitions. [2024-11-23 02:55:23,658 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:23,659 INFO L425 stractBuchiCegarLoop]: Abstraction has 669 states and 975 transitions. [2024-11-23 02:55:23,659 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-23 02:55:23,659 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 669 states and 975 transitions. [2024-11-23 02:55:23,661 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 603 [2024-11-23 02:55:23,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:23,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:23,662 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,665 INFO L745 eck$LassoCheckResult]: Stem: 5252#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 5253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5322#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5323#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5151#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 5152#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5350#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5250#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5086#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5087#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5106#L502 assume !(0 == ~M_E~0); 5107#L502-2 assume !(0 == ~T1_E~0); 5072#L507-1 assume !(0 == ~T2_E~0); 5073#L512-1 assume !(0 == ~T3_E~0); 5153#L517-1 assume !(0 == ~T4_E~0); 5060#L522-1 assume !(0 == ~E_1~0); 5061#L527-1 assume !(0 == ~E_2~0); 5255#L532-1 assume !(0 == ~E_3~0); 5256#L537-1 assume !(0 == ~E_4~0); 5274#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5248#L238 assume !(1 == ~m_pc~0); 5249#L238-2 is_master_triggered_~__retres1~0#1 := 0; 5297#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5230#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5228#L615 assume !(0 != activate_threads_~tmp~1#1); 5229#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5211#L257 assume 1 == ~t1_pc~0; 5212#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5245#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5104#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5105#L623 assume !(0 != activate_threads_~tmp___0~0#1); 5088#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5089#L276 assume !(1 == ~t2_pc~0); 5327#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5409#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5325#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5326#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5434#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5227#L295 assume 1 == ~t3_pc~0; 5118#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5094#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5055#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5056#L639 assume !(0 != activate_threads_~tmp___2~0#1); 5427#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5428#L314 assume !(1 == ~t4_pc~0); 5112#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5111#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5143#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5144#L647 assume !(0 != activate_threads_~tmp___3~0#1); 5210#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5405#L555 assume !(1 == ~M_E~0); 5121#L555-2 assume !(1 == ~T1_E~0); 5122#L560-1 assume !(1 == ~T2_E~0); 5062#L565-1 assume !(1 == ~T3_E~0); 5063#L570-1 assume !(1 == ~T4_E~0); 5217#L575-1 assume !(1 == ~E_1~0); 5355#L580-1 assume !(1 == ~E_2~0); 5266#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5101#L590-1 assume !(1 == ~E_4~0); 5095#L595-1 assume { :end_inline_reset_delta_events } true; 5096#L776-2 [2024-11-23 02:55:23,665 INFO L747 eck$LassoCheckResult]: Loop: 5096#L776-2 assume !false; 5077#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5078#L477-1 assume !false; 5373#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5374#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5198#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5334#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5338#L416 assume !(0 != eval_~tmp~0#1); 5344#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5703#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5701#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5700#L502-5 assume !(0 == ~T1_E~0); 5699#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5697#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5696#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5695#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5694#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5693#L532-3 assume !(0 == ~E_3~0); 5692#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5157#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5158#L238-15 assume !(1 == ~m_pc~0); 5205#L238-17 is_master_triggered_~__retres1~0#1 := 0; 5246#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5141#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5142#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5292#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5293#L257-15 assume 1 == ~t1_pc~0; 5302#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5184#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5378#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5379#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5420#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5425#L276-15 assume 1 == ~t2_pc~0; 5390#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5385#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5386#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5315#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5316#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5090#L295-15 assume 1 == ~t3_pc~0; 5091#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5310#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5431#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5300#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5257#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5258#L314-15 assume !(1 == ~t4_pc~0); 5298#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 5319#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5320#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5421#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5254#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5203#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5204#L555-5 assume !(1 == ~T1_E~0); 5128#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5129#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5422#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5412#L575-3 assume !(1 == ~E_1~0); 5330#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5331#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5369#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5370#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5301#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5082#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5182#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5225#L795 assume !(0 == start_simulation_~tmp~3#1); 5226#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5241#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5242#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5102#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5103#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5123#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5124#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5408#L808 assume !(0 != start_simulation_~tmp___0~1#1); 5096#L776-2 [2024-11-23 02:55:23,666 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,666 INFO L85 PathProgramCache]: Analyzing trace with hash -1404384723, now seen corresponding path program 1 times [2024-11-23 02:55:23,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115647042] [2024-11-23 02:55:23,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:23,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,691 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,691 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115647042] [2024-11-23 02:55:23,691 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115647042] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,691 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:23,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18082234] [2024-11-23 02:55:23,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,691 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:23,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,692 INFO L85 PathProgramCache]: Analyzing trace with hash -115260437, now seen corresponding path program 1 times [2024-11-23 02:55:23,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855837743] [2024-11-23 02:55:23,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:23,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855837743] [2024-11-23 02:55:23,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855837743] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:23,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [658937182] [2024-11-23 02:55:23,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,721 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:23,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:23,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:23,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:23,722 INFO L87 Difference]: Start difference. First operand 669 states and 975 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:23,770 INFO L93 Difference]: Finished difference Result 1189 states and 1721 transitions. [2024-11-23 02:55:23,770 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1189 states and 1721 transitions. [2024-11-23 02:55:23,774 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1118 [2024-11-23 02:55:23,778 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1189 states to 1189 states and 1721 transitions. [2024-11-23 02:55:23,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1189 [2024-11-23 02:55:23,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1189 [2024-11-23 02:55:23,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1189 states and 1721 transitions. [2024-11-23 02:55:23,780 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:23,780 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1189 states and 1721 transitions. [2024-11-23 02:55:23,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1189 states and 1721 transitions. [2024-11-23 02:55:23,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1189 to 1185. [2024-11-23 02:55:23,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.448945147679325) internal successors, (1717), 1184 states have internal predecessors, (1717), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:23,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1717 transitions. [2024-11-23 02:55:23,793 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1717 transitions. [2024-11-23 02:55:23,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:23,794 INFO L425 stractBuchiCegarLoop]: Abstraction has 1185 states and 1717 transitions. [2024-11-23 02:55:23,794 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-23 02:55:23,794 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1717 transitions. [2024-11-23 02:55:23,798 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1114 [2024-11-23 02:55:23,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:23,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:23,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,800 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:23,800 INFO L745 eck$LassoCheckResult]: Stem: 7117#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 7118#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7195#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7196#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7016#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 7017#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7229#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7115#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6951#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6952#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6971#L502 assume !(0 == ~M_E~0); 6972#L502-2 assume !(0 == ~T1_E~0); 6940#L507-1 assume !(0 == ~T2_E~0); 6941#L512-1 assume !(0 == ~T3_E~0); 7019#L517-1 assume !(0 == ~T4_E~0); 6927#L522-1 assume !(0 == ~E_1~0); 6928#L527-1 assume !(0 == ~E_2~0); 7120#L532-1 assume !(0 == ~E_3~0); 7121#L537-1 assume !(0 == ~E_4~0); 7140#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7113#L238 assume !(1 == ~m_pc~0); 7114#L238-2 is_master_triggered_~__retres1~0#1 := 0; 7168#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7094#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7092#L615 assume !(0 != activate_threads_~tmp~1#1); 7093#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7075#L257 assume !(1 == ~t1_pc~0); 7076#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7112#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6969#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6970#L623 assume !(0 != activate_threads_~tmp___0~0#1); 6953#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6954#L276 assume !(1 == ~t2_pc~0); 7200#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7290#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7198#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7199#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7321#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7091#L295 assume 1 == ~t3_pc~0; 6983#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6959#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6920#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6921#L639 assume !(0 != activate_threads_~tmp___2~0#1); 7310#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7311#L314 assume !(1 == ~t4_pc~0); 6977#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6976#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7009#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7010#L647 assume !(0 != activate_threads_~tmp___3~0#1); 7074#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7286#L555 assume !(1 == ~M_E~0); 6986#L555-2 assume !(1 == ~T1_E~0); 6987#L560-1 assume !(1 == ~T2_E~0); 6929#L565-1 assume !(1 == ~T3_E~0); 6930#L570-1 assume !(1 == ~T4_E~0); 7080#L575-1 assume !(1 == ~E_1~0); 7234#L580-1 assume !(1 == ~E_2~0); 7132#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6968#L590-1 assume !(1 == ~E_4~0); 6960#L595-1 assume { :end_inline_reset_delta_events } true; 6961#L776-2 [2024-11-23 02:55:23,800 INFO L747 eck$LassoCheckResult]: Loop: 6961#L776-2 assume !false; 6942#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6943#L477-1 assume !false; 7252#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7253#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7063#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7208#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7222#L416 assume !(0 != eval_~tmp~0#1); 7012#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7013#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7056#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7057#L502-5 assume !(0 == ~T1_E~0); 7302#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7014#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7015#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7002#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7003#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7077#L532-3 assume !(0 == ~E_3~0); 7148#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7022#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7023#L238-15 assume !(1 == ~m_pc~0); 7070#L238-17 is_master_triggered_~__retres1~0#1 := 0; 7110#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7006#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7007#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7163#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7164#L257-15 assume !(1 == ~t1_pc~0); 7047#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 7048#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7258#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7259#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7304#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7309#L276-15 assume 1 == ~t2_pc~0; 7269#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7264#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7265#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7192#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7193#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6955#L295-15 assume 1 == ~t3_pc~0; 6956#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7183#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7316#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7171#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7122#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7123#L314-15 assume !(1 == ~t4_pc~0); 7169#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 7190#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7191#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7305#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7119#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7068#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7069#L555-5 assume !(1 == ~T1_E~0); 6993#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6994#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7306#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7294#L575-3 assume !(1 == ~E_1~0); 7203#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7204#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7248#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7249#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7854#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7850#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7849#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 7848#L795 assume !(0 == start_simulation_~tmp~3#1); 7130#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7105#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7106#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6966#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 6967#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6988#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6989#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7289#L808 assume !(0 != start_simulation_~tmp___0~1#1); 6961#L776-2 [2024-11-23 02:55:23,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1261932300, now seen corresponding path program 1 times [2024-11-23 02:55:23,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757562494] [2024-11-23 02:55:23,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:23,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,871 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757562494] [2024-11-23 02:55:23,871 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757562494] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,874 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,874 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:55:23,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1055223062] [2024-11-23 02:55:23,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,875 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:23,875 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:23,875 INFO L85 PathProgramCache]: Analyzing trace with hash -1423265206, now seen corresponding path program 1 times [2024-11-23 02:55:23,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:23,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1385960742] [2024-11-23 02:55:23,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:23,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:23,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:23,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:23,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:23,899 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1385960742] [2024-11-23 02:55:23,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1385960742] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:23,901 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:23,901 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:23,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1406266151] [2024-11-23 02:55:23,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:23,901 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:23,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:23,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:55:23,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:55:23,902 INFO L87 Difference]: Start difference. First operand 1185 states and 1717 transitions. cyclomatic complexity: 536 Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:24,003 INFO L93 Difference]: Finished difference Result 1248 states and 1780 transitions. [2024-11-23 02:55:24,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1248 states and 1780 transitions. [2024-11-23 02:55:24,009 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1174 [2024-11-23 02:55:24,013 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1248 states to 1248 states and 1780 transitions. [2024-11-23 02:55:24,013 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1248 [2024-11-23 02:55:24,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1248 [2024-11-23 02:55:24,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1248 states and 1780 transitions. [2024-11-23 02:55:24,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:24,015 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1248 states and 1780 transitions. [2024-11-23 02:55:24,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1248 states and 1780 transitions. [2024-11-23 02:55:24,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1248 to 1248. [2024-11-23 02:55:24,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1248 states, 1248 states have (on average 1.4262820512820513) internal successors, (1780), 1247 states have internal predecessors, (1780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1248 states to 1248 states and 1780 transitions. [2024-11-23 02:55:24,030 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1248 states and 1780 transitions. [2024-11-23 02:55:24,030 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:55:24,031 INFO L425 stractBuchiCegarLoop]: Abstraction has 1248 states and 1780 transitions. [2024-11-23 02:55:24,032 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-23 02:55:24,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1248 states and 1780 transitions. [2024-11-23 02:55:24,037 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1174 [2024-11-23 02:55:24,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:24,037 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:24,038 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,038 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,039 INFO L745 eck$LassoCheckResult]: Stem: 9555#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 9556#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 9634#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9635#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9458#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 9459#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9664#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9553#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9393#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9394#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9413#L502 assume !(0 == ~M_E~0); 9414#L502-2 assume !(0 == ~T1_E~0); 9382#L507-1 assume !(0 == ~T2_E~0); 9383#L512-1 assume !(0 == ~T3_E~0); 9461#L517-1 assume !(0 == ~T4_E~0); 9369#L522-1 assume !(0 == ~E_1~0); 9370#L527-1 assume !(0 == ~E_2~0); 9558#L532-1 assume !(0 == ~E_3~0); 9559#L537-1 assume !(0 == ~E_4~0); 9576#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9551#L238 assume !(1 == ~m_pc~0); 9552#L238-2 is_master_triggered_~__retres1~0#1 := 0; 9605#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9534#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9532#L615 assume !(0 != activate_threads_~tmp~1#1); 9533#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9516#L257 assume !(1 == ~t1_pc~0); 9517#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9550#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9411#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9412#L623 assume !(0 != activate_threads_~tmp___0~0#1); 9395#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9396#L276 assume !(1 == ~t2_pc~0); 9639#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9724#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9637#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9638#L631 assume !(0 != activate_threads_~tmp___1~0#1); 9753#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9531#L295 assume 1 == ~t3_pc~0; 9425#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9401#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9362#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9363#L639 assume !(0 != activate_threads_~tmp___2~0#1); 9744#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9745#L314 assume !(1 == ~t4_pc~0); 9419#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9418#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9451#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9452#L647 assume !(0 != activate_threads_~tmp___3~0#1); 9515#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9720#L555 assume !(1 == ~M_E~0); 9428#L555-2 assume !(1 == ~T1_E~0); 9429#L560-1 assume !(1 == ~T2_E~0); 9371#L565-1 assume !(1 == ~T3_E~0); 9372#L570-1 assume !(1 == ~T4_E~0); 9521#L575-1 assume !(1 == ~E_1~0); 9671#L580-1 assume !(1 == ~E_2~0); 9569#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9410#L590-1 assume !(1 == ~E_4~0); 9402#L595-1 assume { :end_inline_reset_delta_events } true; 9403#L776-2 [2024-11-23 02:55:24,039 INFO L747 eck$LassoCheckResult]: Loop: 9403#L776-2 assume !false; 10204#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10200#L477-1 assume !false; 10197#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10068#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10060#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10053#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10045#L416 assume !(0 != eval_~tmp~0#1); 10046#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10444#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10443#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10442#L502-5 assume !(0 == ~T1_E~0); 10440#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10439#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10438#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10437#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10435#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10433#L532-3 assume !(0 == ~E_3~0); 10431#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10429#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10427#L238-15 assume !(1 == ~m_pc~0); 10425#L238-17 is_master_triggered_~__retres1~0#1 := 0; 10423#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10421#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10419#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10417#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10415#L257-15 assume !(1 == ~t1_pc~0); 10413#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 10412#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10408#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10406#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10404#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10402#L276-15 assume 1 == ~t2_pc~0; 10400#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10401#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10445#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10389#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10387#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10385#L295-15 assume 1 == ~t3_pc~0; 10382#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10380#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10378#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10375#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10373#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10371#L314-15 assume !(1 == ~t4_pc~0); 10368#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 10366#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10364#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10362#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10360#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10358#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10356#L555-5 assume !(1 == ~T1_E~0); 10354#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10352#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10350#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10348#L575-3 assume !(1 == ~E_1~0); 10347#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10346#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10345#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10344#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10340#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10335#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10334#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 10329#L795 assume !(0 == start_simulation_~tmp~3#1); 10326#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10324#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10318#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10315#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 10313#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10252#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10230#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 10219#L808 assume !(0 != start_simulation_~tmp___0~1#1); 9403#L776-2 [2024-11-23 02:55:24,039 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,040 INFO L85 PathProgramCache]: Analyzing trace with hash 1127918794, now seen corresponding path program 1 times [2024-11-23 02:55:24,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610711346] [2024-11-23 02:55:24,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:24,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:24,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:24,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:24,078 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610711346] [2024-11-23 02:55:24,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [610711346] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:24,078 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:24,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:24,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256328055] [2024-11-23 02:55:24,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:24,079 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:24,079 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,079 INFO L85 PathProgramCache]: Analyzing trace with hash -1423265206, now seen corresponding path program 2 times [2024-11-23 02:55:24,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967401793] [2024-11-23 02:55:24,080 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:55:24,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,089 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:24,089 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-23 02:55:24,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:24,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:24,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967401793] [2024-11-23 02:55:24,110 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967401793] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:24,110 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:24,110 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:24,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [545283789] [2024-11-23 02:55:24,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:24,111 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:24,111 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:24,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:24,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:24,111 INFO L87 Difference]: Start difference. First operand 1248 states and 1780 transitions. cyclomatic complexity: 536 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:24,146 INFO L93 Difference]: Finished difference Result 2249 states and 3191 transitions. [2024-11-23 02:55:24,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2249 states and 3191 transitions. [2024-11-23 02:55:24,155 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2164 [2024-11-23 02:55:24,162 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2249 states to 2249 states and 3191 transitions. [2024-11-23 02:55:24,162 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2249 [2024-11-23 02:55:24,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2249 [2024-11-23 02:55:24,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2249 states and 3191 transitions. [2024-11-23 02:55:24,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:24,165 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2249 states and 3191 transitions. [2024-11-23 02:55:24,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2249 states and 3191 transitions. [2024-11-23 02:55:24,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2249 to 2241. [2024-11-23 02:55:24,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2241 states, 2241 states have (on average 1.4203480589022757) internal successors, (3183), 2240 states have internal predecessors, (3183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3183 transitions. [2024-11-23 02:55:24,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2241 states and 3183 transitions. [2024-11-23 02:55:24,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:24,191 INFO L425 stractBuchiCegarLoop]: Abstraction has 2241 states and 3183 transitions. [2024-11-23 02:55:24,191 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-23 02:55:24,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2241 states and 3183 transitions. [2024-11-23 02:55:24,198 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2156 [2024-11-23 02:55:24,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:24,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:24,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,199 INFO L745 eck$LassoCheckResult]: Stem: 13064#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 13065#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 13146#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13147#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12962#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 12963#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13181#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13062#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12897#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12898#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12916#L502 assume !(0 == ~M_E~0); 12917#L502-2 assume !(0 == ~T1_E~0); 12883#L507-1 assume !(0 == ~T2_E~0); 12884#L512-1 assume !(0 == ~T3_E~0); 12965#L517-1 assume !(0 == ~T4_E~0); 12871#L522-1 assume !(0 == ~E_1~0); 12872#L527-1 assume !(0 == ~E_2~0); 13067#L532-1 assume !(0 == ~E_3~0); 13068#L537-1 assume !(0 == ~E_4~0); 13085#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13060#L238 assume !(1 == ~m_pc~0); 13061#L238-2 is_master_triggered_~__retres1~0#1 := 0; 13114#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13042#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13040#L615 assume !(0 != activate_threads_~tmp~1#1); 13041#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13021#L257 assume !(1 == ~t1_pc~0); 13022#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13058#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12914#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12915#L623 assume !(0 != activate_threads_~tmp___0~0#1); 12899#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12900#L276 assume !(1 == ~t2_pc~0); 13154#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13247#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13152#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13153#L631 assume !(0 != activate_threads_~tmp___1~0#1); 13282#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13039#L295 assume !(1 == ~t3_pc~0); 12903#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12904#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12866#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12867#L639 assume !(0 != activate_threads_~tmp___2~0#1); 13268#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13269#L314 assume !(1 == ~t4_pc~0); 12922#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12921#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12955#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12956#L647 assume !(0 != activate_threads_~tmp___3~0#1); 13020#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13243#L555 assume !(1 == ~M_E~0); 12930#L555-2 assume !(1 == ~T1_E~0); 12931#L560-1 assume !(1 == ~T2_E~0); 12873#L565-1 assume !(1 == ~T3_E~0); 12874#L570-1 assume !(1 == ~T4_E~0); 13027#L575-1 assume !(1 == ~E_1~0); 13187#L580-1 assume !(1 == ~E_2~0); 13078#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 12913#L590-1 assume !(1 == ~E_4~0); 12905#L595-1 assume { :end_inline_reset_delta_events } true; 12906#L776-2 [2024-11-23 02:55:24,199 INFO L747 eck$LassoCheckResult]: Loop: 12906#L776-2 assume !false; 12888#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12889#L477-1 assume !false; 13209#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 13210#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 13009#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 13164#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13169#L416 assume !(0 != eval_~tmp~0#1); 12958#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12959#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13002#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13003#L502-5 assume !(0 == ~T1_E~0); 13260#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12960#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12961#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12948#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12949#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13023#L532-3 assume !(0 == ~E_3~0); 13093#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12968#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12969#L238-15 assume !(1 == ~m_pc~0); 13016#L238-17 is_master_triggered_~__retres1~0#1 := 0; 13059#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12950#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12951#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13109#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13110#L257-15 assume !(1 == ~t1_pc~0); 12994#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 12995#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13218#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13219#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13262#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13267#L276-15 assume 1 == ~t2_pc~0; 13228#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13230#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14935#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14933#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13143#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12901#L295-15 assume !(1 == ~t3_pc~0); 12902#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 14991#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13279#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13280#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14960#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14959#L314-15 assume !(1 == ~t4_pc~0); 14957#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 14956#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14955#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14954#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14953#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14952#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14951#L555-5 assume !(1 == ~T1_E~0); 14950#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14949#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14948#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14947#L575-3 assume !(1 == ~E_1~0); 14945#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14943#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14941#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14939#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14929#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12992#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12993#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 13036#L795 assume !(0 == start_simulation_~tmp~3#1); 13038#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 13052#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 13053#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12911#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 12912#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12932#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12933#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 13246#L808 assume !(0 != start_simulation_~tmp___0~1#1); 12906#L776-2 [2024-11-23 02:55:24,200 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1014532137, now seen corresponding path program 1 times [2024-11-23 02:55:24,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380191154] [2024-11-23 02:55:24,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:24,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:24,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:24,270 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:24,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [380191154] [2024-11-23 02:55:24,270 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [380191154] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:24,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:24,271 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:24,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104390238] [2024-11-23 02:55:24,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:24,271 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:24,271 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,271 INFO L85 PathProgramCache]: Analyzing trace with hash 1243051817, now seen corresponding path program 1 times [2024-11-23 02:55:24,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195958026] [2024-11-23 02:55:24,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:24,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:24,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:24,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:24,302 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195958026] [2024-11-23 02:55:24,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195958026] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:24,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:24,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:24,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537832821] [2024-11-23 02:55:24,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:24,303 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:24,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:24,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:55:24,303 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:55:24,304 INFO L87 Difference]: Start difference. First operand 2241 states and 3183 transitions. cyclomatic complexity: 950 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:24,425 INFO L93 Difference]: Finished difference Result 4638 states and 6533 transitions. [2024-11-23 02:55:24,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4638 states and 6533 transitions. [2024-11-23 02:55:24,455 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4428 [2024-11-23 02:55:24,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4638 states to 4638 states and 6533 transitions. [2024-11-23 02:55:24,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4638 [2024-11-23 02:55:24,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4638 [2024-11-23 02:55:24,486 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4638 states and 6533 transitions. [2024-11-23 02:55:24,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:24,494 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4638 states and 6533 transitions. [2024-11-23 02:55:24,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4638 states and 6533 transitions. [2024-11-23 02:55:24,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4638 to 4578. [2024-11-23 02:55:24,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4578 states, 4578 states have (on average 1.4104412407164701) internal successors, (6457), 4577 states have internal predecessors, (6457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4578 states to 4578 states and 6457 transitions. [2024-11-23 02:55:24,570 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4578 states and 6457 transitions. [2024-11-23 02:55:24,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:55:24,571 INFO L425 stractBuchiCegarLoop]: Abstraction has 4578 states and 6457 transitions. [2024-11-23 02:55:24,571 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-23 02:55:24,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4578 states and 6457 transitions. [2024-11-23 02:55:24,587 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4376 [2024-11-23 02:55:24,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:24,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:24,588 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,588 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,589 INFO L745 eck$LassoCheckResult]: Stem: 19953#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 19954#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 20044#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20045#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19851#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 19852#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20085#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19951#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19787#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19788#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19807#L502 assume !(0 == ~M_E~0); 19808#L502-2 assume !(0 == ~T1_E~0); 19775#L507-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19776#L512-1 assume !(0 == ~T3_E~0); 19854#L517-1 assume !(0 == ~T4_E~0); 19762#L522-1 assume !(0 == ~E_1~0); 19763#L527-1 assume !(0 == ~E_2~0); 19956#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 19957#L537-1 assume !(0 == ~E_4~0); 20279#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20278#L238 assume !(1 == ~m_pc~0); 20277#L238-2 is_master_triggered_~__retres1~0#1 := 0; 20276#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20275#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20274#L615 assume !(0 != activate_threads_~tmp~1#1); 20273#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20272#L257 assume !(1 == ~t1_pc~0); 20271#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20270#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20269#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20268#L623 assume !(0 != activate_threads_~tmp___0~0#1); 20267#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20266#L276 assume !(1 == ~t2_pc~0); 20265#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20285#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20283#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20260#L631 assume !(0 != activate_threads_~tmp___1~0#1); 20259#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20258#L295 assume !(1 == ~t3_pc~0); 20257#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20256#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20255#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20254#L639 assume !(0 != activate_threads_~tmp___2~0#1); 20253#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20252#L314 assume !(1 == ~t4_pc~0); 20251#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20249#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20248#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20247#L647 assume !(0 != activate_threads_~tmp___3~0#1); 20246#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20245#L555 assume !(1 == ~M_E~0); 20244#L555-2 assume !(1 == ~T1_E~0); 20243#L560-1 assume !(1 == ~T2_E~0); 20242#L565-1 assume !(1 == ~T3_E~0); 20241#L570-1 assume !(1 == ~T4_E~0); 20240#L575-1 assume !(1 == ~E_1~0); 20239#L580-1 assume !(1 == ~E_2~0); 20237#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 20238#L590-1 assume !(1 == ~E_4~0); 21949#L595-1 assume { :end_inline_reset_delta_events } true; 21947#L776-2 [2024-11-23 02:55:24,589 INFO L747 eck$LassoCheckResult]: Loop: 21947#L776-2 assume !false; 21922#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21921#L477-1 assume !false; 21920#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 21684#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 21680#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 21678#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21675#L416 assume !(0 != eval_~tmp~0#1); 21673#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21671#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21669#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21666#L502-5 assume !(0 == ~T1_E~0); 21664#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21660#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21658#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21656#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21654#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21651#L532-3 assume !(0 == ~E_3~0); 21649#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21647#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21645#L238-15 assume !(1 == ~m_pc~0); 21643#L238-17 is_master_triggered_~__retres1~0#1 := 0; 21641#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21640#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21639#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21638#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21637#L257-15 assume !(1 == ~t1_pc~0); 21636#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 21635#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21634#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21633#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21631#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21630#L276-15 assume 1 == ~t2_pc~0; 21628#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21627#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21625#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21619#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21617#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21615#L295-15 assume !(1 == ~t3_pc~0); 21613#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 21610#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21608#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21606#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21604#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21602#L314-15 assume !(1 == ~t4_pc~0); 21598#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 21596#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21594#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21591#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21589#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21587#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21585#L555-5 assume !(1 == ~T1_E~0); 21576#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21575#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21572#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21573#L575-3 assume !(1 == ~E_1~0); 21574#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21571#L585-3 assume !(1 == ~E_3~0); 21566#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21568#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 21562#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 21558#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 21557#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 21266#L795 assume !(0 == start_simulation_~tmp~3#1); 21268#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 21963#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 21958#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 21957#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 21956#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21955#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21954#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 21948#L808 assume !(0 != start_simulation_~tmp___0~1#1); 21947#L776-2 [2024-11-23 02:55:24,593 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,594 INFO L85 PathProgramCache]: Analyzing trace with hash -27236631, now seen corresponding path program 1 times [2024-11-23 02:55:24,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437542892] [2024-11-23 02:55:24,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:24,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:24,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:24,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:24,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437542892] [2024-11-23 02:55:24,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437542892] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:24,624 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:24,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:24,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [166139499] [2024-11-23 02:55:24,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:24,625 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:24,626 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,626 INFO L85 PathProgramCache]: Analyzing trace with hash -36811861, now seen corresponding path program 1 times [2024-11-23 02:55:24,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,626 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706644277] [2024-11-23 02:55:24,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:24,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:24,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:24,655 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:24,655 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706644277] [2024-11-23 02:55:24,655 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706644277] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:24,655 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:24,655 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:24,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038540734] [2024-11-23 02:55:24,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:24,656 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:24,656 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:24,656 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:24,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:24,657 INFO L87 Difference]: Start difference. First operand 4578 states and 6457 transitions. cyclomatic complexity: 1895 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:24,679 INFO L93 Difference]: Finished difference Result 4528 states and 6344 transitions. [2024-11-23 02:55:24,679 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4528 states and 6344 transitions. [2024-11-23 02:55:24,693 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4376 [2024-11-23 02:55:24,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4528 states to 4528 states and 6344 transitions. [2024-11-23 02:55:24,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4528 [2024-11-23 02:55:24,749 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4528 [2024-11-23 02:55:24,749 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4528 states and 6344 transitions. [2024-11-23 02:55:24,752 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:24,752 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4528 states and 6344 transitions. [2024-11-23 02:55:24,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4528 states and 6344 transitions. [2024-11-23 02:55:24,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4528 to 2658. [2024-11-23 02:55:24,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2658 states, 2658 states have (on average 1.3954100827689992) internal successors, (3709), 2657 states have internal predecessors, (3709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2658 states to 2658 states and 3709 transitions. [2024-11-23 02:55:24,788 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2658 states and 3709 transitions. [2024-11-23 02:55:24,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:24,788 INFO L425 stractBuchiCegarLoop]: Abstraction has 2658 states and 3709 transitions. [2024-11-23 02:55:24,788 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-23 02:55:24,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2658 states and 3709 transitions. [2024-11-23 02:55:24,794 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2528 [2024-11-23 02:55:24,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:24,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:24,795 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,795 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:24,795 INFO L745 eck$LassoCheckResult]: Stem: 29072#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 29073#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 29158#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29159#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28964#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 28965#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29198#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29070#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28899#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28900#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28918#L502 assume !(0 == ~M_E~0); 28919#L502-2 assume !(0 == ~T1_E~0); 28888#L507-1 assume !(0 == ~T2_E~0); 28889#L512-1 assume !(0 == ~T3_E~0); 28967#L517-1 assume !(0 == ~T4_E~0); 28875#L522-1 assume !(0 == ~E_1~0); 28876#L527-1 assume !(0 == ~E_2~0); 29075#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 29076#L537-1 assume !(0 == ~E_4~0); 29096#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29097#L238 assume !(1 == ~m_pc~0); 29126#L238-2 is_master_triggered_~__retres1~0#1 := 0; 29127#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29048#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29049#L615 assume !(0 != activate_threads_~tmp~1#1); 29184#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29185#L257 assume !(1 == ~t1_pc~0); 29216#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29217#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28916#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28917#L623 assume !(0 != activate_threads_~tmp___0~0#1); 28901#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28902#L276 assume !(1 == ~t2_pc~0); 29271#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29272#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29163#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29164#L631 assume !(0 != activate_threads_~tmp___1~0#1); 29322#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29323#L295 assume !(1 == ~t3_pc~0); 28905#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28906#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28868#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28869#L639 assume !(0 != activate_threads_~tmp___2~0#1); 29298#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29299#L314 assume !(1 == ~t4_pc~0); 28924#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28923#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28957#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28958#L647 assume !(0 != activate_threads_~tmp___3~0#1); 29266#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29267#L555 assume !(1 == ~M_E~0); 28932#L555-2 assume !(1 == ~T1_E~0); 28933#L560-1 assume !(1 == ~T2_E~0); 28877#L565-1 assume !(1 == ~T3_E~0); 28878#L570-1 assume !(1 == ~T4_E~0); 29205#L575-1 assume !(1 == ~E_1~0); 29206#L580-1 assume !(1 == ~E_2~0); 29350#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 28915#L590-1 assume !(1 == ~E_4~0); 28907#L595-1 assume { :end_inline_reset_delta_events } true; 28908#L776-2 [2024-11-23 02:55:24,796 INFO L747 eck$LassoCheckResult]: Loop: 28908#L776-2 assume !false; 28890#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28891#L477-1 assume !false; 29230#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29231#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 29011#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 29177#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 29181#L416 assume !(0 != eval_~tmp~0#1); 29192#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31381#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31379#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31377#L502-5 assume !(0 == ~T1_E~0); 31375#L507-3 assume !(0 == ~T2_E~0); 31373#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31371#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31369#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31367#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31359#L532-3 assume !(0 == ~E_3~0); 31360#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31498#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31496#L238-15 assume !(1 == ~m_pc~0); 31495#L238-17 is_master_triggered_~__retres1~0#1 := 0; 31494#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31492#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31491#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31490#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31489#L257-15 assume !(1 == ~t1_pc~0); 31488#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 31487#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31485#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31483#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31481#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31479#L276-15 assume 1 == ~t2_pc~0; 31476#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31474#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31473#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31469#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31466#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28903#L295-15 assume !(1 == ~t3_pc~0); 28904#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 29142#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29308#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31389#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31388#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31387#L314-15 assume !(1 == ~t4_pc~0); 31385#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 31384#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31383#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31382#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31380#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31378#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31376#L555-5 assume !(1 == ~T1_E~0); 31374#L560-3 assume !(1 == ~T2_E~0); 31372#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31370#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31368#L575-3 assume !(1 == ~E_1~0); 31366#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31314#L585-3 assume !(1 == ~E_3~0); 31311#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29265#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29131#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 28895#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 28995#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 29042#L795 assume !(0 == start_simulation_~tmp~3#1); 29043#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29059#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 29060#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 28913#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 28914#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28934#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28935#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 29270#L808 assume !(0 != start_simulation_~tmp___0~1#1); 28908#L776-2 [2024-11-23 02:55:24,796 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,796 INFO L85 PathProgramCache]: Analyzing trace with hash 1911925415, now seen corresponding path program 1 times [2024-11-23 02:55:24,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116482028] [2024-11-23 02:55:24,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:24,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:24,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:24,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:24,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116482028] [2024-11-23 02:55:24,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1116482028] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:24,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:24,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:24,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562237032] [2024-11-23 02:55:24,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:24,837 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:24,838 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:24,838 INFO L85 PathProgramCache]: Analyzing trace with hash -652636377, now seen corresponding path program 1 times [2024-11-23 02:55:24,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:24,838 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947098688] [2024-11-23 02:55:24,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:24,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:24,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:24,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:24,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:24,875 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1947098688] [2024-11-23 02:55:24,875 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1947098688] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:24,875 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:24,875 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:24,875 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1688834817] [2024-11-23 02:55:24,875 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:24,875 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:24,876 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:24,876 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:55:24,876 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:55:24,876 INFO L87 Difference]: Start difference. First operand 2658 states and 3709 transitions. cyclomatic complexity: 1059 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:24,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:24,938 INFO L93 Difference]: Finished difference Result 4117 states and 5747 transitions. [2024-11-23 02:55:24,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4117 states and 5747 transitions. [2024-11-23 02:55:24,952 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4004 [2024-11-23 02:55:24,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4117 states to 4117 states and 5747 transitions. [2024-11-23 02:55:24,978 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4117 [2024-11-23 02:55:24,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4117 [2024-11-23 02:55:24,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4117 states and 5747 transitions. [2024-11-23 02:55:24,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:24,984 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4117 states and 5747 transitions. [2024-11-23 02:55:24,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4117 states and 5747 transitions. [2024-11-23 02:55:25,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4117 to 2241. [2024-11-23 02:55:25,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2241 states, 2241 states have (on average 1.390004462293619) internal successors, (3115), 2240 states have internal predecessors, (3115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3115 transitions. [2024-11-23 02:55:25,022 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2241 states and 3115 transitions. [2024-11-23 02:55:25,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:55:25,023 INFO L425 stractBuchiCegarLoop]: Abstraction has 2241 states and 3115 transitions. [2024-11-23 02:55:25,023 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-23 02:55:25,023 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2241 states and 3115 transitions. [2024-11-23 02:55:25,031 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2156 [2024-11-23 02:55:25,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:25,031 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:25,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,032 INFO L745 eck$LassoCheckResult]: Stem: 35849#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 35850#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 35927#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35928#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35750#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 35751#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35962#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35847#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35684#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35685#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35704#L502 assume !(0 == ~M_E~0); 35705#L502-2 assume !(0 == ~T1_E~0); 35673#L507-1 assume !(0 == ~T2_E~0); 35674#L512-1 assume !(0 == ~T3_E~0); 35753#L517-1 assume !(0 == ~T4_E~0); 35660#L522-1 assume !(0 == ~E_1~0); 35661#L527-1 assume !(0 == ~E_2~0); 35852#L532-1 assume !(0 == ~E_3~0); 35853#L537-1 assume !(0 == ~E_4~0); 35871#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35845#L238 assume !(1 == ~m_pc~0); 35846#L238-2 is_master_triggered_~__retres1~0#1 := 0; 35899#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35827#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 35825#L615 assume !(0 != activate_threads_~tmp~1#1); 35826#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35808#L257 assume !(1 == ~t1_pc~0); 35809#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35844#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35702#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 35703#L623 assume !(0 != activate_threads_~tmp___0~0#1); 35686#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35687#L276 assume !(1 == ~t2_pc~0); 35933#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36029#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35931#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 35932#L631 assume !(0 != activate_threads_~tmp___1~0#1); 36065#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35824#L295 assume !(1 == ~t3_pc~0); 35691#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35692#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35653#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 35654#L639 assume !(0 != activate_threads_~tmp___2~0#1); 36053#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36054#L314 assume !(1 == ~t4_pc~0); 35710#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35709#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35743#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 35744#L647 assume !(0 != activate_threads_~tmp___3~0#1); 35807#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36024#L555 assume !(1 == ~M_E~0); 35718#L555-2 assume !(1 == ~T1_E~0); 35719#L560-1 assume !(1 == ~T2_E~0); 35662#L565-1 assume !(1 == ~T3_E~0); 35663#L570-1 assume !(1 == ~T4_E~0); 35814#L575-1 assume !(1 == ~E_1~0); 35968#L580-1 assume !(1 == ~E_2~0); 35864#L585-1 assume !(1 == ~E_3~0); 35701#L590-1 assume !(1 == ~E_4~0); 35693#L595-1 assume { :end_inline_reset_delta_events } true; 35694#L776-2 [2024-11-23 02:55:25,032 INFO L747 eck$LassoCheckResult]: Loop: 35694#L776-2 assume !false; 35675#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35676#L477-1 assume !false; 35989#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 35990#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 35796#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 35942#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35946#L416 assume !(0 != eval_~tmp~0#1); 35956#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37764#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37762#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37760#L502-5 assume !(0 == ~T1_E~0); 37758#L507-3 assume !(0 == ~T2_E~0); 37756#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37754#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37752#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37750#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37748#L532-3 assume !(0 == ~E_3~0); 37745#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37743#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37741#L238-15 assume !(1 == ~m_pc~0); 37739#L238-17 is_master_triggered_~__retres1~0#1 := 0; 37737#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37735#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 37732#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37730#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37728#L257-15 assume !(1 == ~t1_pc~0); 37726#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 37724#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37720#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37718#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37716#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37714#L276-15 assume 1 == ~t2_pc~0; 37712#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37713#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37770#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 37702#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37700#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37698#L295-15 assume !(1 == ~t3_pc~0); 37696#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 37694#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37692#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37689#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37688#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37687#L314-15 assume !(1 == ~t4_pc~0); 37685#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 35919#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35920#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37653#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37652#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37651#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37650#L555-5 assume !(1 == ~T1_E~0); 37649#L560-3 assume !(1 == ~T2_E~0); 37648#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37647#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37646#L575-3 assume !(1 == ~E_1~0); 37645#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37644#L585-3 assume !(1 == ~E_3~0); 37643#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36023#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 35903#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 35680#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 35780#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 35822#L795 assume !(0 == start_simulation_~tmp~3#1); 35823#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 35838#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 35839#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 35699#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 35700#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35720#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35721#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 36028#L808 assume !(0 != start_simulation_~tmp___0~1#1); 35694#L776-2 [2024-11-23 02:55:25,032 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,032 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 1 times [2024-11-23 02:55:25,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038314895] [2024-11-23 02:55:25,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,043 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,078 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,079 INFO L85 PathProgramCache]: Analyzing trace with hash -652636377, now seen corresponding path program 2 times [2024-11-23 02:55:25,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37036919] [2024-11-23 02:55:25,079 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:55:25,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,086 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:25,086 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-23 02:55:25,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,105 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37036919] [2024-11-23 02:55:25,105 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37036919] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,105 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,105 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:25,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320487107] [2024-11-23 02:55:25,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,105 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:25,106 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:25,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:25,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:25,106 INFO L87 Difference]: Start difference. First operand 2241 states and 3115 transitions. cyclomatic complexity: 882 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:25,168 INFO L93 Difference]: Finished difference Result 3409 states and 4693 transitions. [2024-11-23 02:55:25,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3409 states and 4693 transitions. [2024-11-23 02:55:25,230 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3273 [2024-11-23 02:55:25,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3409 states to 3409 states and 4693 transitions. [2024-11-23 02:55:25,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3409 [2024-11-23 02:55:25,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3409 [2024-11-23 02:55:25,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3409 states and 4693 transitions. [2024-11-23 02:55:25,248 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:25,248 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3409 states and 4693 transitions. [2024-11-23 02:55:25,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3409 states and 4693 transitions. [2024-11-23 02:55:25,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3409 to 3397. [2024-11-23 02:55:25,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3397 states, 3397 states have (on average 1.3773918163085075) internal successors, (4679), 3396 states have internal predecessors, (4679), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3397 states to 3397 states and 4679 transitions. [2024-11-23 02:55:25,295 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3397 states and 4679 transitions. [2024-11-23 02:55:25,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:25,296 INFO L425 stractBuchiCegarLoop]: Abstraction has 3397 states and 4679 transitions. [2024-11-23 02:55:25,296 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-23 02:55:25,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3397 states and 4679 transitions. [2024-11-23 02:55:25,305 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3265 [2024-11-23 02:55:25,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:25,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:25,305 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,306 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,306 INFO L745 eck$LassoCheckResult]: Stem: 41511#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 41512#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 41596#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41597#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41405#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 41406#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41635#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41509#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41340#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41341#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41360#L502 assume !(0 == ~M_E~0); 41361#L502-2 assume !(0 == ~T1_E~0); 41326#L507-1 assume !(0 == ~T2_E~0); 41327#L512-1 assume !(0 == ~T3_E~0); 41407#L517-1 assume !(0 == ~T4_E~0); 41313#L522-1 assume 0 == ~E_1~0;~E_1~0 := 1; 41314#L527-1 assume !(0 == ~E_2~0); 41835#L532-1 assume !(0 == ~E_3~0); 41758#L537-1 assume !(0 == ~E_4~0); 41759#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41834#L238 assume !(1 == ~m_pc~0); 41563#L238-2 is_master_triggered_~__retres1~0#1 := 0; 41564#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41830#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 41829#L615 assume !(0 != activate_threads_~tmp~1#1); 41828#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41467#L257 assume !(1 == ~t1_pc~0); 41468#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41505#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41358#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 41359#L623 assume !(0 != activate_threads_~tmp___0~0#1); 41342#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41343#L276 assume !(1 == ~t2_pc~0); 41714#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41796#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41789#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 41790#L631 assume !(0 != activate_threads_~tmp___1~0#1); 41756#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41757#L295 assume !(1 == ~t3_pc~0); 41347#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41348#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41308#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41309#L639 assume !(0 != activate_threads_~tmp___2~0#1); 41732#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41733#L314 assume !(1 == ~t4_pc~0); 41766#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41546#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41398#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41399#L647 assume !(0 != activate_threads_~tmp___3~0#1); 41699#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41700#L555 assume !(1 == ~M_E~0); 41773#L555-2 assume !(1 == ~T1_E~0); 41763#L560-1 assume !(1 == ~T2_E~0); 41764#L565-1 assume !(1 == ~T3_E~0); 41474#L570-1 assume !(1 == ~T4_E~0); 41475#L575-1 assume 1 == ~E_1~0;~E_1~0 := 2; 41641#L580-1 assume !(1 == ~E_2~0); 41529#L585-1 assume !(1 == ~E_3~0); 41357#L590-1 assume !(1 == ~E_4~0); 41349#L595-1 assume { :end_inline_reset_delta_events } true; 41350#L776-2 [2024-11-23 02:55:25,306 INFO L747 eck$LassoCheckResult]: Loop: 41350#L776-2 assume !false; 41911#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41910#L477-1 assume !false; 41909#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 41896#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 41891#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 41888#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 41882#L416 assume !(0 != eval_~tmp~0#1); 41883#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42301#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42297#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42288#L502-5 assume !(0 == ~T1_E~0); 42284#L507-3 assume !(0 == ~T2_E~0); 42283#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42282#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42280#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42279#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42278#L532-3 assume !(0 == ~E_3~0); 42277#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42276#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42275#L238-15 assume !(1 == ~m_pc~0); 42274#L238-17 is_master_triggered_~__retres1~0#1 := 0; 42273#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42272#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 42271#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42270#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42268#L257-15 assume !(1 == ~t1_pc~0); 42266#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 42264#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42262#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 42261#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42259#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42257#L276-15 assume !(1 == ~t2_pc~0); 42256#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 42500#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42497#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 42155#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 42152#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42150#L295-15 assume !(1 == ~t3_pc~0); 42149#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 42147#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42146#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 42145#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42142#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42140#L314-15 assume !(1 == ~t4_pc~0); 42137#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 42135#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42133#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42131#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42129#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42126#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42124#L555-5 assume !(1 == ~T1_E~0); 42122#L560-3 assume !(1 == ~T2_E~0); 42120#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42118#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42116#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42114#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42112#L585-3 assume !(1 == ~E_3~0); 42110#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42109#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 42021#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 42016#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 42006#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 41960#L795 assume !(0 == start_simulation_~tmp~3#1); 41957#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 41955#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 41949#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 41947#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 41945#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41943#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41941#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 41938#L808 assume !(0 != start_simulation_~tmp___0~1#1); 41350#L776-2 [2024-11-23 02:55:25,306 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,306 INFO L85 PathProgramCache]: Analyzing trace with hash 119200679, now seen corresponding path program 1 times [2024-11-23 02:55:25,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586956045] [2024-11-23 02:55:25,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:25,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1586956045] [2024-11-23 02:55:25,336 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1586956045] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,336 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:25,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28169455] [2024-11-23 02:55:25,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,337 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:25,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,337 INFO L85 PathProgramCache]: Analyzing trace with hash 941335938, now seen corresponding path program 1 times [2024-11-23 02:55:25,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7389808] [2024-11-23 02:55:25,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:25,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [7389808] [2024-11-23 02:55:25,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [7389808] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,378 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:55:25,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [604587652] [2024-11-23 02:55:25,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,378 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:25,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:25,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-23 02:55:25,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-23 02:55:25,379 INFO L87 Difference]: Start difference. First operand 3397 states and 4679 transitions. cyclomatic complexity: 1290 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:25,457 INFO L93 Difference]: Finished difference Result 4623 states and 6359 transitions. [2024-11-23 02:55:25,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4623 states and 6359 transitions. [2024-11-23 02:55:25,471 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 4333 [2024-11-23 02:55:25,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4623 states to 4623 states and 6359 transitions. [2024-11-23 02:55:25,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4623 [2024-11-23 02:55:25,483 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4623 [2024-11-23 02:55:25,483 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4623 states and 6359 transitions. [2024-11-23 02:55:25,486 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:25,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4623 states and 6359 transitions. [2024-11-23 02:55:25,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4623 states and 6359 transitions. [2024-11-23 02:55:25,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4623 to 3168. [2024-11-23 02:55:25,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3168 states, 3168 states have (on average 1.3778409090909092) internal successors, (4365), 3167 states have internal predecessors, (4365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3168 states to 3168 states and 4365 transitions. [2024-11-23 02:55:25,525 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3168 states and 4365 transitions. [2024-11-23 02:55:25,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-23 02:55:25,526 INFO L425 stractBuchiCegarLoop]: Abstraction has 3168 states and 4365 transitions. [2024-11-23 02:55:25,526 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-23 02:55:25,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3168 states and 4365 transitions. [2024-11-23 02:55:25,532 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3081 [2024-11-23 02:55:25,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:25,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:25,533 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,533 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,533 INFO L745 eck$LassoCheckResult]: Stem: 49535#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 49536#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 49613#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49614#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49435#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 49436#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49648#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49533#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49371#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49372#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49391#L502 assume !(0 == ~M_E~0); 49392#L502-2 assume !(0 == ~T1_E~0); 49357#L507-1 assume !(0 == ~T2_E~0); 49358#L512-1 assume !(0 == ~T3_E~0); 49437#L517-1 assume !(0 == ~T4_E~0); 49345#L522-1 assume !(0 == ~E_1~0); 49346#L527-1 assume !(0 == ~E_2~0); 49538#L532-1 assume !(0 == ~E_3~0); 49539#L537-1 assume !(0 == ~E_4~0); 49559#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49531#L238 assume !(1 == ~m_pc~0); 49532#L238-2 is_master_triggered_~__retres1~0#1 := 0; 49584#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49513#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 49511#L615 assume !(0 != activate_threads_~tmp~1#1); 49512#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49494#L257 assume !(1 == ~t1_pc~0); 49495#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49528#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49389#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 49390#L623 assume !(0 != activate_threads_~tmp___0~0#1); 49373#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49374#L276 assume !(1 == ~t2_pc~0); 49621#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49716#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49619#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 49620#L631 assume !(0 != activate_threads_~tmp___1~0#1); 49752#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49510#L295 assume !(1 == ~t3_pc~0); 49378#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49379#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49340#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 49341#L639 assume !(0 != activate_threads_~tmp___2~0#1); 49741#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49742#L314 assume !(1 == ~t4_pc~0); 49397#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49396#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49428#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49429#L647 assume !(0 != activate_threads_~tmp___3~0#1); 49493#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49711#L555 assume !(1 == ~M_E~0); 49405#L555-2 assume !(1 == ~T1_E~0); 49406#L560-1 assume !(1 == ~T2_E~0); 49347#L565-1 assume !(1 == ~T3_E~0); 49348#L570-1 assume !(1 == ~T4_E~0); 49500#L575-1 assume !(1 == ~E_1~0); 49654#L580-1 assume !(1 == ~E_2~0); 49552#L585-1 assume !(1 == ~E_3~0); 49386#L590-1 assume !(1 == ~E_4~0); 49380#L595-1 assume { :end_inline_reset_delta_events } true; 49381#L776-2 [2024-11-23 02:55:25,534 INFO L747 eck$LassoCheckResult]: Loop: 49381#L776-2 assume !false; 51384#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51383#L477-1 assume !false; 51382#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 51379#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 51374#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 51371#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 51366#L416 assume !(0 != eval_~tmp~0#1); 51367#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51565#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51564#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51563#L502-5 assume !(0 == ~T1_E~0); 51562#L507-3 assume !(0 == ~T2_E~0); 51561#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51560#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51559#L522-3 assume !(0 == ~E_1~0); 51558#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51557#L532-3 assume !(0 == ~E_3~0); 51556#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51555#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51554#L238-15 assume !(1 == ~m_pc~0); 51553#L238-17 is_master_triggered_~__retres1~0#1 := 0; 51552#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51551#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 51550#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51548#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51546#L257-15 assume !(1 == ~t1_pc~0); 51544#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 51542#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51540#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 51538#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51536#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51534#L276-15 assume 1 == ~t2_pc~0; 51531#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51528#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51525#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 51522#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51519#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51515#L295-15 assume !(1 == ~t3_pc~0); 51511#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 51507#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51503#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 51500#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51497#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51494#L314-15 assume !(1 == ~t4_pc~0); 51490#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 51487#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51484#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 51481#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51478#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51473#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51469#L555-5 assume !(1 == ~T1_E~0); 51465#L560-3 assume !(1 == ~T2_E~0); 51461#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51458#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51455#L575-3 assume !(1 == ~E_1~0); 51452#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51449#L585-3 assume !(1 == ~E_3~0); 51446#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51443#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 51439#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 51433#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 51429#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 51425#L795 assume !(0 == start_simulation_~tmp~3#1); 51422#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 51420#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 51414#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 51410#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 51408#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51404#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51398#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 51393#L808 assume !(0 != start_simulation_~tmp___0~1#1); 49381#L776-2 [2024-11-23 02:55:25,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,534 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 2 times [2024-11-23 02:55:25,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563375254] [2024-11-23 02:55:25,535 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:55:25,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,540 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:25,540 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:25,540 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,550 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,550 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,550 INFO L85 PathProgramCache]: Analyzing trace with hash 608280873, now seen corresponding path program 1 times [2024-11-23 02:55:25,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,550 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148294869] [2024-11-23 02:55:25,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:25,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [148294869] [2024-11-23 02:55:25,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [148294869] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,595 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,595 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:55:25,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561265423] [2024-11-23 02:55:25,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,595 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:25,595 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:25,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:55:25,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:55:25,596 INFO L87 Difference]: Start difference. First operand 3168 states and 4365 transitions. cyclomatic complexity: 1205 Second operand has 5 states, 5 states have (on average 14.4) internal successors, (72), 5 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:25,656 INFO L93 Difference]: Finished difference Result 3236 states and 4433 transitions. [2024-11-23 02:55:25,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3236 states and 4433 transitions. [2024-11-23 02:55:25,664 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3149 [2024-11-23 02:55:25,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3236 states to 3236 states and 4433 transitions. [2024-11-23 02:55:25,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3236 [2024-11-23 02:55:25,671 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3236 [2024-11-23 02:55:25,671 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3236 states and 4433 transitions. [2024-11-23 02:55:25,674 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:25,674 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3236 states and 4433 transitions. [2024-11-23 02:55:25,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3236 states and 4433 transitions. [2024-11-23 02:55:25,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3236 to 3204. [2024-11-23 02:55:25,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3204 states, 3204 states have (on average 1.3735955056179776) internal successors, (4401), 3203 states have internal predecessors, (4401), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3204 states to 3204 states and 4401 transitions. [2024-11-23 02:55:25,719 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3204 states and 4401 transitions. [2024-11-23 02:55:25,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:55:25,719 INFO L425 stractBuchiCegarLoop]: Abstraction has 3204 states and 4401 transitions. [2024-11-23 02:55:25,719 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-23 02:55:25,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3204 states and 4401 transitions. [2024-11-23 02:55:25,725 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3117 [2024-11-23 02:55:25,725 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:25,725 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:25,726 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,726 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:25,726 INFO L745 eck$LassoCheckResult]: Stem: 55948#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 55949#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 56028#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56029#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55848#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 55849#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56064#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55946#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55783#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55784#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55802#L502 assume !(0 == ~M_E~0); 55803#L502-2 assume !(0 == ~T1_E~0); 55769#L507-1 assume !(0 == ~T2_E~0); 55770#L512-1 assume !(0 == ~T3_E~0); 55850#L517-1 assume !(0 == ~T4_E~0); 55757#L522-1 assume !(0 == ~E_1~0); 55758#L527-1 assume !(0 == ~E_2~0); 55951#L532-1 assume !(0 == ~E_3~0); 55952#L537-1 assume !(0 == ~E_4~0); 55972#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55944#L238 assume !(1 == ~m_pc~0); 55945#L238-2 is_master_triggered_~__retres1~0#1 := 0; 55998#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55927#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 55925#L615 assume !(0 != activate_threads_~tmp~1#1); 55926#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55908#L257 assume !(1 == ~t1_pc~0); 55909#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55941#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55800#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 55801#L623 assume !(0 != activate_threads_~tmp___0~0#1); 55785#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55786#L276 assume !(1 == ~t2_pc~0); 56035#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56143#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56033#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56034#L631 assume !(0 != activate_threads_~tmp___1~0#1); 56191#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55924#L295 assume !(1 == ~t3_pc~0); 55789#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55790#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55752#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55753#L639 assume !(0 != activate_threads_~tmp___2~0#1); 56176#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56177#L314 assume !(1 == ~t4_pc~0); 55808#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55807#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55840#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55841#L647 assume !(0 != activate_threads_~tmp___3~0#1); 55907#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56137#L555 assume !(1 == ~M_E~0); 55816#L555-2 assume !(1 == ~T1_E~0); 55817#L560-1 assume !(1 == ~T2_E~0); 55759#L565-1 assume !(1 == ~T3_E~0); 55760#L570-1 assume !(1 == ~T4_E~0); 55914#L575-1 assume !(1 == ~E_1~0); 56073#L580-1 assume !(1 == ~E_2~0); 55964#L585-1 assume !(1 == ~E_3~0); 55797#L590-1 assume !(1 == ~E_4~0); 55791#L595-1 assume { :end_inline_reset_delta_events } true; 55792#L776-2 [2024-11-23 02:55:25,727 INFO L747 eck$LassoCheckResult]: Loop: 55792#L776-2 assume !false; 57994#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57993#L477-1 assume !false; 57992#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 57989#L374 assume !(0 == ~m_st~0); 57990#L378 assume !(0 == ~t1_st~0); 57991#L382 assume !(0 == ~t2_st~0); 57986#L386 assume !(0 == ~t3_st~0); 57988#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 57981#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 57982#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 58852#L416 assume !(0 != eval_~tmp~0#1); 58850#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58847#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58845#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 58844#L502-5 assume !(0 == ~T1_E~0); 58843#L507-3 assume !(0 == ~T2_E~0); 58842#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58796#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55834#L522-3 assume !(0 == ~E_1~0); 55835#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55910#L532-3 assume !(0 == ~E_3~0); 55980#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55854#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55855#L238-15 assume !(1 == ~m_pc~0); 55901#L238-17 is_master_triggered_~__retres1~0#1 := 0; 55942#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55836#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 55837#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55992#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55993#L257-15 assume !(1 == ~t1_pc~0); 56063#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 58941#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58940#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 58939#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58938#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58937#L276-15 assume !(1 == ~t2_pc~0); 58916#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 58915#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58913#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 58910#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 58907#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58906#L295-15 assume !(1 == ~t3_pc~0); 58905#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 58904#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58903#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 58902#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58901#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58900#L314-15 assume !(1 == ~t4_pc~0); 58898#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 56022#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56023#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56174#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56175#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58838#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 56043#L555-5 assume !(1 == ~T1_E~0); 55822#L560-3 assume !(1 == ~T2_E~0); 55823#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58716#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58715#L575-3 assume !(1 == ~E_1~0); 56038#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56039#L585-3 assume !(1 == ~E_3~0); 56091#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56092#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 56003#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 55779#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 55999#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 55922#L795 assume !(0 == start_simulation_~tmp~3#1); 55923#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 58096#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 58008#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 58006#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 58005#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 58003#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 58001#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 57999#L808 assume !(0 != start_simulation_~tmp___0~1#1); 55792#L776-2 [2024-11-23 02:55:25,727 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,727 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 3 times [2024-11-23 02:55:25,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262646370] [2024-11-23 02:55:25,728 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-23 02:55:25,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,734 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-23 02:55:25,735 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:25,735 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:25,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:25,750 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:25,751 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:25,751 INFO L85 PathProgramCache]: Analyzing trace with hash -1629619846, now seen corresponding path program 1 times [2024-11-23 02:55:25,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:25,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461849375] [2024-11-23 02:55:25,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:25,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:25,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:25,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:25,806 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:25,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [461849375] [2024-11-23 02:55:25,807 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [461849375] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:25,807 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:25,807 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-23 02:55:25,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982099984] [2024-11-23 02:55:25,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:25,807 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:25,808 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:25,808 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-23 02:55:25,808 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-23 02:55:25,808 INFO L87 Difference]: Start difference. First operand 3204 states and 4401 transitions. cyclomatic complexity: 1205 Second operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 5 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:25,897 INFO L93 Difference]: Finished difference Result 3285 states and 4458 transitions. [2024-11-23 02:55:25,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3285 states and 4458 transitions. [2024-11-23 02:55:25,906 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3198 [2024-11-23 02:55:25,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3285 states to 3285 states and 4458 transitions. [2024-11-23 02:55:25,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3285 [2024-11-23 02:55:25,920 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3285 [2024-11-23 02:55:25,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3285 states and 4458 transitions. [2024-11-23 02:55:25,923 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:25,923 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3285 states and 4458 transitions. [2024-11-23 02:55:25,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3285 states and 4458 transitions. [2024-11-23 02:55:25,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3285 to 3285. [2024-11-23 02:55:25,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3285 states, 3285 states have (on average 1.3570776255707762) internal successors, (4458), 3284 states have internal predecessors, (4458), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:25,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3285 states to 3285 states and 4458 transitions. [2024-11-23 02:55:25,991 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3285 states and 4458 transitions. [2024-11-23 02:55:25,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-23 02:55:25,992 INFO L425 stractBuchiCegarLoop]: Abstraction has 3285 states and 4458 transitions. [2024-11-23 02:55:25,992 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-23 02:55:25,992 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3285 states and 4458 transitions. [2024-11-23 02:55:26,002 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3198 [2024-11-23 02:55:26,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:26,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:26,004 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:26,004 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:26,004 INFO L745 eck$LassoCheckResult]: Stem: 62446#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 62447#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 62536#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62537#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62344#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 62345#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62573#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62444#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62280#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62281#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62299#L502 assume !(0 == ~M_E~0); 62300#L502-2 assume !(0 == ~T1_E~0); 62266#L507-1 assume !(0 == ~T2_E~0); 62267#L512-1 assume !(0 == ~T3_E~0); 62346#L517-1 assume !(0 == ~T4_E~0); 62254#L522-1 assume !(0 == ~E_1~0); 62255#L527-1 assume !(0 == ~E_2~0); 62449#L532-1 assume !(0 == ~E_3~0); 62450#L537-1 assume !(0 == ~E_4~0); 62470#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62442#L238 assume !(1 == ~m_pc~0); 62443#L238-2 is_master_triggered_~__retres1~0#1 := 0; 62498#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62425#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 62423#L615 assume !(0 != activate_threads_~tmp~1#1); 62424#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62405#L257 assume !(1 == ~t1_pc~0); 62406#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62439#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62297#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 62298#L623 assume !(0 != activate_threads_~tmp___0~0#1); 62282#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62283#L276 assume !(1 == ~t2_pc~0); 62542#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 62656#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62540#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 62541#L631 assume !(0 != activate_threads_~tmp___1~0#1); 62710#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62422#L295 assume !(1 == ~t3_pc~0); 62286#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62287#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62249#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 62250#L639 assume !(0 != activate_threads_~tmp___2~0#1); 62686#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62687#L314 assume !(1 == ~t4_pc~0); 62305#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 62304#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62336#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 62337#L647 assume !(0 != activate_threads_~tmp___3~0#1); 62404#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62647#L555 assume !(1 == ~M_E~0); 62313#L555-2 assume !(1 == ~T1_E~0); 62314#L560-1 assume !(1 == ~T2_E~0); 62256#L565-1 assume !(1 == ~T3_E~0); 62257#L570-1 assume !(1 == ~T4_E~0); 62411#L575-1 assume !(1 == ~E_1~0); 62582#L580-1 assume !(1 == ~E_2~0); 62462#L585-1 assume !(1 == ~E_3~0); 62294#L590-1 assume !(1 == ~E_4~0); 62288#L595-1 assume { :end_inline_reset_delta_events } true; 62289#L776-2 [2024-11-23 02:55:26,004 INFO L747 eck$LassoCheckResult]: Loop: 62289#L776-2 assume !false; 63401#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63400#L477-1 assume !false; 63399#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 63395#L374 assume !(0 == ~m_st~0); 63396#L378 assume !(0 == ~t1_st~0); 63398#L382 assume !(0 == ~t2_st~0); 63393#L386 assume !(0 == ~t3_st~0); 63394#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 63397#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 62874#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 62875#L416 assume !(0 != eval_~tmp~0#1); 63584#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63583#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63582#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63581#L502-5 assume !(0 == ~T1_E~0); 63580#L507-3 assume !(0 == ~T2_E~0); 63579#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 63578#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63577#L522-3 assume !(0 == ~E_1~0); 63576#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 63575#L532-3 assume !(0 == ~E_3~0); 63574#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 63573#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63572#L238-15 assume !(1 == ~m_pc~0); 63571#L238-17 is_master_triggered_~__retres1~0#1 := 0; 63570#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63569#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 63568#L615-15 assume !(0 != activate_threads_~tmp~1#1); 63566#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63564#L257-15 assume !(1 == ~t1_pc~0); 63562#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 63560#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63558#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 63556#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 63554#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63552#L276-15 assume 1 == ~t2_pc~0; 63549#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 63546#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63543#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 63540#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 63537#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63533#L295-15 assume !(1 == ~t3_pc~0); 63529#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 63525#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63521#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 63518#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 63515#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63512#L314-15 assume !(1 == ~t4_pc~0); 63508#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 63505#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63502#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63499#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 63496#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63491#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 63487#L555-5 assume !(1 == ~T1_E~0); 63483#L560-3 assume !(1 == ~T2_E~0); 63479#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 63476#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63473#L575-3 assume !(1 == ~E_1~0); 63470#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 63467#L585-3 assume !(1 == ~E_3~0); 63464#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63461#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 63457#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 63451#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 63447#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 63443#L795 assume !(0 == start_simulation_~tmp~3#1); 63440#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 63438#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 63432#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 63428#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 63426#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63422#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63416#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 63410#L808 assume !(0 != start_simulation_~tmp___0~1#1); 62289#L776-2 [2024-11-23 02:55:26,005 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:26,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 4 times [2024-11-23 02:55:26,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:26,005 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [768692453] [2024-11-23 02:55:26,005 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-23 02:55:26,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:26,015 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-23 02:55:26,015 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:26,015 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:26,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:26,031 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:26,031 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:26,032 INFO L85 PathProgramCache]: Analyzing trace with hash 303917787, now seen corresponding path program 1 times [2024-11-23 02:55:26,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:26,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361523567] [2024-11-23 02:55:26,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:26,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:26,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:26,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:26,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:26,059 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [361523567] [2024-11-23 02:55:26,059 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [361523567] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:26,059 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:26,059 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:26,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121298732] [2024-11-23 02:55:26,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:26,060 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-23 02:55:26,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:26,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:26,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:26,061 INFO L87 Difference]: Start difference. First operand 3285 states and 4458 transitions. cyclomatic complexity: 1181 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:26,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:26,103 INFO L93 Difference]: Finished difference Result 5477 states and 7333 transitions. [2024-11-23 02:55:26,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5477 states and 7333 transitions. [2024-11-23 02:55:26,122 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 5374 [2024-11-23 02:55:26,135 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5477 states to 5477 states and 7333 transitions. [2024-11-23 02:55:26,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5477 [2024-11-23 02:55:26,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5477 [2024-11-23 02:55:26,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5477 states and 7333 transitions. [2024-11-23 02:55:26,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:26,146 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5477 states and 7333 transitions. [2024-11-23 02:55:26,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5477 states and 7333 transitions. [2024-11-23 02:55:26,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5477 to 5341. [2024-11-23 02:55:26,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5341 states, 5341 states have (on average 1.3407601572739187) internal successors, (7161), 5340 states have internal predecessors, (7161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:26,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5341 states to 5341 states and 7161 transitions. [2024-11-23 02:55:26,221 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5341 states and 7161 transitions. [2024-11-23 02:55:26,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:26,222 INFO L425 stractBuchiCegarLoop]: Abstraction has 5341 states and 7161 transitions. [2024-11-23 02:55:26,222 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-23 02:55:26,222 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5341 states and 7161 transitions. [2024-11-23 02:55:26,236 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 5238 [2024-11-23 02:55:26,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:26,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:26,237 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:26,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:26,238 INFO L745 eck$LassoCheckResult]: Stem: 71213#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 71214#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 71303#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 71304#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 71114#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 71115#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 71336#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 71211#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 71048#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71049#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 71067#L502 assume !(0 == ~M_E~0); 71068#L502-2 assume !(0 == ~T1_E~0); 71034#L507-1 assume !(0 == ~T2_E~0); 71035#L512-1 assume !(0 == ~T3_E~0); 71116#L517-1 assume !(0 == ~T4_E~0); 71022#L522-1 assume !(0 == ~E_1~0); 71023#L527-1 assume !(0 == ~E_2~0); 71217#L532-1 assume !(0 == ~E_3~0); 71218#L537-1 assume !(0 == ~E_4~0); 71239#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71209#L238 assume !(1 == ~m_pc~0); 71210#L238-2 is_master_triggered_~__retres1~0#1 := 0; 71269#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71193#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 71191#L615 assume !(0 != activate_threads_~tmp~1#1); 71192#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71173#L257 assume !(1 == ~t1_pc~0); 71174#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 71206#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71065#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 71066#L623 assume !(0 != activate_threads_~tmp___0~0#1); 71050#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71051#L276 assume !(1 == ~t2_pc~0); 71310#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 71404#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71308#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 71309#L631 assume !(0 != activate_threads_~tmp___1~0#1); 71449#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71190#L295 assume !(1 == ~t3_pc~0); 71054#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 71055#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71017#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 71018#L639 assume !(0 != activate_threads_~tmp___2~0#1); 71435#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71436#L314 assume !(1 == ~t4_pc~0); 71073#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 71072#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71105#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 71106#L647 assume !(0 != activate_threads_~tmp___3~0#1); 71172#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71400#L555 assume !(1 == ~M_E~0); 71081#L555-2 assume !(1 == ~T1_E~0); 71082#L560-1 assume !(1 == ~T2_E~0); 71024#L565-1 assume !(1 == ~T3_E~0); 71025#L570-1 assume !(1 == ~T4_E~0); 71179#L575-1 assume !(1 == ~E_1~0); 71344#L580-1 assume !(1 == ~E_2~0); 71231#L585-1 assume !(1 == ~E_3~0); 71062#L590-1 assume !(1 == ~E_4~0); 71056#L595-1 assume { :end_inline_reset_delta_events } true; 71057#L776-2 assume !false; 72650#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 72646#L477-1 [2024-11-23 02:55:26,238 INFO L747 eck$LassoCheckResult]: Loop: 72646#L477-1 assume !false; 72638#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 72631#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 72627#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 72622#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 72618#L416 assume 0 != eval_~tmp~0#1; 72614#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 72608#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 72603#L424-2 havoc eval_~tmp_ndt_1~0#1; 72597#L421-1 assume !(0 == ~t1_st~0); 72590#L435-1 assume !(0 == ~t2_st~0); 72584#L449-1 assume !(0 == ~t3_st~0); 72585#L463-1 assume !(0 == ~t4_st~0); 72646#L477-1 [2024-11-23 02:55:26,238 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:26,238 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 1 times [2024-11-23 02:55:26,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:26,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300935032] [2024-11-23 02:55:26,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:26,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:26,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:26,246 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:26,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:26,259 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:26,259 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:26,260 INFO L85 PathProgramCache]: Analyzing trace with hash 105152312, now seen corresponding path program 1 times [2024-11-23 02:55:26,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:26,260 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464402907] [2024-11-23 02:55:26,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:26,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:26,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:26,263 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:26,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:26,266 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:26,266 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:26,266 INFO L85 PathProgramCache]: Analyzing trace with hash 2080098156, now seen corresponding path program 1 times [2024-11-23 02:55:26,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:26,266 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937033342] [2024-11-23 02:55:26,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:26,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:26,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:26,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:26,293 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:26,293 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937033342] [2024-11-23 02:55:26,294 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937033342] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:26,294 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:26,294 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:26,294 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325829865] [2024-11-23 02:55:26,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:26,353 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:26,353 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:26,353 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:26,353 INFO L87 Difference]: Start difference. First operand 5341 states and 7161 transitions. cyclomatic complexity: 1834 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:26,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:26,428 INFO L93 Difference]: Finished difference Result 9872 states and 13121 transitions. [2024-11-23 02:55:26,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9872 states and 13121 transitions. [2024-11-23 02:55:26,463 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 9094 [2024-11-23 02:55:26,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9872 states to 9872 states and 13121 transitions. [2024-11-23 02:55:26,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9872 [2024-11-23 02:55:26,504 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9872 [2024-11-23 02:55:26,504 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9872 states and 13121 transitions. [2024-11-23 02:55:26,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:26,514 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9872 states and 13121 transitions. [2024-11-23 02:55:26,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9872 states and 13121 transitions. [2024-11-23 02:55:26,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9872 to 9432. [2024-11-23 02:55:26,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9432 states, 9432 states have (on average 1.3317430025445292) internal successors, (12561), 9431 states have internal predecessors, (12561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:26,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9432 states to 9432 states and 12561 transitions. [2024-11-23 02:55:26,669 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9432 states and 12561 transitions. [2024-11-23 02:55:26,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:26,670 INFO L425 stractBuchiCegarLoop]: Abstraction has 9432 states and 12561 transitions. [2024-11-23 02:55:26,670 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-23 02:55:26,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9432 states and 12561 transitions. [2024-11-23 02:55:26,698 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 8654 [2024-11-23 02:55:26,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:26,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:26,699 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:26,699 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:26,699 INFO L745 eck$LassoCheckResult]: Stem: 86437#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 86438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 86525#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86526#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86334#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 86335#L341-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 86702#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87688#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87687#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87686#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87685#L502 assume !(0 == ~M_E~0); 87684#L502-2 assume !(0 == ~T1_E~0); 87683#L507-1 assume !(0 == ~T2_E~0); 87682#L512-1 assume !(0 == ~T3_E~0); 87681#L517-1 assume !(0 == ~T4_E~0); 87680#L522-1 assume !(0 == ~E_1~0); 87679#L527-1 assume !(0 == ~E_2~0); 87678#L532-1 assume !(0 == ~E_3~0); 87677#L537-1 assume !(0 == ~E_4~0); 87676#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87675#L238 assume !(1 == ~m_pc~0); 87674#L238-2 is_master_triggered_~__retres1~0#1 := 0; 87673#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87672#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 87671#L615 assume !(0 != activate_threads_~tmp~1#1); 87670#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86394#L257 assume !(1 == ~t1_pc~0); 86395#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86431#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86432#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 87663#L623 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 86534#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86531#L276 assume !(1 == ~t2_pc~0); 86532#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86683#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86684#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 86688#L631 assume !(0 != activate_threads_~tmp___1~0#1); 86689#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86412#L295 assume !(1 == ~t3_pc~0); 86413#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86400#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86401#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86671#L639 assume !(0 != activate_threads_~tmp___2~0#1); 86672#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86707#L314 assume !(1 == ~t4_pc~0); 86708#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 86474#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86475#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 86392#L647 assume !(0 != activate_threads_~tmp___3~0#1); 86393#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86721#L555 assume !(1 == ~M_E~0); 86722#L555-2 assume !(1 == ~T1_E~0); 86703#L560-1 assume !(1 == ~T2_E~0); 86704#L565-1 assume !(1 == ~T3_E~0); 87586#L570-1 assume !(1 == ~T4_E~0); 87585#L575-1 assume !(1 == ~E_1~0); 87584#L580-1 assume !(1 == ~E_2~0); 87583#L585-1 assume !(1 == ~E_3~0); 86285#L590-1 assume !(1 == ~E_4~0); 86286#L595-1 assume { :end_inline_reset_delta_events } true; 87537#L776-2 assume !false; 87530#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 87527#L477-1 [2024-11-23 02:55:26,703 INFO L747 eck$LassoCheckResult]: Loop: 87527#L477-1 assume !false; 87522#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 87517#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 87512#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 87509#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 87505#L416 assume 0 != eval_~tmp~0#1; 87501#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 87496#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 87497#L424-2 havoc eval_~tmp_ndt_1~0#1; 87580#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 87577#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 87575#L438-2 havoc eval_~tmp_ndt_2~0#1; 87562#L435-1 assume !(0 == ~t2_st~0); 87541#L449-1 assume !(0 == ~t3_st~0); 87532#L463-1 assume !(0 == ~t4_st~0); 87527#L477-1 [2024-11-23 02:55:26,704 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:26,704 INFO L85 PathProgramCache]: Analyzing trace with hash 995820945, now seen corresponding path program 1 times [2024-11-23 02:55:26,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:26,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250150623] [2024-11-23 02:55:26,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:26,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:26,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:26,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:26,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:26,726 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250150623] [2024-11-23 02:55:26,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [250150623] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:26,726 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:26,726 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:26,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [680426254] [2024-11-23 02:55:26,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:26,727 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-23 02:55:26,728 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:26,728 INFO L85 PathProgramCache]: Analyzing trace with hash 1964339025, now seen corresponding path program 1 times [2024-11-23 02:55:26,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:26,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947581217] [2024-11-23 02:55:26,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:26,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:26,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:26,732 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:26,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:26,735 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:26,800 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:26,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:26,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:26,801 INFO L87 Difference]: Start difference. First operand 9432 states and 12561 transitions. cyclomatic complexity: 3149 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:26,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:26,821 INFO L93 Difference]: Finished difference Result 7188 states and 9566 transitions. [2024-11-23 02:55:26,821 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7188 states and 9566 transitions. [2024-11-23 02:55:26,841 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 7073 [2024-11-23 02:55:26,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7188 states to 7188 states and 9566 transitions. [2024-11-23 02:55:26,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7188 [2024-11-23 02:55:26,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7188 [2024-11-23 02:55:26,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7188 states and 9566 transitions. [2024-11-23 02:55:26,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:26,862 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7188 states and 9566 transitions. [2024-11-23 02:55:26,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7188 states and 9566 transitions. [2024-11-23 02:55:26,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7188 to 7188. [2024-11-23 02:55:26,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7188 states, 7188 states have (on average 1.3308291597106288) internal successors, (9566), 7187 states have internal predecessors, (9566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:26,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7188 states to 7188 states and 9566 transitions. [2024-11-23 02:55:26,931 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7188 states and 9566 transitions. [2024-11-23 02:55:26,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:26,932 INFO L425 stractBuchiCegarLoop]: Abstraction has 7188 states and 9566 transitions. [2024-11-23 02:55:26,932 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-23 02:55:26,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7188 states and 9566 transitions. [2024-11-23 02:55:26,948 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 7073 [2024-11-23 02:55:26,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:26,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:26,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:26,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:26,948 INFO L745 eck$LassoCheckResult]: Stem: 103060#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 103061#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 103144#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 103145#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 102959#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 102960#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 103181#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 103058#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 102895#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102896#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 102914#L502 assume !(0 == ~M_E~0); 102915#L502-2 assume !(0 == ~T1_E~0); 102884#L507-1 assume !(0 == ~T2_E~0); 102885#L512-1 assume !(0 == ~T3_E~0); 102963#L517-1 assume !(0 == ~T4_E~0); 102871#L522-1 assume !(0 == ~E_1~0); 102872#L527-1 assume !(0 == ~E_2~0); 103063#L532-1 assume !(0 == ~E_3~0); 103064#L537-1 assume !(0 == ~E_4~0); 103087#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103056#L238 assume !(1 == ~m_pc~0); 103057#L238-2 is_master_triggered_~__retres1~0#1 := 0; 103115#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103039#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 103037#L615 assume !(0 != activate_threads_~tmp~1#1); 103038#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103020#L257 assume !(1 == ~t1_pc~0); 103021#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 103055#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102912#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 102913#L623 assume !(0 != activate_threads_~tmp___0~0#1); 102897#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102898#L276 assume !(1 == ~t2_pc~0); 103150#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 103255#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103148#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 103149#L631 assume !(0 != activate_threads_~tmp___1~0#1); 103300#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103036#L295 assume !(1 == ~t3_pc~0); 102901#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102902#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102864#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 102865#L639 assume !(0 != activate_threads_~tmp___2~0#1); 103286#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103287#L314 assume !(1 == ~t4_pc~0); 102920#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 102919#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102952#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 102953#L647 assume !(0 != activate_threads_~tmp___3~0#1); 103019#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103250#L555 assume !(1 == ~M_E~0); 102928#L555-2 assume !(1 == ~T1_E~0); 102929#L560-1 assume !(1 == ~T2_E~0); 102873#L565-1 assume !(1 == ~T3_E~0); 102874#L570-1 assume !(1 == ~T4_E~0); 103026#L575-1 assume !(1 == ~E_1~0); 103188#L580-1 assume !(1 == ~E_2~0); 103079#L585-1 assume !(1 == ~E_3~0); 102911#L590-1 assume !(1 == ~E_4~0); 102903#L595-1 assume { :end_inline_reset_delta_events } true; 102904#L776-2 assume !false; 103525#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103521#L477-1 [2024-11-23 02:55:26,949 INFO L747 eck$LassoCheckResult]: Loop: 103521#L477-1 assume !false; 103519#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 103516#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 103515#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 103512#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 103493#L416 assume 0 != eval_~tmp~0#1; 103476#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 103433#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 103434#L424-2 havoc eval_~tmp_ndt_1~0#1; 103700#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 103695#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 103679#L438-2 havoc eval_~tmp_ndt_2~0#1; 103534#L435-1 assume !(0 == ~t2_st~0); 103530#L449-1 assume !(0 == ~t3_st~0); 103527#L463-1 assume !(0 == ~t4_st~0); 103521#L477-1 [2024-11-23 02:55:26,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:26,949 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 2 times [2024-11-23 02:55:26,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:26,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135016473] [2024-11-23 02:55:26,949 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:55:26,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:26,955 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:26,956 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:26,956 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:26,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:26,964 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:26,965 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:26,965 INFO L85 PathProgramCache]: Analyzing trace with hash 1964339025, now seen corresponding path program 2 times [2024-11-23 02:55:26,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:26,965 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574633799] [2024-11-23 02:55:26,965 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-23 02:55:26,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:26,969 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:26,969 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:26,969 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:26,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:26,972 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:26,972 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:26,972 INFO L85 PathProgramCache]: Analyzing trace with hash 1511750277, now seen corresponding path program 1 times [2024-11-23 02:55:26,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:26,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654282595] [2024-11-23 02:55:26,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:26,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:27,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:27,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:27,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:27,060 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654282595] [2024-11-23 02:55:27,060 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654282595] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:27,060 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:27,061 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:27,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083017928] [2024-11-23 02:55:27,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:27,117 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:27,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:27,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:27,118 INFO L87 Difference]: Start difference. First operand 7188 states and 9566 transitions. cyclomatic complexity: 2392 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:27,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:27,189 INFO L93 Difference]: Finished difference Result 12625 states and 16724 transitions. [2024-11-23 02:55:27,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12625 states and 16724 transitions. [2024-11-23 02:55:27,245 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 12462 [2024-11-23 02:55:27,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12625 states to 12625 states and 16724 transitions. [2024-11-23 02:55:27,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12625 [2024-11-23 02:55:27,296 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12625 [2024-11-23 02:55:27,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12625 states and 16724 transitions. [2024-11-23 02:55:27,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:27,307 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12625 states and 16724 transitions. [2024-11-23 02:55:27,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12625 states and 16724 transitions. [2024-11-23 02:55:27,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12625 to 11925. [2024-11-23 02:55:27,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11925 states, 11925 states have (on average 1.3269601677148848) internal successors, (15824), 11924 states have internal predecessors, (15824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:27,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11925 states to 11925 states and 15824 transitions. [2024-11-23 02:55:27,423 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11925 states and 15824 transitions. [2024-11-23 02:55:27,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:27,425 INFO L425 stractBuchiCegarLoop]: Abstraction has 11925 states and 15824 transitions. [2024-11-23 02:55:27,425 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-23 02:55:27,425 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11925 states and 15824 transitions. [2024-11-23 02:55:27,454 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 11762 [2024-11-23 02:55:27,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:27,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:27,455 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:27,455 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:27,455 INFO L745 eck$LassoCheckResult]: Stem: 122885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 122886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 122977#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122978#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 122779#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 122780#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 123018#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122882#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122715#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 122716#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 122735#L502 assume !(0 == ~M_E~0); 122736#L502-2 assume !(0 == ~T1_E~0); 122702#L507-1 assume !(0 == ~T2_E~0); 122703#L512-1 assume !(0 == ~T3_E~0); 122781#L517-1 assume !(0 == ~T4_E~0); 122690#L522-1 assume !(0 == ~E_1~0); 122691#L527-1 assume !(0 == ~E_2~0); 122888#L532-1 assume !(0 == ~E_3~0); 122889#L537-1 assume !(0 == ~E_4~0); 122912#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122880#L238 assume !(1 == ~m_pc~0); 122881#L238-2 is_master_triggered_~__retres1~0#1 := 0; 122945#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122862#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 122860#L615 assume !(0 != activate_threads_~tmp~1#1); 122861#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122841#L257 assume !(1 == ~t1_pc~0); 122842#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 122875#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122733#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 122734#L623 assume !(0 != activate_threads_~tmp___0~0#1); 122717#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122718#L276 assume !(1 == ~t2_pc~0); 122985#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 123099#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 122983#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 122984#L631 assume !(0 != activate_threads_~tmp___1~0#1); 123145#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122859#L295 assume !(1 == ~t3_pc~0); 122722#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 122723#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122685#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 122686#L639 assume !(0 != activate_threads_~tmp___2~0#1); 123134#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123135#L314 assume !(1 == ~t4_pc~0); 122741#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 122740#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 122771#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 122772#L647 assume !(0 != activate_threads_~tmp___3~0#1); 122840#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123095#L555 assume !(1 == ~M_E~0); 122749#L555-2 assume !(1 == ~T1_E~0); 122750#L560-1 assume !(1 == ~T2_E~0); 122692#L565-1 assume !(1 == ~T3_E~0); 122693#L570-1 assume !(1 == ~T4_E~0); 122848#L575-1 assume !(1 == ~E_1~0); 123024#L580-1 assume !(1 == ~E_2~0); 122901#L585-1 assume !(1 == ~E_3~0); 122730#L590-1 assume !(1 == ~E_4~0); 122724#L595-1 assume { :end_inline_reset_delta_events } true; 122725#L776-2 assume !false; 126431#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 126429#L477-1 [2024-11-23 02:55:27,455 INFO L747 eck$LassoCheckResult]: Loop: 126429#L477-1 assume !false; 126427#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 126424#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 126422#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 126421#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 126420#L416 assume 0 != eval_~tmp~0#1; 126418#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 126415#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 126416#L424-2 havoc eval_~tmp_ndt_1~0#1; 126592#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 126581#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 126560#L438-2 havoc eval_~tmp_ndt_2~0#1; 126444#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 126442#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 126440#L452-2 havoc eval_~tmp_ndt_3~0#1; 126437#L449-1 assume !(0 == ~t3_st~0); 126433#L463-1 assume !(0 == ~t4_st~0); 126429#L477-1 [2024-11-23 02:55:27,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:27,456 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 3 times [2024-11-23 02:55:27,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:27,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499468406] [2024-11-23 02:55:27,456 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-23 02:55:27,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:27,463 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2024-11-23 02:55:27,464 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:27,464 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:27,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:27,474 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:27,475 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:27,475 INFO L85 PathProgramCache]: Analyzing trace with hash 2090989624, now seen corresponding path program 1 times [2024-11-23 02:55:27,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:27,475 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1115086987] [2024-11-23 02:55:27,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:27,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:27,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:27,478 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:27,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:27,480 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:27,481 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:27,481 INFO L85 PathProgramCache]: Analyzing trace with hash 944899692, now seen corresponding path program 1 times [2024-11-23 02:55:27,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:27,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749129488] [2024-11-23 02:55:27,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:27,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:27,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:27,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:27,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:27,536 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749129488] [2024-11-23 02:55:27,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [749129488] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:27,536 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:27,536 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-23 02:55:27,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [602765064] [2024-11-23 02:55:27,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:27,587 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:27,588 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:27,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:27,588 INFO L87 Difference]: Start difference. First operand 11925 states and 15824 transitions. cyclomatic complexity: 3913 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:27,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:27,648 INFO L93 Difference]: Finished difference Result 14963 states and 19745 transitions. [2024-11-23 02:55:27,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14963 states and 19745 transitions. [2024-11-23 02:55:27,701 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 14772 [2024-11-23 02:55:27,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14963 states to 14963 states and 19745 transitions. [2024-11-23 02:55:27,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14963 [2024-11-23 02:55:27,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14963 [2024-11-23 02:55:27,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14963 states and 19745 transitions. [2024-11-23 02:55:27,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:27,757 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14963 states and 19745 transitions. [2024-11-23 02:55:27,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14963 states and 19745 transitions. [2024-11-23 02:55:27,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14963 to 14523. [2024-11-23 02:55:27,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14523 states, 14523 states have (on average 1.3210080561867383) internal successors, (19185), 14522 states have internal predecessors, (19185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:28,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14523 states to 14523 states and 19185 transitions. [2024-11-23 02:55:28,037 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14523 states and 19185 transitions. [2024-11-23 02:55:28,037 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:28,038 INFO L425 stractBuchiCegarLoop]: Abstraction has 14523 states and 19185 transitions. [2024-11-23 02:55:28,038 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-23 02:55:28,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14523 states and 19185 transitions. [2024-11-23 02:55:28,078 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 14332 [2024-11-23 02:55:28,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:28,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:28,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:28,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:28,080 INFO L745 eck$LassoCheckResult]: Stem: 149781#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 149782#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 149875#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 149876#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 149677#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 149678#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 149915#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 149779#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 149611#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 149612#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 149631#L502 assume !(0 == ~M_E~0); 149632#L502-2 assume !(0 == ~T1_E~0); 149598#L507-1 assume !(0 == ~T2_E~0); 149599#L512-1 assume !(0 == ~T3_E~0); 149679#L517-1 assume !(0 == ~T4_E~0); 149586#L522-1 assume !(0 == ~E_1~0); 149587#L527-1 assume !(0 == ~E_2~0); 149784#L532-1 assume !(0 == ~E_3~0); 149785#L537-1 assume !(0 == ~E_4~0); 149806#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 149777#L238 assume !(1 == ~m_pc~0); 149778#L238-2 is_master_triggered_~__retres1~0#1 := 0; 149837#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149761#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 149759#L615 assume !(0 != activate_threads_~tmp~1#1); 149760#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 149740#L257 assume !(1 == ~t1_pc~0); 149741#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 149774#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 149629#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 149630#L623 assume !(0 != activate_threads_~tmp___0~0#1); 149613#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 149614#L276 assume !(1 == ~t2_pc~0); 149883#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 149994#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 149881#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 149882#L631 assume !(0 != activate_threads_~tmp___1~0#1); 150040#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149758#L295 assume !(1 == ~t3_pc~0); 149618#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 149619#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 149581#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 149582#L639 assume !(0 != activate_threads_~tmp___2~0#1); 150024#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 150025#L314 assume !(1 == ~t4_pc~0); 149637#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 149636#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 149669#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 149670#L647 assume !(0 != activate_threads_~tmp___3~0#1); 149739#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 149988#L555 assume !(1 == ~M_E~0); 149645#L555-2 assume !(1 == ~T1_E~0); 149646#L560-1 assume !(1 == ~T2_E~0); 149588#L565-1 assume !(1 == ~T3_E~0); 149589#L570-1 assume !(1 == ~T4_E~0); 149747#L575-1 assume !(1 == ~E_1~0); 149922#L580-1 assume !(1 == ~E_2~0); 149797#L585-1 assume !(1 == ~E_3~0); 149626#L590-1 assume !(1 == ~E_4~0); 149620#L595-1 assume { :end_inline_reset_delta_events } true; 149621#L776-2 assume !false; 159438#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 159437#L477-1 [2024-11-23 02:55:28,080 INFO L747 eck$LassoCheckResult]: Loop: 159437#L477-1 assume !false; 159436#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 159394#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 159395#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 159467#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 159466#L416 assume 0 != eval_~tmp~0#1; 159463#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 159460#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 159459#L424-2 havoc eval_~tmp_ndt_1~0#1; 159458#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 159456#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 159455#L438-2 havoc eval_~tmp_ndt_2~0#1; 159454#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 159451#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 159449#L452-2 havoc eval_~tmp_ndt_3~0#1; 159447#L449-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 159445#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 159442#L466-2 havoc eval_~tmp_ndt_4~0#1; 159440#L463-1 assume !(0 == ~t4_st~0); 159437#L477-1 [2024-11-23 02:55:28,081 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:28,081 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 4 times [2024-11-23 02:55:28,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:28,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124329263] [2024-11-23 02:55:28,081 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-23 02:55:28,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:28,091 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-23 02:55:28,091 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:28,091 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:28,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:28,102 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:28,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:28,103 INFO L85 PathProgramCache]: Analyzing trace with hash -608301423, now seen corresponding path program 1 times [2024-11-23 02:55:28,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:28,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860034331] [2024-11-23 02:55:28,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:28,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:28,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:28,107 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:28,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:28,110 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:28,111 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:28,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1805868997, now seen corresponding path program 1 times [2024-11-23 02:55:28,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:28,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97684087] [2024-11-23 02:55:28,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:28,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:28,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-23 02:55:28,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-23 02:55:28,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-23 02:55:28,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [97684087] [2024-11-23 02:55:28,145 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [97684087] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-23 02:55:28,145 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-23 02:55:28,145 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-23 02:55:28,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1040642523] [2024-11-23 02:55:28,145 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-23 02:55:28,206 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-23 02:55:28,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-23 02:55:28,207 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-23 02:55:28,207 INFO L87 Difference]: Start difference. First operand 14523 states and 19185 transitions. cyclomatic complexity: 4677 Second operand has 3 states, 2 states have (on average 40.5) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:28,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-23 02:55:28,377 INFO L93 Difference]: Finished difference Result 27493 states and 36157 transitions. [2024-11-23 02:55:28,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27493 states and 36157 transitions. [2024-11-23 02:55:28,476 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 27178 [2024-11-23 02:55:28,570 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27493 states to 27493 states and 36157 transitions. [2024-11-23 02:55:28,570 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27493 [2024-11-23 02:55:28,592 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27493 [2024-11-23 02:55:28,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27493 states and 36157 transitions. [2024-11-23 02:55:28,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-23 02:55:28,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27493 states and 36157 transitions. [2024-11-23 02:55:28,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27493 states and 36157 transitions. [2024-11-23 02:55:28,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27493 to 27493. [2024-11-23 02:55:29,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27493 states, 27493 states have (on average 1.3151347615756739) internal successors, (36157), 27492 states have internal predecessors, (36157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-23 02:55:29,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27493 states to 27493 states and 36157 transitions. [2024-11-23 02:55:29,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27493 states and 36157 transitions. [2024-11-23 02:55:29,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-23 02:55:29,195 INFO L425 stractBuchiCegarLoop]: Abstraction has 27493 states and 36157 transitions. [2024-11-23 02:55:29,195 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-23 02:55:29,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27493 states and 36157 transitions. [2024-11-23 02:55:29,255 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 27178 [2024-11-23 02:55:29,255 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-23 02:55:29,255 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-23 02:55:29,255 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:29,255 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-23 02:55:29,256 INFO L745 eck$LassoCheckResult]: Stem: 191806#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 191807#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 191900#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 191901#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 191702#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 191703#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 191941#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 191804#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 191635#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 191636#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 191655#L502 assume !(0 == ~M_E~0); 191656#L502-2 assume !(0 == ~T1_E~0); 191622#L507-1 assume !(0 == ~T2_E~0); 191623#L512-1 assume !(0 == ~T3_E~0); 191704#L517-1 assume !(0 == ~T4_E~0); 191610#L522-1 assume !(0 == ~E_1~0); 191611#L527-1 assume !(0 == ~E_2~0); 191810#L532-1 assume !(0 == ~E_3~0); 191811#L537-1 assume !(0 == ~E_4~0); 191831#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 191802#L238 assume !(1 == ~m_pc~0); 191803#L238-2 is_master_triggered_~__retres1~0#1 := 0; 191865#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 191785#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 191783#L615 assume !(0 != activate_threads_~tmp~1#1); 191784#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 191764#L257 assume !(1 == ~t1_pc~0); 191765#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 191799#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 191653#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 191654#L623 assume !(0 != activate_threads_~tmp___0~0#1); 191637#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191638#L276 assume !(1 == ~t2_pc~0); 191908#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 192024#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 191906#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 191907#L631 assume !(0 != activate_threads_~tmp___1~0#1); 192068#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 191782#L295 assume !(1 == ~t3_pc~0); 191642#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 191643#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 191605#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 191606#L639 assume !(0 != activate_threads_~tmp___2~0#1); 192058#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192059#L314 assume !(1 == ~t4_pc~0); 191661#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 191660#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 191693#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 191694#L647 assume !(0 != activate_threads_~tmp___3~0#1); 191763#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 192018#L555 assume !(1 == ~M_E~0); 191669#L555-2 assume !(1 == ~T1_E~0); 191670#L560-1 assume !(1 == ~T2_E~0); 191612#L565-1 assume !(1 == ~T3_E~0); 191613#L570-1 assume !(1 == ~T4_E~0); 191771#L575-1 assume !(1 == ~E_1~0); 191948#L580-1 assume !(1 == ~E_2~0); 191822#L585-1 assume !(1 == ~E_3~0); 191650#L590-1 assume !(1 == ~E_4~0); 191644#L595-1 assume { :end_inline_reset_delta_events } true; 191645#L776-2 assume !false; 196504#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 196501#L477-1 [2024-11-23 02:55:29,256 INFO L747 eck$LassoCheckResult]: Loop: 196501#L477-1 assume !false; 196499#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 196496#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 196494#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 196492#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 196490#L416 assume 0 != eval_~tmp~0#1; 196487#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 196484#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 196482#L424-2 havoc eval_~tmp_ndt_1~0#1; 196479#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 196476#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 196474#L438-2 havoc eval_~tmp_ndt_2~0#1; 196470#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 196420#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 196468#L452-2 havoc eval_~tmp_ndt_3~0#1; 197762#L449-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 196511#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 196510#L466-2 havoc eval_~tmp_ndt_4~0#1; 196509#L463-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 196456#L480 assume !(0 != eval_~tmp_ndt_5~0#1); 196505#L480-2 havoc eval_~tmp_ndt_5~0#1; 196501#L477-1 [2024-11-23 02:55:29,256 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:29,256 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 5 times [2024-11-23 02:55:29,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:29,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877560673] [2024-11-23 02:55:29,257 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-23 02:55:29,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:29,264 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-23 02:55:29,264 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-23 02:55:29,264 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:29,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:29,272 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:29,273 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:29,273 INFO L85 PathProgramCache]: Analyzing trace with hash -462124120, now seen corresponding path program 1 times [2024-11-23 02:55:29,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:29,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027534395] [2024-11-23 02:55:29,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:29,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:29,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:29,278 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:29,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:29,282 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:29,283 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-23 02:55:29,284 INFO L85 PathProgramCache]: Analyzing trace with hash 273309660, now seen corresponding path program 1 times [2024-11-23 02:55:29,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-23 02:55:29,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280096312] [2024-11-23 02:55:29,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-23 02:55:29,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-23 02:55:29,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:29,292 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:29,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:29,304 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-23 02:55:30,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:30,201 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-23 02:55:30,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-23 02:55:30,357 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 23.11 02:55:30 BoogieIcfgContainer [2024-11-23 02:55:30,357 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-23 02:55:30,358 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-23 02:55:30,358 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-23 02:55:30,358 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-23 02:55:30,362 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:55:22" (3/4) ... [2024-11-23 02:55:30,364 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-23 02:55:30,425 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-23 02:55:30,425 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-23 02:55:30,426 INFO L158 Benchmark]: Toolchain (without parser) took 9606.59ms. Allocated memory was 142.6MB in the beginning and 1.6GB in the end (delta: 1.4GB). Free memory was 73.1MB in the beginning and 1.2GB in the end (delta: -1.1GB). Peak memory consumption was 310.5MB. Max. memory is 16.1GB. [2024-11-23 02:55:30,426 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 142.6MB. Free memory is still 95.5MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-23 02:55:30,426 INFO L158 Benchmark]: CACSL2BoogieTranslator took 332.10ms. Allocated memory is still 142.6MB. Free memory was 72.9MB in the beginning and 55.8MB in the end (delta: 17.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-23 02:55:30,426 INFO L158 Benchmark]: Boogie Procedure Inliner took 68.26ms. Allocated memory is still 142.6MB. Free memory was 55.7MB in the beginning and 111.6MB in the end (delta: -55.9MB). Peak memory consumption was 9.2MB. Max. memory is 16.1GB. [2024-11-23 02:55:30,427 INFO L158 Benchmark]: Boogie Preprocessor took 123.32ms. Allocated memory was 142.6MB in the beginning and 184.5MB in the end (delta: 41.9MB). Free memory was 111.5MB in the beginning and 150.8MB in the end (delta: -39.2MB). Peak memory consumption was 10.0MB. Max. memory is 16.1GB. [2024-11-23 02:55:30,427 INFO L158 Benchmark]: RCFGBuilder took 910.69ms. Allocated memory is still 184.5MB. Free memory was 150.8MB in the beginning and 95.2MB in the end (delta: 55.6MB). Peak memory consumption was 54.5MB. Max. memory is 16.1GB. [2024-11-23 02:55:30,427 INFO L158 Benchmark]: BuchiAutomizer took 8099.96ms. Allocated memory was 184.5MB in the beginning and 1.6GB in the end (delta: 1.4GB). Free memory was 95.2MB in the beginning and 1.2GB in the end (delta: -1.1GB). Peak memory consumption was 278.7MB. Max. memory is 16.1GB. [2024-11-23 02:55:30,427 INFO L158 Benchmark]: Witness Printer took 67.69ms. Allocated memory is still 1.6GB. Free memory was 1.2GB in the beginning and 1.2GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2024-11-23 02:55:30,428 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 142.6MB. Free memory is still 95.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 332.10ms. Allocated memory is still 142.6MB. Free memory was 72.9MB in the beginning and 55.8MB in the end (delta: 17.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 68.26ms. Allocated memory is still 142.6MB. Free memory was 55.7MB in the beginning and 111.6MB in the end (delta: -55.9MB). Peak memory consumption was 9.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 123.32ms. Allocated memory was 142.6MB in the beginning and 184.5MB in the end (delta: 41.9MB). Free memory was 111.5MB in the beginning and 150.8MB in the end (delta: -39.2MB). Peak memory consumption was 10.0MB. Max. memory is 16.1GB. * RCFGBuilder took 910.69ms. Allocated memory is still 184.5MB. Free memory was 150.8MB in the beginning and 95.2MB in the end (delta: 55.6MB). Peak memory consumption was 54.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 8099.96ms. Allocated memory was 184.5MB in the beginning and 1.6GB in the end (delta: 1.4GB). Free memory was 95.2MB in the beginning and 1.2GB in the end (delta: -1.1GB). Peak memory consumption was 278.7MB. Max. memory is 16.1GB. * Witness Printer took 67.69ms. Allocated memory is still 1.6GB. Free memory was 1.2GB in the beginning and 1.2GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 27493 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.9s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 3.3s. Construction of modules took 0.5s. Büchi inclusion checks took 3.6s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 1.8s AutomataMinimizationTime, 22 MinimizatonAttempts, 7069 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 0.8s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 11060 SdHoareTripleChecker+Valid, 0.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 11060 mSDsluCounter, 24052 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 10511 mSDsCounter, 223 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 639 IncrementalHoareTripleChecker+Invalid, 862 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 223 mSolverCounterUnsat, 13541 mSDtfsCounter, 639 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 411]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp_ndt_1)) [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_2)) [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_3)) [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_4)) [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 411]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp_ndt_1)) [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_2)) [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_3)) [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_4)) [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-23 02:55:30,448 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)